Channel coding method and apparatus

Abstract

A channel coding method and apparatus. In the method, a sending apparatus performs low-density parity-check code (LDPC) coding on an input bit sequence on the basis of a first base graph that includes a first core matrix and corresponds to a first initial transmission code rate, so as to obtain a coded bit sequence, wherein the first base graph is one of N base graphs; the N base graphs further comprise a second base graph; the second base graph includes a second core matrix and corresponds to a second initial transmission code rate; N is an integer greater than or equal to 2; elements in the first base graph are zero elements and non-zero elements, and elements in the second base graph are zero elements and non-zero elements; the number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph; the second initial transmission code rate is less than the first initial transmission code rate; and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The method can reduce the complexity of channel coding and channel decoding.

Description

Channel coding method and apparatus

[0001] The present application claims priority to the Chinese patent application No. 202411239602.2, filed on September 4, 2024, and entitled “Channel coding method and apparatus”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication technology, and in particular to a channel coding method and apparatus. BACKGROUND

[0003] Channel coding is one of the core technologies in the field of wireless communication. To meet the requirements of channel coding in three application scenarios in a communication system, such as a 5th generation (5G) communication system, a low-density parity-check code (LDPC) can be used to encode an input bit sequence.

[0004] The LDPC code can be a raptor-like structure, and the LDPC code of the raptor-like structure includes a high-rate core matrix and an extension matrix. In a scenario of channel coding using the LDPC code of the raptor-like structure, how to reduce the complexity of channel coding and channel decoding remains to be studied. SUMMARY

[0005] Embodiments of the present application provide a channel coding method and apparatus, which can reduce the complexity of channel coding and channel decoding.

[0006] In a first aspect, embodiments of the present application provide a channel coding method. The method can be applied to a sending device side, such as a sending device or a communication module in the sending device, or a circuit or chip responsible for communication functions in the sending device (such as a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or a system in package (SIP) chip containing a modem core). The sending device can be a terminal or a network device. Taking the case where the method is applied to the sending device as an example, in the method, the sending device encodes an input bit sequence based on a first base graph containing a first core matrix corresponding to a first initial transmission code rate, to obtain an encoded bit sequence.

[0007] The first base graph is one of N base graphs, and the N base graphs further include a second base graph, the second base graph includes a second core matrix and corresponds to a second initial transmission code rate, N is an integer greater than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The first core matrix includes a sub-matrix A1 and a sub-matrix B1, the second core matrix includes a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2. B1 includes columns with a weight of 3 and a sub-matrix B'1 of a double-diagonal structure. B2 includes columns with a weight of 3 and a sub-matrix B'2 of a double-diagonal structure.

[0008] It can be seen that, by the above method, different initial transmission code rates do not need to share one core matrix, and the smaller the initial transmission code rate is, the greater the number of rows of the core matrix is, the base graphs to which different core matrices belong have the same number of rows and columns, which can make the proportion of non-zero elements in the core matrix with a smaller initial transmission code rate smaller, that is, the core matrix with a smaller initial transmission code rate can have a larger sparsity, so that the sparsity of the base graph can be reduced, and the complexity of channel encoding and channel decoding can be reduced.

[0009] In an alternative implementation, the number of rows of the second core matrix is greater than the number of rows of the first core matrix, which can be replaced by: the number of columns of the second core matrix is greater than the number of columns of the first core matrix. It can be seen that the smaller the initial transmission code rate is, the greater the number of columns of the core matrix is, which can make the core matrix with a smaller initial transmission code rate have a larger sparsity, and thus the complexity of channel encoding and channel decoding can be reduced.

[0010] In another alternative implementation, the number of rows of the second core matrix is greater than the number of rows of the first core matrix, which can be replaced by: the number of rows of the second core matrix is greater than the number of rows of the first core matrix, and the number of columns of the second core matrix is greater than the number of columns of the first core matrix. It can be seen that the smaller the initial transmission code rate is, the greater the number of rows and columns of the core matrix is, which can make the core matrix with a smaller initial transmission code rate have a larger sparsity, and thus the complexity of channel encoding and channel decoding can be reduced.

[0011] In an alternative implementation, the number of rows of the first core matrix is associated with the first initial transmission code rate R1, and the number of rows of the second core matrix is associated with the second initial transmission code rate R2, R1 and R2 are both positive real numbers. In this way, the number of rows of the core matrix is associated with the initial transmission code rate, which is conducive to making the core matrix with a smaller initial transmission code rate have a larger sparsity, and thus is conducive to reducing the complexity of channel encoding and channel decoding.

[0012] The number of rows of the first core matrix is associated with R1, which can be understood as that the number of rows of the first core matrix has a correlation with R1, or that the number of rows of the first core matrix is determined based on R1. Similarly, the number of rows of the second core matrix is associated with R2, which can be understood as that the number of rows of the second core matrix has a correlation with R2, or that the number of rows of the second core matrix is determined based on R2.

[0013] In an optional embodiment, the number of rows m core1 is further associated with at least one of the following: the number of columns k b of A1, the number of punctured columns n prune1 in A1. core2 is further associated with at least one of the following: the number of columns k b of A2, the number of punctured columns n prune2 in A2. core1 , m core2 , k b , n prune1 , and n prune2 are integers greater than or equal to 0.

[0014] The number of rows m core1 is further associated with at least one of the following: k b , n prune1 , which can be understood as that m core1 is further associated with k b , n prune1 , or that m core1 is further determined based on k b and n prune1 . Similarly, the number of rows m core2 is further associated with at least one of the following: k b , n prune2 , which can be understood as that m core2 is further associated with k b , n prune2 , or that m core2 is further determined based on k b and n prune2 .

[0015] In an optional embodiment, the punctured column in A1 can be understood as a punctured column of the first core matrix, or a punctured column of the first base graph, which is not limited in the embodiments of the present application. Similarly, the punctured column in A2 can be understood as a punctured column of the second core matrix, or a punctured column of the second base graph, which is not limited in the embodiments of the present application.

[0016] In an optional embodiment, m core1 satisfies: m core2 satisfy: in, This indicates rounding down. It can be seen that the smaller the initial transmission code rate, the larger the number of rows in the core array. This method allows a smaller initial transmission code rate to correspond to a core array with a larger number of rows, thus enabling the core array with a smaller initial transmission code rate to have greater sparsity, which reduces the complexity of channel coding and channel decoding.

[0017] In one optional implementation, the first core array has m rows. core1 The second core array has p*m rows. core1 Among them, A2's p*m core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched column, and its relationship with m in A1. core1 The non-zero elements in the row and column with punched holes are in the same position. In A1, the non-punched column contains p groups of non-zero elements, and in A2, the q-th m-th non-punched column... core1 The row contains the q-th non-zero element from the p-th non-zero elements, and A2 has p*m core1 The qth m in the row core1 The position of the q-th non-zero element included in the row, and the m of A1 core1 The non-zero elements in the q-th group included in the row are in the same position. Additionally, m... core1 Let p be a positive integer, p be an integer greater than or equal to 2, and q be an integer greater than or equal to 1 and less than or equal to p.

[0018] It is evident that the number of rows in the second core array can be obtained by expanding the number of rows in the first core array by a factor of p. Furthermore, the positions of the non-zero elements in the punched columns of the second core array are associated with the positions of the non-zero elements in the punched columns of the first core array, and the positions of the non-zero elements in the non-punched columns of the second core array are associated with the positions of the non-punched columns of the first core array. This method allows the transmitting device to store a high-bit-rate first core array and a low-bit-rate second core array based on the first core array, reducing the storage overhead of the storage matrix.

[0019] In one optional implementation, the first initial transmission code rate and the second initial transmission code rate belong to different code rate ranges. Therefore, when different initial transmission code rates belong to different code rate ranges, different initial transmission code rates correspond to core matrices with different numbers of rows. Compared with core matrices with different initial transmission code rates corresponding to different numbers of rows within the same code rate range, this method can reduce the storage overhead of the storage matrix.

[0020] In a second aspect, the embodiments of the present application further provide a channel decoding method, which can be applied to a receiving device, such as a receiving device or a communication module in the receiving device, or a circuit or chip (such as a modem chip, also known as a baseband chip, or a SoC chip containing a modem core or a SIP chip) responsible for communication functions in the receiving device. The receiving device can be a network device or a terminal. Taking the case where the method is applied to a receiving device, in the method, the receiving device performs low-density parity-check code (LDPC) decoding on an input bit sequence based on a first base graph containing a first core matrix corresponding to a first initial transmission code rate, to obtain a decoded bit sequence.

[0021] The first base graph is one of N base graphs, and the N base graphs further include a second base graph containing a second core matrix and corresponding to a second initial transmission code rate. N is an integer greater than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The first core matrix includes a sub-matrix A1 and a sub-matrix B1, and the second core matrix includes a sub-matrix A2 and a sub-matrix B2. The number of columns of A1 is equal to the number of columns of A2. B1 includes columns with a weight of 3 and a sub-matrix B'1 of a double-diagonal structure. B2 includes columns with a weight of 3 and a sub-matrix B'2 of a double-diagonal structure.

[0022] It can be seen that, by the above method, different initial transmission code rates do not need to share one core matrix, and the smaller the initial transmission code rate is, the greater the number of rows of the core matrix is. The base graphs to which different core matrices belong have the same number of rows and columns, which can make the proportion of non-zero elements in the core matrix with a smaller initial transmission code rate smaller, that is, the core matrix with a smaller initial transmission code rate can have a larger sparsity, so as to reduce the sparsity of the base graph, and further reduce the complexity of channel encoding and channel decoding.

[0023] In an alternative embodiment, the number of rows of the second core matrix is greater than the number of rows of the first core matrix, which can be replaced by: the number of columns of the second core matrix is greater than the number of columns of the first core matrix. It can be seen that the smaller the initial transmission code rate is, the greater the number of columns of the core matrix is, which can make the core matrix with a smaller initial transmission code rate have a larger sparsity, so as to reduce the complexity of channel encoding and channel decoding.

[0024] In another alternative embodiment, the number of rows of the second core matrix is greater than the number of rows of the first core matrix, which can be replaced by: the number of rows of the second core matrix is greater than the number of rows of the first core matrix, and the number of columns of the second core matrix is greater than the number of columns of the first core matrix. It can be seen that the smaller the initial transmission code rate is, the greater the number of rows and columns of the core matrix is, which can make the core matrix with a smaller initial transmission code rate have a larger sparsity, so as to reduce the complexity of channel encoding and channel decoding.

[0025] In one optional implementation, the number of rows in the first core array is associated with a first initial transmission code rate R1, and the number of rows in the second core array is associated with a second initial transmission code rate R2, where R1 and R2 are both positive real numbers. In this approach, the number of rows in the core array is associated with the initial transmission code rate, which helps to ensure that the core array with a smaller initial transmission code rate has greater sparsity, thereby reducing the complexity of channel coding and channel decoding.

[0026] The number of rows in the first core matrix is ​​related to R1, which can be understood as: there is a correlation between the number of rows in the first core matrix and R1, or the number of rows in the first core matrix is ​​determined based on R1. Similarly, the number of rows in the second core matrix is ​​related to R2, which can be understood as: there is a correlation between the number of rows in the second core matrix and R2, or the number of rows in the second core matrix is ​​determined based on R2.

[0027] In one optional implementation, the first core array has m rows. core1 It is also associated with at least one of the following: the number of columns k in A1 b The number of columns n of the punched columns in A1 prune1 The number of rows m of the second core matrix core2 It is also associated with at least one of the following: the number of columns k in A2 b The number of columns n of the punched columns in A2 prune2 m core1 m core2 k b n prune1 and n prune2 All are integers greater than or equal to 0.

[0028] Where, m core1 It is also associated with at least one of the following: k b n prune1 , can be understood as: m core1 Also with k b n prune1 There is a relationship between them, or it can be understood as: m core1 Also based on k b and n prune1 Confirmed. Similarly, m core2 It is also associated with at least one of the following: k b n prune2 , can be understood as: m core2 Also with k b n prune2 There is a relationship between them, or it can be understood as: m core2 Also based on k b and n prine2 Sure.

[0029] In an optional embodiment, the puncturing columns in A1 can be understood as the puncturing columns of the first core matrix, or can be understood as the puncturing columns of the first base graph, and the embodiments of the present application do not limit this. Similarly, the puncturing columns in A2 can be understood as the puncturing columns of the second core matrix, or can be understood as the puncturing columns of the second base graph, and the embodiments of the present application do not limit this.

[0030] In an optional embodiment, m core1 satisfies: m core2 satisfies: wherein, denotes the floor function. It can be seen that the smaller the initial transmission code rate is, the larger the number of rows of the core matrix is. This method can enable a smaller initial transmission code rate to correspond to a core matrix with a larger number of rows, and thus can enable a core matrix with a smaller initial transmission code rate to have a larger sparsity, thereby reducing the complexity of channel encoding and channel decoding.

[0031] In an optional embodiment, the number of rows of the first core matrix is m core1 , and the number of rows of the second core matrix is p*m core1 . Wherein, the position of the non-zero elements of the qth m core1 row puncturing column in the p*m core1 rows of A2 is the same as the position of the non-zero elements of the m core1 row puncturing column in A1. The qth m core1 row non-puncturing column in A2 includes the qth group of non-zero elements in the p groups of non-zero elements, and the position of the qth group of non-zero elements included in the qth m core1 row in the p*m core1 rows of A2 is the same as the position of the qth group of non-zero elements included in the m core1 row in A1. In addition, m T is a positive integer, p is an integer greater than or equal to 2, and q is an integer greater than or equal to 1 and less than or equal to p.

[0032] It can be seen that the number of rows of the second core matrix can be obtained by expanding the number of rows of the first core matrix by p times. In addition, the position of the non-zero elements of the puncturing column in the second core matrix is associated with the position of the non-zero elements of the puncturing column in the first core matrix, and the position of the non-zero elements of the non-puncturing column in the second core matrix is associated with the position of the non-zero elements of the non-puncturing column in the first core matrix. This method can enable the receiving device to store the first core matrix with a high code rate and obtain the second core matrix with a low code rate based on the first core matrix, thereby reducing the storage overhead of storing the matrix.

[0033] In an alternative embodiment, the first initial transmission code rate and the second initial transmission code rate belong to different code rate intervals. Thus, when different initial transmission code rates belong to different code rate intervals, different initial transmission code rates correspond to different numbers of core matrices, which can reduce the storage overhead of the storage matrix compared with the case where different initial transmission code rates in the same code rate interval correspond to different numbers of core matrices.

[0034] In a third aspect, the embodiments of the present application further provide a communication device, which has the functions of the first aspect, for example, the communication device includes modules or units or means corresponding to the operations of the first aspect, which can be implemented by software, or by hardware, or by a combination of software and hardware.

[0035] In a possible design, the communication device can include a processing unit and a communication unit, where the processing unit is configured to support the communication device to perform the corresponding functions in the above method. The communication unit is configured to support the communication between the communication device and another communication device. The communication device can further include a storage unit, which is configured to be coupled with the processing unit and the communication unit, and save the necessary program instructions and data of the communication device.

[0036] In an embodiment, the communication device includes a processing unit and a communication unit, where the communication unit is configured to transmit and receive signals / signaling.

[0037] The processing unit is configured to perform LDPC encoding on the input bit sequence based on a first base graph including a first core matrix corresponding to the first initial transmission code rate, to obtain an encoded bit sequence.

[0038] The first base graph is one of N base graphs, and the N base graphs further include a second base graph, the second base graph includes a second core matrix and corresponds to a second initial transmission code rate, N is an integer greater than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The first core matrix includes a sub-matrix A1 and a sub-matrix B1, the second core matrix includes a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2. B1 includes columns with a weight of 3 and a sub-matrix B'1 with a double diagonal structure. B2 includes columns with a weight of 3 and a sub-matrix B'2 with a double diagonal structure.

[0039] In addition, in this aspect, other alternative embodiments of the communication device can refer to the related content of the first aspect, which will not be described in detail here.

[0040] As an example, the communication unit can be a transceiver or a communication interface, the storage unit can be a memory, and the processing unit can be a processor.

[0041] In an implementation form, the communication apparatus comprises a processor and a transceiver configured to transceive signals / signaling.

[0042] The processor is configured to perform LDPC encoding on the input bit sequence based on a first base graph comprising a first core matrix corresponding to a first initial transmission code rate, to obtain an encoded bit sequence.

[0043] The first base graph is one of N base graphs, and the N base graphs further comprise a second base graph, the second base graph comprises a second core matrix and corresponds to a second initial transmission code rate, N is an integer greater than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The first core matrix comprises a sub-matrix A1 and a sub-matrix B1, the second core matrix comprises a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2. B1 comprises columns with a weight of 3 and a sub-matrix B'1 of a double diagonal structure. B2 comprises columns with a weight of 3 and a sub-matrix B'2 of a double diagonal structure.

[0044] In addition, in this aspect, other optional implementation forms of the communication apparatus can refer to the related content of the first aspect described above, which will not be described in detail here.

[0045] In a fourth aspect, the embodiments of the present application further provide a communication apparatus, which has the functions of the second aspect described above, for example, the communication apparatus comprises a module or unit or means corresponding to the operations of the second aspect described above, which can be implemented by software, or by hardware, or by a combination of software and hardware.

[0046] In a possible design, the communication apparatus can include a processing unit and a communication unit in its structure, where the processing unit is configured to support the communication apparatus to perform the corresponding functions in the above method. The communication unit is configured to support the communication between the communication apparatus and another communication apparatus. The communication apparatus can further include a storage unit configured to be coupled with the processing unit and the communication unit, and save the necessary program instructions and data of the communication apparatus.

[0047] In an implementation form, the communication apparatus comprises a processing unit and a communication unit configured to transceive signals / signaling.

[0048] The processing unit is configured to perform LDPC decoding on the input bit sequence based on a first base graph corresponding to the first initial transmission code rate and containing a first core matrix, to obtain a decoded bit sequence.

[0049] The first base graph is one of N base graphs, the N base graphs further include a second base graph, the second base graph contains a second core matrix and corresponds to a second initial transmission code rate, N is an integer greater than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The first core matrix includes a sub-matrix A1 and a sub-matrix B1, the second core matrix includes a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2. B1 includes columns with a weight of 3 and a sub-matrix B'1 of a double diagonal structure. B2 includes columns with a weight of 3 and a sub-matrix B'2 of a double diagonal structure.

[0050] In addition, in this aspect, other optional implementations of the communication device can refer to the related content of the second aspect described above, which will not be described in detail here.

[0051] For example, the communication unit can be a transceiver or a communication interface, the storage unit can be a memory, and the processing unit can be a processor.

[0052] In an embodiment, the communication device includes a processor and a transceiver, and the transceiver is configured to transmit and receive signals / signaling.

[0053] The processing unit is configured to perform LDPC decoding on the input bit sequence based on a first base graph corresponding to the first initial transmission code rate and containing a first core matrix, to obtain a decoded bit sequence.

[0054] The first base graph is one of N base graphs, the N base graphs further include a second base graph, the second base graph contains a second core matrix and corresponds to a second initial transmission code rate, N is an integer greater than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The first core matrix includes a sub-matrix A1 and a sub-matrix B1, the second core matrix includes a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2. B1 includes columns with a weight of 3 and a sub-matrix B'1 of a double diagonal structure. B2 includes columns with a weight of 3 and a sub-matrix B'2 of a double diagonal structure.

[0055] In addition, in this aspect, the other optional implementation of the communication device can refer to the related content of the second aspect described above, which will not be described in detail here.

[0056] In another implementation, the communication device of the third aspect and the fourth aspect is a chip or a chip system. The processing unit can also be implemented as a processing circuit or a logic circuit; the communication unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or related circuit on the chip or chip system, etc.

[0057] In the implementation process, the processor can be used to perform, for example but not limited to, baseband related processing, and the transceiver can be used to perform, for example but not limited to, radio frequency transmission and reception. The above-mentioned devices can be respectively arranged on chips independent of each other, or at least part or all of them can be arranged on the same chip. For example, the processor can be further divided into an analog baseband processor and a digital baseband processor. Among them, the analog baseband processor can be integrated on the same chip as the transceiver, and the digital baseband processor can be arranged on an independent chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, the digital baseband processor can be integrated on the same chip as various application processors (such as but not limited to, graphic processors, multimedia processors, etc.). Such a chip can be called SoC. Whether to arrange each device independently on different chips or to integrate them on one or more chips often depends on the needs of product design. The embodiments of the present application do not limit the implementation form of the above-mentioned devices.

[0058] In the fifth aspect, the embodiments of the present application further provide a communication device, which includes an interface circuit and one or more processors. The one or more processors are coupled with a memory. The memory is used to store part or all of the necessary computer programs or instructions for implementing the functions related to the above-mentioned first aspect. The one or more processors can execute the computer programs or instructions, and when the computer programs or instructions are executed, they make the communication device implement the method in any possible design or implementation manner in the above-mentioned first aspect. The interface circuit is used to realize the communication function within the communication device and / or the communication function between the communication device and other devices or components.

[0059] In a possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0060] In a possible design, the communication device can further include the memory.

[0061] The above-mentioned communication device can be a sending device, a communication module in the sending device, or a chip responsible for the communication function in the sending device, such as a modem chip (also known as a baseband chip) or a SoC or SIP chip containing a modem module.

[0062] In a sixth aspect, the embodiments of the present application further provide a communication apparatus, which comprises an interface circuit and one or more processors. The one or more processors are coupled with a memory. The memory is configured to store part or all of the necessary computer programs or instructions for implementing the functions related to the second aspect. The one or more processors can execute the computer programs or instructions, and when the computer programs or instructions are executed, the communication apparatus implements the method in any possible design or implementation manner of the second aspect. The interface circuit is configured to implement the communication function within the communication apparatus and / or the communication function between the communication apparatus and other apparatuses or components.

[0063] In a possible design, the processor is configured to communicate with other apparatuses or components through the interface circuit.

[0064] In a possible design, the communication apparatus further comprises the memory.

[0065] The communication apparatus can be a receiving apparatus, a communication module in the receiving apparatus, or a chip responsible for the communication function in the receiving apparatus, such as a modem chip (also referred to as a baseband chip) or a SoC or SIP chip containing a modem module.

[0066] In a seventh aspect, the embodiments of the present application further provide a communication system, which comprises a sending apparatus for executing the method in any of the first aspect and a receiving apparatus for executing the method in any of the second aspect. In another possible design, the system can further comprise other apparatuses / functional network elements that interact with at least one of the sending apparatus and the receiving apparatus.

[0067] In an eighth aspect, the embodiments of the present application provide a computer readable storage medium for storing instructions, which, when executed by a computer, implement the method in any of the first aspect or the second aspect.

[0068] In a ninth aspect, the embodiments of the present application further provide a computer program product comprising instructions, which, when executed on a computer, implement the method in any of the first aspect or the second aspect.

[0069] In a tenth aspect, an embodiment of the present application provides a chip system, which comprises a processor and an interface, the interface being configured to acquire a program or an instruction, and the processor being configured to invoke the program or the instruction to implement or support the functions related to the sending device implementing the first aspect or the receiving device implementing the second aspect. For example, at least one of the data and the information related to the above method is determined or processed. In a possible design, the chip system further comprises a memory, and the memory is configured to store necessary program instructions and data. The chip system can be composed of a chip, or can comprise a chip and other discrete devices.

[0070] In an eleventh aspect, an embodiment of the present application provides a communication device, comprising a processor configured to execute computer programs or executable instructions stored in a memory, and when the computer programs or executable instructions are executed, the device performs the method in the first aspect or the second aspect and any possible implementation.

[0071] In a possible implementation, the processor and the memory are integrated together.

[0072] In another possible implementation, the memory is located outside the communication device.

[0073] The advantages of the third aspect to the eleventh aspect can refer to the advantages of the first aspect or the second aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0074] FIG. 1 is a schematic diagram of a system architecture provided by an embodiment of the present application;

[0075] FIG. 2 is a schematic diagram of a Tanner graph provided by an embodiment of the present application;

[0076] FIG. 3 and FIG. 9 are schematic diagrams of a base graph of an LDPC code provided by an embodiment of the present application;

[0077] FIG. 4, FIG. 10a and FIG. 10b are schematic diagrams of a base matrix provided by an embodiment of the present application;

[0078] FIG. 5 is a schematic diagram of a matrix corresponding to each element in a base matrix provided by an embodiment of the present application;

[0079] FIG. 6, FIG. 24 to FIG. 27 are schematic diagrams of structures of a base graph provided by an embodiment of the present application;

[0080] FIG. 7 is a schematic diagram of a sub-matrix B provided by an embodiment of the present application;

[0081] FIG. 8 and FIG. 15 are schematic diagrams of strategies of base graph selection provided by an embodiment of the present application;

[0082] FIG. 11 and FIG. 12 are base graph diagrams of 1 / 3 code rate and 1 / 2 code rate, respectively, according to an embodiment of the present application;

[0083] FIG. 13 is a flow diagram of a channel coding method according to an embodiment of the present application;

[0084] FIG. 14 is a diagram of the relationship between the initial transmission code rate and the number of rows of a core matrix according to an embodiment of the present application;

[0085] FIG. 16, FIG. 18, FIG. 19, FIG. 21 and FIG. 22 are diagrams of core matrices according to embodiments of the present application;

[0086] FIG. 17, FIG. 20 and FIG. 23 are diagrams of weight comparisons according to embodiments of the present application;

[0087] FIG. 28 is a flow diagram of a channel decoding method according to an embodiment of the present application;

[0088] FIG. 29 and FIG. 30 are diagrams of base graph selection and base graph reading processes according to embodiments of the present application;

[0089] FIG. 31 is a diagram of a communication system according to an embodiment of the present application;

[0090] FIG. 32 is a diagram of a communication device according to an embodiment of the present application;

[0091] FIG. 33 is a diagram of a terminal according to an embodiment of the present application. DETAILED DESCRIPTION

[0092] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application.

[0093] FIG. 1 is a diagram of a possible, non-limiting system architecture. As shown in FIG. 1, a communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. The RAN 100 includes at least one RAN node (e.g., 110a and 110b in FIG. 1, collectively referred to as 110) and at least one terminal (e.g., 120a-120j in FIG. 1, collectively referred to as 120). The RAN 100 can also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in FIG. 1), etc. The terminal 120 is connected to the RAN node 110 in a wireless manner. The RAN node 110 is connected to the core network 200 in a wireless or wired manner. The core network device in the core network 200 and the RAN node 110 in the RAN 100 can be different physical devices, or can be the same physical device integrated with the core network logical function and the radio access network logical function.

[0094] The RAN 100 can be a 3rd generation partnership project (3GPP) related cellular system, e.g., a 5th generation (5G) mobile communication system, or a future oriented evolved system. The RAN 100 can also be an open radio access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. The RAN 100 can also be a communication system that combines two or more of the above systems.

[0095] The RAN nodes 110, which can also be referred to as access network devices, RAN entities or access nodes, etc., form part of the communication system 100 and are configured to facilitate wireless access to the communication system 100 for terminals. The RAN nodes 110 in the communication system 100 can be of the same type or of different types. In some scenarios, the roles of the RAN nodes 110 and the terminals 120 are relative, e.g., the network element 120i in Figure 1 can be a helicopter or a drone, which can be configured to be a mobile base station, for a terminal 120j that accesses the RAN 100 through the network element 120i, the network element 120i is a base station; but for the base station 110a, the network element 120i is a terminal. The RAN nodes 110 and the terminals 120 are sometimes referred to as communication apparatuses, e.g., the network elements 110a and 110b in Figure 1 can be understood as communication apparatuses with base station functionalities, and the network elements 120a-120j can be understood as communication apparatuses with terminal functionalities.

[0096] In a possible scenario, the RAN node can be a base station (BS), an evolved Node B (eNodeB), an access point (AP), a transmission reception point (TRP), a next generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system, etc. The RAN node can be a macro base station (such as 110a in FIG. 1), a micro base station or an indoor station (such as 110b in FIG. 1), a relay node or a donor node, or a wireless controller in a CRAN scenario. Optionally, the RAN node can also be a server, a wearable device, a vehicle or a vehicle-mounted device, etc. For example, the access network device in vehicle to everything (V2X) technology can be a road side unit (RSU). All or part of the functions of the RAN node in the present application can also be implemented by software functions running on hardware, or by virtualized functions instantiated on a platform (such as a cloud platform). The RAN node can also be provided with a communication module, circuit or chip for performing corresponding communication functions, and program instructions for performing corresponding communication functions. The RAN node in the present application can also be a logical node, a logical module or software that can implement all or part of the functions of the RAN node.

[0097] In another possible scenario, multiple RAN nodes cooperate to assist a terminal to implement wireless access, and different RAN nodes respectively implement part of the functions of a base station. For example, the RAN node can be a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU), etc. The CU and the DU can be separately arranged, or can be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or a radio frequency unit, such as a remote radio unit (RRU), an active antenna processing unit (AAU), or a remote radio head (RRH).

[0098] In different systems, the CU (or CU-CP and CU-UP), DU or RU can also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, the CU can also be referred to as O-CU (open CU), the DU can also be referred to as O-DU, the CU-CP can also be referred to as O-CU-CP, the CU-UP can also be referred to as O-CU-UP, and the RU can also be referred to as O-RU. For the convenience of description, the CU, CU-CP, CU-UP, DU and RU are taken as examples for description in this application. Any one of the CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0099] In the embodiments of the present application, the RAN node can also have different expressions, such as a network device. In this application, the network device is used for description hereinafter unless otherwise specified.

[0100] A terminal can be a device or module with corresponding communication functions and can access the above communication system. The terminal can also be referred to as a terminal device, a user equipment (UE), a mobile station, a mobile terminal, etc. The terminal can be widely used in various scenarios, such as device-to-device (D2D) communication, V2X communication, machine-type communication (MTC), internet of things (IOT), virtual reality, augmented reality, industrial control, autonomous driving, remote medical treatment, smart power grid, smart furniture, smart office, smart wear, smart transportation, smart city, etc. The terminal can be a mobile phone, a tablet computer, a computer with wireless transceiver function, a wearable device, a vehicle, a drone, a helicopter, an airplane, a ship, a robot, a mechanical arm, a smart home device, a wireless communication function transport vehicle, a communication module, etc. The embodiments of the present application do not limit the device form of the terminal. The terminal usually has a communication module, circuit or chip for executing corresponding communication functions. The terminal also has program instructions for executing corresponding communication functions.

[0101] The embodiments of the present application can be applied to various mobile communication scenarios, for example, including but not limited to a point-to-point single connection communication scenario, a multi-hop single connection communication scenario, a dual connectivity (DC) communication scenario, and a multi-hop connection communication scenario. It should be noted that the exemplary communication scenarios of the present application do not limit the network architecture applicable to the present application. Any one of the network side devices in the cellular network charges other devices, which is the network architecture available in the present application. The application scenarios of the present application include but are not limited to the network device charging the terminal device, the network device charging the network device, the network device charging the relay, the relay base station charging the terminal device, the plurality of network devices charging the terminal device, the plurality of network devices charging the plurality of terminal devices, and any one or more of the network side devices charging one or more devices.

[0102] In the embodiments of the present application, the sending device can be a terminal device, and the receiving device can be a network device. Alternatively, the sending device can be a network device, and the receiving device can be a terminal device. Alternatively, the sending device and the receiving device can both be terminal devices. Alternatively, the sending device and the receiving device can both be network devices. Alternatively, the sending device and the receiving device can also be processors, modules, chips, or chip systems or software modules that support the implementation of the corresponding methods. The embodiments of the present application do not limit the specific forms of the sending device and the receiving device.

[0103] In the embodiments of the present application, the functions of the network device can also be performed by a module (such as a chip) in the network device, or by a control subsystem containing the functions of the network device. The control subsystem containing the functions of the network device herein can be a control center in the above-mentioned application scenarios such as smart grid, industrial control, intelligent transportation, and smart city. The functions of the terminal device can also be performed by a module (such as a chip or a modem) in the terminal device, or by a device containing the functions of the terminal device.

[0104] The embodiments disclosed in the present application will present various aspects, embodiments or features of the present application around a system including a plurality of devices, components, modules, etc. It should be understood and appreciated that each system can include additional devices, components, modules, etc., and / or can not include all the devices, components, modules, etc. discussed in connection with the drawings. In addition, combinations of these solutions can also be used.

[0105] In order to facilitate the understanding of the solutions of the embodiments of the present application, the terms that can be involved in the embodiments of the present application are explained below.

[0106] 1. Low-density parity-check code (LDPC) code, parity-check matrix H, base graph.

[0107] An LDPC code is a kind of linear block code, and a parity check matrix thereof has a sparse characteristic, and the proportion of elements 1 in the parity check matrix is extremely small, so it is also called a low-density parity check code. For an LDPC code with K information bits and N code length, the dimension of a parity check matrix H thereof is (N-K) x N, and a code word c of the corresponding LDPC code can be defined by the parity check matrix H as follows: c = {c | Hc T = 0, c e {0, 1} N} (1)

[0108] In the parity check matrix H, each row corresponds to a check equation of the LDPC code, and N-K check equations correspond to N-K check nodes of the LDPC code; each column corresponds to a code element of the LDPC code, and N code elements correspond to N variable nodes of the LDPC code. Wherein, K and N are positive integers. Non-zero elements h i,j in the parity check matrix H indicate that the ith check node is connected to the jth variable node. The number of non-zero elements in each row of the check matrix is the degree of the check node, and the number of non-zero elements in each column is the degree of the variable node. If the degrees of all check nodes are equal, and the degrees of all variable nodes are also equal, the matrix corresponds to a regular code, otherwise it is an irregular code.

[0109] For example, a check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is as follows:

[0110] Wherein, V0, V1, …, V9 represent variable nodes, and C0, C1, …, C4 represent check nodes.

[0111] In addition, the LDPC code can be represented by a graph model, which includes a Tanner graph, a factor graph and a tree graph, etc., and the description of the Tanner graph is simple and intuitive. For example, FIG. 2 is a schematic diagram of a Tanner graph. Specifically, FIG. 2 is a schematic diagram of a Tanner graph of the check matrix H shown in the above formula (2). As shown in FIG. 2, the connection line in FIG. 2 represents the connection relationship between the check nodes and the variable nodes in the parity check matrix H. For example, the check node C0 in the parity check matrix H has a connection relationship with the variable nodes V0, V1, V2 and V6, and the check node C0 in FIG. 2 is connected with the variable nodes V0, V1, V2 and V6.

[0112] In addition, the parity check matrix H of the LDPC code can be obtained by a base graph (BG) and a shift value. The base graph can generally include m*n matrix entries, which can be represented in the form of a matrix with m rows and n columns, and the matrix entries are 0 or 1. The entry represented as 0 is also referred to as a zero entry, which means that the entry can be replaced by a zero matrix of Z*Z. The entry represented as 1 is also referred to as a non-zero entry, which means that the entry can be replaced by a circulant permutation matrix of Z*Z. That is, each matrix entry in the base graph represents a zero matrix or a circulant permutation matrix. For example, FIG. 3 is a schematic diagram of a base graph of an LDPC code. Specifically, FIG. 3 shows a base graph of an exemplary LDPC code with quasi-cyclic (QC) structure, m=4 and n=26. It should be noted that in the application, the row numbers and column numbers of the base graph and the matrix are numbered from 0, which is only for the convenience of description. For example, the 0th column represents the first column of the base graph and the matrix, the 1st column represents the second column of the base graph and the matrix, the 0th row represents the first row of the base graph and the matrix, the 1st row represents the second row of the base graph and the matrix, and so on.

[0113] It can be understood that the row numbers and column numbers can also be numbered from 1, and the corresponding row numbers and column numbers are obtained by adding 1 to the row numbers and column numbers shown in the application. For example, if the row numbers or column numbers are numbered from 1, the 1st column represents the first column of the base graph and the matrix, the 2nd column represents the second column of the base graph and the matrix, the 1st row represents the first row of the base graph and the matrix, the 2nd row represents the second row of the base graph and the matrix, and so on.

[0114] If the element in the i-th row and the j-th column of the base graph is a non-zero element, and the shift value is P i,j , P i,j is an integer greater than or equal to 0, then the non-zero element in the i-th row and the j-th column can be replaced by a corresponding circulant permutation matrix of Z*Z with P i,j , and the circulant permutation matrix can be obtained by performing P i,j times of right or left cyclic shift on a unit matrix of Z*Z. It can be seen that each zero element in the base graph is replaced by a zero matrix of Z*Z, and each non-zero element is replaced by a corresponding circulant permutation matrix of Z*Z with the shift value, so that the parity check matrix of the LDPC code can be obtained. Z is a positive integer, which can also be referred to as a lifting factor, and sometimes can also be referred to as a lifting size or a lifting factor. Z can be determined according to the code block size supported by the system and / or the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z).

[0115] P i,j may be different P i,j For simplicity, the system usually also defines a base matrix of m rows and n columns. In the base matrix, each element corresponds to the position of each element in the base graph. The zero elements in the base graph remain unchanged in the base matrix. The non-zero elements in the i-th row and the j-th column of the base graph remain unchanged in the base matrix and can be represented as V i,j , where P i,j = V i,j mod Z (A mod B means A is taken modulo B). In the embodiments of the present application, the base matrix can also be referred to as the offset matrix of the base graph. For example, FIG. 4 is a schematic diagram of a base matrix. The base matrix shown in FIG. 4 is a base matrix corresponding to the base graph shown in FIG. 3.

[0116] For example, FIG. 5 is a schematic diagram of a matrix corresponding to each element in a base matrix. Specifically, FIG. 5 is a schematic diagram of a matrix corresponding to the non-zero elements in the base graph when the extension factor Z = 4. i,j As shown in FIG. 5, when Z = 4, each zero element represented as -1 is replaced by a 4*4 all-zero matrix A. If P 2,3 = 2, the non-zero element in the 2nd row and the 3rd column is replaced by a 4*4 cyclic permutation matrix D shown in FIG. 5, which is obtained by performing 2 right cyclic shifts on a 4*4 unit matrix B. If P 2,4 = 0, the non-zero element in the 2nd row and the 4th column is replaced by the unit matrix B. Similarly, the above is only an example and is not limited thereto. Usually, the base graph or the base matrix of the LDPC code can also include p built-in puncture bit columns, where p can be an integer from 0 to 2. These columns participate in encoding, but the corresponding system bits are not transmitted, and the code rate of the LDPC code base matrix satisfies For example, if there are 2 built-in puncture bit columns in the base graph shown in FIG. 3, the code rate of the base matrix is (26-4) / (26-2) = 11 / 12, which is approximately 0.92.

[0117] The LDPC code used in the wireless communication system is a QC-LDPC code. The check part of the QC-LDPC code has a double-diagonal structure or a raptor-like structure, which can simplify the encoding and support incremental redundancy hybrid retransmission. In the decoder of the QC-LDPC code, a QC-LDPC shift network (QSN), a Banyan network or a Benes network is usually used to implement the cyclic shift of information.

[0118] A QC-LDPC code with a raptor-like structure has a base graph matrix of size m rows and n columns, which can include five submatrices A, B, C, D, and I. The weights of the matrices are determined by the number of non-zero elements; the row weight (row weight) refers to the number of non-zero elements in a row, and the column weight (column weight) refers to the number of non-zero elements in a column. Figure 6 shows a schematic diagram of one such base graph structure. As shown in Figure 6, where:

[0119] Submatrix A is m A line n A A matrix of columns, the size of which can be m A ×n A Each column corresponds to Z systematic bits in the LDPC code, which are sometimes also called information bits.

[0120] Submatrix B is m A line m A A square matrix of columns, the size of which can be m A ×m A Each column corresponds to Z parity bits in the LDPC code. Submatrix B includes a double-diagonal submatrix B′ and a column of matrices with a weight of 3 (referred to as a 3-column weighted column), where the 3-column weighted column can be placed before submatrix B′; submatrix B can also include one or more columns of matrices with a weight of 1 (referred to as a single-column weighted column), for example. For example, Figure 7 is a schematic diagram of one type of submatrix B. As shown in 7a of Figure 7, the 3-column weighted column is placed before submatrix B′. In addition, submatrix B can include a column of matrices with a weight of 1, which can be implemented as shown in 7b or 7c of Figure 7.

[0121] The matrix generated based on submatrix A and submatrix B is usually called the core matrix, which can be used to support high bit rate encoding. Submatrix A is the information bit part of the core matrix, and submatrix B is the parity bit part of the core matrix.

[0122] Submatrix C is a matrix of all zeros and its size is m. A ×m D .

[0123] Submatrix I is the identity matrix with size m. D ×m D And it is the extended check bit portion.

[0124] The size of the submatrix D is m D ×(n A +m A )m D It is typically used to generate low-rate check bits, which are part of the extended information bits.

[0125] It can be seen that [A B] corresponds to the core matrix H of the LDPC code core ; [D I] corresponds to the extension matrix H of the LDPC code ext .

[0126] It can be understood that, from the perspective of the mathematical definition, since C is a full zero matrix and I is a unit matrix, in a possible implementation, the base graph of the matrix for encoding or decoding can also be represented by a matrix composed of sub-matrices A and B, or a matrix composed of sub-matrices A, B and D. Since the structures of sub-matrices C and I are relatively fixed, the structures of the two parts of sub-matrices A, B and D are one of the factors affecting the encoding and decoding performance of the LDPC code.

[0127] In addition, the base graph may, for example, include two types: BG1 and BG2, but the type of the base graph is not limited in the present application. The size of BG1 is 46x68, the size of the core matrix H core in BG1 is 4x26, and the minimum code rate supported by BG1 is 1 / 3. BG1 is mainly used in a scenario with high throughput requirement, high code rate and long code length. The size of BG2 is 42x52, the size of the core matrix H core in BG2 is 4x14, and BG2 is mainly used in a scenario with low throughput requirement, low code rate and short code length.

[0128] The sending device selects which one of BG1 and BG2 to perform channel coding according to the transfer block size (TBS) and the target code rate. Referring to FIG. 8, which is a schematic diagram of a base graph selection strategy. As shown in FIG. 8, if A≤292, or A≤3824 and R≤0.67, or R≤0.25, BG2 is selected to perform channel coding, otherwise, BG1 is selected to perform channel coding. Wherein, A is the transfer block size, and A is the transfer block size excluding CRC check bits, and R is the target code rate obtained from the modulation and coding scheme (MCS) table at the initial transmission.

[0129] 2. LDPC encoding.

[0130] The LDPC encoding refers to channel encoding of an input bit sequence by using an LDPC code to obtain an encoded bit sequence. When encoding is performed by using an LDPC matrix with a raptor-like structure, one possible implementation is that the sub-matrix A and the matrix of the sub-matrix B, i.e., the core matrix, can be encoded first to obtain the check bits corresponding to the sub-matrix B, and then the entire matrix is encoded to obtain the check bits corresponding to the sub-matrix I. Since the sub-matrix B can include a sub-matrix B' with a double-diagonal structure and a single-column repetition, the check bits corresponding to the double-diagonal structure can be obtained first, and then the check bits corresponding to the single-column repetition can be obtained.

[0131] An example of encoding is given below. It is assumed that the core matrix part composed of the sub-matrix A and the sub-matrix B is H core , the last row and the last column of H core are removed, i.e., the single-column repetition and the row in which the non-zero elements of the column are located are removed, to obtain a matrix part H core-dual , and the check bits in H core-dual are denoted as H e = [H e1 H e2 ], H e1 is a 3-column repetition, and H e2 is a double-diagonal structure. According to the definition of the LDPC code matrix, H core-dual · [S P e ] T = 0, where S is an input sequence, a vector composed of information bits, P e is a vector composed of check bits, and [S P e ] T denotes the transpose of the matrix composed of the input sequence S and P e . Therefore, the check bits corresponding to H core-dual can be calculated first according to the input sequence S and H core-dual , and the input sequence S includes all information bits; then the check bits corresponding to the single-column repetition in the sub-matrix B are calculated according to the obtained check bits corresponding to H core-dual and the input sequence S, at this time, all check bits corresponding to the sub-matrix B can be obtained; and then the check bits corresponding to the sub-matrix I are obtained by using the sub-matrix D part to encode according to the input sequence S and the check bits corresponding to the sub-matrix B, so that all information bits and all check bits are obtained, which constitute an encoded sequence, i.e., an LDPC code sequence.

[0132] Optionally, the LDPC code encoding can also include shortening and puncturing operations. The shortened bits and the punctured bits are not transmitted.

[0133] In the above, the truncation is usually from the last bit of the information bits, and can be performed in different ways. For example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last s0 bits of the input sequence S to obtain an input sequence S', and then the input sequence S' is encoded by the LDPC matrix. For another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last (s0 mod Z) bits of the input sequence S to obtain an input sequence S', and then the input sequence S' is encoded by the LDPC matrix. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last s0 bits of the sub-matrix A to obtain an input sequence S', and then the input sequence S' is encoded by the LDPC matrix. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last (s0 mod Z) bits of the sub-matrix A to obtain an input sequence S', and then the input sequence S' is encoded by the LDPC matrix. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last s0 columns of the LDPC matrix H to obtain an LDPC matrix H', and then the input sequence S is encoded by the LDPC matrix H'. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last (s0 mod Z) columns of the LDPC matrix H to obtain an LDPC matrix H', and then the input sequence S is encoded by the LDPC matrix H'. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last s0 columns of the sub-matrix A to obtain an input sequence S', and then the input sequence S' is encoded by the LDPC matrix. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last (s0 mod Z) columns of the sub-matrix A to obtain an input sequence S', and then the input sequence S' is encoded by the LDPC matrix. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last s0 columns of the LDPC matrix H to obtain an LDPC matrix H', and then the input sequence S is encoded by the LDPC matrix H'. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last (s0 mod Z) columns of the LDPC matrix H to obtain an LDPC matrix H', and then the input sequence S is encoded by the LDPC matrix H'. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last s0 columns of the sub-matrix A to obtain an input sequence S', and then the input sequence S' is encoded by the LDPC matrix. For yet another example, the number of bits s0 to be truncated can be set to known bits (e.g., 0 or null, or other values) in the last (s0 mod Z) columns of the sub-matrix A to obtain an input sequence S', and then the input sequence S' is encoded by the LDPC matrix.

[0134] In the above, the puncturing can be performed on the built-in puncturing bits or the parity bits in the input sequence. When the puncturing is performed on the parity bits, the puncturing is usually performed from the last bit of the parity bits, or can be performed according to a predetermined puncturing order. In one possible implementation, the input sequence is first encoded, and then the last p bits of the parity bits or the p bits according to the predetermined puncturing order are selected according to the number of bits p to be punctured, and the p bits are not transmitted. In another possible implementation, the p columns of the matrix corresponding to the punctured bits and the p rows in which the non-zero elements are located in the columns can be determined, and the rows and columns are not used for encoding, so that the corresponding parity bits are not generated.

[0135] It should be noted that the above encoding methods are only examples, and other encoding methods known to those skilled in the art can also be used based on the base graph and / or the base matrix provided in the present application, and the present application is not limited in this regard. The decoding methods involved in the present application can be various decoding methods, for example, the min-sum (MS) decoding method or the belief propagation (BP) decoding method. For example, the input sequence is initialized and iteratively processed, and then hard decision detection is performed, and the hard decision result is checked. If the decoding result satisfies the check equation, the decoding is successful, the iteration is terminated, and the decision result is output. If the check equation is not satisfied, the iteration is performed again within a maximum number of iterations. If the maximum number of iterations is reached and the check fails, the decoding fails. It can be understood that those skilled in the art can understand the principle of the MS decoding method, and thus the principle of the MS decoding method is not described in detail herein.

[0136] It should be noted that the above decoding methods are only examples, and other decoding methods known to those skilled in the art can also be used based on the base graph and / or the base matrix provided in the present application, and the present application is not limited in this regard.

[0137] Generally, an LDPC code can be obtained based on the design of a base graph and / or a base matrix. For example, optimization of the positions of zero elements and non-zero elements in the base graph or the base matrix can determine the upper bound of the performance of the LDPC code, and the error floor of the LDPC code can be determined according to the offset value in the base matrix. Improving the coding and decoding performance and reducing the error floor are one of the goals of determining the base graph and the base matrix. By designing the base graph and / or the base matrix, the coding or decoding performance can be improved, and the error floor can be reduced. The code length in a wireless communication system is flexible, for example, it can be 2560 bits, 38400 bits, etc. FIG. 9 is a schematic diagram of a base graph of an LDPC code, and FIGS. 10a and 10b are two base matrix examples of the base graph shown in FIG. 9, respectively. The value set of the extension factor Z corresponding to PCM0 shown in FIG. 10a is {2, 4, 8, 16, 32, 64, 128, 256}, and the value set of the extension factor Z corresponding to PCM1 shown in FIG. 10b is {3, 6, 12, 24, 48, 96, 192, 384}. Therefore, the maximum value of the offset Z corresponding to PCM0 shown in FIG. 10a is 256, and the maximum value of the offset Z corresponding to PCM1 shown in FIG. 10b is 384. Therefore, the same base graph (base graph 1) shown in FIGS. 10a and 10b corresponds to different base matrices, and the maximum values of the offset Z corresponding to different base matrices are not the same, which can meet the performance requirements of different code lengths.

[0138] For convenience of explanation and understanding, the column numbers and the row numbers are shown at the uppermost side and the leftmost side in FIG. 9 and FIGS. 10a and 10b. As shown in FIG. 9, the top row 0 to 67 (i.e., 0 to 67 columns) in FIG. 9 represents the column numbers, and the leftmost column 0 to 45 (i.e., 0 to 45 rows) represents the row numbers. That is, the matrix size of the base graph shown in FIG. 9 is 46 rows and 68 columns. In addition, for the PCM of BG1, since the sub-matrix C and the sub-matrix I are the same, the sub-matrix C and the sub-matrix I are omitted in FIGS. 10a and 10b.

[0139] The LDPC with the Raptor-like structure corresponds to a base graph, different initial transmission code rates correspond to a same high code rate core matrix, and the extension matrix of different initial transmission code rates is obtained based on a same core matrix, which causes the sparsity of the base graph of the medium and low code rate to be small, thereby causing the complexity of channel coding and channel decoding to be large. For example, FIG. 11 and FIG. 12 are BG1 schematic diagrams of 1 / 3 code rate and 1 / 2 code rate respectively. In FIG. 11 and FIG. 12, the black marked positions represent non-zero elements in the corresponding positions of the matrix, and the positions not marked in black represent zero elements in the corresponding positions of the matrix. The base graph in the subsequent application is represented in this way. As shown in FIG. 11 and FIG. 12, the sub-matrix A, the sub-matrix B and the sub-matrix D part in the BG1 under the 1 / 3 code rate and the 1 / 2 code rate are relatively dense (or the sparsity is small), so that the weight of the base graph is large, thereby causing more nodes to be calculated in the coding and decoding, which causes the coding and decoding complexity to be large.

[0140] The scheme provided by the embodiment of the application can be applied to channel coding / decoding between communication devices. The channel coding / decoding between communication devices can include channel coding / decoding between a network device and a terminal device, channel coding / decoding between network devices, and channel coding / decoding between terminal devices. The channel coding / decoding can also be referred to as coding, and the coding can also be described as channel coding and decoding, network coding, outer code, source channel joint coding and decoding. The coding structure can also be referred to as coding, code type and code design, and the coding structure can also be described as concatenated code, hierarchical code, coupled code, outer code, sliding window code, product code and ladder code.

[0141] In the application, the sending information can be understood as that a device sends information to another device, or can also be understood as that a logical module in a device sends information to another logical module. For example, the sending device sending information can be understood as that the sending device sends information to another device (such as a receiving device), or can be understood as that a logical module 1 in the sending device sends information to a logical module 2 in the sending device.

[0142] In the application, the receiving information can be understood as that a device receives information from another device, or can also be understood as that a logical module in a device receives information from another logical module. For example, the receiving device receiving information can be understood as that the receiving device receives information from another device (such as a sending device), or can be understood as that a logical module 1 in the receiving device receives information from a logical module 2 in the receiving device.

[0143] In the present application, "sending information to (for example, a receiving device)" or related illustrations in the drawings can be understood as that the destination of the information is the receiving device. It can include directly or indirectly sending information to the receiving device. In the present application, "receiving information from (for example, a sending device)" or "receiving information from (for example, a sending device)" or "receiving information sent by (for example, a sending device)", or related illustrations in the drawings can be understood as that the source of the information is the sending device, and can include directly or indirectly receiving information from the sending device. The information can be processed between the source and the destination of the information transmission, for example, format change, etc., but the destination can understand the effective information from the source. Similar expressions in the present application can be understood similarly, and will not be repeated here.

[0144] The channel encoding method, the channel decoding method and the apparatus will be further described below with reference to the drawings. It can be understood that the present application is illustrated by taking the sending device and the receiving device as the execution subject of the interactive illustration, but the present application does not limit the execution subject of the interactive illustration. For example, the method executed by the sending device in the present application can also be implemented by a module in the sending device, or a logical node, a logical module or software capable of realizing all or part of the function of the encoding device; the method executed by the receiving device in the present application can also be implemented by a module in the receiving device, or a logical node, a logical module or software capable of realizing all or part of the function of the decoding device. The module in the sending device and / or the receiving device can be, for example, a circuit, a chip or a chip system (such as a modem chip, also known as a baseband chip, or a system on chip SOC chip or a SIP chip containing a modem core). The sending device can be a terminal or a network device, and the receiving device can be a network device or a terminal.

[0145] The present application embodiment proposes a channel encoding method, and FIG. 13 is a flowchart of the channel encoding method. The channel encoding method is described from the perspective of the sending device. The channel encoding method includes but is not limited to the following steps:

[0146] S1301. The sending device performs LDPC encoding on the input bit sequence based on a first base graph containing a first core matrix corresponding to a first initial transmission code rate, to obtain an encoded bit sequence.

[0147] The first base graph is one of N base graphs, and the N base graphs further include a second base graph containing a second core matrix and corresponding to a second initial transmission code rate. N is an integer greater than or equal to 2. The first initial transmission code rate and the second initial transmission code rate are code rates when different input bit sequences are initially transmitted by using LDPC, and the first initial transmission code rate is greater than the second initial transmission code rate. It can be seen that the sending device can also perform LDPC encoding on the input bit sequence based on a second base graph containing a second core matrix corresponding to a second initial transmission code rate, to obtain an encoded bit sequence.

[0148] The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. In one possible manner, the non-zero elements are 1, and the elements in the first base graph and / or the second base graph are 0 and 1. In another possible manner, the non-zero elements include 1 and other numerical values, which can be, for example, 2, 3, 4, and the like. For example, the non-zero elements are 1 and 2, and the elements in the first base graph and / or the second base graph are 0, 1, and 2. In yet another possible manner, the non-zero elements are integers other than 1, for example, the non-zero elements are 2 and 3, and the elements in the first base graph and / or the second base graph are 0, 2, and 3.

[0149] In addition, the number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. In other words, the sizes (dimensions) of the first base graph and the second base graph are equal. As can be seen, the base graphs corresponding to different initial transmission code rates have equal sizes (dimensions).

[0150] In an optional embodiment, the first base graph and the second base graph can be the BG1 described above, or the BG2 described above, or a BG defined in a future communication system, and the embodiments of the present application do not limit this.

[0151] In addition, the first core matrix includes a sub-matrix A1 and a sub-matrix B1, and the second core matrix includes a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2. Among them, A1 is the information bit part of the first core matrix, B1 is the check bit part of the first core matrix, A2 is the information bit part of the second core matrix, and B2 is the check bit part of the second core matrix.

[0152] B1 includes columns with a weight of 3, and a sub-matrix B'1 with a double diagonal structure; B2 includes columns with a weight of 3, and a sub-matrix B'2 with a double diagonal structure. Among them, the "weight" refers to the number of non-zero elements, and B1 and B2 both include columns with a weight of 3, indicating that B1 and B2 both include columns with a number of non-zero elements of 3. B1 includes a sub-matrix B'1 with a double diagonal structure, which can be understood as: B1 includes B'1, and the weight of the columns in B'1 is 2, that is, the number of non-zero elements in each column of B'1 is 2. B2 includes a sub-matrix B'2 with a double diagonal structure, which can be understood as: B2 includes B'2, and the weight of the columns in B'2 is 2, that is, the number of non-zero elements in each column of B'2 is 2.

[0153] In the present application, the "weight" described in relation to the column can also be referred to as "column weight", which refers to the number of non-zero elements in a column of the matrix. The "weight" described in relation to the row can also be referred to as "row weight", which refers to the number of non-zero elements in a row of the matrix.

[0154] In a possible manner, the number of rows of the second core matrix is greater than the number of rows of the first core matrix. In another possible manner, the number of columns of the second core matrix is greater than the number of columns of the first core matrix. In yet another possible manner, the number of rows of the second core matrix is greater than the number of rows of the first core matrix, and the number of columns of the second core matrix is greater than the number of columns of the first core matrix. As can be seen, the smaller the initial transmission code rate of the input bit sequence, the greater at least one of the following of the core matrix: the number of rows or the number of columns, so that the proportion of non-zero elements in the core matrix corresponding to the medium and low code rate can be small, that is, the medium and low code rate can correspond to a core matrix with a large sparsity, or in other words, the medium and low code rate can correspond to a core matrix with a small weight, thereby reducing the number of nodes required for calculation when the sending device performs channel encoding, and reducing the number of nodes required for calculation when the receiving device performs channel decoding, and reducing the complexity of channel encoding and channel decoding.

[0155] In the embodiments of the present application, the medium and low code rate can refer to a code rate with an initial transmission code rate less than a first preset value, and the high code rate can refer to a code rate with an initial transmission code rate greater than or equal to the first preset value, where the first preset value can be previously negotiated or defined by the sending device and the receiving device.

[0156] The embodiments of the first core matrix and the second core matrix are described in detail below through embodiment a and embodiment b:

[0157] Embodiment a: the first core matrix is associated with the first initial transmission code rate, and the second core matrix is associated with the second initial transmission code rate.

[0158] Specifically, the number of rows of the first core matrix is associated with the first initial transmission code rate R1, and the number of rows of the second core matrix is associated with the second initial transmission code rate R2, where R1 and R2 are positive real numbers. The number of rows of the first core matrix is associated with the first initial transmission code rate, which can be understood as: the number of rows of the first core matrix can be determined based on the first initial transmission code rate. Similarly, the number of rows of the second core matrix is associated with the second initial transmission code rate, which can be understood as: the number of rows of the second core matrix can be determined based on the second initial transmission code rate. In other words, the sending device can determine the number of rows of the first core matrix based on the first initial transmission code rate, and can determine the number of rows of the second core matrix based on the second initial transmission code rate.

[0159] In another optional embodiment, the number of rows m core1 of the first core matrix is further associated with at least one of the following: the number of columns k b of A1, the number n prune1 of punctured columns in A1, the number of rows m core2 of the second core matrix is further associated with at least one of the following: the number of columns k b of A2, the number n prune2 of punctured columns in A2, m core1 , m core2 , k b , n prune1and n prune2 are positive integers.

[0160] wherein the column number of A1 and the column number of A2 are equal, and equal to the column number of the system bits. The column number of the punctured columns in A1 can also be understood as: the column number of the punctured columns in the first core matrix, or can also be understood as: the column number of the punctured columns in the first base graph. Similarly, the column number of the punctured columns in A2 can also be understood as: the column number of the punctured columns in the second core matrix, or can also be understood as: the column number of the punctured columns in the second base graph.

[0161] The row number of the first core matrix is also associated with at least one of: the column number of A1, the column number of the punctured columns in A1, and can be understood as: the row number of the first core matrix can also be determined based on at least one of: the column number of A1, the column number of the punctured columns in A1. Similarly, the row number of the second core matrix is also associated with at least one of: the column number of A2, the column number of the punctured columns in A2, and can be understood as: the row number of the second core matrix can also be determined based on at least one of: the column number of A2, the column number of the punctured columns in A2. Or, the sending device can also determine the row number of the first core matrix based on at least one of: the column number of A1, the column number of the punctured columns in A1, and can also determine the row number of the second core matrix based on at least one of: the column number of A2, the column number of the punctured columns in A2.

[0162] In an optional implementation, m core1 and m core2 respectively satisfy:

[0163] wherein, represents the floor.

[0164] It can be seen that the sending device can determine the row number m core1 of the first core matrix based on the relationship between m b , R1, k rune1 and np core1 in formula (3). The sending device can also determine the row number m core2 of the second core matrix based on the relationship between m b , R2, k prune2 and n core2 in formula (4).

[0165] As can be seen from formula (3) and formula (4), the row number of the core matrix is related to the initial transmission code rate of the input bit sequence, and the greater the initial transmission code rate, the smaller the row number of the core matrix, or in other words, the smaller the initial transmission code rate, the greater the row number of the core matrix. Therefore, since the second initial transmission code rate is smaller than the first initial transmission code rate, the row number of the second core matrix is greater than the row number of the first core matrix.

[0166] In addition, the column number n core1the number of columns of B1 is equal to m core1 × m core1 the number of columns of B1 is equal to m core1 the number of columns of the first core matrix n core1 is equal to k b + m core1 so that the number of columns of the first core matrix is associated with the number of columns of A1 and the number of rows of the first core matrix. Similarly, the number of columns of the second core matrix n core2 the number of columns of B2 is equal to m core2 × m core2 the number of columns of B2 is equal to m core2 the number of columns of the second core matrix n core2 is equal to k b + m core2 so that the number of columns of the second core matrix is associated with the number of columns of A2 and the number of rows of the second core matrix. Since m core2 is greater than m core1 , the number of columns of the second core matrix n core2 is greater than the number of columns of the first core matrix n core1 .

[0167] It can be seen that the sending device can determine the number of rows of the first core matrix based on the first initial transmission code rate, so as to determine the number of columns of the first core matrix, and then determine the first core matrix based on the number of rows and columns of the first core matrix. The sending device can determine the number of rows of the second core matrix based on the second initial transmission code rate, so as to determine the number of columns of the second core matrix, and then determine the second core matrix based on the number of rows and columns of the second core matrix. Specifically, the sending device can determine the first core matrix based on the number of rows and columns of the first core matrix through a method of density evolution and computer assistance. The sending device can determine the second core matrix based on the number of rows and columns of the second core matrix through a method of density evolution and computer assistance.

[0168] It can be seen from the above that the number of rows of the first core matrix is associated with the first initial transmission code rate, the number of columns of the first core matrix is associated with the number of rows of the first core matrix, and thus the number of rows and columns of the first core matrix are both associated with the first initial transmission code rate, so that the first core matrix is associated with the first initial transmission code rate. Similarly, the number of rows of the second core matrix is associated with the second initial transmission code rate, the number of columns of the second core matrix is associated with the number of rows of the first core matrix, and thus the number of rows and columns of the second core matrix are both associated with the second initial transmission code rate, so that the second core matrix is associated with the second initial transmission code rate.

[0169] In summary, the smaller the initial transmission code rate of the bit sequence, the larger the number of rows of the core matrix. For example, FIG. 14 is a schematic diagram of the relationship between the initial transmission code rate and the number of rows of the core matrix. As shown in FIG. 14, the smaller the initial transmission code rate of the bit sequence, the larger the number of rows of the core matrix, or in other words, the larger the initial transmission code rate of the bit sequence, the smaller the number of rows of the core matrix. However, in this manner, if the initial transmission code rate is divided too finely, there are too many types of the number of rows of the core matrix, which can correspond to too many types of BGs, and can easily cause waste of storage. Therefore, the sending device can map different code rate intervals to different numbers of rows of the core matrix, so that different code rate intervals can correspond to different BG types, and this manner can save storage resources of the storage matrix. For example, Table 1 is a mapping relationship table of code rate intervals and the number of rows of the core matrix. As shown in Table 1, when the interval of the initial transmission code rate is (0.67, 0.95], the number of rows of the core matrix is 4, and the corresponding BG type is type-A in BG1; when the interval of the initial transmission code rate is (0.5, 0.67], the number of rows of the core matrix is 13, and the corresponding BG type is type-B in BG1; and when the interval of the initial transmission code rate is (0.25, 0.5], the number of rows of the core matrix is 24, and the corresponding BG type is type-C in BG1.

[0170] In addition, the number of rows of the core matrix corresponding to each of the three code rate intervals in Table 1 is equal to the number of rows of the core matrix corresponding to the highest code rate value in the code rate interval. That is, the number of rows of the core matrix corresponding to the initial transmission code rate interval (0.67, 0.95] is equal to the number of rows of the core matrix corresponding to the initial transmission code rate of 0.95, which is 4; the number of rows of the core matrix corresponding to the initial transmission code rate interval (0.5, 0.67] is equal to the number of rows of the core matrix corresponding to the initial transmission code rate of 0.67, which is 13; and the number of rows of the core matrix corresponding to the initial transmission code rate interval (0.25, 0.5] is equal to the number of rows of the core matrix corresponding to the initial transmission code rate of 0.5, which is 24.

[0171] Table 1

[0172] It can be seen that when the initial transmission code rate of the bit sequence belongs to the same code rate interval, the number of rows of the core matrix is equal, and the selected BG type is the same; when the initial transmission code rate of the bit sequence belongs to different code rate intervals, the number of rows of the core matrix is not equal, and the selected BG type is not the same. Compared with the manner in which different initial transmission code rates belonging to the same code rate interval correspond to different numbers of rows of the core matrix, this manner can save storage overhead of the storage matrix.

[0173] In an optional implementation, the first initial transmission code rate and the second initial transmission code rate belong to different code rate intervals, so that the number of rows of the second core matrix corresponding to the second initial transmission code rate is not equal to the number of rows of the first core matrix corresponding to the first initial transmission code rate.

[0174] In an alternative embodiment, the sending device maps different code rate intervals to different numbers of rows of the core matrix, so that different code rate intervals can correspond to different BG types. For example, FIG. 15 is a schematic diagram of a base graph selection strategy. As shown in FIG. 15, the BG1 part, the initial transmission code rate from high to low corresponds to BG1TypeA / B / C… / N respectively. Then, when the sending device selects BG1 for channel coding, different BG1 types can be selected based on the code rate interval in which the initial transmission code rate is located.

[0175] In this embodiment 2, the number of rows of the core matrix is different when the initial transmission code rate is different, so that the core matrix corresponding to different initial transmission code rates is different. Compared with the core matrix of a high code rate in NR, this method is advantageous in making the base graph containing the core matrix have a smaller weight, and thus can reduce the complexity of channel coding and channel decoding.

[0176] For example, taking the number of rows of the core matrix equal to 24 as an example, the BG1 in the new radio (NR) of 5G and the BG1type-C in Table 1 above are compared. FIG. 16 is a schematic diagram of a core matrix. Specifically, FIG. 16 is a schematic diagram of the structure of the 24-row core matrix in BG1type-C in Table 1 above. For NR, the schematic diagram of the structure of the 24-row matrix in BG1 is shown in FIG. 12 above. As shown in FIG. 12, in NR, the matrix structure of BG1 is a typical Raptor-Like structure, and the density of the matrix is relatively dense, so the complexity of channel coding and channel decoding is relatively high. As shown in FIG. 16, the density of the core matrix in BG1Type-C is relatively sparse, so the complexity of channel coding and channel decoding is relatively low. In addition, the check part of the core matrix in FIG. 16 is a double diagonal structure, which can further improve the connectivity of the matrix compared with the single diagonal structure in Raptor-Like.

[0177] In addition, according to a protograph based extrinsic information transfer (PEXIT) threshold analysis, the threshold of the NR BG1 and the BG1 type-C matrix is 0.57 dB and 0.6 dB respectively after 50 iterations, and the thresholds of the two are close, so the BG1 Type-C and the NR BG1 in Table 1 have similar decoding performance. FIG. 17 is a weight comparison diagram. Specifically, FIG. 17 is a weight comparison diagram of the matrix column of the NR BG1 and the BG1 type-C. As shown in FIG. 17, the matrix in the BG1 Type-C has a lower average column weight than the matrix in the NR BG1, and the average column weight of the matrix in the BG1 Type-C is reduced by 26% compared with the matrix in the NR BG1. Therefore, the matrix in the BG1 Type-C of Table 1 can make the channel encoding and channel decoding have lower complexity.

[0178] Embodiment b: the first core matrix is associated with the first initial transmission code rate, and the second core matrix is associated with the second initial transmission code rate and the first core matrix.

[0179] In an optional embodiment, the number of rows of the first core matrix is associated with the first initial transmission code rate R1, and the embodiments can refer to the description of the above-mentioned embodiment a, and will not be repeated here.

[0180] In an optional embodiment, the number of rows m of the first core matrix is core1 is also associated with at least one of the following: the number of columns k of A1 b , the number of punctured columns np of A1 rune1 , and the embodiments can refer to the description of the above-mentioned embodiment a, and will not be repeated here.

[0181] In an optional embodiment, the number of rows m of the first core matrix is core1 satisfies the relationship shown in the above formula (3), and the embodiments can refer to the description of the above-mentioned embodiment a, and will not be repeated here.

[0182] In addition, the number of columns of the first core matrix is equal to the number of columns of A1 plus the number of columns of B1, and the embodiments can refer to the description of the above-mentioned embodiment a, and will not be repeated here.

[0183] It can be seen that the embodiments of the number of rows and columns of the first core matrix in embodiment b are the same as the embodiments of the number of rows and columns of the first core matrix in the above-mentioned embodiment a. Or in other words, in embodiment b, the sending device can determine the number of rows and columns of the first core matrix based on the embodiments of the number of rows and columns of the first core matrix in the above-mentioned embodiment a.

[0184] In an optional implementation, the second core matrix is associated with the second initial transmission code rate and the first core matrix. It can be understood that when the initial transmission code rate of the bit sequence is the second initial transmission code rate, the second core matrix corresponding to the second initial transmission code rate is determined based on the first core matrix. Alternatively, the sending device determines the second core matrix corresponding to the second initial transmission code rate based on the first core matrix corresponding to the first initial transmission code rate when the initial transmission code rate of the bit sequence is the second initial transmission code rate.

[0185] In an optional implementation, the number of rows of the second core matrix is p*m core1 , that is, the number of rows of the second core matrix is p times the number of rows of the first core matrix, and p is an integer greater than or equal to 2. Alternatively, when the second initial transmission code rate is less than the first initial transmission code rate, the sending device can determine the number of rows of the second core matrix corresponding to the second initial transmission code rate as p times the number of rows of the first core matrix corresponding to the first initial transmission code rate. Alternatively, when the second initial transmission code rate is less than the first initial transmission code rate, the sending device can expand the number of rows of the first core matrix corresponding to the first initial transmission code rate by p times to obtain the number of rows of the second core matrix corresponding to the second initial transmission code rate. Wherein, the first initial transmission code rate and the second initial transmission code rate belong to different code rate intervals, or the first initial transmission code rate and the second initial transmission code rate belong to the same code rate interval, which can be pre-divided or determined by the sending device and the receiving device. When the first initial transmission code rate and the second initial transmission code rate belong to different code rate intervals, the number of rows of the core matrix corresponding to different code rate intervals is not equal, which can save storage resources. When the first initial transmission code rate and the second initial transmission code rate belong to the same code rate interval, the number of rows of the core matrix corresponding to different initial transmission code rates is not equal.

[0186] In addition, the non-zero element positions of the p*m core1 th column in the qth m core1 row of A2 are the same as the non-zero element positions of the m core1 th column in the row of A1, p is an integer greater than or equal to 2, and q is an integer greater than or equal to 1 and less than or equal to p. Alternatively, the sending device can copy the non-zero element positions of the m core1 th column in the row of A1 to the qth m core1 th column in the row of A2 to obtain the non-zero element positions of the p*m core1 th column in each row of A2. core1

[0187] The p groups of non-zero elements in the non-punctured column of A1 include the qth group of non-zero elements in the qth m core1 row of the non-punctured column of A2, and the position of the qth group of non-zero elements in the qth m core1 row of A2 is the same as the position of the m core1 th column in the row of A1. core1 ​The positions of the qth group of non-zero elements included in the p*m core1 row of A2 are the same as the positions of the qth group of non-zero elements included in the non-punctured column of A1. core1 row of A2 are the same as the positions of the qth group of non-zero elements included in the non-punctured column of A1.

[0188] It can be seen that the sending device can determine the positions of the non-zero elements of the punctured column of A2 of the second core matrix based on the positions of the non-zero elements of the punctured column of A1 of the first core matrix, and can determine the positions of the non-zero elements of the non-punctured column of A2 of the second core matrix based on the positions of the non-zero elements of the non-punctured column of A1 of the first core matrix. That is, when the initial transmission code rate is the second initial transmission code rate, the sending device can determine the second core matrix corresponding to the second initial transmission code rate based on the first core matrix corresponding to the first initial transmission code rate, so that the second core matrix is associated with the second initial transmission code rate and the first core matrix.

[0189] Optionally, the manner in which the sending device determines the first core matrix based on the second core matrix when the initial transmission code rate is the second code rate can also be regarded as performing row splitting on the first core matrix to obtain the second core matrix, the number of rows of the second core matrix being p times the number of rows of the first core matrix, the p*m core1 row of A2 being the same as the positions of the non-zero elements of the m core1 row of A1. core1 row of A2 being the same as the positions of the non-zero elements of the m core1 row of A2 being the same as the positions of the non-zero elements of the m core1 row of A2 being the same as the positions of the non-zero elements of the m core1 row of A1. core1 row of A1.

[0190] When the second initial transmission code rate is less than the first initial transmission code rate, the manner in which the sending device determines the second core matrix based on the first core matrix and the second initial transmission code rate is compared with the manner in which the second core matrix is directly determined based on the second initial transmission code rate in the above-described embodiment a, the sending device does not need to store core matrices corresponding to multiple different initial transmission code rates, such as the first core matrix corresponding to the first initial transmission code rate which is relatively high in initial transmission code rate, and does not need to store the second core matrix corresponding to the second initial transmission code rate which is relatively low in initial transmission code rate, the second core matrix being obtained by splitting the first core matrix, so that the storage overhead of the sending device in storing the number of matrices can be reduced.

[0191] For example, FIG. 18 and FIG. 19 are structural diagrams of a first core array and a second core array, respectively. As shown in FIG. 18, the size of the first core array is 4x26. As shown in FIG. 19, the size of the second core array is 8x30, i.e., the number of rows of the second core array is twice the number of rows of the first core array. In FIG. 18 and FIG. 19, the positions marked with "☆", "▲", "□" and "○" are positions of non-zero elements, and the positions without marks are positions of zero elements. Among them, the position marked with "☆" in FIG. 18 is the position of a non-zero element of a punctured column of A1 in the first core array, and the position marked with "☆" in FIG. 19 is the position of a non-zero element of a punctured column of A2 in the second core array. The positions marked with "▲" and "□" in FIG. 18 are positions of non-zero elements of non-punctured columns of A1 in the first core array, and the positions marked with "▲" and "□" in FIG. 19 are positions of non-zero elements of non-punctured columns of A2 in the second core array. The position marked with "○" in FIG. 18 is the position of a non-zero element of B1 in the first core array, and the position marked with "○" in FIG. 19 is the position of a non-zero element of B2 in the second core array. The position marked with "▲" in FIG. 18 can be regarded as the position of a first group of non-zero elements of a non-punctured column of A1, and the position marked with "□" can be regarded as the position of a second group of non-zero elements of a punctured column of A1.

[0192] The positions of non-zero elements of punctured columns (the first column and the second column) in the first four rows and the second four rows of the second core array in FIG. 19 are the same as the positions of non-zero elements of punctured columns (the first column and the second column) in the four rows of the first core array in FIG. 18, i.e., the positions of non-zero elements marked with "☆" in the first four rows and the second four rows of the first two columns in FIG. 19 are the same as the positions of non-zero elements marked with "☆" in the first two columns in FIG. 18.

[0193] As shown in FIG. 18 and FIG. 19, the first group of non-zero elements included in the first four rows of non-punctured columns of A2 is the same as the first group of non-zero elements included in the four rows of A1, i.e., the positions of non-zero elements marked with "▲" in the first four rows of non-punctured columns in FIG. 19 are the same as the positions of non-zero elements marked with "▲" in non-punctured columns in FIG. 18. The second group of non-zero elements included in the second four rows of non-punctured columns of A2 is the same as the second group of non-zero elements included in the four rows of A1, i.e., the positions of non-zero elements marked with "□" in the second four rows of non-punctured columns in FIG. 19 are the same as the positions of non-zero elements marked with "□" in non-punctured columns in FIG. 18.

[0194] In addition, B1 in FIG. 18 includes a column with a weight of 3 and a sub-matrix with a weight of 2. B2 in FIG. 19 includes a column with a weight of 3 and a sub-matrix with a weight of 2.

[0195] Referring to Table 2, Table 2 is a threshold comparison table of the NR BG1 and the core array in FIG. 19. As shown in Table 2, the threshold of the NR BG1 and the core array in FIG. 19 under 5 iterations, and the threshold of the NR BG1 and the core array in FIG. 19 under 20 iterations are close, thus the core array in FIG. 19 and the NR BG1 have similar decoding performance.

[0196] Table 2

[0197] Referring to FIG. 20, FIG. 20 is another weight comparison diagram. Specifically, FIG. 20 is a weight comparison diagram of the NR BG1 and the core array in FIG. 19. As shown in FIG. 20, the core array in FIG. 19 has a lower average column weight than the NR BG1, and the average column weight of the core array in FIG. 19 is reduced by about 10% compared with the NR BG1. Thus, the core array in FIG. 19 can make the channel encoding and channel decoding have a lower complexity.

[0198] For example, FIG. 21 and FIG. 22 are structural diagrams of a first core array and a second core array, respectively. As shown in FIG. 21, the size of the first core array is 4x26. As shown in FIG. 22, the size of the second core array is 12x34, that is, the number of rows of the second core array is twice the number of rows of the first core array. The first core array shown in FIG. 21 has the same size as the first core array shown in FIG. 18, and the positions of the non-zero elements in the first core array are the same, and the difference is that the positions of the non-zero elements of the non-punctured columns in A1 in FIG. 21 are marked as three groups of non-zero element positions, that is, the non-punctured columns in A1 in FIG. 21 include three groups of non-zero elements. Among them, the positions marked with "▲" in FIG. 21 can be regarded as the positions of the first group of non-zero elements of the non-punctured columns in A1, the positions marked with "□" can be regarded as the positions of the second group of non-zero elements of the non-punctured columns in A1, the positions marked with "■" can be regarded as the positions of the third group of non-zero elements of the non-punctured columns in A1.

[0199] The positions of the non-zero elements of the punctured columns (the first column and the second column) in the first 4 rows, the second 4 rows and the third 4 rows of the second core array in FIG. 22 are the same as the positions of the non-zero elements of the punctured columns (the first column and the second column) in the first core array in FIG. 21, that is, the positions of the non-zero elements marked with "☆" in the first 4 rows, the second 4 rows and the third 4 rows of the first two columns in FIG. 22 are the same as the positions of the non-zero elements marked with "☆" in the first two columns in FIG. 21.

[0200] As shown in FIG. 21 and FIG. 22, the position of the first group of non-zero elements included in the first 4 rows of the non-punctured columns in A2 is the same as the position of the first group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "A" in the first 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "A" in the non-punctured columns in FIG. 21. The position of the second group of non-zero elements included in the second 4 rows of the non-punctured columns in A2 is the same as the position of the second group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "B" in the second 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "B" in the non-punctured columns in FIG. 21. The position of the third group of non-zero elements included in the third 4 rows of the non-punctured columns in A2 is the same as the position of the third group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "C" in the third 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "C" in the non-punctured columns in FIG. 21. As shown in FIG. 21 and FIG. 22, the position of the first group of non-zero elements included in the first 4 rows of the non-punctured columns in A2 is the same as the position of the first group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "A" in the first 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "A" in the non-punctured columns in FIG. 21. The position of the second group of non-zero elements included in the second 4 rows of the non-punctured columns in A2 is the same as the position of the second group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "B" in the second 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "B" in the non-punctured columns in FIG. 21. The position of the third group of non-zero elements included in the third 4 rows of the non-punctured columns in A2 is the same as the position of the third group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "C" in the third 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "C" in the non-punctured columns in FIG. 21. As shown in FIG. 21 and FIG. 22, the position of the first group of non-zero elements included in the first 4 rows of the non-punctured columns in A2 is the same as the position of the first group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "A" in the first 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "A" in the non-punctured columns in FIG. 21. The position of the second group of non-zero elements included in the second 4 rows of the non-punctured columns in A2 is the same as the position of the second group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "B" in the second 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "B" in the non-punctured columns in FIG. 21. The position of the third group of non-zero elements included in the third 4 rows of the non-punctured columns in A2 is the same as the position of the third group of non-zero elements included in the 4 rows of Al, i.e., the position of the non-zero elements marked by "C" in the third 4 rows of the non-punctured columns in FIG. 22 is the same as the position of the non-zero elements marked by "C" in the non-punctured columns in FIG. 21.

[0201] In addition, B1 in FIG. 21 includes columns with weight 3 and sub-matrices with weight 2. B2 in FIG. 22 includes columns with weight 3 and sub-matrices with weight 2.

[0202] Please refer to Table 3, which is a table of threshold values of NR BG1 and the core matrix in FIG. 22. As shown in Table 3, the threshold values of NR BG1 and the core matrix in FIG. 26 after 5 iterations and the threshold values of NR BG1 and the core matrix in FIG. 22 after 20 iterations are close to each other, so the matrix in FIG. 22 and NR BG1 have similar decoding performance.

[0203] Table 3

[0204] Please refer to FIG. 23, which is another weight comparison diagram. Specifically, FIG. 23 is a weight comparison diagram of NR BG1 and the core matrix in FIG. 22. As shown in FIG. 23, the core matrix in FIG. 22 has a lower average column weight than NR BG1, and the average column weight of the core matrix in FIG. 22 is reduced by about 30% compared with NR BG1. Therefore, the core matrix in FIG. 22 can make the channel encoding and channel decoding have lower complexity.

[0205] It is evident that the first core array and the second core array can be determined through the above implementation methods a and b. Regardless of which implementation method is used to determine the first core array and the second core array, when the second initial transmission code rate is less than the first initial transmission code rate, the number of rows in the second core array is greater than the number of rows in the first core array, and the number of columns in the second core array is greater than the number of columns in the first core array. That is, the size (dimension) of the second core array is greater than the size (dimension) of the first core array. This allows the initial transmission code rate of medium and low code rates to have a core array with greater sparsity, and thus the initial transmission code rate of medium and low code rates to have a base map with greater sparsity, which can reduce the complexity of channel coding and channel decoding.

[0206] Furthermore, if the number of information bits varies in different core matrices corresponding to different code rates, the code block segmentation and the selection of the boost factor become more complex. However, if the number of columns A1 in the first core matrix is ​​equal to the number of columns A2 in the second core matrix, meaning the number of information bits in both matrices remains unchanged, the columns of the parity check matrices corresponding to the first and second core matrices will not change. This simplifies code block segmentation and improves the selection and matching rate process.

[0207] Optionally, the first core array may be determined based on the first initial transmission code rate and other implementation methods, and the second core array may be determined based on the second initial transmission code rate and other implementation methods. This application embodiment does not limit this.

[0208] In addition, the transmitting device can also determine a first base map containing a first core array corresponding to a first initial transmission code rate, and determine a second base map containing a second core array corresponding to a second initial transmission code rate.

[0209] In one optional implementation, the number of columns n1 of the first base map is related to the mother code rate R. m1 The number of columns k in A1 b And the number of columns n of the punched columns in A1 prune1 Correspondingly, the number of columns n2 in the second base map is related to the code rate R of the mother code. m2 The number of columns k in A2 b And the number of columns n of the punched columns in A2 prune2 The number of columns n1 in the first base map is related to the mother code rate R. m1 The number of columns k in A1 b And the number of columns n of the punched columns in A1 prune1 Related, can be understood as: the number of columns n1 in the first base graph can be based on R m1 k b and n prune1 Certainly. Or rather, the transmitting device can be based on R. m1 k b and n prune1 Determine the number of columns n1 of the first base map. The number of columns n2 of the second base map is related to the code rate R of the mother code.m2 , the number of columns k of A2 b , the number of columns n of punctured columns in A2 prune2 , and A2 are associated with similar understanding, and will not be described again.

[0210] In an optional embodiment, the number of columns n1 of the first base graph satisfies: The number of columns n2 of the second base graph satisfies: In other words, the sending device can determine the number of columns n1 of the first base graph based on the above relationship satisfied between n1 and R m1 , k b , and n prune1 ; and can determine the number of columns n2 of the second base graph based on the above relationship satisfied between n2 and R m2 , k b , and n prune2 .

[0211] Optionally, the number of columns n prune1 of punctured columns in A1 is equal to the number of columns n prune2 of punctured columns in A2, the mother code rate R m1 is equal to the mother code rate R m2 , and the number of columns n1 of the first base graph is equal to the number of columns n2 of the second base graph.

[0212] Optionally, the number of columns n prune1 of punctured columns in A1 is not equal to the number of columns n prune2 of punctured columns in A2, the mother code rate R m1 is not equal to the mother code rate R m2 , but the number of columns n1 of the first base graph is still equal to the number of columns n2 of the second base graph.

[0213] In an optional embodiment, the number of rows m1 of the first base graph satisfies: m1 = n1 - k b , and the number of rows m1 of the second base graph satisfies: m2 = n2 - k b . In other words, the sending device can determine the number of rows m1 of the first base graph based on the above relationship satisfied between m1 and n1 and k b , and can determine the number of rows m2 of the second base graph based on the above relationship satisfied between m2 and n2 and k b . Since n1 is equal to n2, the number of rows m1 of the first base graph is equal to the number of rows m2 of the second base graph.

[0214] It can be seen that the number of rows m1 of the first base graph is equal to the number of rows m2 of the second base graph, and the number of columns n1 of the first base graph is equal to the number of columns n2 of the second base graph. That is, when the initial transmission code rates are different, the number of rows and the number of columns of the base graphs corresponding to different initial transmission code rates are equal. For ease of description, the number of rows of the first base graph and the number of rows of the second base graph are both m, and the number of columns of the first base graph and the number of columns of the second base graph are both n.

[0215] Optionally, the sending device can determine the first base graph containing the first core matrix based on the number of rows and the number of columns of the first base graph, and determine the second base graph containing the second core matrix based on the number of rows and the number of columns of the second base graph.

[0216] Optionally, the first base graph further includes a sub-matrix D1, and the second base graph further includes a sub-matrix D2. The D1 and D2 are information bit parts of the first extended matrix in the first base graph. The number of rows of the D1 is determined based on the number of rows of the first base graph and the number of rows of the first core matrix, the number of columns of the D1 is determined based on the number of columns of the first base graph and the number of columns of the first core matrix, the number of rows of the D2 is determined based on the number of rows of the second base graph and the number of rows of the second core matrix, and the number of columns of the D2 is determined based on the number of columns of the second base graph and the number of columns of the second core matrix. Alternatively, the sending device can determine the number of rows of the D1 based on the number of rows of the first base graph and the number of rows of the first core matrix, determine the number of columns of the D1 based on the number of columns of the first base graph and the number of columns of the first core matrix, determine the number of rows of the D2 based on the number of rows of the second base graph and the number of rows of the second core matrix, and determine the number of columns of the D2 based on the number of columns of the second base graph and the number of columns of the second core matrix.

[0217] Specifically, the number of rows of the D1 in the first base graph is equal to the number of rows of the first base graph minus the number of rows of the first core matrix, and the number of columns of the D1 is equal to the number of columns of the first core matrix. That is, the number of rows m ext1 and the number of columns n ext1 of the D1 satisfy: m ext1 = m-m core1 , and n ext1 = n core1 .

[0218] Similarly, the number of rows of the D2 in the second base graph is equal to the number of rows of the second base graph minus the number of rows of the second core matrix, and the number of columns of the D2 is equal to the number of columns of the second core matrix. That is, the number of rows m ext2 and the number of columns n ext2 of the D2 satisfy: m ext2 = m-m core2 , and n ext2 = n core2 .

[0219] Optionally, the first base graph further includes a sub-matrix C1, and the second base graph further includes a sub-matrix C2, and the C1 and C2 are all-zero matrices. The number of rows of the C1 is equal to the number of rows of the first core matrix, the number of columns of the C1 is equal to the number of columns of the first extended matrix, the number of rows of the C2 is equal to the number of rows of the second core matrix, and the number of columns of the C2 is equal to the number of columns of the second extended matrix.

[0220] Optionally, the first base graph further comprises a sub-matrix I1, and the second base graph further comprises a sub-matrix I1. Wherein, I1 and I1 are check bit parts of the first extension matrix in the first base graph. The row number and the column number of I1 are equal to the row number of D1, and the row number and the column number of I2 are equal to the row number of D2.

[0221] For example, referring to FIG. 24, which is a structural diagram of a first base graph. The first base graph in FIG. 24 comprises a first core matrix, which comprises a sub-matrix A1 and a sub-matrix B1, and further comprises a sub-matrix C1, a sub-matrix D1 and a sub-matrix I1. Wherein, C1 is a full zero matrix, D1 is an information bit part of the first extension matrix, and I1 is a check bit part of the first extension matrix.

[0222] It can be seen that the sending device can determine the first base graph comprising the first core matrix based on the first initial transmission code rate, so as to perform retransmission on the input bit sequence based on the first base graph. Optionally, the sending device can also determine the first base graph comprising the second core matrix based on the second initial transmission code rate, so as to perform retransmission on the input bit sequence based on the second base graph.

[0223] In summary, the second initial transmission code rate is less than the first initial transmission code rate. Whether the second core matrix is determined based on the second initial transmission code rate or the first core matrix, the row number of the second core matrix is greater than the row number of the first core matrix, and the column number of the second core matrix is greater than the column number of the first core matrix. The row number of the second base graph is equal to the row number of the first base graph, and the column number of the second base graph is equal to the column number of the first base graph. For example, FIG. 25 and FIG. 26 are structural diagrams of a first base graph and a second base graph respectively. The row number of the first base graph shown in FIG. 25 is equal to the row number of the second base graph shown in FIG. 26, and the column number of the first base graph shown in FIG. 25 is equal to the column number of the second base graph shown in FIG. 26. In addition, in FIG. 25 and FIG. 26, I element represents a non-zero element, such as element 1; and A element represents a cyclic shift matrix of a unit matrix.

[0224] In an optional implementation, the sending device performs LDPC encoding on the input bit sequence based on the first base graph comprising the first core matrix corresponding to the first initial transmission code rate to obtain the encoded bit sequence, comprising: performing LDPC encoding on the input bit sequence by using the first core matrix in the first base graph to obtain the encoded bit sequence.

[0225] Specifically, when the first initial transmission code rate is equal to the highest initial transmission code rate value in the initial transmission code rate interval, the sending device performs LDPC encoding on the input bit sequence based on the first base graph, and actually uses the first core matrix in the first base graph, that is, performs LDPC encoding on the input bit sequence based on the first core matrix in the first base graph. For example, when the first initial transmission code rate is equal to 0.95 in Table 1 above, the sending device performs LDPC encoding on the input bit sequence based on the first base graph to obtain the encoded bit sequence, including: performing LDPC encoding on the input bit sequence using the first core matrix in the first base graph to obtain the encoded bit sequence.

[0226] In another optional implementation, the sending device performs LDPC encoding on the input bit sequence based on the first base graph corresponding to the first initial transmission code rate to obtain the encoded bit sequence, including: performing LDPC encoding on the input bit sequence using the first core matrix and the extended part in the first base graph to obtain the encoded bit sequence. The extended part in the first base graph is obtained by extending the first core matrix by Δm rows and Δn columns.

[0227] Specifically, when the first initial transmission code rate is less than the highest initial transmission code rate value in the initial transmission code rate interval, the sending device performs LDPC encoding on the input bit sequence based on the first base graph, and actually uses the first core matrix in the first base graph and the extended part extended based on the first core matrix. For example, FIG. 27 is a structure diagram of a first base graph. Specifically, FIG. 27 is a first base graph corresponding to an initial transmission code rate interval of (0.67, 0.95], and the core matrix in the first base graph is the core matrix when the initial transmission code rate is 0.95. Then, when the first initial transmission code rate is 0.9, the first core matrix is still as shown in the first core matrix in FIG. 27. However, since the first initial transmission code rate belongs to the interval (0.67, 0.95] and is less than 0.95, when the sending device performs LDPC encoding on the input bit sequence based on the first base graph, it actually not only uses the first core matrix, but also uses the extended part in the black and bold implementation frame in FIG. 27, which is obtained by extending the lower right corner of the first core matrix in FIG. 27 by Δm rows and extending the lower right corner of the first core matrix in FIG. 27 by Δn columns, Δm = Δn = 4.

[0228] In another alternative embodiment, the sending device encodes the input bit sequence based on the first base graph corresponding to the first initial code rate, to obtain the encoded bit sequence, including: encoding the input bit sequence based on all the matrices of the first base graph to obtain the encoded bit sequence. That is, the base graph used by the sending device to encode the input bit sequence based on the first base graph is the first base graph itself. This embodiment is applicable to the scenario where the first initial code rate is equal to the highest code rate of the initial code rate interval, and is also applicable to the scenario where the first initial code rate is less than the highest code rate of the initial code rate interval, i.e., this embodiment is applicable to the scenario where the first initial code rate is any value.

[0229] In a possible manner, when the base graph used by the sending device to encode the input bit sequence based on the first base graph is the first base graph itself, the sending device can further puncture the encoded bit sequence to obtain a punctured bit sequence. When the first initial code rate is equal to the highest code rate of the initial code rate interval, the first core matrix in the first base graph should actually be used by the sending device to encode the input bit sequence. Therefore, the encoded bit sequence obtained by the sending device based on the first base graph itself includes redundant parts, which are obtained by the sending device based on the remaining part of the first base graph other than the first core matrix. Therefore, the sending device needs to puncture and remove the redundant parts in the encoded bit sequence to ensure that the output bit sequence is a correctly encoded bit sequence.

[0230] When the first initial code rate is less than the highest code rate of the initial code rate interval, the first core matrix plus the extension part in the first base graph should actually be used by the sending device to encode the input bit sequence. Therefore, the encoded bit sequence obtained by the sending device based on the first base graph itself includes redundant parts, which are obtained by the sending device based on the part of the first base graph other than the first core matrix and the extension part. Therefore, the sending device needs to puncture and remove the redundant parts in the encoded bit sequence to ensure that the output bit sequence is a correctly encoded bit sequence.

[0231] It can be seen that when the sending device LDPC encodes the input bits based on the first base graph, the first core matrix in the first base graph can be actually used, or the first core matrix in the first base graph plus the extended part obtained based on the first core matrix, or the first base graph itself can be used. Whether the sending device specifically uses the first core matrix in the first base graph or the first core matrix in the first base graph and the extended part obtained based on the first core matrix to LDPC encode the input bit sequence can be determined based on the first initial transmission code rate. In addition, regardless of the value of the first initial transmission code rate, the sending device can use the first base graph itself to LDPC encode the input bit sequence, and puncture the encoded bit sequence to obtain the output bit sequence.

[0232] It should be noted that, regardless of whether the sending device uses the first core matrix in the first base graph to LDPC encode the input bit sequence, or uses the first core matrix in the first base graph and the extended part obtained based on the first core matrix to LDPC encode the input bit sequence, or uses the first base graph itself to LDPC encode the input bit sequence, the detailed process of LDPC encoding can be referred to the above LDPC encoding, and will not be repeated here.

[0233] Optionally, when the sending device LDPC encodes the input bits using the first core matrix in the first base graph, the corresponding base matrix is determined based on the first core matrix, and then the parity check matrix H is determined based on the base matrix and the offset value, and then the input bit sequence is LDPC encoded based on the parity check matrix H. Optionally, when the sending device LDPC encodes the input bit sequence using the first core matrix in the first base graph and the extended part obtained based on the first core matrix, the corresponding base matrix is determined based on the first core matrix and the extended part obtained based on the first core matrix, and then the parity check matrix H is determined based on the base matrix and the offset value, and then the input bit sequence is LDPC encoded based on the parity check matrix H. Optionally, when the sending device uses the first base graph itself to LDPC encode the input bit sequence, the sending device determines the corresponding base matrix based on the first base graph, and then determines the parity check matrix H based on the base matrix and the offset value, and then LDPC encodes the input bit sequence based on the parity check matrix H.

[0234] In an optional implementation, after the sending device obtains the encoded bit sequence, the sending device can sequentially perform the following operations on the encoded bit sequence to obtain the signal to be transmitted over the air: modulation, layer mapping, precoding, framing, inverse fast Fourier transform (IFFT), and intermediate and radio frequency (IRF).

[0235] Optionally, the sending device further sends a first signal, the first signal being a signal processed by the sending device on the input bit sequence through LDPC encoding, modulation, layer mapping, precoding, framing, IFFT and IRF.

[0236] It can be seen that, in the embodiments of the present application, the second initial transmission code rate is smaller than the first initial transmission code rate, the number of rows of the second core matrix corresponding to the second initial transmission code rate is equal to the number of rows of the first core matrix corresponding to the first initial transmission code rate, and the size of the second base graph including the second core matrix corresponding to the second initial transmission code rate is equal to the size of the first base graph including the first core matrix corresponding to the first initial transmission code rate. Then, different initial transmission code rates do not need to share one core matrix, and the smaller the initial transmission code rate is, the greater the number of rows of the core matrix is. The base graphs to which different core matrices belong have the same number of rows and columns, which can make the proportion of non-zero elements in the core matrix with a smaller initial transmission code rate smaller, that is, make the core matrix with a smaller initial transmission code rate have a greater sparsity, so as to reduce the sparsity of the base graph, and further reduce the complexity of channel encoding and channel decoding.

[0237] The embodiments of the present application also propose a channel decoding method, and FIG. 28 is a flow diagram of the channel decoding method. The channel decoding method is described from the perspective of a receiving device. The channel decoding method includes but is not limited to the following steps:

[0238] S2801. The receiving device performs LDPC decoding on the input bit sequence based on a first base graph including a first core matrix corresponding to a first initial transmission code rate, to obtain a decoded bit sequence.

[0239] The first base graph is one of N base graphs, the N base graphs further include a second base graph, the second base graph includes a second core matrix and corresponds to a second initial transmission code rate, and N is an integer greater than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. The second initial transmission code rate is smaller than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The first core matrix includes a sub-matrix A1 and a sub-matrix B1, the second core matrix includes a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2. B1 includes columns with a weight of 3 and a sub-matrix B'1 of a double-diagonal structure. B2 includes columns with a weight of 3 and a sub-matrix B'2 of a double-diagonal structure.

[0240] In addition, the implementation of the first initial transmission code rate, the second initial transmission code rate, the first core matrix, the third core matrix, the first base graph and the second base graph in the embodiments of the present application can refer to the description in the channel encoding method, and will not be repeated here.

[0241] In the embodiments of the present application, the receiving device performs LDPC decoding on the input bit sequence based on the first base graph containing the first core matrix corresponding to the first initial transmission code rate. The implementation of the transmitting device performing LDPC encoding on the input bit sequence based on the first base graph containing the first core matrix corresponding to the first initial transmission code rate in the channel encoding method described above will not be repeated.

[0242] For example, when the transmitting device performs LDPC encoding on the input bit sequence using the first core matrix in the first base graph, the receiving device correspondingly performs LDPC decoding on the input bit sequence using the first core matrix in the first base graph. For another example, when the transmitting device performs LDPC encoding on the input bit sequence using the first core matrix and the extension part in the first base graph, the receiving device correspondingly performs LDPC decoding on the input bit sequence using the first core matrix and the extension part in the first base graph. For another example, when the transmitting device performs LDPC encoding on the input bit sequence using all the matrices in the first base graph, the receiving device correspondingly performs LDPC decoding on the input bit sequence using all the matrices in the first base graph.

[0243] In an optional implementation, before the receiving device performs LDPC decoding on the input bit sequence based on the first base graph containing the first core matrix corresponding to the first initial transmission code rate, the receiving device further receives the first signal from the transmitting device, and sequentially performs the following operations on the first signal to obtain the input bit sequence: IRF, fast Fourier transform (FFT), de-framing, equalization, de-layer mapping, and demodulation.

[0244] The following is an example of the selection process of a BG, taking the determination of the number of rows of the core matrix according to the initial transmission code rate in the above embodiment a as an example. Referring to FIG. 29, FIG. 29 is a schematic diagram of a base graph selection process. As shown in FIG. 29, the process of selecting a BG includes: determining to select BG1 or BG2 according to the size of the transport block and the initial transmission code rate; if it is determined to select BG1, determining the number of rows of the core matrix according to the initial transmission code rate, that is, determining the type of BG1; and reading the matrix corresponding to the type of BG1 from the storage unit. In addition, if BG2 is selected, the matrix corresponding to BG2 is directly read from the storage unit.

[0245] The following is an example of a BG reading process using the low-rate core matrix obtained by row splitting of the high-rate core matrix in the above embodiment b. Referring to FIG. 30, which is a schematic diagram of a base graph reading process. As shown in FIG. 30, the storage unit stores the extension matrices of BG1 at different rates, the core matrix of BG1 at a high rate, and the matrix of BG2. The storage unit also includes a row splitting unit and a matrix merging unit. The row splitting unit can perform row splitting on the core matrix of BG1 at a high rate to obtain a low-rate core matrix, and the matrix merging unit can merge the low-rate core matrix obtained by the row splitting unit and the low-rate extension matrix to obtain a merged matrix, and output the merged matrix. Thus, when the BG selection result is BG2, the output result is the matrix of BG2; and when the BG selection result is BG1, the output result is the merged matrix output by the matrix merging unit. In this way, the storage unit stores the core matrix of BG1 at a high rate and the extension matrices corresponding to different rates, and after reading the core matrix of BG1 at a high rate from the storage unit, the entire matrix can be restored according to the row splitting manner, so that the restored matrix can be used for LDPC encoding.

[0246] It can be seen that, in the embodiments of the present application, the second initial transmission rate is less than the first initial transmission rate, the number of rows of the second core matrix corresponding to the second initial transmission rate is equal to the number of rows of the first core matrix corresponding to the first initial transmission rate, and the size of the second base graph including the second core matrix corresponding to the second initial transmission rate is equal to the size of the first base graph including the first core matrix corresponding to the first initial transmission rate. Then, different initial transmission rates do not need to share a core matrix, and the smaller the initial transmission rate, the greater the number of rows of the core matrix, and the base graphs to which different core matrices belong have the same number of rows and columns, which can make the proportion of non-zero elements in the core matrix with a smaller initial transmission rate smaller, that is, the core matrix with a smaller initial transmission rate can have a larger sparsity, so as to reduce the sparsity of the base graph, and further reduce the complexity of channel decoding.

[0247] In addition, FIG. 31 is a schematic diagram of a communication system 3100 to which embodiments of the present application can be applied. As shown in FIG. 31, on the transmitting device 310 side, information data is subjected to operations such as cyclic redundancy check (CRC) calculation, code block segmentation, channel coding, rate matching, interleaving, and modulation, and the processed information data is transmitted. On the receiving device 320 side, information is received, and the received information data is subjected to operations such as demodulation, deinterleaving, de-rate matching, channel decoding, code block merging, and transport block CRC, and the processed information data is obtained. The processing on the transmitting device side can be performed by, for example, a transmitting device, a module (for example, a circuit, a chip, or a chip system (such as a modem chip, or an SoC chip or an SIP chip including a modem core, and the like), or a logical node, a logical module, or software capable of realizing all or part of the encoding apparatus) in the transmitting device. The processing on the receiving device side can be performed by, for example, a receiving device, a module (for example, a circuit, a chip, or a chip system (such as a modem chip, or an SoC chip or an SIP chip including a modem core, and the like), or a logical node, a logical module, or software capable of realizing all or part of the receiving device) in the receiving device.

[0248] The transmitting device side can perform corresponding encoding according to the structure of the base graph provided by the embodiments of the present application, such as LDPC encoding according to the structure of the first base graph in the present application. The receiving device side can perform corresponding decoding according to the structure of the base graph provided by the embodiments of the present application, such as LDPC decoding according to the structure of the first base graph in the present application. The encoding and / or decoding in the present application can be realized in the form of hardware, software, or a combination of hardware and software. In the case of a large demand for the throughput of encoding / decoding, a hardware accelerator (HAC) can be used for realization.

[0249] For the technical solutions described above, the corresponding device implementation solutions are further described below.

[0250] In order to implement the functions in the methods provided by the embodiments of the present application, the terminal-side device and the network-side device can include hardware structures and / or software modules, and the above functions can be implemented in the form of hardware structures, software modules, or hardware structures plus software modules. Whether a certain function in the above functions is implemented in the form of hardware structure, software module, or hardware structure plus software module depends on specific application and design constraints of the technical solutions.

[0251] Figure 32 illustrates a possible exemplary block diagram of the communication device involved in the embodiments of this application. As shown in Figure 32, the communication device 3200 may include modules or units for implementing the method embodiments described above. In one possible design, the communication device 3200 includes a communication unit 3201 and a processing unit 3202. Optionally, the communication device 3200 may further include a storage unit 3203 for storing device program code and / or data.

[0252] The communication device 3200 can be the transmitting device in the above embodiments, for example, the transmitting device or the communication module in the transmitting device, or the circuit or chip in the transmitting device responsible for the communication function.

[0253] For example, in one embodiment, the processing unit 3202 is used to: perform low-density parity-check code (LDPC) encoding on the input bit sequence based on a first base map containing a first core array corresponding to a first initial transmission code rate, to obtain the encoded bit sequence.

[0254] Wherein, the first base map is one of N base maps, and the N base maps also include a second base map, the second base map containing a second core matrix and corresponding to a second initial transmission code rate, and N is an integer greater than or equal to 2; the elements in the first base map are zero elements and non-zero elements, and the elements in the second base map are also zero elements and non-zero elements; the number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map; the second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix; the first core matrix includes submatrix A1 and submatrix B1, and the second core matrix includes submatrix A2 and submatrix B2, the number of columns in A1 is equal to the number of columns in A2; B1 includes columns with a weight of 3, and a submatrix B′1 with a double diagonal structure; B2 includes columns with a weight of 3, and a submatrix B′2 with a double diagonal structure.

[0255] In one possible design, the number of rows of the first core array is associated with the first initial transmission rate R1; the number of rows of the second core array is associated with the second initial transmission rate R2; wherein R1 and R2 are both positive real numbers.

[0256] In one possible design, the first core array has m rows. core1 It is also associated with at least one of the following: the number of columns k of A1. b The number of columns n of the punched columns in A1 prune1 The number of rows m of the second core array core2 It is also associated with at least one of the following: the number of columns k of A2. b The number of columns n of the punched columns in A2 prune2 The mcore1 The m core2 The k b The n prune1 and the n prune2 All are integers greater than or equal to 0.

[0257] In one possible design, the m core1 satisfy: The m core2 satisfy: in, This indicates rounding down to the nearest integer.

[0258] In another possible design, the first core array has m rows. core1 The second core array has p*m rows. core1 The p*m of A2 core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched hole, and the m of A1. core1 The non-zero elements in the row and column with punched holes are in the same position; the non-punched column in A1 includes p groups of non-zero elements, and the q-th m-th element in the non-punched column in A2... core1 The row includes the q-th non-zero element from the p-th non-zero element group, and the p*m of A2 core1 The qth m in the row core1 The position of the qth non-zero element included in the row, and the m of A1 core1 The positions of the non-zero elements in the q-th group included in the row are the same; the m core1 q is a positive integer, where p is an integer greater than or equal to 2, and q is an integer greater than or equal to 1 and less than or equal to p.

[0259] In one possible design, the first initial transmission bit rate and the second initial transmission bit rate belong to different bit rate ranges.

[0260] In one possible design, when the communication device 3200 is a transmitting device or a communication module within a transmitting device, the function of the processing unit 3202 can be implemented by one or more processors. Specifically, the processor may include a modem chip, or a system-on-a-chip (SoC) chip or a SIP chip containing a modem core. The function of the communication unit 3201 can be implemented by transceiver circuitry.

[0261] In a possible design, when the communication apparatus 3200 is a circuit or a chip responsible for communication functions in a sending apparatus, such as a modem chip or a system on chip (SoC) chip or a SIP chip including a modem core, the function of the processing unit 3202 can be implemented by circuitry including one or more processors or processor cores in the chip. The function of the communication unit 3201 can be implemented by interface circuitry or data transceiver circuitry on the chip.

[0262] The communication apparatus 3200 can be a receiving apparatus in the above-described embodiments, for example, a receiving apparatus or a communication module in a receiving apparatus, or a circuit or a chip responsible for communication functions in a receiving apparatus.

[0263] For example, in an embodiment, the processing unit 3202 is configured to perform low-density parity-check code (LDPC) decoding on the input bit sequence based on a first base graph including a first core matrix corresponding to a first initial transmission code rate, to obtain a decoded bit sequence.

[0264] The first base graph is one of N base graphs, and the N base graphs further include a second base graph including a second core matrix corresponding to a second initial transmission code rate. N is an integer greater than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix. The first core matrix includes a sub-matrix A1 and a sub-matrix B1, and the second core matrix includes a sub-matrix A2 and a sub-matrix B2. The number of columns of A1 is equal to the number of columns of A2. B1 includes columns with a weight of 3 and a sub-matrix B'1 of a double-diagonal structure. B2 includes columns with a weight of 3 and a sub-matrix B'2 of a double-diagonal structure.

[0265] It can be understood that the division of units in the above-described apparatus is merely a logical division of functions, and one function unit can correspond to one function, or two or more functions can be integrated into one function unit. In actual implementation, all or part of the units can be integrated into one physical entity, or distributed on different physical entities. In addition, the function units can be implemented in the form of hardware, in the form of software, or in the form of a combination of hardware and software.

[0266] In one example, the functional units in any of the above apparatuses can be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (ASICs), or, one or more central processing units (CPUs), one or more microcontroller units (MCUs), one or more digital signal processors (DSPs), or, one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0267] In one example, the storage unit 3203 can include random access memory, flash memory, read only memory, programmable read only memory, electrically programmable read only memory and / or registers, etc.

[0268] Referring to FIG. 33, a structure diagram of a terminal 3300 is provided according to an embodiment of the present application. The terminal 3300 can correspond to the terminal shown in FIG. 1, and can be used to implement the operations of the transmitting apparatus or the receiving apparatus in the above embodiments. As shown in FIG. 33, the terminal includes one or more antennas 3310, a radio frequency processing system 3320, and a processor system 3330.

[0269] In the downlink or sidelink direction, the radio frequency processing system 3320 receives radio frequency signals through the antenna 3310, and sends the signals after radio frequency processing to the processor system 3330 for further processing. In the uplink or sidelink direction, the processor system 3330 performs signal processing on the information at the terminal side, and sends the signal to the radio frequency processing system 3320. The radio frequency processing system 3320 performs radio frequency processing on the signal, and transmits the signal through the antenna 3310.

[0270] In one example, the radio frequency processing system 3320, which serves as a communication interface for the terminal to communicate with outside, can include a radio frequency front end 3321 (RFFE) and a radio frequency transceiver 3322 (RF transceiver). The RFFE 3321 is mainly used for one or more of shaping, passband selection, or gain processing of RF signals received by an antenna or to be transmitted through an antenna, and can include one or more of radio frequency switches, duplexers, filters, power amplifiers, antenna tuning, and low noise amplifiers. The RFFE 3321 can be circuitry composed of a plurality of discrete devices, or can be integrated and packaged in one or more chips. The radio frequency transceiver 3322 is used to process RF signals received by the RFFE into baseband / intermediate frequency signals for further processing by the processor system 3330, and to process baseband / intermediate frequency signals provided by the processor system 3330 into RF signals for transmission to the RFFE 3321. The baseband / intermediate frequency signals transmitted between the radio frequency transceiver 3322 and the processor system 3330 can be digital signals or analog signals. The radio frequency transceiver 3322 can be implemented by one or more chips, which are commonly referred to as radio frequency chips (RFIC).

[0271] In one example, the processor system 3330 can include one or more processors for processing signals and executing one or more communication protocols. Optionally, the processor system 3330 can further include a memory 3336. In one example, the one or more processors include at least one baseband processor 3331 (also referred to as a modem processor). The memory 3336 is used to store data and / or computer program instructions. Optionally, the processor system 3330 can further include one or more application processors 3332 for implementing processing of terminal operating systems and application layers. Optionally, the processor system 3330 can further include one or more of a voice subsystem 3333, a multimedia subsystem 3334, or an interface circuit 3335. The voice subsystem 3333 is used to process voice signals, the multimedia subsystem 3334 is used to process multimedia related operations such as video encoding and decoding, image processing, etc., and the interface circuit 3335 is used to implement communication with other terminal components such as a display 3340, an input device 3350, a memory 3360, etc. The above-mentioned components in the processor system 3330 can communicate with each other through a bus or a communication interface circuit.

[0272] In an example, the processor system 3330 can be packaged as one processor chip, such as a SoC chip or a SIP chip. In an example, the processor system 3330 can be a system composed of multiple chips, for example, the baseband processor 3331 can be packaged as a separate chip, or packaged as a chip with part or all of the circuitry of the radio frequency processing system.

[0273] In an example, the memory 3336 can be an on-chip memory, i.e., located on the chip of the processor system 3330. In an example, the memory 3360 can be an off-chip memory, i.e., located off the chip of the processor system 3330.

[0274] In an example, the baseband processor 3331 can include one or more processor cores 33311 and interface circuitry 33314. The one or more processor cores 33311 are configured to process signals and execute one or more communication protocols. Optionally, the baseband processor 3331 can further include a memory 33312 configured to store at least part of corresponding computer program instructions and / or data. In an example, the one or more processor cores 33311 implement the relevant operations in the above method embodiments (such as performing S1301 or S2801) by executing the computer program instructions stored in the memory 33312. In this disclosure, the memory 33312 configured to store corresponding computer program instructions and / or data can mean that the memory 33312 is configured to store all corresponding computer program instructions and / or data for execution by the processor core 33311; or can mean that the memory 33312 is configured to store part of corresponding computer program instructions and / or data, which includes computer program instructions and / or data currently needed for execution by the processor core 33311, and the memory 33312 can store different parts of computer program instructions and / or data for execution by the processor core 33311 multiple times to implement the relevant operations in the above method embodiments. The interface circuitry 33314 serves as a communication interface to enable communication with other components, such as transmitting signals with the radio frequency processing system 3320, communicating with other subsystems and related components of the processor system 3330 through a bus, such as transmitting data control signals with the application processor 3332, and transmitting data or computer program instructions with the memory 3336 or the memory 3360. Optionally, to reduce the load of the processor core, a baseband signal processing circuit 33313 can be further provided to implement at least part of the processing of baseband signals, including one or more of demodulation, modulation, encoding, or decoding of signals.

[0275] In an example, the communication apparatus provided in the present application can be the terminal 3300, a communication module including the processor system 3330 and the radio frequency processing system 3320, the processor system 3330, or the baseband processor 3331.

[0276] The processor, processor system, application processor, baseband processor, processor circuit, or processor core can be collectively referred to as a processor, which can include one or a combination of a CPU, a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor), or a neural processing unit (NPU).

[0277] The above-mentioned memory can include one or more of the following storage media: random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), phase-change memory (PCM), resistive RAM (ReRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable ROM (EPROM), hard disk, etc. In one example, computer program instructions for implementing the above-embodiments can be stored on a non-volatile memory, such as at least part of the above-mentioned memory 3360 (e.g., one or more of ROM, flash memory, EPROM, or hard disk). During terminal operation, the corresponding computer program instructions can be partially or entirely loaded onto a memory with faster transmission speed than the processor, such as at least part of the above-mentioned memory 3336 and / or memory 33312 (e.g., one or more of RAM, SRAM, DRAM, PCM, RERAM, MRAM, FRAM, cache, or register), for execution by the processor to implement the steps in the above-embodiments.

[0278] In one example, the radio frequency transceiver 3322 and the radio frequency front end 3321 can also be packaged in one chip. In one example, the radio frequency transceiver 3322, the radio frequency front end 3321, and the baseband processor 3331 can also be packaged in one chip.

[0279] The embodiments of the present application and any method embodiments of the above-mentioned channel encoding method and channel decoding method are based on the same concept, and have the same technical effects. For specific principles, refer to the description of any method embodiments of the above-mentioned channel encoding method and channel decoding method, which will not be repeated here.

[0280] The embodiments of the present application further provide a communication system, which comprises a sending device for implementing the method in any of the above method embodiments and a receiving device for implementing the method in any of the above method embodiments. In another possible design, the system can further comprise other devices / function network elements interacting with at least one of the sending device and the receiving device.

[0281] The embodiments of the present application further provide a chip, which comprises a processor, and the processor invokes a computer program stored in a memory to enable a communication device comprising the chip to implement the functions of any of the above method embodiments.

[0282] The embodiments of the present application further provide a computer readable storage medium for storing computer software instructions, which, when executed by a communication device, implement the functions of any of the above method embodiments.

[0283] The embodiments of the present application further provide a computer program product for storing computer software instructions, which, when executed by a communication device, implement the functions of any of the above method embodiments.

[0284] The embodiments of the present application further provide a computer program, which, when executed on a computer, implement the functions of any of the above method embodiments.

[0285] The terms "system" and "network" in the embodiments of the present application can be used interchangeably. "At least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the cases of A alone, A and B together, and B alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, "at least one of A, B or C" includes A, B, C, AB, AC, BC or ABC, and "at least one of A, B and C" can also be understood to include A, B, C, AB, AC, BC or ABC. In addition, unless otherwise specified, the ordinal numbers "first", "second", etc. mentioned in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the order, time sequence, priority or importance of the multiple objects.

[0286] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In a software embodiment, various software modules are stored in memory (such as RAM, ROM, etc.) and executed by one or more general-purpose or special-purpose processors. In a hardware embodiment, various functions are performed by various hardware components. In an embodiment that is a combination of software and hardware, various functions are performed by a combination of software and hardware.

[0287] The present application is described in reference to the flow diagrams and / or block diagrams of the methods, apparatus (systems) and computer program products according to this application. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0288] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flow diagrams and / or block diagrams block or blocks.

[0289] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks.

[0290] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A channel coding method characterized by, The method comprises: performing low-density parity-check code (LDPC) encoding on the input bit sequence based on a first base graph corresponding to a first initial transmission code rate and containing a first core matrix, to obtain an encoded bit sequence; the first base graph is one of N base graphs, the N base graphs further comprising a second base graph containing a second core matrix and corresponding to a second initial transmission code rate, N being an integer greater than or equal to 2; elements in the first base graph are zero elements and non-zero elements, and elements in the second base graph are zero elements and non-zero elements; the number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph; the second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix; the first core matrix comprises a sub-matrix A1 and a sub-matrix B1, the second core matrix comprises a sub-matrix A2 and a sub-matrix B2, and the number of columns of the A1 is equal to the number of columns of the A2; the B1 comprises columns with a weight of 3 and a sub-matrix B'1 of a double diagonal structure; the B2 comprises columns with a weight of 3 and a sub-matrix B'2 of a double diagonal structure.

2. The method of claim 1, wherein the number of rows of the first core matrix is associated with the first initial transmission code rate R1; the number of rows of the second core matrix is associated with the second initial transmission code rate R2; wherein the R1 and the R2 are both positive real numbers.

3. The method of claim 2, wherein the number of rows m of the first core array core1 is further associated with at least one of: the number of columns k of the A1 b the number of punctured columns np in the A1 rune1 ; the number of rows m of the second core array core2 is further associated with at least one of: the number of columns k of the A2 b the number of punctured columns np in the A2 rune2 ; The m core1 , the m core2 , the k b , the n prune1 , and the n prune2 are all integers greater than or equal to 0.

4. The method of claim 3, wherein The m core1 Satisfies: The m core2 Satisfies: wherein denotes a floor function.

5. The method of claim 1 or 2, wherein The number of rows of the first core matrix is m core1 The number of rows of the second core matrix is p*m core1 ​ p*m of A2 core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched hole, and the m of A1. core1 The non-zero elements in rows and columns with punched holes are in the same position; The non-punctured column in the A1 includes a p group of non-zero elements, the qth m core1 column of the non-punctured column in the A2 includes a qth group of non-zero elements in the p group of non-zero elements, and the p*m core1 column of the A2 includes a qth group of non-zero elements core1 The position of the qth group of non-zero elements included in the p*m core1 column of the A1 is the same as the position of the qth group of non-zero elements included in the m The m core1 is a positive integer, the p is an integer greater than or equal to 2, and the q is an integer greater than or equal to 1 and less than or equal to the p.

6. The method of any one of claims 1 to 5, wherein the first initial transmission code rate and the second initial transmission code rate belong to different code rate intervals.

7. A communication device, characterized by The device comprises: a processing unit configured to perform low-density parity-check code (LDPC) encoding on the input bit sequence based on a first base graph corresponding to a first initial transmission code rate and containing a first core matrix, to obtain an encoded bit sequence; the first base graph is one of N base graphs, the N base graphs further comprising a second base graph containing a second core matrix and corresponding to a second initial transmission code rate, N being an integer greater than or equal to 2; elements in the first base graph are zero elements and non-zero elements, and elements in the second base graph are zero elements and non-zero elements; the number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph; the second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix; the first core matrix comprises a sub-matrix A1 and a sub-matrix B1, the second core matrix comprises a sub-matrix A2 and a sub-matrix B2, and the number of columns of the A1 is equal to the number of columns of the A2; the B1 comprises columns with a weight of 3 and a sub-matrix B'1 of a double diagonal structure; the B2 comprises columns with a weight of 3 and a sub-matrix B'2 of a double diagonal structure.

8. The device of claim 7, wherein a number of rows of the first core matrix is associated with the first initial transmission code rate R1; a number of rows of the second core matrix is associated with the second initial transmission code rate R2; wherein the R1 and the R2 are both positive real numbers.

9. The apparatus of claim 8, wherein a number of rows m of the first core array core1 a number of columns k of the A1 b a number of punctured columns n in the A1 prune1 ; the number of rows m of the second core array core2 is further associated with at least one of: the number of columns k of the A2 b the number of punctured columns n in the A2 prune2 ; The m eore1 , the m core2 , the k b , the np rune1 , and the np rune2 are all integers greater than or equal to 0.

10. The apparatus of claim 9, wherein The m core1 Satisfies: The m core2 Satisfies: wherein, represents a floor function.

11. The apparatus of claim 7 or 8, wherein The number of rows of the first core matrix is m core1 The number of rows of the second core matrix is p*m core1 ​ The p*m of the A2 core1 The qth m in the qth row core1 The non-zero element position of the m in the puncturing column of the row is same as the m of the A1 core1 The non-zero element position of the m in the puncturing column of the row is same as the m of the A1 The non-punched column in A1 includes p groups of non-zero elements, and the q-th m-th element in the non-punched column in A2... core1 The row includes the q-th non-zero element from the p-th non-zero element group, and the p*m of A2 core1 The qth m in the row core1 The position of the qth non-zero element included in the row, and the m of A1 core1 The non-zero elements in the q-th group included in the row are in the same position; The m core1 is a positive integer, the p is an integer greater than or equal to 2, and the q is an integer greater than or equal to 1 and less than or equal to the p.

12. The apparatus of any one of claims 7 to 11, wherein the first initial transmission code rate and the second initial transmission code rate belong to different code rate intervals.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions which, when executed on a computer, cause the method according to any one of claims 1 to 6 to be performed.

14. A computer program product comprising instructions, characterized in that, The computer readable storage medium stores instructions which, when executed on a computer, cause the method according to any one of claims 1 to 6 to be performed.

15. A communications device, characterized by comprise means for performing the method of any one of claims 1 to 6.

16. A communications device, characterized by comprise one or more processors coupled with a memory for storing computer programs or instructions which, when executed by the one or more processors, cause the apparatus to implement the method of any one of claims 1 to 6.

17. The apparatus of claim 16, wherein, The interface circuit is configured to implement a communication function within the apparatus and / or a communication function of the apparatus with other apparatuses or components.

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