Display panel and display device

Abstract

A display panel and a display device, relating to the technical field of display. The display panel comprises circuit areas (CA) arranged in an array along a row direction and a column direction. The display panel further comprises a driving transistor (T3) and a storage capacitor (CST), the storage capacitor comprising a first electrode plate (EP1) arranged on a first gate layer (GT1) and a second electrode plate (EP2) arranged on a second gate layer (GT2), wherein the first electrode plate serves as a gate electrode of the driving transistor, and the second electrode plate is used for loading a driving power supply voltage. The display panel also comprises a plurality of data lines (DL), and comprises a plurality of first connection lines (CL1) extending in the column direction and a plurality of second connection lines (CL2) extending in the row direction. The display panel has a first routing group (LS1), the first routing group comprising a data line, a first connection line and a second connection line that are connected to each other, wherein the second connection line is arranged on the side of the second electrode plate away from a base substrate, and the orthographic projection of the second connection line on the base substrate overlaps with the orthographic projection of the second electrode plate on the base substrate.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] FIP (Fanout in Pixel) technology can integrate the diagonal wires of the fanout area in the display area, which can significantly reduce the lower frame space of the display panel, realize the extreme narrow frame of the product, and improve the visual experience. The FIP technology has been widely applied in the design of display panels. In related technologies, the data signal of the horizontal wire of the FIP and the gate signal of the driving transistor are easy to crosstalk, thereby affecting the display quality of the display panel.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] The present disclosure aims to overcome the shortcomings of the prior art, and provides a display panel and a display device to improve the display quality of the display panel.

[0006] According to one aspect of the present disclosure, a display panel is provided, comprising circuit areas arranged in a row direction and a column direction; the circuit areas are provided with pixel driving circuits for driving sub-pixels;

[0007] The display panel further comprises a substrate, a transistor layer, a source-drain metal layer, and a pixel layer which are sequentially stacked;

[0008] The transistor layer comprises a first gate layer and a second gate layer which are sequentially stacked on the substrate;

[0009] The pixel driving circuit comprises a driving transistor and a storage capacitor provided in the transistor layer; the storage capacitor comprises a first electrode plate provided in the first gate layer and a second electrode plate provided in the second gate layer, the first electrode plate serving as the gate of the driving transistor, and the second electrode plate being used for loading a driving power voltage;

[0010] The display panel further comprises a plurality of data lines extending in the column direction, and a plurality of first connection lines extending in the column direction and a plurality of second connection lines extending in the row direction;

[0011] The display panel has a first wiring group, the first wiring group includes mutually connected data lines, first connection lines, and second connection lines; the second connection lines are arranged on a side of the second electrode plates away from the substrate substrate, and a projection of the second connection lines on the substrate substrate overlaps a projection of the second electrode plates on the substrate substrate.

[0012] In an embodiment of the present disclosure, the second gate layer further includes second electrode wires for electrically connecting two adjacent second electrode plates in the same row;

[0013] The second connection lines include first connection sub-lines corresponding to the second electrode plates and second connection sub-lines corresponding to the second electrode wires;

[0014] The first connection sub-line and the corresponding second electrode plate are located in the same circuit area row, and a projection of the first connection sub-line in the row direction is located within a projection of the second electrode plate in the row direction;

[0015] The second connection sub-line and the corresponding second electrode wire are located in the same circuit area row, and a projection of the second connection sub-line in the row direction is located within a projection of the second electrode wire in the row direction;

[0016] A projection of the first connection sub-line on the substrate substrate is located within a projection of the corresponding second electrode plate on the substrate substrate.

[0017] In an embodiment of the present disclosure, the second connection sub-line includes second connection main sub-lines and second connection auxiliary sub-lines arranged alternately in sequence; the second connection main sub-line and the second connection auxiliary sub-line are connected by the first connection sub-line;

[0018] A projection of the second connection main sub-line on the substrate substrate overlaps a projection of the corresponding second electrode wire on the substrate substrate, and a projection of the second connection auxiliary sub-line on the substrate substrate does not overlap a projection of the corresponding second electrode wire on the substrate substrate.

[0019] In an embodiment of the present disclosure, the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer arranged in sequence in a direction away from the substrate substrate;

[0020] The first connection line includes third connection sub-lines and fourth connection sub-lines arranged alternately in sequence and connected in the column direction, the third connection sub-line is located in the first source-drain metal layer, and the fourth connection sub-line is located in the second source-drain metal layer;

[0021] The display panel is further provided with a first switching structure corresponding to the first wiring group, and the third connection sub-wire and the second connection wire are electrically connected through the first switching structure.

[0022] In an embodiment of the present disclosure, the display panel further has a second wiring group; the second wiring group includes a plurality of first connection wires and a plurality of second connection wires, and the plurality of first connection wires and the plurality of second connection wires are electrically connected to each other; and the second wiring group is used to load a reference power supply voltage.

[0023] In an embodiment of the present disclosure, the source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked in a direction away from the substrate substrate;

[0024] The first connection wire includes a third connection sub-wire and a fourth connection sub-wire which are sequentially and alternately arranged and connected in the column direction, the third connection sub-wire is located in the first source-drain metal layer, and the fourth connection sub-wire is located in the second source-drain metal layer;

[0025] The second wiring group includes a plurality of second switching structures, and the third connection sub-wire and the second connection wire are electrically connected through the second switching structure.

[0026] In an embodiment of the present disclosure, the pixel driving circuit has a first light-emitting control transistor and a second light-emitting control transistor; a first electrode of the first light-emitting control transistor is electrically connected to a first electrode of the driving transistor, and a first electrode of the second light-emitting control transistor is electrically connected to a second electrode of the driving transistor;

[0027] The first gate layer is provided with a first light-emitting control signal wire for loading a first light-emitting control signal and extending in the row direction, and a second light-emitting control signal wire for loading a second light-emitting control signal and extending in the row direction; in the column direction, a projection of the first light-emitting control signal wire on the substrate substrate and a projection of the second light-emitting control signal wire on the substrate substrate are located on both sides of a projection of the corresponding first electrode plate on the substrate substrate;

[0028] The first light-emitting control signal wire is electrically connected to a gate of the first light-emitting control transistor;

[0029] The second light-emitting control signal wire is electrically connected to a gate of the second light-emitting control transistor.

[0030] In an embodiment of the present disclosure, the pixel driving circuit has an electrode reset transistor, a node control transistor and a light emitting element; a first electrode of the electrode reset transistor is electrically connected with a pixel electrode of the light emitting element; a second electrode of the node control transistor is electrically connected with a first electrode of the driving transistor;

[0031] The first gate layer is provided with a second reset control signal wire for loading a second reset control signal and extending in the row direction, and a third reset control signal wire for loading a third reset control signal and extending in the row direction; in the column direction, the orthographic projection of the second reset control signal wire on the substrate substrate and the orthographic projection of the third reset control signal wire on the substrate substrate are located on both sides of the orthographic projection of the corresponding first electrode plate on the substrate substrate;

[0032] The second reset control signal wire is electrically connected with the gate of the node control transistor;

[0033] The third reset control signal wire is electrically connected with the gate of the electrode reset transistor.

[0034] In an embodiment of the present disclosure, the display panel further comprises a plurality of initialization auxiliary wires extending in the column direction; the first connection lines and the initialization auxiliary wires are arranged alternately in sequence; the initialization auxiliary wires are used for being electrically connected with the initialization voltage wires located in the transistor layer.

[0035] In an embodiment of the present disclosure, the initialization voltage wires comprise a first initialization voltage wire for loading a first initialization voltage to a circuit row and extending in the row direction, a second initialization voltage wire for loading a second initialization voltage to a circuit row and extending in the row direction, and a third initialization voltage wire for loading a third initialization voltage to a circuit row and extending in the row direction.

[0036] The initialization auxiliary wires comprise a first initialization auxiliary wire for being electrically connected with each of the first initialization voltage wires, a second initialization auxiliary wire for being electrically connected with each of the second initialization voltage wires, and a third initialization auxiliary wire for being electrically connected with each of the third initialization voltage wires.

[0037] In an embodiment of the present disclosure, in one circuit region row, along the column direction, the orthogonal projection of the first initialization voltage wire on the substrate substrate is located between the orthogonal projection of the third initialization voltage wire on the substrate substrate and the orthogonal projection of the second initialization voltage wire on the substrate substrate, and the orthogonal projection of the first initialization voltage wire on the substrate substrate and the orthogonal projection of the second initialization voltage wire on the substrate substrate are located on both sides of the orthogonal projection of the corresponding second electrode plate on the substrate substrate.

[0038] In an embodiment of the present disclosure, among the initialization auxiliary wires arranged along the row direction, the first initialization auxiliary wire, the second initialization auxiliary wire and the third initialization auxiliary wire are arranged in a cycle in sequence.

[0039] In an embodiment of the present disclosure, the first initialization auxiliary wire is electrically connected with each first initialization voltage wire through a first bridge structure; the second initialization auxiliary wire is electrically connected with each second initialization voltage wire through a second bridge structure; and the third initialization auxiliary wire is electrically connected with each third initialization voltage wire through a third bridge structure.

[0040] In an embodiment of the present disclosure, two circuit region columns are arranged between two adjacent first connection lines, two circuit region columns are arranged between two adjacent initialization auxiliary wires, and along the row direction, the first connection lines and the initialization auxiliary wires are alternately arranged in sequence.

[0041] According to another aspect of the present disclosure, a display device is provided, which comprises the display panel described above.

[0042] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0043] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0044] FIG. 1 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0045] FIG. 2 is a schematic diagram of a display panel in an embodiment of the present disclosure.

[0046] FIG. 3 is a schematic diagram of the first connection line and the second connection line connected in one embodiment of the present disclosure.

[0047] FIG. 4 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0048] FIG. 5 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0049] FIG. 6 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0050] FIG. 7 is a schematic diagram of a display panel in one embodiment of the present disclosure, which is intended to show the stacking relationship of the first gate layer, the third gate layer, the first source-drain metal layer, and the second source-drain metal layer.

[0051] FIG. 8 is a schematic diagram of a display panel in one embodiment of the present disclosure, which is intended to show the stacking relationship of the first gate layer, the third gate layer, and the first source-drain metal layer.

[0052] FIG. 9 is a schematic diagram of the first source-drain metal layer in one embodiment of the present disclosure.

[0053] FIG. 10 is a schematic diagram of the second source-drain metal layer in one embodiment of the present disclosure.

[0054] FIG. 11 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0055] FIG. 12 is a schematic diagram of a display panel in one embodiment of the present disclosure, which is intended to show the stacking relationship of the first gate layer, the third gate layer, the first source-drain metal layer, and the second source-drain metal layer.

[0056] FIG. 13 is a schematic diagram of a display panel in one embodiment of the present disclosure, which is intended to show the stacking relationship of the first gate layer, the third gate layer, and the first source-drain metal layer.

[0057] FIG. 14 is a schematic diagram of the first source-drain metal layer in one embodiment of the present disclosure.

[0058] FIG. 15 is a schematic diagram of the second source-drain metal layer in one embodiment of the present disclosure.

[0059] FIG. 16 is a schematic diagram of the stacking of various film layers in one circuit region in one embodiment of the present disclosure.

[0060] FIG. 17 is a schematic diagram of the stacking of various film layers in one circuit region in one embodiment of the present disclosure, in which the first source-drain metal layer and the second source-drain metal layer are removed.

[0061] FIG. 18 is a diagram of a first gate layer, a second gate layer, a first source-drain metal layer, and a second source-drain metal layer in a circuit region in one embodiment of the present disclosure.

[0062] FIG. 19 is a diagram of the first gate layer, the second gate layer, the first source-drain metal layer, and the second source-drain metal layer in FIG. 18.

[0063] FIG. 20 is a diagram of a metal light-shielding layer in one embodiment of the present disclosure.

[0064] FIG. 21 is a diagram of a low-temperature polysilicon semiconductor layer in one embodiment of the present disclosure.

[0065] FIG. 22 is a diagram of a first gate layer in one embodiment of the present disclosure.

[0066] FIG. 23 is a diagram of a second gate layer in one embodiment of the present disclosure.

[0067] FIG. 24 is a diagram of a metal-oxide semiconductor layer in one embodiment of the present disclosure.

[0068] FIG. 25 is a diagram of a third gate layer in one embodiment of the present disclosure.

[0069] FIG. 26 is a diagram of a third gate layer in one embodiment of the present disclosure.

[0070] FIG. 27 is a diagram of a first source-drain metal layer in one embodiment of the present disclosure.

[0071] FIG. 28 is a diagram of a first connection line and a second connection line in one embodiment of the present disclosure.

[0072] FIG. 29 is a diagram of a first source-drain metal layer in one embodiment of the present disclosure.

[0073] FIG. 30 is a diagram of a first source-drain metal layer in one embodiment of the present disclosure.

[0074] FIG. 31 is a diagram of a second source-drain metal layer in one embodiment of the present disclosure.

[0075] FIG. 32 is a diagram of a second source-drain metal layer in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0076] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided as example embodiments so that this disclosure will be thorough and complete, and will fully convey the scope thereof to those skilled in the art. Like reference numerals refer to like elements throughout the drawings, and descriptions of the same elements will be omitted from descriptions of other figures where appropriate. Furthermore, the drawings are in simplified form and not to precise scale. However, the applicants believe the drawings sufficiently represent relative dimensions and are accurate enough to support the claims herein and to fully convey details of the example embodiments to those who view the drawings.

[0077] Although relative terms such as "on", "under", "lower", "upper" and the like can be used herein to describe one element's relationship to another element as the device is positioned in accordance with an example embodiment, such terminology is used in the present description for the purpose of convenience only. It will be understood that the terms and expressions of the present description are used as terms of description and not of limitation. Thus, for example, if a device is turned over, elements described as being "on" another element would then be oriented "under" the other element. Such terminology can include the case where one element is directly on another element or one element is indirectly in contact with another element through one or more other elements.

[0078] The terms "one", "a", "an", "the", and "at least one" are used to mean that "one or more" than one of the specified element / s, component / s, etc. is / are present; the terms "includes", "including", and "has", "having", and "containing", "containing", are used to mean "comprising", and are meant not to exclude the presence of additional element / s, component / s, etc. The terms "first", "second", and "third", etc. are used merely as labels, and are not meant to impose numerical requirements on their objects.

[0079] In the embodiments of the present disclosure, a thin film transistor includes an active layer, a gate insulating layer and a gate which are stacked. The active layer is located in a semiconductor layer, and the active layer includes a channel region and a source and a drain which are respectively located on both sides of the channel region. The channel region maintains a semiconductor property, and the source and the drain are both conductive. In the embodiments of the present disclosure, the functions of the source and the drain are sometimes exchanged with each other, i.e., the source and the drain can be exchanged with each other, in the case of using transistors with opposite polarities or in the case of changing the current direction in the operation of a circuit. In the embodiments of the present disclosure, for any one transistor, one of the source and the drain is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor. In the embodiments of the present disclosure, at least part of a signal has a high level and a low level; one of the high level and the low level can be a gate-on level of the signal, which can make a controlled transistor turn on; and the other of the high level and the low level can be a gate-off level of the signal, which can make the controlled transistor turn off. For example, for a signal for controlling a P-type transistor (which can be loaded to a control terminal of the P-type transistor), the gate-on level of the signal is the low level, and the gate-off level of the signal is the high level. For another example, for a signal for controlling an N-type transistor (which can be loaded to a control terminal of the N-type transistor), the gate-on level of the signal is the high level, and the gate-off level of the signal is the low level.

[0080] The structural layer A is located on the side of the structural layer B away from the substrate, which can be understood as that the structural layer A is formed on the side of the structural layer B away from the substrate. When the structural layer B is a patterned structure, part of the structure of the structural layer A can also be located at the same physical height of the structural layer B or below the physical height of the structural layer B, wherein the substrate is the height reference.

[0081] It should be noted that the "same layer" in the embodiments of the present disclosure can refer to a film layer on the same structural layer. For example, the film layers on the same layer can be film layers of a specific pattern formed by the same film forming process. Of course, the film layers of the specific pattern can also be at different heights or have different thicknesses.

[0082] The display device provided by the embodiments of the present disclosure includes a display panel. The display device can be a television, a computer screen, a smart phone, a smart watch screen, a vehicle window, a cabin glass, or other types of display devices.

[0083] In the related art, in order to reduce the display panel lower frame space, realize the extreme narrow edge of the product, and improve the visual experience, FIP technology (the diagonal wire of the fan-shaped area is integrated in the display area, that is, the horizontal wire is connected with the corresponding data line, the vertical wire is connected with the end of the horizontal wire away from the data line, and then the vertical wire is led out at the lower frame of the display panel) is often used. However, the data signal of the horizontal wire and the gate signal of the driving transistor are easy to crosstalk, thereby affecting the display quality of the display panel.

[0084] To solve the above problems, the display panel PNL provided by the present disclosure includes a circuit area CA arranged in a row direction DH and a column direction DV. The circuit area CA is provided with a pixel driving circuit for driving a sub-pixel. The display panel PNL includes a substrate SBT, a driving layer DRL, and a pixel layer PIXL arranged in sequence. The driving layer DRL includes a transistor layer TL and a source-drain metal layer SD arranged in sequence on the substrate SBT. The transistor layer TL includes a first gate layer GT1 and a second gate layer GT2 arranged in sequence on the substrate SBT. The pixel driving circuit includes a driving transistor T3 and a storage capacitor CST arranged in the transistor layer TL. The storage capacitor CST includes a first electrode plate EP1 arranged in the first gate layer GT1 and a second electrode plate EP2 arranged in the second gate layer GT2. The first electrode plate EP1 serves as a gate of the driving transistor T3, and the second electrode plate EP2 is used to load a driving power voltage VDD. The display panel PNL further includes a plurality of data lines DL extending in the column direction DV, a plurality of first connection lines CL1 extending in the column direction DV, and a plurality of second connection lines CL2 extending in the row direction DH. The display panel PNL has a first wiring group LS1 including one data line DL, one first connection line CL1, and one second connection line CL2. The second connection line CL2 is arranged on a side of the second electrode plate EP2 away from the substrate SBT (not shown in the figure), and the orthographic projection of the second connection line CL2 on the substrate SBT overlaps the orthographic projection of the second electrode plate EP2 on the substrate SBT. In an example, the second connection line CL2 can be arranged in the source-drain metal layer SD, and the orthographic projection of the second connection line CL2 on the substrate SBT is located within the orthographic projection of the second electrode plate EP2 on the substrate SBT. For example, the second connection line CL2 can be arranged in the first source-drain metal layer SD1 or the second source-drain metal layer SD2. In another example, the second connection line CL2 can be arranged in a film layer between the source-drain metal layer SD and the second gate layer GT2. For example, the second gate layer GT2 and the source-drain metal layer SD have a third gate layer GT3 therebetween, and the second connection line CL2 can be arranged in the third gate layer GT3. The orthographic projection of the second connection line CL2 on the substrate SBT partially overlaps the orthographic projection of the second electrode plate EP2 on the substrate SBT.

[0085] On the one hand, the first connection line CL1 is electrically connected with the data line DL through the second connection line CL2, which can realize the purpose of accumulating the wire for electrically connecting the display panel PNL and the driving chip in the lower frame of the display panel PNL, reduce the space of the fan-shaped area, realize the reasonable layout of the connection line between the display panel PNL and the driving chip, help to reduce the space of the lower frame of the display panel PNL, and improve the narrow frame of the display panel PNL; on the other hand, by loading the driving power voltage VDD on the second electrode plate EP2, and the orthogonal projection of the second connection line CL2 on the substrate SBT overlaps with the orthogonal projection of the second electrode plate EP2 on the substrate SBT, so that the second electrode plate EP2 is located between the gate of the driving transistor T3 and the corresponding second connection line CL2, and the driving power voltage VDD loaded on the second electrode plate EP2 is used to shield the gate signal of the driving transistor T3 and the data signal on the corresponding second connection line CL2, so as to reduce the crosstalk between the gate signal of the driving transistor T3 and the data signal on the corresponding second connection line CL2 in the FIP technology, and improve the display quality of the display panel PNL. In addition, since the driving power voltage VDD is a more stable constant voltage, it has a more excellent shielding effect and improves the reliability.

[0086] The basic principle of the pixel driving circuit will be described as follows in combination with the equivalent circuit diagram of the pixel driving circuit.

[0087] FIG. 5 illustrates an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure. It can be understood that the pixel driving circuit in the embodiment of the present disclosure can also be a pixel driving circuit of other structures. When the structure of the pixel driving circuit changes, the structure of each film layer in the embodiment of the present disclosure can also be adjusted adaptively.

[0088] In the embodiment of the present disclosure, the pixel driving circuit can also be 8T1C (8 transistors and 1 storage capacitor), 9T1C (9 transistors and 1 storage capacitor), 10T1C (10 transistors and 1 storage capacitor), etc., and the present embodiment does not make specific limitation thereto.

[0089] The pixel driving circuit shown in FIG. 5 includes a first initialization voltage line VIL1 loading a first initialization voltage Vinit1, a second initialization voltage line VIL2 loading a second initialization voltage Vinit2, a third initialization voltage line VIL3 loading a third initialization voltage Vinit3, a first reset control signal line RNL loading a first reset control signal RN, a second reset control signal line RH1L loading a second reset control signal RH1, a third reset control signal line RH2L loading a third reset control signal RH2, a first scan signal line GNL loading a first scan signal GN, a second scan signal line GPL loading a second scan signal GP, a first emission control signal line EM1L loading a first emission control signal EM1, a second emission control signal line EM2L loading a second emission control signal EM2, a driving power voltage line VDDL loading a driving power voltage VDD, a data line DL loading a data signal Data, a gate reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data write transistor T4, a first emission control transistor T5, a second emission control transistor T6, an electrode reset transistor T7, a node control transistor T8, an auxiliary transistor T9, a storage capacitor CST, a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5.

[0090] The gate reset transistor T1 and the threshold compensation transistor T2 are N-type transistors, and the driving transistor T3, the data write transistor T4, the first emission control transistor T5, the second emission control transistor T6, the electrode reset transistor T7, the node control transistor T8, and the auxiliary transistor T9 are P-type transistors, so as to reduce the leakage current of the first node N1 through the gate reset transistor T1 and the threshold compensation transistor T2. In some other embodiments of the present disclosure, the auxiliary transistor T9 can also be an N-type transistor, so as to further reduce the leakage current of the first node N1.

[0091] The first electrode of the gate reset transistor T1 is electrically connected to the first initialization voltage line VIL1 loading the first initialization voltage Vinit1, the gate of the gate reset transistor T1 is connected to the first reset control signal line RNL loading the first reset control signal RN, and the second electrode of the gate reset transistor T1 is connected to the fifth node N5. The gate reset transistor T1 is configured to load the first initialization voltage Vinit1 to the fifth node N5 in response to the gating level of the first reset control signal RN.

[0092] The first electrode of the threshold compensation transistor T2 is electrically connected with the third node N3, the second electrode of the threshold compensation transistor T2 is electrically connected with the fifth node N5, and the gate of the threshold compensation transistor T2 is connected with a first scan signal line GNL loaded with the first scan signal GN. The threshold compensation transistor T2 is configured to enable the communication between the third node N3 and the fifth node N5 in response to the gating level of the first scan signal GN.

[0093] The first electrode of the driving transistor T3 is connected with the second node N2, the second electrode of the driving transistor T3 is connected with the third node N3, and the gate of the driving transistor T3 is connected with the first node N1. The driving transistor T3 is configured to output a driving current under the control of the voltage on the first node N1.

[0094] The first electrode of the data writing transistor T4 is electrically connected with a data line DL loaded with a data signal Data, the second electrode of the data writing transistor T4 is electrically connected with the second node N2, and the gate of the data writing transistor T4 is connected with a second scan signal line GPL loaded with a second scan signal GP. The data writing transistor T4 is configured to load the data signal Data to the second node N2 in response to the gating level of the second scan signal GP.

[0095] The first electrode of the first light emitting control transistor T5 is electrically connected with a driving power voltage line VDDL loaded with a driving power voltage VDD, the second electrode of the first light emitting control transistor T5 is connected with the second node N2, and the gate of the first light emitting control transistor T5 is connected with a first light emitting control signal line EM1L loaded with a first light emitting control signal EM1. The first light emitting control transistor T5 is configured to be turned on in response to the gating level of the first light emitting control signal EM1.

[0096] The first electrode of the second light emitting control transistor T6 is connected with the third node N3, the second electrode of the second light emitting control transistor T6 is connected with the fourth node N4, and the gate of the second light emitting control transistor T6 is connected with a second light emitting control signal line EM2L loaded with a second light emitting control signal EM2. The second light emitting control transistor T6 is configured to be turned on in response to the gating level of the second light emitting control signal EM2.

[0097] It should be noted that in some embodiments, the first light emitting control signal EM1 loaded at the gate of the first light emitting control transistor T5 and the second light emitting control signal EM2 loaded at the gate of the second light emitting control transistor T6 can be set to open out of synchronization, that is, the gate of the first light emitting control transistor T5 can be loaded with the gating level of the first light emitting control signal EM1 first, and then the gate of the second light emitting control transistor T6 can be loaded with the gating level of the second light emitting control signal EM2; or, the gate of the second light emitting control transistor T6 can be loaded with the gating level of the second light emitting control signal EM2 first, and then the gate of the first light emitting control transistor T5 can be loaded with the gating level of the first light emitting control signal EM1.

[0098] The first electrode of the electrode reset transistor T7 is connected with the second initialization voltage wire VIL2 loaded with the second initialization voltage Vinit2, the gate of the electrode reset transistor T7 is connected with the third reset control signal wire RH2L loaded with the third reset control signal RH2, and the second electrode of the electrode reset transistor T7 is connected with the fourth node N4. The electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the gating level of the third reset control signal RH2.

[0099] The first electrode of the node control transistor T8 is connected with the third initialization voltage wire VIL3 loaded with the third initialization voltage Vinit3, the gate of the node control transistor T8 is connected with the second reset control signal wire RH1L loaded with the second reset control signal RH1, and the second electrode of the node control transistor T8 is connected with the second node N2. The node control transistor T8 is used to load the third initialization voltage Vinit3 to the second node N2 in response to the gating level of the second reset control signal RH1.

[0100] The first electrode of the auxiliary transistor T9 is connected with the fifth node N5, the gate of the auxiliary transistor T9 is connected with the second scan signal wire GPL loaded with the second scan signal GP, and the second electrode of the auxiliary transistor T9 is connected with the first node N1. The auxiliary transistor T9 is used to communicate the first node N1 with the fifth node N5 in response to the gating level of the second scan signal GP.

[0101] The pixel electrode of the light emitting element is connected with the pixel driving circuit (not specifically shown in the drawings of the present application), and the common electrode is used to load the reference power voltage VSS.

[0102] One end of the storage capacitor CST is connected with the first node N1, and the other end is connected with the driving power voltage wire VDDL. It should be noted that in the pixel driving circuit shown in FIG. 5, the wires of various signals are not shown, and only various signals are shown.

[0103] The display panel PNL in the embodiments of the present disclosure will be described in detail below in combination with the structure of each film layer in the display panel PNL.

[0104] FIG. 4 is a schematic diagram illustrating a film layer structure of a display panel PNL according to an embodiment of the present disclosure. Referring to FIG. 4, in some embodiments of the present disclosure, the display panel PNL includes a driving layer DRL and a pixel layer PIXL which are sequentially stacked on the substrate SBT.

[0105] Optionally, the substrate SBT can be a substrate SBT made of inorganic material, a substrate SBT made of organic material, or a composite substrate made of a substrate SBT made of inorganic material and a substrate SBT made of organic material. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda lime glass, quartz glass, sapphire glass, etc.

[0106] In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0107] Optionally, in the driving layer DRL, any one pixel driving circuit can include a thin film transistor and a storage capacitor CST (not shown in the drawings). Further, the thin film transistor can be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; and the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0108] It can be understood that the types of any two transistors among the transistors in the pixel driving circuit can be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors can be N-type transistors and some transistors can be P-type transistors. For another example, in some other embodiments, in a pixel driving circuit, the material of the active layer of some transistors can be low-temperature polysilicon semiconductor material and the material of the active layer of some transistors can be metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors and some thin film transistors are metal oxide transistors.

[0109] Optionally, referring to FIG. 4, the driving layer DRL can include a buffer layer (for example, the first buffer layer Buff1 and the second buffer layer Buff2 shown in FIG. 4) stacked on the substrate SBT, a metal light shielding layer BSM arranged between the first buffer layer Buff1 and the substrate SBT, a semiconductor layer (for example, a low-temperature polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL) in the pixel layer PIXL, a gate insulating layer (for example, the first gate insulating layer GI1, the second gate insulating layer GI2 and the third gate insulating layer GI3 shown in FIG. 4), a gate layer (for example, the first gate layer GT1 and the second gate layer GT2 shown in FIG. 4), an interlayer dielectric layer ILD, a source-drain metal layer (for example, the first source-drain metal layer SD1 and the second source-drain metal layer SD2 shown in FIG. 4), a planarization layer (for example, the first planarization layer PLN1 and the second planarization layer PLN2 shown in FIG. 4) and the like. Each thin film transistor and the storage capacitor CST (not specifically labeled in the drawings of the present disclosure) can be formed by the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source-drain metal layer and the like. Of course, other film layers can also be used. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer can be used to form the active layer of the transistor (including the first electrode, the second electrode and the channel region of the transistor) and can also be used to form part of the wiring or the conductive structure by being conductive if necessary. The first source-drain metal layer SD1 can be used to form the scanning signal wiring. The gate layer can be used to form one or more of the gate layer wiring such as the reset control signal wiring, the light-emitting control signal wiring and the like, can also be used to form the gate electrode of the transistor, and can also be used to form part or all of the electrode plate of the storage capacitor CST. The source-drain metal layer can be used to form the data line, the driving power voltage wiring and the like, and can also be used to form part of the electrode plate of the storage capacitor CST.

[0110] Of course, in other embodiments of the present disclosure, the driving layer DRL can also include other film layers as needed, for example, it can also include a metal light shielding layer BSM between the semiconductor layer and the substrate SBT, etc. Any one of the above-mentioned semiconductor layer, gate layer, source-drain metal layer, etc. film layer can also be multi-layered as needed, for example, the driving layer DRL can include two different semiconductor layers, or include two or three source-drain metal layers, or include two or three gate layers; accordingly, the insulating film layer in the driving layer DRL (such as the gate insulating layer, the interlayer dielectric layer ILD, the planarization layer, etc.) can be adaptively increased or decreased, or a new insulating film layer can be added as needed.

[0111] Optionally, the pixel layer PIXL can include a pixel electrode layer PEL, a light-emitting functional layer EL, and a common electrode layer COML which are sequentially stacked. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes PE, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edges of the pixel electrode PE and exposes at least a partial internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode (the area directly connected to the light-emitting functional layer EL), and further define the light-emitting area and light-emitting area of the sub-pixel. The common electrode layer COML covers the light-emitting functional layer EL as a common electrode. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EL, so that the light-emitting functional layer EL emits light. The part of the light-emitting functional layer EL between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element as a sub-pixel. Among them, one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel, and the other serves as a cathode of the sub-pixel.

[0112] In this example, the display panel is an OLED (Organic Light Emitting Diode) display panel. The light-emitting functional layer EL can include an organic light-emitting layer, and can include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Further, the organic light-emitting layer can include a light-emitting layer host material and a light-emitting layer guest material, which can be a fluorescent dopant or a phosphorescent dopant, and in particular can be a thermally activated delayed fluorescence material.

[0113] It can be understood that the display panel can also be other types of display panels, for example, it can also be a QLED display panel, a QD-OLED display panel, or other types of display panels.

[0114] Referring to FIG. 4, the display panel can further include a thin film encapsulation layer TFE, which can be disposed on a surface of the pixel layer PIXL away from the substrate base plate SBT, and can include inorganic encapsulation layers and organic encapsulation layers alternately stacked. The inorganic encapsulation layers can effectively block moisture and oxygen from the outside, so as to avoid water and oxygen from invading the pixel layer PIXL and causing the materials in the pixel layer PIXL to age. Optionally, the edges of the inorganic encapsulation layers can be located in the peripheral area. The organic encapsulation layers are located between two adjacent inorganic encapsulation layers, so as to achieve planarization and weaken the stress between the inorganic encapsulation layers. The edges of the organic encapsulation layers can be located between the edges of the display area and the edges of the inorganic encapsulation layers.

[0115] Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer (not specifically shown in the drawings) stacked in sequence on a side of the pixel layer PIXL away from the substrate base plate SBT. The first inorganic encapsulation layer covers the display area and extends to the outside of the barrier wall; the organic encapsulation layer covers the display area and extends to the inside of the barrier wall; and the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the barrier wall. On the outside of the barrier wall, the second inorganic encapsulation layer is in contact with the first inorganic encapsulation layer. In this way, the organic encapsulation layer is enclosed by the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the stress on the first inorganic encapsulation layer and the second inorganic encapsulation layer is balanced. The first inorganic encapsulation layer and the second inorganic encapsulation layer enclose the organic encapsulation layer, so as to isolate the organic encapsulation layer from water and oxygen. Of course, in other embodiments of the present disclosure, the display panel can also not be provided with the thin film encapsulation layer TFE, but other ways can be used to encapsulate and protect the pixel layer.

[0116] In some embodiments of the present disclosure, the display panel can further include a touch metal layer (not specifically shown in the drawings), which can be disposed on a side of the thin film transistor away from the pixel layer PIXL, so that the display panel has a touch function.

[0117] In this embodiment, referring to FIG. 4, the driving layer DRL can further include a transistor layer TL, a first source-drain metal layer SD1 and a second source-drain metal layer SD2; the transistor layer TL is a combination of various film layers disposed between the substrate base plate SBT and the first source-drain metal layer SD1, and can form various thin film transistors required by the pixel driving circuit.

[0118] In an embodiment of the present disclosure, referring to FIG. 19, FIG. 23, FIG. 27 and FIG. 28, the second gate layer GT2 further comprises a second electrode trace EP2L for electrically connecting the same-row adjacent two second electrode plates EP2. The second connection line CL2 comprises a first connection sub-line CL21 corresponding to the second electrode plate EP2 and a second connection sub-line CL22 corresponding to the second electrode trace EP2L. The first connection sub-line CL21 and the corresponding second electrode plate EP2 are located in the same circuit area row HCA (not shown in the figure), and the orthogonal projection of the first connection sub-line CL21 in the row direction DH is located within the orthogonal projection of the corresponding second electrode plate EP2 in the row direction DH. The second connection sub-line CL22 and the corresponding second electrode trace EP2L are located in the same circuit area row HCA, and the orthogonal projection of the second connection sub-line CL22 in the row direction DH is located within the orthogonal projection of the corresponding second electrode trace EP2L in the row direction DH. The orthogonal projection of the first connection sub-line CL21 on the substrate SBT is located within the orthogonal projection of the corresponding second electrode plate EP2 on the substrate SBT. In this way, the second electrode plate EP2 can separate the gate of the corresponding driving transistor T3 from the first connection sub-line CL21, so that the gate of the driving transistor T3 does not have a direct area with the first connection sub-line CL21, facilitating shielding of the gate signal of the driving transistor T3 from the data signal on the first connection sub-line CL21 by loading a driving power voltage VDD on the second electrode plate EP2. It can be understood that the orthogonal projection of the second connection sub-line CL22 on the substrate SBT and the orthogonal projection of the corresponding second electrode trace EP2L on the substrate SBT can overlap or not overlap. Since the gate of the driving transistor T3 serves as the first electrode plate EP1, in the same storage capacitor CST, the orthogonal projection of the first electrode plate EP1 on the substrate SBT and the orthogonal projection of the corresponding second electrode plate EP2 on the substrate SBT can coincide, and the orthogonal projection of the second connection sub-line CL22 on the substrate SBT and the orthogonal projection of the corresponding first electrode plate EP1 on the substrate SBT do not overlap. Therefore, the second connection sub-line CL22 does not cause signal crosstalk with the gate of the corresponding driving transistor T3.

[0119] In an embodiment of the present disclosure, the display area array of the display panel PNL is provided with a plurality of circuit areas CA. The plurality of circuit areas CA form a plurality of circuit area rows HCA and a plurality of circuit area columns VCA. The plurality of circuit area rows HCA are arranged along the column direction DV; the plurality of circuit area columns VCA are arranged along the row direction DH. The circuit area row HCA comprises a plurality of circuit areas CA arranged in sequence and adjacent along the row direction DH. The circuit area column VCA comprises a plurality of circuit areas CA arranged in sequence and adjacent along the column direction DV.

[0120] In an embodiment of the present disclosure, referring to FIG. 3, FIG. 19, FIG. 23, FIG. 27, FIG. 28, the second connection sub-wire CL22 includes a second connection main sub-wire CL221 and a second connection auxiliary sub-wire CL222 arranged alternately in sequence. The second connection main sub-wire CL221 and the second connection auxiliary sub-wire CL222 are connected by the first connection sub-wire CL21. The orthogonal projection of the second connection main sub-wire CL221 on the substrate SBT (not shown in the figure) overlaps with the orthogonal projection of the corresponding second electrode trace EP2L on the substrate SBT, and the orthogonal projection of the second connection auxiliary sub-wire CL222 on the substrate SBT does not overlap with the orthogonal projection of the corresponding second electrode trace EP2L on the substrate SBT. In this way, by overlapping the orthogonal projection of the second connection main sub-wire CL221 on the substrate SBT with the orthogonal projection of the corresponding second electrode trace EP2L on the substrate SBT, as much as possible, the signal shielding of the second connection sub-wire CL22 and the gate of the corresponding driving transistor T3 by the driving power supply voltage VDD is facilitated, and the signal crosstalk between the data signal on the second connection sub-wire CL22 and the gate signal of the corresponding driving transistor T3 is reduced.

[0121] In an embodiment of the present disclosure, referring to FIG. 1, FIG. 4, FIG. 8, FIG. 9, FIG. 10, the source-drain metal layer SD includes a first source-drain metal layer SD1 and a second source-drain metal layer SD2 stacked in sequence in a direction away from the substrate SBT. The first connection wire CL1 includes a third connection sub-wire CL11 and a fourth connection sub-wire CL12 arranged alternately in sequence and connected in the column direction DV, the third connection sub-wire CL11 is located in the first source-drain metal layer SD1, and the fourth connection sub-wire CL12 is located in the second source-drain metal layer SD2. The display panel PNL is also provided with a first switching structure LS1T corresponding to the first trace group LS1, and the third connection sub-wire CL11 and the second connection wire CL2 are electrically connected through the first switching structure LS1T. In this way, within one first trace group LS1, the data signal on the data line DL is sequentially switched to the display area of the display panel PNL through the second connection wire CL2, the first switching structure LS1T, the third connection sub-wire CL11, and the fourth connection sub-wire CL12, which facilitates the narrow frame design of the display panel PNL.

[0122] In an embodiment of the present disclosure, referring to FIG. 2, FIG. 11, FIG. 12, FIG. 13, FIG. 14, and FIG. 15, the display panel PNL further has a second wiring group LS2. The second wiring group LS2 includes a plurality of first connection lines CL1 and a plurality of second connection lines CL2, and the plurality of first connection lines CL1 and the plurality of second connection lines CL2 are electrically connected to each other. In this way, since the area of the second wiring group LS2 on the display panel PNL does not need to transfer the data line DL, the display panel PNL is gridded by the second wiring group LS2 and the reference power supply voltage VSS (not shown in the figure) is loaded to the second wiring group LS2, so as to improve the display uniformity of the display panel PNL. That is, the display panel PNL is divided into two areas, referring to FIG. 1 and FIG. 6, one area is provided with a plurality of first wiring groups LS1 to transfer the data signal on the data line DL to the display area. Referring to FIG. 2 and FIG. 11, the other area is provided with the second wiring group LS2, and the reference power supply voltage VSS is loaded to the gridded second wiring group LS2, so as to improve the display uniformity of the display panel PNL.

[0123] In an embodiment of the present disclosure, referring to FIG. 2, FIG. 3, FIG. 11, FIG. 12, FIG. 13, FIG. 14, and FIG. 15, the source-drain metal layer SD (not shown in the figure) includes a first source-drain metal layer SD1 and a second source-drain metal layer SD2 which are sequentially stacked in a direction away from the substrate base plate SBT (not shown in the figure). The first connection line CL1 includes a third connection sub-line CL11 and a fourth connection sub-line CL12 which are sequentially and alternately arranged and connected in the column direction DV, the third connection sub-line CL11 is located in the first source-drain metal layer SD1, and the fourth connection sub-line CL12 is located in the second source-drain metal layer SD2. The second wiring group LS2 includes a plurality of second transfer structures LS2T, one third connection sub-line CL11 and one second connection line CL2 are electrically connected by one second transfer structure LS2T, and each first connection line CL1 and each second connection line CL2 are electrically connected by the second transfer structure LS2T, so that the second wiring group LS2 is a grid structure composed of the plurality of first connection lines CL1 and the plurality of second connection lines CL2, and the second wiring group LS2 is used to load the reference power supply voltage VSS (not shown in the figure).

[0124] In an embodiment of the present disclosure, referring to FIG. 5 and FIG. 22, the pixel driving circuit has a first light emitting control transistor T5 and a second light emitting control transistor T6. The first electrode of the first light emitting control transistor T5 is electrically connected with the first electrode of the driving transistor T3, and the first electrode of the second light emitting control transistor T6 is electrically connected with the second electrode of the driving transistor T3. The first gate layer GT1 is provided with a first light emitting control signal wire EM1L for loading a first light emitting control signal EM1 and extending along the row direction DH, and a second light emitting control signal wire EM2L for loading a second light emitting control signal EM2 and extending along the row direction DH. Along the column direction DV, the orthogonal projection of the first light emitting control signal wire EM1L on the substrate SBT (not shown in the figure) and the orthogonal projection of the second light emitting control signal wire EM2L on the substrate SBT are located on both sides of the orthogonal projection of the corresponding first electrode plate EP1 on the substrate SBT; the first light emitting control signal wire EM1L is electrically connected with the gate of the first light emitting control transistor T5; and the second light emitting control signal wire EM2L is electrically connected with the gate of the second light emitting control transistor T6. In an example, each circuit area row HCA (not shown in the figure) has one first light emitting control signal wire EM1L and one second light emitting control signal wire EM2L, and the first light emitting control signal wire EM1L and the second light emitting control signal wire EM2L corresponding to one circuit area row HCA are independent of the first light emitting control signal wire EM1L and the second light emitting control signal wire EM2L corresponding to other circuit area rows HCA. In another example, referring to FIG. 22, each circuit area row HCA (not shown in the figure) has one first light emitting control signal wire EM1L and one second light emitting control signal wire EM2L. In two adjacent circuit area rows HCA, along the column direction DV, the second light emitting control signal wire EM2L corresponding to the previous circuit area row HCA serves as the first light emitting control signal wire EM1L corresponding to the next circuit area row HCA. In this way, on the one hand, driving the gate of the first light emitting control transistor T5 and the gate of the second light emitting control transistor T6 separately enables the conduction time of the first light emitting control transistor T5 and the second light emitting control transistor T6 to be controlled individually by the first light emitting control signal EM1 and the second light emitting control signal EM2, so as to control the light emitting time of the light emitting element. On the other hand, in two adjacent circuit area rows HCA, by using the second light emitting control signal wire EM2L corresponding to the previous circuit area row HCA as the first light emitting control signal wire EM1L corresponding to the next circuit area row HCA, the number of gate wires can be reduced, and the wiring space of the first gate layer GT1 can be improved.

[0125] In an embodiment of the present disclosure, referring to FIG. 5 and FIG. 22, the pixel driving circuit has an electrode reset transistor T7, a node control transistor T8 and a light emitting element. The first electrode of the electrode reset transistor T7 is electrically connected with the pixel electrode of the light emitting element; the second electrode of the node control transistor T8 is electrically connected with the first electrode of the driving transistor T3. The first gate layer GT1 is provided with a second reset control signal wire RH1L for loading the second reset control signal RH1 and extending along the row direction DH, and a third reset control signal wire RH2L for loading the third reset control signal RH2 and extending along the row direction DH; along the column direction DV, the orthogonal projection of the second reset control signal wire RH1L on the substrate SBT and the orthogonal projection of the third reset control signal wire RH2L on the substrate SBT are located on both sides of the orthogonal projection of the corresponding first electrode plate EP1 on the substrate SBT. The second reset control signal wire RH1L is electrically connected with the gate of the node control transistor T8; the third reset control signal wire RH2L is electrically connected with the gate of the electrode reset transistor T7. In an example, each circuit area row HCA has one second reset control signal wire RH1L and one third reset control signal wire RH2L, and the second reset control signal wire RH1L and the third reset control signal wire RH2L corresponding to one circuit area row HCA are independent of the second reset control signal wire RH1L and the third reset control signal wire RH2L corresponding to other circuit area rows HCA. In another example, referring to FIG. 22, each circuit area row HCA (not shown in the figure) has one second reset control signal wire RH1L and one third reset control signal wire RH2L. In the adjacent two circuit area rows HCA, along the column direction DV, the third reset control signal wire RH2L corresponding to the previous circuit area row HCA serves as the second reset control signal wire RH1L corresponding to the next circuit area row HCA. In this way, on the one hand, the gate of the electrode reset transistor T7 and the gate of the node control transistor T8 are driven separately, the conduction time of the node control transistor T8 and the electrode reset transistor T7 can be controlled individually by the second reset control signal RH1 and the third reset control signal RH2, in the threshold compensation stage and the data writing stage, the node control transistor T8 is off, the electrode reset transistor T7 can still be on, the second initialization voltage Vinit2 can still reset the pixel electrode of the light emitting element, and the service life of the light emitting element is improved. On the other hand, in the adjacent two circuit area rows HCA, by using the third reset control signal wire RH2L corresponding to the previous circuit area row HCA as the second reset control signal wire RH1L corresponding to the next circuit area row HCA, the number of gate wires can be reduced, and the wiring space of the first gate layer GT1 is further improved.

[0126] In an embodiment of the present disclosure, referring to FIG. 1, FIG. 2, FIG. 6, FIG. 11, the display panel PNL further comprises a plurality of initialization auxiliary wires VILX extending along the column direction DV. The first connection lines CL1 and the initialization auxiliary wires VILX are arranged alternately in sequence; the initialization auxiliary wires VILX are used to be electrically connected with the initialization voltage wires VIL located in the transistor layer TL (not shown in the figure). In this way, the meshing of the initialization voltage can be achieved, and the display uniformity of the display panel PNL can be improved.

[0127] In an embodiment of the present disclosure, referring to FIG. 1, FIG. 2, FIG. 5, FIG. 6 and FIG. 11, the initialization voltage wires VIL comprise a first initialization voltage wire VIL1 used to load the first initialization voltage Vinit1 to the circuit area row HCA and extending along the row direction DH, a second initialization voltage wire VIL2 used to load the second initialization voltage Vinit2 to the circuit area row HCA and extending along the row direction DH, and a third initialization voltage wire VIL3 used to load the third initialization voltage Vinit3 to the circuit area row HCA and extending along the row direction DH. The initialization auxiliary wires VILX comprise a first initialization auxiliary wire VILX1 used to be electrically connected with each first initialization voltage wire VIL1, a second initialization auxiliary wire VILX2 used to be electrically connected with each second initialization voltage wire VIL2, and a third initialization auxiliary wire VILX3 used to be electrically connected with each third initialization voltage wire VIL3. In this way, the first initialization voltage Vinit1 loaded on the first initialization voltage wire VIL1 can be loaded on the first initialization auxiliary wire VILX1 to achieve the meshing of the first initialization voltage Vinit1; the second initialization voltage Vinit2 loaded on the second initialization voltage wire VIL2 can be loaded on the second initialization auxiliary wire VILX2 to achieve the meshing of the second initialization voltage Vinit2; and the third initialization voltage Vinit3 loaded on the third initialization voltage wire VIL3 can be loaded on the third initialization auxiliary wire VILX3 to achieve the meshing of the third initialization voltage Vinit3, further improving the display uniformity of the display panel PNL.

[0128] In an embodiment of the present disclosure, referring to FIG. 1, FIG. 2, FIG. 17, in one circuit row HCA, along the column direction DV, the orthogonal projection of the first initialization voltage wire VIL1 on the substrate SBT (not shown in the figure) is located between the orthogonal projection of the third initialization voltage wire VIL3 on the substrate SBT and the orthogonal projection of the second initialization voltage wire VIL2 on the substrate SBT, and the orthogonal projection of the first initialization voltage wire VIL1 on the substrate SBT and the orthogonal projection of the second initialization voltage wire VIL2 on the substrate SBT are located on both sides of the orthogonal projection of the corresponding second electrode plate EP2 on the substrate SBT. In this way, the reasonable layout of the corresponding first initialization voltage wire VIL1, second initialization voltage wire VIL2 and third initialization voltage wire VIL3 of one circuit row HCA is achieved.

[0129] In an embodiment of the present disclosure, referring to FIG. 1, FIG. 2, FIG. 10, FIG. 15, among the initialization auxiliary wires VILX arranged along the row direction DH, the first initialization auxiliary wire VILX1, the second initialization auxiliary wire VILX2 and the third initialization auxiliary wire VILX3 are arranged in turn in a periodical manner. In another embodiment of the present disclosure, among the initialization auxiliary wires VILX arranged along the row direction DH, the first initialization auxiliary wire VILX1, the third initialization auxiliary wire VILX3 and the second initialization auxiliary wire VILX2 can be arranged in turn in a periodical manner. In another embodiment of the present disclosure, the second initialization auxiliary wire VILX2, the first initialization auxiliary wire VILX1 and the third initialization auxiliary wire VILX3 can be arranged in turn in a periodical manner. In this way, the uniform distribution of the initialization auxiliary wires VILX in the display panel PNL can be achieved, and the display uniformity of the display panel PNL is further improved.

[0130] In an embodiment of the present disclosure, referring to FIG. 7-10, the first initialization auxiliary wire VILX1 is electrically connected to each first initialization voltage wire VIL1 through the first bridge structure VIL1T; the second initialization auxiliary wire VILX2 is electrically connected to each second initialization voltage wire VIL2 through the second bridge structure VIL2T; and the third initialization auxiliary wire VILX3 is electrically connected to each third initialization voltage wire VIL3 through the third bridge structure VIL3T. In this way, the first initialization voltage Vinit1 is loaded to the first initialization auxiliary wire VILX1, the second initialization voltage Vinit2 is loaded to the second initialization auxiliary wire VILX2, and the third initialization voltage Vinit3 is loaded to the third initialization auxiliary wire VILX3, which facilitates the meshing of the initialization voltage and improves the display uniformity of the display panel PNL.

[0131] In one embodiment of the present disclosure, referring to FIG. 1 and FIG. 2, two circuit area columns VCA are arranged between two adjacent first connection lines CL1, two circuit area columns VCA are arranged between two adjacent initialization auxiliary wires VILX, and the first connection lines CL1 and the initialization auxiliary wires VILX are arranged alternately along the row direction DH. For example, in five adjacent circuit area columns VCA, one first connection line CL1 is arranged between the first circuit area column VCA and the second circuit area column VCA along the row direction DH, one initialization auxiliary wire VILX is arranged between the second circuit area column VCA and the third circuit area column VCA, one first connection line CL1 is arranged between the third circuit area column VCA and the fourth circuit area column VCA, and one initialization auxiliary wire VILX is arranged between the fourth circuit area column VCA and the fifth circuit area column VCA. In this way, the first connection lines CL1 and the initialization auxiliary wires VILX can be arranged alternately, so as to improve the display uniformity of the display panel PNL.

[0132] The film layer structures of the driving layer DRL will be described in detail below in combination with the distribution of the positions of the transistors and the distribution of the signal wires in the 9T1C pixel driving circuit shown in FIG. 5 (wherein the driving layer DRL is shown to include a metal light shielding layer BSM, a low-temperature polysilicon semiconductor layer PSCL, a first gate layer GT1, a second gate layer GT2, a metal oxide semiconductor layer OSCL, a third gate layer GT3, a first source-drain metal layer SD1, and a second source-drain metal layer SD2 which are sequentially stacked on the substrate base plate SBT):

[0133] FIG. 16 illustrates a schematic view of the stacking of the metal light shielding layer BSM, the low-temperature polysilicon semiconductor layer PSCL, the first gate layer GT1, the second gate layer GT2, the metal-oxide semiconductor layer OSCL, the third gate layer GT3, the first source-drain metal layer SD1 and the second source-drain metal layer SD2 in one circuit area CA in an embodiment of the present disclosure. FIG. 17 illustrates a schematic view of the stacking of the metal light shielding layer BSM, the low-temperature polysilicon semiconductor layer PSCL, the first gate layer GT1, the second gate layer GT2, the metal-oxide semiconductor layer OSCL and the third gate layer GT3 in one circuit area CA in an embodiment of the present disclosure. FIG. 18 illustrates a schematic view of the stacking of the first gate layer GT1, the second gate layer GT2, the first source-drain metal layer SD1 and the second source-drain metal layer SD2 in one circuit area CA in an embodiment of the present disclosure. FIG. 19 illustrates a schematic view of the stacking of the first gate layer GT1, the second gate layer GT2 and the first source-drain metal layer SD1 in one circuit area CA in an embodiment of the present disclosure. FIG. 20 illustrates a schematic view of the metal light shielding layer BSM in an embodiment of the present disclosure. Referring to FIGS. 16, 17 and 20, the metal light shielding layer BSM includes a plurality of light shielding layer bodies BSMB arranged in an array and corresponding to each circuit area CA one by one, and a normal projection of the light shielding layer body BSMB on the substrate SBT (not shown in the figure) covers at least a normal projection of the active layer of the driving transistor T3 in the corresponding circuit area CA on the substrate SBT, so as to achieve the effect of shielding light for the driving transistor T3. The two adjacent light shielding layer bodies BSMB are electrically connected through the light shielding layer trace BSML; that is, one light shielding layer body BSMB has a total of four light shielding layer traces BSML in the row direction DH and the column direction DV. Among them, two light shielding layer traces BSML extend in the column direction DV, and the other two light shielding layer traces BSML extend in the row direction DH, so that each light shielding layer body BSMB forms a grid, which is conducive to improving the uniformity of the display panel PNL.

[0134] FIG. 21 illustrates a schematic diagram of a low-temperature polysilicon semiconductor layer PSCL in an embodiment of the present disclosure. Referring to FIGS. 16, 17 and 21, the active layers, channel regions of the driving transistors T3-T9 are located on the low-temperature polysilicon semiconductor layer PSCL. Among them, the channel region T5A of the first light-emitting control transistor, the channel region T8A of the node control transistor, and the channel region T4A of the data writing transistor are arranged along the column direction DV, the channel region T6A of the second light-emitting control transistor and the channel region T7A of the electrode reset transistor are arranged along the column direction DV, and the channel region T4A of the data writing transistor and the channel region T9A of the auxiliary transistor are arranged along the row direction DH. Along the row direction DH, the channel region T3A of the driving transistor is located between the channel region T4A of the data writing transistor and the channel region T6A of the second light-emitting control transistor. Along the column direction DV, the channel region T3A of the driving transistor is located between the channel region T6A of the second light-emitting control transistor and the channel region T9A of the auxiliary transistor, and the channel region T4A of the data writing transistor and the channel region T5A of the first light-emitting control transistor are located on both sides of the channel region T8A of the node control transistor.

[0135] The low-temperature polysilicon semiconductor layer PSCL is provided with a fourth lower via hole region HA4, a fifth lower via hole region HA5, a tenth lower via hole region HA10, an eleventh lower via hole region HA11, a twelfth lower via hole region HA12, a fourteenth lower via hole region HA14, a fifteenth lower via hole region HA15, a seventeenth lower via hole region HA17, a nineteenth lower via hole region HA19, a twentieth lower via hole region HA21, and a twenty-second lower via hole region HA22.

[0136] FIG. 22 illustrates a schematic diagram of the first gate layer GT1 in an embodiment of the present disclosure. Referring to FIGS. 17, 21 and 22, the first gate layer GT1 is provided with a first initialization voltage wire VIL1, a first emission control signal wire EM1L, a second emission control signal wire EM2L, a second reset control signal wire RH1L, a third reset control signal wire RH2L, a second scan signal wire GPL, a first electrode plate EP1. The first initialization voltage wire VIL1 extends along the row direction DH and is used to load the first initialization voltage Vinit1 to the gate reset transistor T1, and the first initialization voltage wire VIL1 has a second lower via area HA2. The first emission control signal wire EM1L extends along the row direction DH and overlaps with the channel area T5A of the first emission control transistor to form the gate of the first emission control transistor T5; the first emission control signal wire EM1L is used to load the first emission control signal EM1 to the first emission control transistor T5. The second emission control signal wire EM2L extends along the row direction DH and overlaps with the channel area T6A of the second emission control transistor to form the gate of the second emission control transistor T6; the second emission control signal wire EM2L is used to load the second emission control signal EM2 to the second emission control transistor T6. The second reset control signal wire RH1L extends along the row direction DH and overlaps with the channel area T8A of the node control transistor to form the gate of the node control transistor T8; the second reset control signal wire RH1L is used to load the second reset control signal RH1 to the node control transistor T8. The third reset control signal wire RH2L extends along the row direction DH and overlaps with the channel area T7A of the electrode reset transistor to form the gate of the electrode reset transistor T7; the third reset control signal wire RH2L is used to load the third reset control signal RH2 to the electrode reset transistor T7. The second reset control signal wire RH1L is used to load the second reset control signal RH1 to the node control transistor T8. The second scan signal wire GPL extends along the row direction DH and sequentially overlaps with the channel area T4A of the data write transistor and the channel area T9A of the auxiliary transistor to multiplex the gates of the data write transistor T4 and the auxiliary transistor T9; the second scan signal wire GPL is used to load the second scan signal GP to the data write transistor T4 and the auxiliary transistor T9. The first electrode plate EP1 overlaps with the channel area T3A of the driving transistor to serve as the gate of the driving transistor T3, and the first electrode plate EP1 has a sixth lower via area HA6.

[0137] In an embodiment of the disclosure, referring to FIG. 22, in the first gate layer GT1, the first light-emitting control signal wire EM1L, the second reset control signal wire RH1L, the first initialization voltage wire VIL1, the second scan signal wire GPL, the first electrode plate EP1, the second light-emitting control signal wire EM2L, and the third reset control signal wire RH2L are arranged in sequence along the column direction DV.

[0138] FIG. 23 illustrates a schematic diagram of the second gate layer GT2 in an embodiment of the disclosure. Referring to FIGS. 17, 23 and 24, the second gate layer GT2 is provided with the first reset control signal lower wire RNLA, the first scan signal upper wire GNLA, the second electrode plate EP2, and the second electrode wire EP2L. The first reset control signal lower wire RNLA extends along the row direction DH and overlaps with the channel region T1A of the gate reset transistor to form the gate of the gate reset transistor T1, and the first reset control signal lower wire RNLA is used to load the first reset control signal RN to the gate reset transistor T1. The first scan signal upper wire GNLA extends along the row direction DH and overlaps with the channel region T2A of the threshold compensation transistor to form the gate of the threshold compensation transistor T2, and the first scan signal upper wire GNLA is used to load the first scan signal GN to the threshold compensation transistor T2. In the same circuit area CA, the orthographic projection of the second electrode plate EP2 on the substrate SBT at least covers the orthographic projection of the first electrode plate EP1 on the substrate SBT. In the circuit area row HCA, two adjacent second electrode plates EP2 are electrically connected by the second electrode wire EP2L, and two adjacent circuit areas CA are symmetrically arranged along the column direction DV, so that the second electrode wire EP2L includes the second electrode main wire EP2L1 and the second electrode auxiliary wire EP2L2. The second electrode main wire EP2L1 and the second electrode auxiliary wire EP2L2 are electrically connected by the second electrode plate EP2, and the second electrode main wire EP2L1 and the second electrode auxiliary wire EP2L2 extend along the row direction DH. The second electrode main wire EP2L1 is provided with an eighth lower via region HA8.

[0139] Fig. 24 illustrates a schematic diagram of the metal-oxide semiconductor layer OSCL in an embodiment of the present disclosure. Referring to Figs. 17 and 24, the active layers, channel regions of the gate reset transistor T1 and the threshold compensation transistor T2 are located on the metal-oxide semiconductor layer OSCL. Among them, the channel region T1A of the gate reset transistor and the channel region T2A of the threshold compensation transistor are arranged along the column direction DV. Along the column direction DV, the orthogonal projection of the channel region T2A of the threshold compensation transistor on the substrate SBT is located on both sides of the orthogonal projection of the channel region T3A of the driving transistor on the substrate SBT. Along the row direction DH, the orthogonal projection of the channel region T2A of the threshold compensation transistor on the substrate SBT is located on both sides of the orthogonal projection of the channel region T4A of the data write transistor on the substrate SBT. The metal-oxide semiconductor layer OSCL is provided with a first lower via region HA1, a third lower via region HA3, and an eighteenth lower via region HA18.

[0140] FIG. 25 illustrates a schematic diagram of the third gate layer GT3 in an embodiment of the present disclosure. FIG. 26 illustrates a schematic diagram of the third gate layer GT3 in an embodiment of the present disclosure. In FIG. 25, a schematic diagram of the structure of the third gate layer GT3 when the second initialization voltage Vinit2 is gridded in one circuit area CA; in FIG. 26, a schematic diagram of the structure of the third gate layer GT3 when the third initialization voltage Vinit3 is gridded in one circuit area CA. Referring to FIGS. 17, 24 and 25, the third gate layer GT3 is provided with the first reset control signal upper wire RNLB, the first scan signal lower wire GNLB, the second initialization voltage wire VIL2 and the third initialization voltage wire VIL3. The first reset control signal upper wire RNLB extends along the row direction DH and overlaps the channel region T1A of the gate reset transistor to form the gate of the gate reset transistor T1; the first reset control signal upper wire RNLB is used to load the first reset control signal RN to the gate reset transistor T1. The first scan signal lower wire GNLB extends along the row direction DH and overlaps the channel region T2A of the threshold compensation transistor to form the gate of the threshold compensation transistor T2; the first scan signal lower wire GNLB is used to load the first scan signal GN to the threshold compensation transistor T2. In the same circuit area CA, the orthogonal projection of the first reset control signal upper wire RNLB on the substrate SBT overlaps the orthogonal projection of the first reset control signal lower wire RNLA on the substrate SBT, so that the gate reset transistor T1 has a double-gate structure; the orthogonal projection of the first scan signal lower wire GNLB on the substrate SBT overlaps the orthogonal projection of the first scan signal upper wire GNLA on the substrate SBT, so that the threshold compensation transistor T2 has a double-gate structure. The second initialization voltage wire VIL2 extends along the row direction DH and is used to load the second initialization voltage Vinit2 to the electrode reset transistor T7; the second initialization voltage wire VIL2 has the twentieth lower via region HA20. The third initialization voltage wire VIL3 extends along the row direction DH and is used to load the third initialization voltage Vinit3 to the node control transistor T8; the third initialization voltage wire VIL3 has the thirteenth lower via region HA13.

[0141] In one example, referring to FIG. 25, when the second initialization voltage Vinit2 is gridded, the third initialization voltage wire VIL3 has the thirteenth lower via region HA13. In another example, referring to FIG. 26, when the third initialization voltage Vinit3 is gridded, the third initialization voltage wire VIL3 has the thirteenth lower via region HA13 and the twenty-eighth lower via region HA28. In the third gate layer GT3, the third initialization voltage wire VIL3, the first reset control signal upper wire RNLB, the first scan signal lower wire GNLB and the second initialization voltage wire VIL2 of the same circuit area CA are arranged along the column direction DV in sequence.

[0142] It can be understood that the first scan signal wire GNL includes a first scan signal upper wire GNLA and a first scan signal lower wire GNLB, so that the first scan signal upper wire GNLA and the first scan signal lower wire GNLB jointly load the first scan signal GN to the threshold compensation transistor T2, thereby forming a double-gate structure of the threshold compensation transistor T2. The first reset control signal wire RNL includes a first reset control signal lower wire RNLA and a first reset control signal upper wire RNLB, so that the first reset control signal lower wire RNLA and the first reset control signal upper wire RNLB jointly load the first reset control signal RN to the gate reset transistor T1, thereby forming a double-gate structure of the gate reset transistor T1.

[0143] FIGS. 27-30 respectively illustrate a schematic diagram of the first source-drain metal layer SD1 in an embodiment of the present disclosure. FIG. 27 is a structural schematic diagram of the first source-drain metal layer SD1 when the first initialization voltage Vinit1 is gridded in one circuit area CA; FIG. 28 is a schematic diagram of the connection of the second connection line CL2, the first transfer structure LS1T and the first connection line CL1, which is intended to show the composition of the second connection line CL2; FIG. 29 is a structural schematic diagram of the first source-drain metal layer SD1 when the second initialization voltage Vinit2 is gridded in one circuit area CA; and FIG. 30 is a structural schematic diagram of the first source-drain metal layer SD1 when the third initialization voltage Vinit3 is gridded in one circuit area CA.

[0144] Referring to FIG. 27, the first source-drain metal layer SD1 includes a first bridge portion MA1, a second bridge portion MA2, a third bridge portion MA3, a fourth bridge portion MA4, a fifth bridge portion MA5, a sixth bridge portion MA6, a seventh bridge portion MA7, an eighth bridge portion MA8, a ninth bridge portion MA9, a tenth bridge portion MA10, an eleventh bridge portion MA11, a third connection sub-line CL11, a second connection line CL2, and a first transfer structure LS1T. The first source-drain metal layer SD1 further includes a first bridge structure VIL1T, a second bridge structure VIL2T, a third bridge structure VIL3T, and a second transfer structure LS2T.

[0145] FIG. 31 and FIG. 32 illustrate schematic diagrams of the second source-drain metal layer SD2 in one embodiment of the present disclosure. FIG. 31 is a schematic diagram of the structure of the second source-drain metal layer SD2 when the first initialization voltage Vinit1 or the third initialization voltage Vinit3 is gridded in one circuit area CA; FIG. 32 is a schematic diagram of the structure of the second source-drain metal layer SD2 when the second initialization voltage Vinit2 is gridded in one circuit area CA. Referring to FIG. 31 and FIG. 32, the second source-drain metal layer SD2 includes the twelfth bridge MA12, the driving power supply voltage wire VDDL, the data line DL, the fourth connection sub-wire CL12, and the initialization auxiliary wire VILX.

[0146] The first bridge MA1 is provided with a first upper via region HB1 and a second upper via region HB2. The first upper via region HB1 overlaps the first lower via region HA1 and is electrically connected by a via; the second upper via region HB2 overlaps the second lower via region HA2 and is electrically connected by a via. In this way, the first pole of the gate reset transistor T1 and the first initialization voltage wire VIL1 can be electrically connected by the first bridge MA1, so that the first initialization voltage Vinit1 can be loaded to the first pole of the gate reset transistor T1.

[0147] The second bridge MA2 is provided with a third upper via region HB3 and a fourth upper via region HB4. The third upper via region HB3 overlaps the third lower via region HA3 and is electrically connected by a via; the fourth upper via region HB4 overlaps the fourth lower via region HA4 and is electrically connected by a via. In this way, the second pole of the gate reset transistor T1, the first pole of the auxiliary transistor T9, and the second pole of the threshold compensation transistor T2 can be electrically connected by the second bridge MA2.

[0148] The third bridge MA3 is provided with a fifth upper via region HB5 and a sixth upper via region HB6. The fifth upper via region HB5 overlaps the fifth lower via region HA5 and is electrically connected by a via; the sixth upper via region HB6 overlaps the sixth lower via region HA6 and is electrically connected by a via. In this way, the second pole of the auxiliary transistor T9 and the gate of the driving transistor T3 can be electrically connected by the third bridge MA3.

[0149] The fourth bridge MA4 is provided with a seventh lower via region HA7 and an eighth upper via region HB8. The driving power supply voltage wire VDDL extends along the column direction DV, and the driving power supply voltage wire VDDL is provided with a seventh upper via region HB7. The seventh lower via region HA7 overlaps the seventh upper via region HB7 and is electrically connected by a via; the eighth upper via region HB8 overlaps the eighth lower via region HA8 and is electrically connected by a via. In this way, the driving power supply voltage wire VDDL and the second electrode plate EP2 can be electrically connected by the fourth bridge MA4.

[0150] The ninth lower via region HA9 and the tenth upper via region HB10 are arranged on the fifth bridge MA5. The ninth upper via region HB9 is further arranged on the driving power voltage wire VDDL. The ninth lower via region HA9 overlaps with the ninth upper via region HB9 and is electrically connected by a via; the tenth upper via region HB10 overlaps with the tenth lower via region HA10 and is electrically connected by a via. In this way, the driving power voltage wire VDDL and the first electrode of the first light-emitting control transistor T5 can be electrically connected through the fifth bridge MA5.

[0151] The eleventh upper via region HB11 and the twelfth upper via region HB12 are arranged on the sixth bridge MA6. The eleventh upper via region HB11 overlaps with the eleventh lower via region HA11 and is electrically connected by a via; the twelfth upper via region HB12 overlaps with the twelfth lower via region HA12 and is electrically connected by a via. In this way, the second electrode of the first light-emitting control transistor T5 and the first electrode of the driving transistor T3 can be electrically connected through the sixth bridge MA6.

[0152] The thirteenth upper via region HB13 and the fourteenth upper via region HB14 are arranged on the seventh bridge MA7. The thirteenth upper via region HB13 overlaps with the thirteenth lower via region HA13 and is electrically connected by a via; the fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14 and is electrically connected by a via. In this way, the third initialization voltage wire VIL3 and the first electrode of the node control transistor T8 can be electrically connected through the seventh bridge MA7.

[0153] The sixth bridge MA6 comprises a sixth main bridge MA61 and a sixth auxiliary bridge MA62 which are integrally connected. The eleventh upper via region HB11 is arranged on the sixth main bridge MA61, and the twelfth upper via region HB12 is arranged on the sixth auxiliary bridge MA62. The fifteenth upper via region HB15 is further arranged on the sixth auxiliary bridge MA62; the fifteenth upper via region HB15 overlaps with the fifteenth lower via region HA15 and is electrically connected by a via. In this way, the second electrode of the node control transistor T8 and the second electrode of the data write transistor T4 can be electrically connected to the first electrode of the driving transistor T3 through the sixth auxiliary bridge MA62.

[0154] The eighth bridge MA8 is provided with a sixteenth via hole area HA16 and a seventeenth via hole area HB17. The data line DL extends along the column direction DV, and the data line DL is provided with a sixteenth via hole area HB16. The sixteenth via hole area HA16 overlaps with the sixteenth via hole area HB16 and is electrically connected by a via hole; the seventeenth via hole area HB17 overlaps with the seventeenth via hole area HA17 and is electrically connected by a via hole. In this way, the data line DL and the first electrode of the data writing transistor T4 can be electrically connected through the eighth bridge MA8.

[0155] The ninth bridge MA9 is provided with an eighteenth via hole area HB18 and a nineteenth via hole area HB19. The eighteenth via hole area HB18 overlaps with the eighteenth via hole area HA18 and is electrically connected by a via hole; the nineteenth via hole area HB19 overlaps with the nineteenth via hole area HA19 and is electrically connected by a via hole. In this way, the first electrode of the threshold compensation transistor T2, the second electrode of the driving transistor T3 and the first electrode of the second light emitting control transistor T6 can be electrically connected through the ninth bridge MA9.

[0156] The tenth bridge MA10 is provided with a twentieth via hole area HB20 and a twenty-first via hole area HB21. The twentieth via hole area HB20 overlaps with the twentieth via hole area HA20 and is electrically connected by a via hole; the twenty-first via hole area HB21 overlaps with the twentieth via hole area HA21 and is electrically connected by a via hole. In this way, the second initialization voltage wire VIL2 and the first electrode of the electrode reset transistor T7 can be electrically connected through the tenth bridge MA10.

[0157] The eleventh bridge MA11 is provided with a twenty-second via hole area HB22 and a twenty-third via hole area HA23. The twelfth bridge MA12 is provided with a twenty-third via hole area HB23. The twenty-second via hole area HB22 overlaps with the twenty-second via hole area HA22 and is electrically connected by a via hole; the twenty-third via hole area HA23 overlaps with the twenty-third via hole area HB23 and is electrically connected by a via hole. In this way, the second electrode of the second light emitting control transistor T6, the second electrode of the electrode reset transistor T7 and the pixel electrode of the light emitting element can be electrically connected through the eleventh bridge MA11.

[0158] The twelfth bridge MA12 is also provided with a twenty-third via hole area HC23. The twenty-third via hole area HC23 is used to be electrically connected with the pixel electrode of the light emitting element through a via hole, so as to facilitate the electrical connection between the light emitting element and the pixel driving circuit.

[0159] Referring to FIG. 27, FIG. 28, and FIG. 31, the third connection sub-line CL11 is integrally connected with the second connection sub-line CL222 through the first adapter structure LS1T. The second connection sub-line CL222 extends along the row direction DH, and the first adapter structure LS1T and the third connection sub-line CL11 extend along the column direction DV. The second connection sub-line CL222 is provided with a twenty-fourth lower via hole area HA24, the first adapter structure LS1T is provided with a twenty-fifth lower via hole area HA25, and the third connection sub-line CL11 is provided with a twenty-sixth lower via hole area HA26; the fourth connection sub-line CL12 is provided with a twenty-fifth upper via hole area HB25 and a twenty-sixth upper via hole area HB26, and the data line DL is further provided with a twenty-fourth upper via hole area HB24. Among them, the twenty-fourth lower via hole area HA24 and the twenty-fourth upper via hole area HB24 overlap and are electrically connected through the via hole to realize the electrical connection between the data line DL and the second connection sub-line CL222. The twenty-fifth lower via hole area HA25 and the twenty-fifth upper via hole area HB25 overlap and are electrically connected through the via hole to realize the electrical connection between the second connection sub-line CL222 and the third connection sub-line CL11, and realize the electrical connection between the first adapter structure LS1T and the fourth connection sub-line CL12. The twenty-sixth lower via hole area HA26 and the twenty-sixth upper via hole area HB26 overlap and are electrically connected through the via hole to realize the electrical connection between the third connection sub-line CL11 and the fourth connection sub-line CL12, so as to facilitate the electrical connection between the first connection line CL1, the second connection line CL2, and the data line DL, and further facilitate the reasonable layout of the FIP technology.

[0160] It can be understood that in an embodiment of the present disclosure, the first adapter structure LS1T and the second adapter structure LS2T are respectively the adapter structures in the first wiring group LS1 and the second wiring group LS2, which have substantially the same structure and both realize the electrical connection between the second connection line CL2 and the first connection line CL1. However, referring to FIG. 1 and FIG. 7, in the first wiring group LS1, since one data line DL needs to realize the FIP technology through one second connection line CL2 and one first connection line CL1, the data signal on the data line DL loaded on the second connection line CL2, and one first connection line CL1 is only electrically connected with one second connection line CL2 through one first adapter structure LS1T, and one second connection line CL2 is only electrically connected with one first connection line CL1 through one first adapter structure LS1T. Referring to FIG. 2 and FIG. 12, in the second wiring group LS2, since the second connection line CL2 does not need to adapt the data line DL, each first connection line CL1 and each second connection line CL2 need to form a mesh to load the reference power supply voltage VSS, therefore, one first connection line CL1 is electrically connected with each second connection line CL2 through the second adapter structure LS2T, and one second connection line CL2 is electrically connected with each first connection line CL1 through the second adapter structure LS2T.

[0161] In an embodiment of the disclosure, referring to FIGS. 31 and 32, the second source-drain metal layer SD2, the fourth connection sub-line CL12, the data line DL, the driving power supply voltage trace VDDL, and the initialization auxiliary trace VILX extend along the column direction DV and are arranged in sequence along the row direction DH.

[0162] In an embodiment of the disclosure, referring to FIGS. 27 and 31, the first bridge MA1 is integrally connected with the first bridge structure VIL1T, and the first bridge structure VIL1T is provided with a twenty-seventh lower via hole region HA27 and extends along the column direction DV; the first initialization auxiliary trace VILX1 is provided with a twenty-seventh upper via hole region HB27. The twenty-seventh lower via hole region HA27 and the twenty-seventh upper via hole region HB27 overlap and are electrically connected through a via hole; in this way, the first initialization voltage trace VIL1 is electrically connected to the first initialization auxiliary trace VILX1 through the first bridge structure VIL1T, so that the first initialization voltage Vinit1 loaded on the first initialization voltage trace VIL1 is loaded on the first initialization auxiliary trace VILX1, the gridization of the first initialization voltage Vinit1 is realized, and the display uniformity of the display panel PNL is improved.

[0163] In an embodiment of the disclosure, referring to FIGS. 29 and 32, the tenth bridge MA10 is integrally connected with the second bridge structure VIL2T, and the second bridge structure VIL2T is provided with a twenty-seventh lower via hole region HA27, and the second initialization auxiliary trace VILX2 is provided with a twenty-seventh upper via hole region HB27. The twenty-seventh lower via hole region HA27 and the twenty-seventh upper via hole region HB27 overlap and are electrically connected through a via hole; in this way, the second initialization voltage trace VIL2 is electrically connected to the second initialization auxiliary trace VILX2 through the tenth bridge MA10 and the second bridge structure VIL2T, so that the second initialization voltage Vinit2 loaded on the first initialization voltage trace VIL1 is loaded on the second initialization auxiliary trace VILX2, the gridization of the second initialization voltage Vinit2 is realized, and the display uniformity of the display panel PNL is improved.

[0164] In an example, referring to FIG. 29, the second bridge structure VIL2T includes a horizontal segment and a vertical segment which are integrally connected. The horizontal segment is integrally connected with the tenth bridge MA10 away from one end of the vertical segment, and the twenty-seventh lower via hole region HA27 is arranged at the end of the vertical segment away from the horizontal segment. The horizontal segment extends along the row direction DH, and the vertical segment extends along the column direction DV.

[0165] In one embodiment of the present disclosure, referring to FIG. 30 and FIG. 31, the third bridge structure VIL3T is provided with a twenty-seventh lower via region HA27 and a twenty-eighth upper via region HB28, and the third initialization auxiliary wire VILX3 is provided with a twenty-seventh upper via region HB27. The twenty-seventh lower via region HA27 overlaps with the twenty-seventh upper via region HB27 and is electrically connected by a via; the twenty-eighth upper via region HB28 overlaps with the twenty-eighth lower via region HA28 and is electrically connected by a via; in this way, the third initialization voltage wire VIL3 and the third initialization auxiliary wire VILX3 are electrically connected by the third bridge structure VIL3T, so that the third initialization voltage Vinit3 loaded on the third initialization voltage wire VIL3 is loaded on the third initialization auxiliary wire VILX3, the meshing of the third initialization voltage Vinit3 is realized, and the display uniformity of the display panel PNL is improved.

[0166] Other embodiments of the present disclosure will be apparent to those skilled in the art with the consideration of the specification and practice of the disclosure disclosed herein. The present application is intended to cover any variations, uses or adaptive changes of the present disclosure following the general principles of the present disclosure and including common knowledge or conventional technical means in the art which are not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising circuit regions arranged in a row direction and a column direction; the circuit regions are provided with pixel driving circuits for driving sub-pixels; the display panel further comprises a substrate, a transistor layer, a source-drain metal layer, and a pixel layer which are sequentially stacked; wherein the transistor layer comprises a first gate layer and a second gate layer which are sequentially stacked on the substrate; the pixel driving circuit comprises a driving transistor and a storage capacitor which are arranged in the transistor layer; the storage capacitor comprises a first electrode plate arranged in the first gate layer and a second electrode plate arranged in the second gate layer, the first electrode plate serving as a gate of the driving transistor, and the second electrode plate being used for loading a driving power voltage; the display panel further comprises a plurality of data lines extending in the column direction, and a plurality of first connection lines extending in the column direction and a plurality of second connection lines extending in the row direction; the display panel has a first wiring group, the first wiring group comprising the data lines, the first connection lines, and the second connection lines which are connected to each other; the second connection lines are arranged on a side of the second electrode plate away from the substrate, and a projection of the second connection lines on the substrate overlaps a projection of the second electrode plate on the substrate.

2. The display panel of claim 1, wherein, the second gate layer further comprises a second electrode wiring for electrically connecting two second electrode plates in the same row; the second connection line comprises a first connection sub-line corresponding to the second electrode plate and a second connection sub-line corresponding to the second electrode wiring; the first connection sub-line and the corresponding second electrode plate are located in the same circuit region row, and a projection of the first connection sub-line in the row direction is located within a projection of the second electrode plate in the row direction; the second connection sub-line and the corresponding second electrode wiring are located in the same circuit region row, and a projection of the second connection sub-line in the row direction is located within a projection of the second electrode wiring in the row direction; a projection of the first connection sub-line on the substrate is located within a projection of the corresponding second electrode plate on the substrate.

3. The display panel of claim 2, wherein, the second connection sub-line comprises a second connection main sub-line and a second connection auxiliary sub-line which are sequentially and alternately arranged; the second connection main sub-line and the second connection auxiliary sub-line are connected by the first connection sub-line; a projection of the second connection main sub-line on the substrate overlaps a projection of the corresponding second electrode wiring on the substrate, and a projection of the second connection auxiliary sub-line on the substrate does not overlap a projection of the corresponding second electrode wiring on the substrate.

4. The display panel of claim 1, wherein, the source-drain metal layer comprises a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked in a direction away from the substrate; the first connection line comprises a third connection sub-line and a fourth connection sub-line which are sequentially and alternately arranged and connected in the column direction; the third connection sub-line is located in the first source-drain metal layer, and the fourth connection sub-line is located in the second source-drain metal layer; The display panel is further provided with a first switching structure corresponding to the first wiring group, and the third connection sub-wire and the second connection wire are electrically connected through the first switching structure.

5. The display panel of claim 1, wherein, The display panel further has a second wiring group; the second wiring group includes a plurality of first connection wires and a plurality of second connection wires, and the plurality of first connection wires and the plurality of second connection wires are electrically connected with each other; the second wiring group is used for loading a reference power supply voltage.

6. The display panel of claim 5, wherein, The source-drain metal layer includes a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked in a direction away from the substrate substrate. The first connection wire includes a third connection sub-wire and a fourth connection sub-wire which are sequentially and alternately arranged and connected along the column direction, the third connection sub-wire is located in the first source-drain metal layer, and the fourth connection sub-wire is located in the second source-drain metal layer. The second wiring group includes a plurality of second switching structures, and the third connection sub-wire and the second connection wire are electrically connected through the second switching structure.

7. The display panel of claim 1, wherein, The pixel driving circuit has a first light-emitting control transistor and a second light-emitting control transistor; the first electrode of the first light-emitting control transistor is electrically connected with the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is electrically connected with the second electrode of the driving transistor; The first gate layer is provided with a first light-emitting control signal wire for loading a first light-emitting control signal and extending in the row direction, and a second light-emitting control signal wire for loading a second light-emitting control signal and extending in the row direction; Along the column direction, the orthographic projection of the first light-emitting control signal wire on the substrate substrate and the orthographic projection of the second light-emitting control signal wire on the substrate substrate are located on both sides of the orthographic projection of the corresponding first electrode plate on the substrate substrate; The first light-emitting control signal wire is electrically connected with the gate of the first light-emitting control transistor; The second light-emitting control signal wire is electrically connected with the gate of the second light-emitting control transistor.

8. The display panel of claim 1, wherein, The pixel driving circuit has an electrode reset transistor, a node control transistor and a light-emitting element; the first electrode of the electrode reset transistor is electrically connected with the pixel electrode of the light-emitting element; the second electrode of the node control transistor is electrically connected with the first electrode of the driving transistor; The first gate layer is provided with a second reset control signal wire for loading a second reset control signal and extending in the row direction, and a third reset control signal wire for loading a third reset control signal and extending in the row direction; along the column direction, the orthographic projection of the second reset control signal wire on the substrate substrate and the orthographic projection of the third reset control signal wire on the substrate substrate are located on both sides of the orthographic projection of the corresponding first electrode plate on the substrate substrate; The second reset control signal wire is electrically connected with the gate of the node control transistor; The third reset control signal wire is electrically connected with the gate of the electrode reset transistor.

9. The display panel of claim 1, wherein, The display panel further comprises a plurality of initialization auxiliary wires extending along the column direction; the first connection wires and the initialization auxiliary wires are arranged alternately in sequence; the initialization auxiliary wires are used to electrically connect with the initialization voltage wires in the transistor layer.

10. The display panel of claim 9, wherein, The initialization voltage wires comprise first initialization voltage wires used to load first initialization voltage to circuit rows and extending along the row direction, second initialization voltage wires used to load second initialization voltage to circuit rows and extending along the row direction, and third initialization voltage wires used to load third initialization voltage to circuit rows and extending along the row direction. The initialization auxiliary wires comprise first initialization auxiliary wires used to electrically connect with each of the first initialization voltage wires, second initialization auxiliary wires used to electrically connect with each of the second initialization voltage wires, and third initialization auxiliary wires used to electrically connect with each of the third initialization voltage wires.

11. The display panel of claim 10, wherein, In one circuit row, along the column direction, the orthogonal projection of the first initialization voltage wire on the substrate substrate is located between the orthogonal projection of the third initialization voltage wire on the substrate substrate and the orthogonal projection of the second initialization voltage wire on the substrate substrate, and the orthogonal projection of the first initialization voltage wire on the substrate substrate and the orthogonal projection of the second initialization voltage wire on the substrate substrate are located on both sides of the orthogonal projection of the corresponding second electrode plate on the substrate substrate.

12. The display panel of claim 10, wherein, In each of the initialization auxiliary wires arranged along the row direction, the first initialization auxiliary wire, the second initialization auxiliary wire, and the third initialization auxiliary wire are arranged periodically in sequence.

13. The display panel of claim 10, wherein, The first initialization auxiliary wire and each of the first initialization voltage wires are electrically connected through a first bridge structure; the second initialization auxiliary wire and each of the second initialization voltage wires are electrically connected through a second bridge structure; and the third initialization auxiliary wire and each of the third initialization voltage wires are electrically connected through a third bridge structure.

14. The display panel according to any one of claims 9 to 13, wherein Two circuit columns are arranged between two adjacent first connection wires, two circuit columns are arranged between two adjacent initialization auxiliary wires, and along the row direction, the first connection wires and the initialization auxiliary wires are arranged alternately in sequence.

15. A display device comprising the display panel of any one of claims 1-14.

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