Projection device and projection image processing method

Abstract

The present application relates to a projection device and a projection image processing method. The device comprises: a system-level control circuit, configured to receive a raw image signal sent by a video signal source and convert the raw image signal into an intermediate image signal that matches a display processing control circuit; the display processing control circuit, configured to divide the intermediate image signal into a plurality of signal segments according to row content or column content of an image characterized by the intermediate image signal, sequentially perform buffer processing on the plurality of signal segments to obtain buffer signals, and, according to a refresh rate configured for the display processing control circuit, convert the buffer signals into display drive signals corresponding to pixel content of different primary colors; and a display drive chip, configured to, for a plurality of spatially adjacent pixel sets loaded on the display drive chip, modulate projection light beams on the basis of the display drive signal of each pixel set.

Description

Projection device and projection image processing method

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 2024112965339, filed on September 14, 2024, entitled "A projection device and a projection image processing method", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of display devices, in particular to a projection device and a projection image processing method. BACKGROUND

[0004] With the rapid development of display technology, various display devices have emerged. Among them, the projection device can convert the received image signal into a projection picture and project it onto the screen for the user to watch.

[0005] The traditional projection device has obvious delay in the processing of the projection image. In the scene with high real-time requirement such as instant messaging interaction and online game, the delay in processing the projection image will seriously affect the display effect of the projection image. SUMMARY

[0006] The present application provides a projection device and a projection image processing method to solve the problem that the delay in processing the projection image of the traditional projection technology limits the application scene.

[0007] In a first aspect, some embodiments provide a projection device, comprising a system-level control circuit, a display processing control circuit and a display driving chip, wherein the display processing control circuit is connected to the system-level control circuit and the display driving chip.

[0008] The system-level control circuit is configured to:

[0009] receive an original image signal sent by a video signal source, and convert the original image signal into an intermediate image signal matched with the display processing control circuit;

[0010] The display processing control circuit is configured to:

[0011] According to the row content or column content of the image represented by the intermediate image signal, the intermediate image signal is divided into a plurality of signal segments, and the plurality of signal segments are sequentially subjected to cache processing to obtain a cache signal;

[0012] According to the refresh rate configured for the display processing control circuit, the cache signal is converted into a display driving signal corresponding to the pixel content of different primary color lights;

[0013] The display driving chip is configured to:

[0014] The display driving chip is configured to:

[0015] According to the display driving signal of each pixel set, the display driving chip modulates the projection light beam.

[0016] The signal conversion module is configured to receive the original image signal sent by the video signal source and convert the original image signal into an intermediate image signal matched with the display processing control circuit.

[0017] According to the row content or column content of the image represented by the intermediate image signal, the signal conversion module divides the intermediate image signal into a plurality of signal segments and sequentially buffers the plurality of signal segments to obtain a buffered signal.

[0018] According to the refresh rate configured for the display processing control circuit, the refresh module converts the buffered signal into a display driving signal corresponding to the pixel content of different primary color light.

[0019] According to the display driving signal of each pixel set, the display driving chip modulates the projection light beam.

[0020] The display processing control circuit is configured to:

[0021] The signal conversion module is configured to receive the original image signal sent by the video signal source and convert the original image signal into an intermediate image signal matched with the display processing control circuit.

[0022] According to the row content or column content of the image represented by the intermediate image signal, the signal conversion module divides the intermediate image signal into a plurality of signal segments and sequentially buffers the plurality of signal segments to obtain a buffered signal.

[0023] According to the refresh rate configured for the display processing control circuit, the refresh module converts the buffered signal into a display driving signal corresponding to the pixel content of different primary color light.

[0024] According to the display driving signal of each pixel set, the display driving chip modulates the projection light beam.

[0025] In a fourth aspect, some embodiments further provide a projection device. The projection device comprises a memory and a processor, the memory stores a computer program, and the processor implements the steps of the projection image processing method provided in the second aspect when executing the computer program.

[0026] In a fifth aspect, some embodiments further provide a computer readable storage medium. The computer readable storage medium stores a computer program, and the computer program implements the steps of the projection image processing method provided in the second aspect when executed by a processor.

[0027] In a sixth aspect, some embodiments further provide a computer program product. The computer program product comprises a computer program, and the computer program implements the steps of the projection image processing method provided in the second aspect when executed by a processor.

[0028] According to the above technical solution, the original image signal is converted to obtain an intermediate image signal, the intermediate image signal is divided into a plurality of signal segments, the segment rolling buffer processing is performed on the intermediate image signal to obtain a buffer signal, the delay in the image signal buffer process can be reduced, the buffer signal is converted into a display driving signal corresponding to the pixel content of different primary color light according to the refresh rate configured for the display processing control circuit, the delay in the pixel color refresh process can be reduced by configuring a relatively high refresh rate, and the display processing delay can be reduced by modulating the projection light beam according to the display driving signal of each pixel set loaded on the display driving chip. The image signal buffer, pixel color refresh and display processing are comprehensively optimized, the delay in the projection image display processing can be systematically reduced, the display requirement in a scene with high real-time requirement can be matched, the application scenarios of the projection device can be expanded, and the display effect can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0030] FIG. 1 is a structural schematic diagram of a projection device according to some embodiments of the present application;

[0031] FIG. 2 is a projection imaging light path principle diagram of the projection device according to some embodiments of the present application;

[0032] FIG. 3 is a composition schematic diagram of a projection system according to some embodiments of the present application;

[0033] FIG. 4 is a schematic diagram of a circuit control of a projection device according to some embodiments of the present application;

[0034] FIG. 5 is a schematic diagram of a chip structure of a projection device according to some embodiments of the present application;

[0035] FIG. 6 is a schematic diagram of an implementation principle of a segment scrolling buffer processing according to some embodiments of the present application;

[0036] FIG. 7 is a schematic diagram of color components of an RGB image according to some embodiments of the present application;

[0037] FIG. 8 is a schematic diagram of refresh periods under different refresh frequencies according to some embodiments of the present application;

[0038] FIG. 9 is a schematic diagram of refresh periods supporting variable refresh rates according to some embodiments of the present application;

[0039] FIG. 10 is a schematic diagram of a display driving process according to some embodiments of the present application;

[0040] FIG. 11 is a schematic diagram of a block loading process according to some embodiments of the present application;

[0041] FIG. 12 is a schematic diagram of a principle of pixel color refresh according to some embodiments of the present application;

[0042] FIG. 13 is a schematic diagram of a structure of a system-level control circuit according to some embodiments of the present application;

[0043] FIG. 14 is a schematic diagram of a structure of a display processing control circuit according to some embodiments of the present application;

[0044] FIG. 15 is a schematic diagram of a flow of a projection image processing method according to some embodiments of the present application. DETAILED DESCRIPTION

[0045] The embodiments will be described in detail with reference to the drawings, of which examples are shown. In the following description, references are made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments. Differing embodiments do not necessarily exhibit all of the described aspects of the application. The embodiments described in the following are merely illustrative of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0046] It should be noted that the brief description of terms in the present application is only for the convenience of understanding the following described embodiments, and is not intended to limit the embodiments of the present application. Unless otherwise specified, these terms should be understood according to their ordinary and general meanings.

[0047] The terms "first", "second", "third", and the like in the description and in the claims of the present application and above-described drawings are used for distinguishing between similar or identical objects and do not necessarily have to indicate a specific order or sequence, unless otherwise specified. It is to be understood that the terms so used are interchangeable under appropriate circumstances.

[0048] The terms "comprises", "comprising", "includes", "including", "has", "having" and their conjugates, as used herein, are intended to cover the presence of a stated component, but not to preclude the presence or addition of one or more other components, whether or not they are listed in the specification.

[0049] The term "module" refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software codes that can perform the function related to the component.

[0050] In embodiments of the present application, the projection device refers to a device having the ability of projecting image display and data processing. For example, the projection device includes, but is not limited to, a smart television, a projector, an advertising screen, a wearable device, a virtual reality device, an augmented reality device, etc.

[0051] FIG. 1 is a structural diagram of a projection device according to some embodiments. Referring to FIG. 1, the projection device 1 includes a light source 10, a light modulation assembly 20, and a lens 30. The projection device 1 can further include a housing 40 (only part of the housing 40 is shown in FIG. 1).

[0052] The light source 10 is configured to provide an illumination light beam (e.g., a laser light beam). The light modulation assembly 20 is configured to modulate the illumination light beam provided by the light source 10 using an image signal to obtain a projection light beam. The lens 30 is configured to project the projection light beam on a screen or a wall to form a projection picture. The light source 10, the light modulation assembly 20, and the lens 30 can be assembled in the housing 40.

[0053] In some embodiments, the light source 10, the light modulation assembly 20, and the lens 30 can be connected in sequence along the direction of light beam propagation.

[0054] The light source 10, the light modulation assembly 20, and the lens 30 can be respectively wrapped by corresponding housings. The respective housings of the light source 10, the light modulation assembly 20, and the lens 30 can support the corresponding optical components and make the optical components meet certain sealing or airtightness requirements.

[0055] One end of the light modulation assembly 20 is connected with the lens 30, and the light modulation assembly 20 and the lens 30 are arranged along the direction of projection light beam emission (e.g., parallel to the N direction) of the projection device 1. The other end of the light modulation assembly 20 can be connected with the light source 10.

[0056] In some embodiments, the arrangement direction of the light source 10 and the light modulation component 20 is substantially perpendicular to the arrangement direction of the light modulation component 20 and the lens 30, i.e., in the projection device 1, the exiting direction of the projection light beam (e.g., parallel to the N direction) is substantially perpendicular to the exiting direction of the illumination light beam (e.g., parallel to the M direction). Such a connection structure can on the one hand adapt to the light path characteristics of the reflective light valve (to be described below) in the light modulation component 20, and on the other hand, is also conducive to shortening the length of the light path in a single direction, so that more space can be provided for arranging the components of the projection device 1.

[0057] FIG. 2 is a schematic diagram of a projection imaging light path of a projection device according to some embodiments. Referring to FIG. 2, the illumination light beam emitted by the light source 10 enters the light modulation component 20. The light source 10 includes a laser component, which in some examples can emit blue laser light, and further includes a wavelength conversion device configured to receive the blue laser light and excite it to generate other primary colors in addition to blue, so that the blue laser light and the other primary colors generated by excitation together form the illumination light beam. In other examples, the light source 10 includes a three-color laser component configured to emit a three-color laser light beam, and does not need to provide a wavelength conversion device, and the three-color laser light has a wide color gamut and high brightness, and can provide a high-quality illumination light beam.

[0058] The light modulation component 20 includes a light valve 240. The light valve 240 is configured to modulate the illumination light beam incident thereon into a projection light beam according to an image signal, and to direct the projection light beam to the lens 30.

[0059] The light modulation component 20 further includes a first light homogenizing component 210. The first light homogenizing component 210 and the light valve 240 are arranged in sequence along the propagation direction of the light beam. The first light homogenizing component 210 is configured to homogenize the illumination light beam incident thereon and direct the homogenized light beam to the light valve 240.

[0060] In some embodiments, the first light homogenizing component 210 is a light pipe. The light pipe receives the illumination light beam provided by the light source 10 and homogenizes the illumination light beam. In some embodiments, the light exit port of the light pipe is rectangular. The light pipe can shape the light spot of the light beam so that the shape of the light spot of the light beam matches the shape of the light valve. In some embodiments, the first light homogenizing component 210 can also be a compound eye lens.

[0061] The light valve 240 can be a reflective light valve. The light valve 240 includes a plurality of reflective pieces, each of which corresponds to a pixel in the projection image. Illustratively, according to the projection image to be displayed, the reflective pieces of the light valve 240 corresponding to the pixels to be displayed in a bright state can reflect the light beam to the lens 30, and the light beam reflected to the lens 30 is referred to as a projection light beam. In this way, the light valve 240 can modulate the illumination light beam to obtain a projection light beam, and display the image through the projection light beam.

[0062] In some embodiments, the light valve 240 is a Digital Micromirror Device (DMD). The Digital Micromirror Device includes a plurality of (e.g., thousands of) tiny mirrors that can be individually driven to rotate. The plurality of tiny mirrors can be arranged in an array. One tiny mirror (e.g., each tiny mirror) corresponds to one pixel in the projected image to be displayed.

[0063] With continued reference to FIG. 2, in some embodiments, the projection device 1 can further include an illumination lens group between the light valve 240 and the first light uniformizing component 210. The illumination lens group includes a mirror 220, a convex lens 230, and a prism assembly 250. The light beam that has been uniformized by the first light uniformizing component 210 can be directed to the light valve 240 by the illumination lens group.

[0064] The illumination light beam emitted from the first light uniformizing component 210 is directed to the mirror 220, which reflects the illumination light beam directed thereto to the convex lens 230. The convex lens 230 converges the illumination light beam directed thereto to the prism assembly 250, which reflects the illumination light beam directed thereto to the light valve 240.

[0065] FIG. 3 provides a projection system including a projection device body and a projection screen.

[0066] FIG. 4 is a circuit control schematic diagram of a projection device.

[0067] The projection device 1 includes a display control circuit 130. The display control circuit 130 is connected to a front-end multimedia signal board (also referred to as a system SOC board, configured to decode audio and video streams). After receiving a video signal, the display control circuit 130 can process the video signal (e.g., perform geometric correction processing), and can also generate a dimming signal based on the processed video signal.

[0068] The projection device 1 further includes a light source driving circuit 140. The display control circuit 130 is connected to the light source driving circuit 140, so that the display control circuit 130 can transmit the dimming signal to the light source driving circuit 140.

[0069] The dimming signal can include an analog dimming (Adim) signal and a pulse width modulation (Pwm) signal.

[0070] The Pwm signal is configured to control the presence or absence of a driving current transmitted to the light source, and the Adim signal in the dimming signal is configured to control the magnitude of the current value of the driving current. In the following embodiments, a laser light source 50 is taken as an example for illustration.

[0071] The light source driving circuit 140 can also be referred to as a laser source driving circuit, and can be a DC-DC conversion circuit, for example, a voltage boosting circuit or a voltage reducing circuit.

[0072] The light source driving circuit 140 is configured to receive a dimming signal and a power supply input voltage of the power supply circuit 110, and convert the input power supply input voltage into a power supply output voltage based on the dimming signal, and output a driving current to the laser light source 50.

[0073] The laser light source 50 emits light under the driving of the driving current and transmits the light to the light modulation assembly 20.

[0074] The laser light source 50 can include at least one laser 51, and the color of the light beams emitted by the at least one laser 51 can be the same or different.

[0075] Each laser 51 can include a plurality of laser light emitting chips.

[0076] The laser light source 50 can include a single-color laser or a multi-color laser, such as a dual-color laser including a red laser and a blue laser, or a three-color laser including a red laser, a blue laser, and a green laser.

[0077] The number of light source driving circuits 140 is the same as the number of lasers 51, and each light source driving circuit 140 corresponds to one laser 51.

[0078] In this example, the laser light source 50 includes a three-color laser including a red laser, a blue laser, and a green laser. Then, the projection device includes a red light source driving circuit 140_R, a green light source driving circuit 140_G, and a blue light source driving circuit 140_B. Each of the three lasers 51 is connected to its corresponding light source driving circuit 140.

[0079] The three-color lasers 51 can emit red light, green light, and blue light, respectively, under the driving of the driving current. Based on the principle of color synthesis in optics, the three colors of light can be combined and uniformized to obtain white light.

[0080] Continuing to refer to FIG. 4, the light beams emitted by the laser light source 50 are transmitted to the light modulation assembly 20.

[0081] The digital micromirror device (DMD) and a DMD driving circuit are integrated in the light modulation assembly 20. The DMD is a core light modulation device of the light modulation assembly 20. The DMD driving circuit is configured to drive the DMD to work based on a video signal. In this way, the DMD is configured to modulate the light beam emitted by the laser light source 50 under the control of the DMD driving circuit to obtain an image to be projected and displayed.

[0082] For example, the DMD receives a driving control signal corresponding to an image signal, and flips the surface of tens of thousands of tiny mirrors by a positive angle or a negative angle corresponding to the driving control signal, forms an image to be projected and displayed by a light beam irradiating the surface, and reflects the light beam into a projection lens.

[0083] The light modulation assembly 20 transmits the image to be projected and displayed to the projection lens, which can magnify the image to be projected and displayed and project the image to be projected and displayed in the form of a light beam to a target object. The target object can be a projection screen or a wall surface.

[0084] The projection lens can be an ultra-short-focus projection lens, which is configured to project an image light beam onto a projection screen to realize projection image display. The projection device in the embodiment example can be an ultra-short-focus projection device.

[0085] In some embodiments, as shown in FIG. 5, a projection device is provided, which includes a system-level control circuit 510, a display processing control circuit 520, and a display driving chip 530. The display processing control circuit 520 is connected to the system-level control circuit 510 and the display driving chip 530.

[0086] The system-level control circuit 510 is configured to receive an original image signal sent by a video signal source, and convert the original image signal into an intermediate image signal matched with the display processing control circuit. The display processing control circuit 520 is configured to divide the intermediate image signal into a plurality of signal segments according to the row content or column content of the image represented by the intermediate image signal, sequentially perform segment rolling buffer processing on each signal segment to obtain a buffer signal, and convert the buffer signal into a display driving signal corresponding to the pixel content of different primary color lights according to a refresh rate supported by the display processing control circuit 520. The display driving chip 530 is configured to modulate a projection light beam according to the display driving signal of each pixel set loaded on the display driving chip 530.

[0087] The system-level control circuit 510 can be installed on a multimedia signal board, the display processing control circuit 520 can include the display control circuit 130, and the display driving chip 530 can be disposed with the light source driving circuit 140.

[0088] In this embodiment, the system-level control circuit can receive an original image signal sent by a video signal source and a frame rate of the original image signal. The frame rate refers to the frequency of images appearing on a projection screen in units of frames, or can be understood as the number of images displayed on the projection screen per second. The video signal source can be a signal source that establishes a communication connection with the system-level control circuit. The video signal source can include an HDMI (high definition multimedia interface) signal source, an analog / digital television channel signal source, a USB (universal serial bus) channel signal source, or a network video application signal source. The network video application signal source can be a background server of an application installed in the projection device. The application can be a fitness, video call, search, or game application.

[0089] That is, the system-level control circuit can receive an original image signal sent by a video signal source and convert the original image signal to an intermediate image signal recognizable by a display processing control circuit at the back end by processing the original image signal. The intermediate image signal can be, for example, a timing signal. The processing of the original image signal can include, for example, at least one of gamut conversion, high dynamic range (HDR) adjustment, resolution adjustment, and the like.

[0090] The display processing control circuit can obtain the intermediate image signal output by the system-level control circuit, perform a cache processing on the intermediate image signal to obtain a cache signal, and then perform a pixel color refresh processing on an image represented by the cache signal to obtain a display driving signal of the image.

[0091] That is, as shown in FIG. 6, the display processing control circuit can divide the intermediate image signal into a plurality of signal segments according to the row content or column content of the image represented by the intermediate image signal. Thus, the display processing control circuit can perform a cache processing on each signal segment in sequence in units of segments to implement a segment rolling buffer processing.

[0092] In some embodiments, the display processing control circuit can divide the intermediate image signal corresponding to a complete image frame into N segments evenly, and each signal segment corresponds to a part of the image frame.

[0093] In some embodiments, N is a positive integer greater than or equal to 3.

[0094] The segment rolling buffer processing procedure for the image frame is essentially to sequentially perform rolling buffer on the intermediate image signal corresponding to the image frame according to signal segments. The advantage of this buffer mode is that the storage space unit is a segment, which is smaller than the storage space unit of a frame or the storage space unit of a half frame in related technologies. The storage space and the image delay are positively correlated, that is, the smaller the storage space, the smaller the image delay, and vice versa. It can be understood that in the segment rolling buffer processing procedure, the actual delay time is the ratio of the single frame image refresh time to the number of segments. For example, in FIG. 6, when the frame rate of the intermediate image signal is 120 Hz, the single frame image refresh time is 1 / 120 Hz, that is, 8.3 ms, and if the number of segments is 10, the actual delay time in the segment rolling buffer processing procedure is equal to 8.3 ms divided by 10, that is, 0.83 ms.

[0095] As shown in Table 1, compared with the first mode (for example, single buffer processing) and the second mode (for example, double buffer processing) in related technologies, the delay time of the segment rolling buffer processing provided by the present application is the shortest. The delay time of the first mode is one frame image refresh time, and the delay time of the second mode is half frame image refresh time. For example, when the frame rate of the intermediate image signal is 120 Hz, the delay time of the first mode is 8.3 ms x 1 = 8.3 ms, the delay time of the second mode is 8.3 ms x 0.5 = 4.16 ms, and when the segment buffer processing is adopted and the intermediate image signal is divided into 10 signal segments, the delay time is 8.3 ms / 10 = 0.83 ms. Wherein, VSYNC is the field frequency or frame frequency of the input original image signal, which corresponds to the frame rate of the intermediate image signal. For example, when the original image signal is 3840x2160@60Hz, VSYNC is equal to 60Hz.

[0096] Table 1: Comparison of buffer processing delay of different buffer processing modes

[0097] It should be noted that the number of segments of the intermediate image signal can be a fixed value configured, or can change with the change of the intermediate image signal.

[0098] In some embodiments, to ensure the smooth progress of signal buffer processing, the display processing control circuit can determine the number of segments according to the signal processing capability of itself and the data amount of the intermediate image signal. For example, the number of segments can be determined by machine learning, or determined based on a mapping table in which the relationship between the number of segments and the signal processing capability and the data amount of the intermediate image signal is stored. The number of segments is inversely related to the signal processing capability and positively related to the data amount of the intermediate image signal.

[0099] In some embodiments, the display processing control circuit can determine the number of segments of the intermediate image signal according to a desired delay duration in the signal buffering process and a single-frame image refresh time corresponding to the intermediate image signal, so that the buffering delay of the intermediate image signal is equal to the desired delay duration.

[0100] After obtaining the buffered signal, the display processing control circuit needs to perform pixel color refresh processing on the image represented by the buffered signal, and convert the buffered signal into a display driving signal corresponding to the pixel content of different primary color light. As shown in FIG. 8, each frame of image corresponds to one complete R, G, B color refresh cycle (CC), and each frame of image can be decomposed into R component, G component and B component. The CC corresponds to the refresh time of one frame of image.

[0101] In some embodiments, the refresh rate can be configured as the highest refresh rate supported by the display processing control circuit. The highest refresh rate supported by the display processing control circuit can be the maximum value of the refresh rate configured based on the performance of the display processing control circuit.

[0102] In some embodiments, for a display processing control circuit based on DLP (Digital Light Processing) technology, the pixel color refresh processing is usually performed at an integer multiple of 4 of the VSYNC. For example, in the case of VSYNC being 60 Hz, 1 CC corresponds to 60 Hz, 4 CC corresponds to 240 Hz, and 8 CC corresponds to 480 Hz.

[0103] That is, the DLP chip divides the 4K resolution intermediate image signal transmitted by the system-level control circuit into four 2K resolution sub-frame signals, and uses image algorithm function and a mirror to realize pixel multiplication. Taking the case where the resolution of the DMD is 1920x1080 (2K resolution) and the resolution of the image represented by the buffered signal is 3840x2160 (4K resolution) as an example. First, the 4K resolution image signal to be displayed is processed by image algorithm (sampling and framing), that is, one frame of 4K resolution image signal is divided into four 2K resolution sub-frame signals, and then the four sub-frame signals are displayed in time using a mirror. The mirror is a device that can change the direction of light. Using one mirror to perform two-dimensional motion up, down, left and right, the refresh display of four 2K resolution sub-frame images can be completed, and finally the 4K resolution image display is completed within one VSYNC cycle.

[0104] As shown in FIG. 8, Frame2 and Frame3 represent the 2nd frame image and the 3rd frame image respectively, and so on. If the pixel color refresh processing is performed at the refresh rate of 8CC, each 2K resolution sub-frame image corresponds to 2 complete R, G, B color refresh periods, i.e. 1 sub-frame refresh period = 2*RGBframe. If the pixel color refresh processing is performed at the refresh rate of 16CC, each 2K resolution sub-frame image corresponds to 4 complete R, G, B color refresh periods, i.e. 1 sub-frame refresh period = 4*RGBframe.

[0105] As shown in Table 2, in the pixel color refresh processing, the higher the refresh rate, the smaller the pixel color refresh delay.

[0106] Table 2 comparison of pixel color refresh delay under different refresh rates

[0107] In practical applications, the frame rate of the intermediate image signal output by the system-level control circuit is not fixed, for example, it can be changed according to 30Hz, 60Hz, 120Hz. In this case, as shown in FIG. 9, the pixel color refresh processing can be performed at a fixed refresh rate of 16CC to ensure that the display device better matches the signal frame rate output by the game console or computer, and can reduce the problems of image color separation and flicker, and bring a smoother visual experience.

[0108] As shown in Table 3, for the display processing control circuit, the total display processing delay t total is equal to the sum of the cache processing delay t input and the pixel color refresh delay t process . According to Table 3, the total display processing delay t total is related to the cache processing mode, and the t input of the segment cache processing is the shortest, and the total display processing delay t total is related to the pixel color refresh rate, and the higher the refresh rate, the smaller the t process . In summary, the display processing control circuit can minimize the display processing delay by selecting the segment cache processing and applying the highest refresh rate supported by itself. As shown in Table 3, the shortest delay t total may be only 1.33ms.

[0109] Table 3 comparison of total display processing delay under different processing modes

[0110] The obtained display driving signal is transmitted to a display driving chip connected with the display processing control circuit, so as to modulate the projection light beam by the display driving signal, and realize image loading and display. As shown in FIG. 10, the image data display driving process includes data loading, display synchronization pulse, refreshing display, data clearing instruction, clearing synchronization pulse, clearing completion and the like. The display driving chip divides the data of one frame of image into a plurality of spatially adjacent pixel sets (BLOCK), such as BLOCK0#-BLOCK15# in FIG. 11. Then, the loading of display driving signal is performed on each pixel set in turn according to the steps of BLOCK data loading, BLOCK display synchronization pulse, BLOCK refreshing display, BLOCK data clearing instruction, BLOCK clearing synchronization pulse and BLOCK clearing completion. After the clearing completion step of the last BLOCK is completed, the modulation of the projection light beam is completed, and then the light beam is projected into the projection picture to display the image represented by the original image signal. As shown in FIG. 11, since the multiple pixel sets can be processed synchronously during the loading process of the driving signal, the delay caused by the loading process of the driving signal can be reduced. For example, the third step in FIG. 11 loads the data of BLOCK1# at the same time when BLOCK0# displays the synchronization pulse.

[0111] It should be noted that the way of dividing the image into a plurality of pixel sets is not unique. For example, as shown in FIG. 11, the image can be divided according to the row content. In other examples, the image can also be divided according to the column content, and the division of the pixel sets can also be performed on the row and the column respectively. The loading sequence of the display driving signal of different pixel sets is also not unique. Taking FIG. 11 as an example, the display driving signal can be loaded in the order from top to bottom, or in the order from bottom to top, or in the order from the middle to the edge. In summary, the division way of the pixel sets and the loading sequence of the display driving signal are not limited in the embodiment.

[0112] The above technical scheme has the following advantages or beneficial effects: the intermediate image signal converted from the original image signal is divided into multiple signal segments, segment rolling cache processing is realized for the intermediate image signal, a cache signal is obtained, and the delay in the image signal cache process can be reduced; the cache signal is converted into a display driving signal corresponding to the pixel content of different primary color light according to the refresh rate configured for the display processing control circuit, the delay in the pixel color refresh processing process can be reduced by configuring a relatively high refresh rate; for a plurality of pixel sets that are spatially adjacent and loaded onto the display driving chip, the projection light beam is modulated according to the display driving signal of each pixel set, and the delay in the display processing process can be reduced. The application can systematically reduce the delay in the projection image display processing process by comprehensively optimizing the image signal cache, pixel color refresh and display processing processes, so as to match the display requirements in scenarios with relatively high real-time requirements, which is beneficial to expand the application scenarios of the projection equipment and improve the display effect.

[0113] In some embodiments, the system-level control circuit, when receiving the original image signal sent by the video signal source and converting the original image signal into the intermediate image signal matched with the display processing control circuit, is configured to: obtain the original image signal sent by each of the plurality of video signal sources; and convert each original image signal into an intermediate image signal matched with the display processing control circuit.

[0114] The projection equipment of the application can be applied to a single-channel video processing scene, and can also be applied to a multi-channel video processing scene. In the multi-channel video processing scene, the system-level control circuit can simultaneously receive the original image signal corresponding to each of the plurality of video signal sources. For example, in a multi-functional conference room scene, different types of video signal sources can be connected through multiple input interfaces to realize multi-channel signal source projection display; for another example, in a scene detection scene, the original image signal sent by a terminal held by a different player can be received to realize rapid switching and efficient demonstration of a game picture.

[0115] That is, the system-level control circuit can obtain the original image signal sent by each of the plurality of video signal sources. Then, each original image signal is processed and converted into an intermediate image signal matched with the display processing control circuit.

[0116] It should be noted that the process of converting different original image signals into corresponding intermediate image signals can be the same or different. For example, the system-level control circuit can perform brightness adjustment on the original image signal if the brightness of the image represented by the original image signal exceeds the set brightness range, and no brightness adjustment is performed if the brightness of the image represented by the original image signal is within the set brightness range. For another example, the system-level control circuit can perform HDR adjustment on the original image signal of a professional or commercial level image according to the type of the image represented by the original image signal, so as to improve the quality and visual effect of the subsequently displayed image. The professional or commercial level image can include a movie, a game, an advertisement, etc.

[0117] The above technical solution has the following advantages or beneficial effects: in a multi-path video processing scene, the system-level control circuit converts each original image signal into an intermediate image signal matched with the display processing control circuit, which can match the projection requirements of the multi-path video processing scene, and is conducive to expanding the application scenarios of the projection device.

[0118] In some embodiments, when the system-level control circuit converts each original image signal into an intermediate image signal matched with the display processing control circuit, it is configured to: obtain a target resolution configured for a projection picture; for each original image signal, perform scaling processing on the original image signal if the image resolution corresponding to the original image signal is inconsistent with the target resolution, to obtain a target image signal corresponding to the target resolution; and convert the target image signal into an intermediate image signal matched with the display processing control circuit.

[0119] The target resolution configured for the projection picture refers to the resolution of the projection display device output to the screen. In some embodiments, the target resolution can refer to the physical resolution of the projection device, such as 1080p (1920*1080) or 4K (3840*2160), etc. In some embodiments, the target resolution can also be a resolution set by the user through the controller. It can be understood that the set resolution usually does not exceed the physical resolution of the device to ensure the clarity of the displayed picture.

[0120] That is, the system-level control circuit can obtain a target resolution configured for a projection picture on the one hand, and perform resolution detection on each input original image signal on the other hand to determine the image resolution corresponding to each original image signal. In some embodiments, the system-level control circuit can use a method based on pixel clock counting to perform resolution detection on the original image signal to determine the image resolution corresponding to the original image signal.

[0121] Among them, the method based on pixel clock counting is usually used for resolution detection of video signal. First, the rising edge or falling edge of field signal is detected as the beginning of a frame of video, then the pixel clock is counted when the DE (Data Enable) signal is valid, and the count value recorded when the current DE signal is invalid is the valid pixel number of the frame.

[0122] For each original image signal, after determining the image resolution corresponding to the original image signal, the system-level control circuit can compare the image resolution with the target resolution of the projection picture. In the case that the image resolution is consistent with the target resolution, the original image signal does not need to be scaled and is directly converted into an intermediate image signal matching the display processing control circuit; in the case that the image resolution is inconsistent with the target resolution, the system-level control circuit needs to scale the original image signal to obtain a target image signal corresponding to the target resolution, and then convert the target image signal into an intermediate image signal matching the display processing control circuit.

[0123] For example, in the case that the image resolution is greater than the target resolution, the system-level control circuit needs to compress the original image signal so that multiple pixel signals are compressed into one pixel signal, thereby obtaining a target image signal with the target resolution; in the case that the image resolution is less than the target resolution, the system-level control circuit needs to amplify the original image signal so that one pixel signal is amplified into multiple pixel signals, thereby obtaining a target image signal with the target resolution. For example, the image resolution corresponding to the input original image signal is 1920x1080, and the target resolution output to the screen is 3840x2160, so the original image signal needs to be amplified to 4 pixels from 1 pixel, thereby obtaining a target image signal with the resolution of 3840x2160.

[0124] The above technical solution has the following advantages or beneficial effects: based on the target resolution configured for the projection picture, the resolution of the original image signal is scaled, which can ensure that the output intermediate image signal can match the resolution requirement of the projection picture, so that the display processing control circuit and the display driving chip in the back end do not need to convert the signal resolution again, which can reduce the workload of the back-end display processing, and is conducive to improving the overall working efficiency of the projection image processing process.

[0125] In some embodiments, the display processing control circuit is configured to, when splitting the intermediate image signals into a plurality of signal segments according to the row content or the column content of the images represented by the intermediate image signals, determine a desired delay duration in the signal buffering process; for each intermediate image signal, determine a segment number N adapted to the desired delay duration according to the single-frame image refresh time of the image represented by the intermediate image signal; and split the intermediate image signal into N signal segments according to the row content or the column content of the image.

[0126] wherein N is a positive integer.

[0127] In practical applications, in a multi-path video input scenario, the signal frame rates corresponding to different video signal sources can be different. In this case, if the intermediate image signals are split based on the same segment number, the buffering delays corresponding to different video signal sources in the segment rolling buffering process will be different, thereby causing the subsequent display images to be out of synchronization.

[0128] Therefore, the display processing control circuit can determine the desired delay duration in the buffering process of the intermediate image signals according to the frame rates of the intermediate image signals. The desired delay duration is less than the single-frame image refresh time and is a divisor of the single-frame image refresh time.

[0129] In some embodiments, the display processing control circuit can determine the single-frame image refresh time corresponding to each intermediate image signal according to the frame rate of the intermediate image signal, and then determine the greatest common divisor of the single-frame image refresh times as the desired delay duration in the signal buffering process. The greatest common divisor of the single-frame image refresh times refers to a number that can be divided by each single-frame image refresh time. For example, as shown in FIG. 7, for three signals of 60 Hz, 120 Hz and 240 Hz, the single-frame image refresh times are 16.6 ms, 8.33 ms and 4.17 ms respectively. Since 16.6, 8.33 and 4.17 can all be divided by 0.83, 0.83 ms can be determined as the desired delay duration.

[0130] After the desired delay duration is determined, the display processing control circuit can, for each intermediate image signal, divide the single-frame image refresh time of the image represented by the intermediate image signal by the desired delay duration to obtain the segment number N for the intermediate image signal. Finally, the display processing control circuit splits the intermediate image signal into N signal segments according to the row content or the column content of the image represented by the intermediate image signal. For example, as shown in Table 1, the intermediate image signal of 60 Hz is divided into 20 signal segments; the intermediate image signal of 120 Hz is divided into 10 signal segments; and the intermediate image signal of 240 Hz is divided into 5 signal segments, so that the buffering processing delay durations of different intermediate image signals are the same.

[0131] The technical scheme has the following advantages or beneficial effects: according to the frame rate of the intermediate image signal, the number of segments matched with the intermediate image signal is determined, and then the segment rolling buffer processing is performed, so that the delay of the buffered signals is the same, thereby ensuring the adaptation of different original image signals in the projection display process while reducing the delay, and the projection display effect is further improved.

[0132] In some embodiments, when the display processing control circuit converts the buffered signal into the display driving signal corresponding to the pixel content of different primary color light according to the refresh rate configured for the display processing control circuit, the display processing control circuit is further configured to: generate a color refresh enable signal matched with the highest refresh rate according to the refresh rate configured for the display processing control circuit; and convert the buffered signal into the display driving signal corresponding to the pixel content of different primary color light under the driving of the color refresh enable signal.

[0133] The color refresh enable signal plays a crucial role in the projection display process, and is configured to control and manage the transmission of color data in the display device to ensure accurate display of images. For the RGB color space, the refresh process of pixel color includes the refresh of the blue component of the image, the refresh of the green component of the image, and the refresh of the red component of the image. Therefore, corresponding color refresh enable signals need to be generated for different color components.

[0134] As shown in FIG. 12, during the pixel color refresh process, the display processing control circuit needs to generate a corresponding color refresh enable signal for each color component, which includes a red component enable signal (R_EN), a green component enable signal (G_EN), and a blue component enable signal (B_EN). On this basis, the refresh timing of each component is determined. As shown in FIG. 12, the red light source is first switched to be effective, then the green light source is switched to be effective, and finally the blue light source is switched to be effective, and the corresponding refresh timing is R_EN->G_EN->B_EN. Thus, the image represented by the buffered signal can be subjected to pixel color refresh processing under the control of the color refresh enable signal to obtain the display driving signal of the image.

[0135] In some embodiments, the frequency of the color refresh enable signal can be consistent with the highest refresh rate supported by the display processing control circuit, so as to ensure that the pixel color refresh processing can be performed according to the highest refresh rate.

[0136] In some embodiments, the color refresh enable signal can be a Duty signal, and a frequency of the Duty signal and a refresh rate of the pixel color are the same. The Duty signal is composed of a red enable signal R EN, a green enable signal G EN, a blue enable signal B EN, and OR logic.

[0137] The above technical solutions have the following advantages or beneficial effects: generating the color refresh enable signal according to the refresh rate configured for the display processing control circuit, and being able to reduce the delay in the pixel color refresh process by configuring a relatively high refresh rate.

[0138] In some embodiments, the display processing control circuit is further configured to: obtain chip parameters and usage information of the display processing control circuit; and determine the refresh rate configured for the display processing control circuit based on a theoretical refresh rate supported by the chip parameters and a refresh rate attenuation amount corresponding to the usage information.

[0139] The chip parameters can include important indicators for describing and evaluating chip performance, including but not limited to process, core number, frequency, power consumption, and cache size, etc. The usage information of the display processing control circuit can include cumulative usage time, chip temperature, etc.

[0140] According to the chip parameters of the display processing control circuit, the highest theoretical refresh rate supported by the chip can be determined, i.e., the theoretical refresh rate. However, due to the influence of physical aging, environmental stress, temperature, and other factors during use, the chip may have performance degradation problems during use.

[0141] Based on this, a correlation between the usage information and the refresh rate attenuation amount can be established, and the refresh rate attenuation amount of the display processing control circuit can be determined in real time according to the current usage information of the display processing control circuit and the correlation. For example, the refresh rate attenuation amount can be positively correlated with the cumulative usage time. In one implementation, the refresh rate attenuation amount Δ can be determined according to the cumulative usage time T1 and the chip temperature Temp of the chip, for example, according to the following formula: Δ = a * T1 + b * Temp. Wherein, a and b are weights, the value range is (0, 1), and the sum of a and b is 1.

[0142] After the theoretical refresh rate and the refresh rate attenuation amount are determined, the theoretical refresh rate can be subtracted by the refresh rate attenuation amount to obtain the refresh rate configured for the display processing control circuit.

[0143] The above technical solution has the following advantages or beneficial effects: on the basis of the theoretical refresh rate supported by the chip parameters, the refresh rate attenuation amount corresponding to the use information is superimposed to configure the refresh rate for the display processing control circuit, which can adaptively adjust the refresh rate in different use stages, thereby minimizing the delay time while ensuring smooth refresh processing.

[0144] In some embodiments, the display driving chip is further configured to: determine an image resolution of the image; determine a first pixel amount of the image in a first direction and a second pixel amount of the image in a second direction according to the image resolution; select a target number matching the image resolution from a plurality of candidate block numbers based on at least one of the first pixel amount or the second pixel amount; and divide the image into a plurality of spatially adjacent pixel sets according to the target number.

[0145] The first direction is perpendicular to the second direction. As shown in FIG. 3, the first direction is the row direction H, and the second direction can be the column direction L; or the first direction is the column direction L, and the second direction can be the row direction H.

[0146] The at least one of the first pixel amount or the second pixel amount refers to the first pixel amount or the second pixel amount, or the first pixel amount and the second pixel amount.

[0147] The candidate block number refers to a block number as a candidate. The plurality of candidate block numbers can be represented as a value range, such as [10, 20] or [10, 30], or can be represented as a plurality of specific numerical values, such as {10, 11, 12, 13, 14, 15, 16, 17} or {13, 14, 15, 20, 25}.

[0148] The target number matching the image resolution means that the target number is a divisor of at least one of the first pixel amount or the second pixel amount. That is, the target number can be divided by at least one of the first pixel amount or the second pixel amount.

[0149] The display driving chip can determine an image resolution of an image represented by the buffered signal, and determine a first pixel amount of the image in a first direction and a second pixel amount of the image in a second direction according to the image resolution. For example, when the image resolution is 1366x768, the pixel amount of the image in the column direction can be determined as 1366, and the pixel amount of the image in the row direction can be determined as 768, that is, the image contains 1366 columns and 768 rows.

[0150] Then, the display driving chip selects a target number matching the image resolution from a plurality of candidate block numbers based on at least one of the first pixel amount or the second pixel amount, and divides the image into a plurality of spatially adjacent pixel sets according to the target number.

[0151] For example, in the case of an image resolution of 1366x768 and a value range of the candidate number of blocks being [10, 20], since 768 can be divided by 16, the display processing control circuit can determine 16 as the target number, and divide the image into 16 pixel sets in the row direction, so that each pixel set contains 48 rows of pixels.

[0152] In an implementation, if there are at least two target numbers matching the image resolution in the plurality of candidate numbers of blocks, the target number with the largest value can be selected for image division, so as to increase the number of blocks and further reduce the delay of the display processing process.

[0153] For example, in the case of an image resolution of 1920x1080 and a value range of the candidate number of blocks being [10, 20], 1920 can be divided by 10, 12, 15, 16 and 20. In this case, the display processing control circuit can determine 20 as the target number, and divide the image into 20 pixel sets in the column direction, so that each pixel set contains 96 columns of pixels.

[0154] The above technical solutions have the following advantages or beneficial effects: determining the target number matching the image resolution according to the pixel amount can adapt to the image division requirements of different image resolutions, and is conducive to further expanding the application scenarios of the projection device.

[0155] In some embodiments, when selecting the target number matching the image resolution from the plurality of candidate numbers of blocks, the display driving chip is configured to: select a divisor of the target pixel amount from the plurality of candidate numbers of blocks as the target number M matching the image resolution. In the case of this embodiment, when dividing the image into a plurality of spatially adjacent pixel sets according to the target number, the display driving chip is configured to: divide the image into M pixel sets spatially adjacent in the target direction corresponding to the target pixel amount according to the target number.

[0156] wherein M is a positive integer; the target pixel amount is the first pixel amount or the second pixel amount; and the target direction is the first direction or the second direction.

[0157] The display driving chip can determine the target pixel amount having a divisor in the plurality of candidate numbers of blocks from the first pixel amount and the second pixel amount, and select the divisor of the target pixel amount in the plurality of candidate numbers of blocks as the target number matching the image resolution. Then, the image is divided into a plurality of spatially adjacent pixel sets in the target direction corresponding to the target pixel amount according to the target number.

[0158] For example, in the case of an image resolution of 1366x768 and a candidate block quantity value range of [10, 20], since 1366 does not have a divisor in the above value range, and 768 has a divisor in the above value range, 768 can be determined as the target pixel quantity, and a divisor 16 of 768 is further determined as the target quantity. Then, the image is divided into 16 spatially adjacent pixel sets in the row direction.

[0159] The above technical solution has the following advantages or beneficial effects: according to the numerical relationship between the candidate block quantity and the pixel quantity, the target pixel quantity is selected from the first pixel quantity and the second pixel quantity, and the target quantity for image block is determined based on the target pixel quantity, which can flexibly select the row direction or the column direction for pixel set division, and is beneficial to further expand the application scenarios of the projection device.

[0160] In some embodiments, when the display driving chip selects the target quantity matching the image resolution from the plurality of candidate block quantities, it is configured to: select a first divisor of the first pixel quantity as a first target quantity M1 corresponding to the first direction, and select a second divisor of the second pixel quantity as a second target quantity M2 corresponding to the second direction, from the plurality of candidate block quantities. In the case of this embodiment, when the display driving chip divides the image into a plurality of pixel sets according to the target quantity, it is further configured to: divide the image into M1*M2 spatially adjacent pixel sets according to the first target quantity M1 and the second target quantity M2.

[0161] wherein M1 and M2 are both positive integers.

[0162] If the first pixel quantity and the second pixel quantity both have divisors in the plurality of candidate block quantities, the display driving chip can select a first divisor of the first pixel quantity as a first target quantity corresponding to the first direction, and select a second divisor of the second pixel quantity as a second target quantity corresponding to the second direction, from the plurality of candidate block quantities. Then, the image is divided into pixel sets in the first direction corresponding to the first pixel quantity according to the first target quantity, and the image is divided into pixel sets in the second direction corresponding to the second pixel quantity according to the second target quantity. Thus, the number of pixel sets obtained is the product of the first target quantity and the second target quantity.

[0163] For example, in the case that the image resolution is 1920x1080 and the range of the number of candidate blocks is [10, 20], since 1920 can be divided by 20 and 1080 can be divided by 12, the display processing control circuit divides the image into 20 pixel sets in the length direction and 12 pixel sets in the height direction. Thus, one frame of image can be divided into 240 pixel sets, each of which contains 96 columns of pixels and 90 rows of pixels.

[0164] The above technical solution has the following advantages or beneficial effects: dividing the pixel sets in the first direction and the second direction can effectively increase the number of pixel sets, thereby reducing the delay of the display processing.

[0165] In one implementation, as shown in FIG. 13, a schematic diagram of the system-level control circuit (system-level SOC) is provided, including the following structures:

[0166] The signal source switching switch 1301 is configured to detect different video signal sources and switch to the corresponding input signal source channel.

[0167] The single / multi-channel video processing module 1302 is configured to select single-channel video processing and multi-channel video processing according to different applications when switching to a network video application signal source.

[0168] The signal processing module 1303 is configured to perform timing detection, resolution detection, and frame rate detection on the input signal, and perform color gamut conversion and gamma correction, etc.

[0169] The resolution adjustment module 1304 is configured to perform scaling down or up processing on the signal resolution. For example, the resolution of the input signal is 1920x1080, and the resolution of the output to the screen is 3840x2160, so the signal needs to be scaled up, and one pixel will become four pixels.

[0170] The signal format conversion module 1305 is configured to process the input signal and output the timing signal required by the back-end display.

[0171] In one implementation, as shown in FIG. 14, a schematic diagram of the display processing control circuit is provided, including the following structures:

[0172] The input signal interface 1401 is configured to receive the intermediate image signal and UI data output by the system-level control circuit.

[0173] The signal format conversion circuit 1402 is configured to convert the video signal format of the signal output by the front-end system-level control circuit to match the subsequent signal processing requirements.

[0174] The signal processing circuit 1403 is configured to process the input signal in terms of brightness, contrast, color, and definition to improve the pixel quality.

[0175] The frame rate format conversion module 1404 is configured to process the input video signal according to the resolution and frame rate, output the corresponding frame rate and resolution, and perform cache processing and pixel color refresh processing on the intermediate image signal input by the system-level control circuit.

[0176] The geometric correction module 1405 is configured to perform image correction on the input signal according to the input correction parameters, and finally correct it to a rectangle.

[0177] The galvanometer processing module 1406 is configured to perform image processing such as pixel expansion and pixel array reconstruction on the input data to improve the display resolution. The galvanometer processing module 1406 includes a galvanometer drive signal generator, an operational amplifier unit, and a galvanometer unit.

[0178] The image quality processing module 1407 is configured to perform primary color correction, color mixing correction, white balance processing, and the like on the image signal.

[0179] The DLP display format conversion 1408 is configured to encode the video format and convert it into a mapping format signal conforming to DMD display.

[0180] The DMD data interface 1409 is configured to perform data transmission on the input mapping format signal conforming to DMD display according to a high-speed signal transmission protocol.

[0181] The DMD control interface 1410 is configured to output instructions to control the DMD to realize corresponding functions.

[0182] The memory and storage control module 1411 is the control center of the DLP display unit program storage, data operation, and output instruction.

[0183] The laser drive module 1412 is configured to receive the red, green, and blue primary color brightness Pwm signals and the duty cycle Duty signals of the DLP processing unit. The Pwm represents the brightness value of each primary color signal, and the Duty signal represents the weight proportion of each primary color signal in a complete color cycle signal.

[0184] Based on the same inventive concept, some embodiments of the present application also provide a projection image processing method applied to the above-mentioned projection device. The implementation scheme for solving the problem provided by the method is similar to the implementation scheme described in the above-mentioned projection device embodiments, so the specific limitations in one or more projection image processing embodiments provided below can refer to the limitations of the projection device described above, and will not be repeated here.

[0185] In some embodiments, the application also provides a projection image processing method applied to the projection device described above. In some embodiments, as shown in FIG. 15, the projection image processing method comprises the following steps:

[0186] In step S1502, the original image signals sent by the video signal sources are received, and the original image signals are converted into intermediate image signals matched with the display processing control circuit;

[0187] In step S1504, the intermediate image signals are divided into a plurality of signal segments according to the row content or column content of the image represented by the intermediate image signals, and the segment rolling buffer processing is sequentially performed on each signal segment to obtain a buffer signal;

[0188] In step S1506, the buffer signal is converted into a display driving signal corresponding to the pixel content of different primary color light according to the refresh rate configured for the display processing control circuit;

[0189] In step S1508, the projection light beams are modulated according to the display driving signal of each pixel set loaded on the display driving chip.

[0190] In some embodiments, step S1502 comprises: obtaining original image signals respectively sent by a plurality of video signal sources; and converting each original image signal into an intermediate image signal matched with the display processing control circuit.

[0191] In some embodiments, converting each original image signal into an intermediate image signal matched with the display processing control circuit comprises: obtaining a target resolution configured for the projection picture; and for each original image signal, performing scaling processing on the original image signal in the case that the image resolution corresponding to the original image signal is inconsistent with the target resolution to obtain a target image signal corresponding to the target resolution; and converting the target image signal into an intermediate image signal matched with the display processing control circuit.

[0192] In some embodiments, dividing the intermediate image signal into a plurality of signal segments according to the row content or column content of the image represented by the intermediate image signal comprises: determining an expected delay duration in the signal buffer process; for each intermediate image signal, determining a segment number N adapted to the expected delay duration according to the single-frame image refresh time of the image represented by the intermediate image signal; and dividing the intermediate image signal into N signal segments according to the row content or column content of the image. Wherein, N is a positive integer.

[0193] In some embodiments, the step S1506 comprises: generating a color refresh enable signal matching the highest refresh rate according to the refresh rate configured for the display processing control circuit; and converting the cache signal into a display driving signal corresponding to the pixel content of the different primary color light under the driving of the color refresh enable signal.

[0194] In some embodiments, the projection image processing method further comprises: obtaining chip parameters and usage information of the display processing control circuit; and determining the refresh rate configured for the display processing control circuit based on a theoretical refresh rate supported by the chip parameters and superimposing a refresh rate attenuation amount corresponding to the usage information.

[0195] In some embodiments, the step of dividing the image into a plurality of pixel sets that are spatially adjacent comprises: determining an image resolution of the image; determining a first pixel amount of the image in a first direction and a second pixel amount of the image in a second direction according to the image resolution; selecting a target number matching the image resolution from a plurality of candidate block numbers based on at least one of the first pixel amount or the second pixel amount; and dividing the image into a plurality of pixel sets that are spatially adjacent according to the target number. The first direction is perpendicular to the second direction.

[0196] In some embodiments, the step of selecting a target number matching the image resolution from a plurality of candidate block numbers comprises: selecting a divisor of a target pixel amount from the plurality of candidate block numbers as the target number M matching the image resolution. In the case of this embodiment, the step of dividing the image into a plurality of pixel sets that are spatially adjacent according to the target number comprises: dividing the image into M pixel sets that are spatially adjacent in a target direction corresponding to the target pixel amount. The M is a positive integer; the target pixel amount is the first pixel amount or the second pixel amount; and the target direction is the first direction or the second direction.

[0197] In some embodiments, the step of selecting a target number matching the image resolution from a plurality of candidate block numbers comprises: selecting a first divisor of the first pixel amount from the plurality of candidate block numbers as a first target number M1 corresponding to the first direction, and selecting a second divisor of the second pixel amount as a second target number M2 corresponding to the second direction. In the case of this embodiment, the step of dividing the image into a plurality of pixel sets that are spatially adjacent according to the target number comprises: dividing the image into M1*M2 pixel sets that are spatially adjacent according to the first target number M1 and the second target number M2.

[0198] Based on the same inventive concept, the application further provides a projection image processing device for implementing the projection image processing method described above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more projection image processing device embodiments provided below can refer to the limitations of the projection image processing method described above, which will not be repeated here.

[0199] In some embodiments, the application further provides a projection image processing device applied to the projection device described above. In this embodiment, the projection image processing device comprises:

[0200] A signal conversion module configured to receive the original image signals sent by the video signal sources, and convert the original image signals into intermediate image signals matched with the display processing control circuit;

[0201] A signal cache module configured to split the intermediate image signals into a plurality of signal segments according to the row content or column content of the images represented by the intermediate image signals, and sequentially perform segment rolling cache processing on each signal segment to obtain cache signals;

[0202] A refreshing module configured to convert the cache signals into display driving signals corresponding to the pixel content of different primary color lights according to the refresh rate configured for the display processing control circuit;

[0203] A display module configured to modulate the projection light beams according to the display driving signals of each pixel set for the spatially adjacent pixel sets loaded onto the display driving chip.

[0204] In some embodiments, the signal conversion module comprises: a signal acquisition unit configured to acquire the original image signals respectively sent by the plurality of video signal sources; and a signal conversion unit configured to convert each original image signal into an intermediate image signal matched with the display processing control circuit.

[0205] In some embodiments, the signal conversion unit is configured to: acquire a target resolution configured for the projection picture; and for each original image signal, perform scaling processing on the original image signal to obtain a target image signal corresponding to the target resolution in the case that the image resolution corresponding to the original image signal is inconsistent with the target resolution, and convert the target image signal into an intermediate image signal matched with the display processing control circuit.

[0206] In some embodiments, the signal cache module is configured to: determine an expected delay duration in the signal cache process; for each intermediate image signal, determine a segment number N adapted to the expected delay duration according to the single-frame image refreshing time of the image represented by the intermediate image signal; and split the intermediate image signal into N signal segments according to the row content or column content of the image. Wherein, N is a positive integer.

[0207] In some embodiments, the refreshing module is configured to generate a color refreshing enable signal matching the highest refreshing rate according to the refreshing rate configured for the display processing control circuit; and convert the cache signal into a display driving signal corresponding to the pixel content of the different primary color light under the driving of the color refreshing enable signal.

[0208] In some embodiments, the projection image processing apparatus further comprises a refreshing rate determination module configured to: acquire the chip parameters and usage information of the display processing control circuit; and determine the refreshing rate configured for the display processing control circuit by superimposing the refreshing rate attenuation corresponding to the usage information on the basis of the theoretical refreshing rate supported by the chip parameters.

[0209] In some embodiments, the display module comprises: a resolution determination unit configured to determine an image resolution of an image; a pixel quantity determination unit configured to determine a first pixel quantity of the image in a first direction and a second pixel quantity of the image in a second direction according to the image resolution; a target quantity determination unit configured to select a target quantity matching the image resolution from a plurality of candidate block quantities based on at least one of the first pixel quantity or the second pixel quantity; and an image division unit configured to divide the image into a plurality of spatially adjacent pixel sets according to the target quantity. The first direction is perpendicular to the second direction.

[0210] In some embodiments, the target quantity determination unit is configured to select a divisor of the target pixel quantity from the plurality of candidate block quantities as the target quantity M matching the image resolution. In the case of this embodiment, the image division unit is configured to divide the image into M spatially adjacent pixel sets in a target direction corresponding to the target pixel quantity. The M is a positive integer; the target pixel quantity is the first pixel quantity or the second pixel quantity; and the target direction is the first direction or the second direction.

[0211] In some embodiments, the target quantity determination unit is configured to select a first divisor of the first pixel quantity as a first target quantity M1 corresponding to the first direction and a second divisor of the second pixel quantity as a second target quantity M2 corresponding to the second direction from the plurality of candidate block quantities. In the case of this embodiment, the image division unit is configured to divide the image into M1*M2 spatially adjacent pixel sets according to the first target quantity M1 and the second target quantity M2.

[0212] Each of the above modules in the projection image processing apparatus can be realized by software, hardware, and a combination thereof in whole or in part. Each of the above modules can be embedded in or independent of a processor in the projection device in hardware form, or can be stored in a memory in the projection device in software form so as to be called and executed by the processor to perform the operations corresponding to each of the above modules.

[0213] In some embodiments, a projection device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the above method steps when executing the computer program.

[0214] In some embodiments, a computer readable storage medium is provided, storing a computer program, and the computer program implementing the above method steps when executed by a processor.

[0215] In some embodiments, a computer program product is provided, comprising a computer program, and the computer program implementing the above method steps when executed by a processor.

[0216] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to a memory, database or other medium used in the embodiments provided in the present application can include at least one of a non-volatile and volatile memory. The non-volatile memory can include a read-only memory (ROM), a magnetic tape, a floppy disk, a flash memory, an optical storage, a high-density embedded non-volatile memory, a resistive memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric memory (FRAM), a phase change memory (PCM), a graphene memory, etc. The volatile memory can include a random access memory (RAM) or an external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0217] Any technical features in the above embodiments can be combined, and for the sake of brevity, not all possible combinations are described above, however, as long as the combinations of technical features do not have contradictions, they shall be considered within the scope of the present disclosure.

[0218] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent scope of the present application. It shall be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall be within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A projection device, comprising a system-level control circuit, a display processing control circuit and a display driving chip; the display processing control circuit is connected to the system-level control circuit and the display driving chip; wherein the system-level control circuit is configured to: receive an original image signal sent by a video signal source, and convert the original image signal into an intermediate image signal matched with the display processing control circuit; the display processing control circuit is configured to: segment the intermediate image signal into a plurality of signal segments according to row content or column content of an image represented by the intermediate image signal, and sequentially perform buffer processing on the plurality of signal segments to obtain a buffer signal; convert the buffer signal into display driving signals corresponding to pixel content of different primary color lights according to a refresh rate configured for the display processing control circuit; the display driving chip is configured to: modulate a projection light beam according to display driving signals of a plurality of pixel sets loaded on the display driving chip in a spatially adjacent manner.

2. The apparatus of claim 1, wherein, When receiving an original image signal sent by a video signal source and converting the original image signal into an intermediate image signal matched with the display processing control circuit, the system-level control circuit is configured to: obtain original image signals respectively sent by a plurality of video signal sources; convert each of the original image signals into an intermediate image signal matched with the display processing control circuit.

3. The apparatus of claim 2, wherein, When converting each of the original image signals into an intermediate image signal matched with the display processing control circuit, the system-level control circuit is configured to: obtain a target resolution configured for the projection picture; for each of the original image signals, perform scaling processing on the original image signal in a case where an image resolution corresponding to the original image signal is inconsistent with the target resolution to obtain a target image signal corresponding to the target resolution; convert the target image signal into an intermediate image signal matched with the display processing control circuit.

4. The apparatus of claim 2, wherein, When segmenting the intermediate image signal into a plurality of signal segments according to row content or column content of an image represented by the intermediate image signal, the display processing control circuit is configured to: determine an expected delay duration in a signal buffer process; for each of the intermediate image signals, determine a segment number N adapted to the expected delay duration according to a single-frame image refresh time of an image represented by the intermediate image signal; wherein N is a positive integer; segment the intermediate image signal into N signal segments according to the row content or the column content of the image.

5. The apparatus of any one of claims 1 to 4, wherein, When converting the buffer signal into display driving signals corresponding to pixel content of different primary color lights according to a refresh rate configured for the display processing control circuit, the display processing control circuit is configured to: generate a color refresh enable signal matched with the refresh rate according to the refresh rate configured for the display processing control circuit; convert the buffer signal into display driving signals corresponding to pixel content of different primary color lights under driving of the color refresh enable signal.

6. The apparatus of any one of claims 1 to 4, wherein, The display processing control circuit is further configured to: acquire a chip parameter and usage information of the display processing control circuit; on the basis of a theoretical refresh rate supported by the chip parameter, superimpose a refresh rate attenuation quantity corresponding to the usage information to determine a refresh rate configured for the display processing control circuit.

7. The apparatus of any one of claims 1 to 4, wherein, the display driving chip is further configured to: determine an image resolution of the image; determine a first pixel quantity of the image in a first direction and a second pixel quantity of the image in a second direction according to the image resolution; the first direction is perpendicular to the second direction; based on at least one of the first pixel quantity or the second pixel quantity, select a target quantity matching the image resolution from a plurality of candidate block quantities; divide the image into a plurality of spatially adjacent pixel sets according to the target quantity.

8. The apparatus of claim 7, wherein, when the display driving chip selects a target quantity matching the image resolution from a plurality of candidate block quantities, it is configured to: select a divisor of the target pixel quantity from the plurality of candidate block quantities as the target quantity M matching the image resolution; wherein M is a positive integer; the target pixel quantity is the first pixel quantity or the second pixel quantity; when the display driving chip divides the image into a plurality of spatially adjacent pixel sets according to the target quantity, it is further configured to: divide the image into M pixel sets spatially adjacent in a target direction corresponding to the target pixel quantity; the target direction is the first direction or the second direction.

9. The apparatus of claim 7, wherein, when the display driving chip selects a target quantity matching the image resolution from a plurality of candidate block quantities, it is configured to: select a first divisor of the first pixel quantity as a first target quantity M1 corresponding to the first direction and a second divisor of the second pixel quantity as a second target quantity M2 corresponding to the second direction from the plurality of candidate block quantities; wherein M1 and M2 are both positive integers; when the display driving chip divides the image into a plurality of spatially adjacent pixel sets according to the target quantity, it is further configured to: divide the image into M1*M2 pixel sets spatially adjacent according to the first target quantity M1 and the second target quantity M2.

10. A projection image processing method applied to the projection device of any one of claims 1 to 9, the method comprising: receiving an original image signal sent by a video signal source and converting the original image signal into an intermediate image signal matching the display processing control circuit; segmenting the intermediate image signal into a plurality of signal segments according to row content or column content of an image represented by the intermediate image signal, and sequentially performing buffer processing on the plurality of signal segments to obtain a buffer signal; converting the buffer signal into display driving signals corresponding to pixel content of different primary color lights according to a refresh rate configured for the display processing control circuit; modulating projection light beams according to respective display driving signals of a plurality of spatially adjacent pixel sets loaded on the display driving chip.

11. The method of claim 10, wherein, Receiving the original image signals sent by the video signal sources, and converting the original image signals into intermediate image signals matched with the display processing control circuit, comprising: Obtaining original image signals respectively sent by a plurality of video signal sources; Converting each of the original image signals into an intermediate image signal matched with the display processing control circuit.

12. The method of claim 11, wherein, Converting each of the original image signals into an intermediate image signal matched with the display processing control circuit, comprising: Obtaining a target resolution configured for a projection picture; For each of the original image signals, performing scaling processing on the original image signal in a case where an image resolution corresponding to the original image signal is inconsistent with the target resolution, to obtain a target image signal corresponding to the target resolution; Converting the target image signal into an intermediate image signal matched with the display processing control circuit.

13. The method of claim 11, wherein, According to row content or column content of an image represented by the intermediate image signal, the intermediate image signal is divided into a plurality of signal segments, comprising: Determining an expected delay duration in a signal buffering process; For each of the intermediate image signals, determining a segment number N adapted to the expected delay duration according to a single-frame image refresh time of an image represented by the intermediate image signal; wherein N is a positive integer; According to the row content or column content of the image, the intermediate image signal is divided into N signal segments.

14. The method according to any one of claims 10-13, wherein, According to a refresh rate configured for the display processing control circuit, the buffered signal is converted into display driving signals corresponding to pixel content of different primary color lights, comprising: According to a refresh rate configured for the display processing control circuit, a color refresh enable signal matched with the refresh rate is generated; Under the driving of the color refresh enable signal, the buffered signal is converted into display driving signals corresponding to pixel content of different primary color lights.

15. The method according to any one of claims 10-13, wherein, The method further comprises: Obtaining chip parameters and usage information of the display processing control circuit; On the basis of a theoretical refresh rate supported by the chip parameters, a refresh rate attenuation amount corresponding to the usage information is superimposed to determine a refresh rate configured for the display processing control circuit.

16. The method of any one of claims 10-13, wherein, The method further comprises: Determining an image resolution of the image; According to the image resolution, a first pixel amount of the image in a first direction and a second pixel amount of the image in a second direction are determined; the first direction is perpendicular to the second direction; Based on at least one of the first pixel amount or the second pixel amount, a target number matched with the image resolution is selected from a plurality of candidate block numbers; According to the target number, the image is divided into a plurality of spatially adjacent pixel sets.

17. The method of claim 16, wherein, Selecting, from a plurality of candidate block numbers, a target number matched with the image resolution, comprising: Selecting a divisor of a target pixel amount from a plurality of candidate block numbers as a target number M matched with the image resolution; wherein M is a positive integer; the target pixel amount is the first pixel amount or the second pixel amount; The dividing, according to the target number, the image into a plurality of spatially adjacent pixel sets comprises: In a target direction corresponding to the target pixel quantity, the image is divided into M pixel sets which are spatially adjacent; the target direction is the first direction or the second direction.

18. The method of claim 16, wherein, From the plurality of candidate block numbers, a target number matching the image resolution is selected, including: From the plurality of candidate block numbers, a first divisor of the first pixel quantity is selected as a first target number M1 corresponding to the first direction, and a second divisor of the second pixel quantity is selected as a second target number M2 corresponding to the second direction; wherein M1 and M2 are both positive integers; The step of dividing the image into a plurality of pixel sets which are spatially adjacent according to the target number includes: The image is divided into M1*M2 pixel sets which are spatially adjacent according to the first target number M1 and the second target number M2.

19. A projection device comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of the projection image processing method according to any one of claims 10-18 when executing the computer program.

20. A computer readable storage medium having stored thereon a computer program, the computer program implementing the steps of the projection image processing method according to any one of claims 10-18 when executed by a processor.

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