Method for obtaining check matrix, and communication apparatus

Abstract

The present application provides a method for obtaining a check matrix, and a communication apparatus. In the method, a communication apparatus can obtain a check matrix on the basis of a first base matrix. Compared with a base graph, patch elements are added to the first base matrix, and the patch elements may correspond to cyclically shifted submatrices in a check matrix. Therefore, the number of non-zero elements in the check matrix can be increased, thereby reducing the presence of low column weights in the check matrix, improving the decoding performance of a floor region, and improving reliability. In addition, according to the present solution, the positions of the patch elements are further determined on the basis of a target bit rate, so that the addition of the patch elements can obtain a greater benefit.

Description

Method for obtaining check matrix and communication device

[0001] The present application claims priority to the Chinese patent application No. 202411298868.4, filed on September 14, 2024, with the State Intellectual Property Office of China, and entitled "Method for obtaining check matrix and communication device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of wireless communication, in particular to a method for obtaining a check matrix and a communication device. BACKGROUND

[0003] Low density parity check (LDPC) code is a kind of linear block code with sparse check matrix. LDPC code not only has good performance of approaching Shannon limit, but also has low decoding complexity and flexible structure. Therefore, it has been well applied in some communication systems.

[0004] At present, when LDPC encoding is performed by using base graph (BG) 1 and BG 2 defined in the protocol of new radio (NR), in a lower signal noise ratio (SNR) interval, the block error rate (BLER) significantly decreases with the increase of SNR; and in a higher SNR interval, the trend of BLER decreasing with the increase of SNR slows down, and a relatively obvious error floor appears, which may lead to low decoding performance, especially for some scenarios with high reliability requirement, which has potential risks.

[0005] Therefore, how to improve the decoding performance of error floor and improve reliability has become a technical problem to be solved. SUMMARY

[0006] The present application provides a method for obtaining a check matrix and a communication device, so as to improve the decoding performance of error floor and improve reliability.

[0007] In a first aspect, a method for obtaining a check matrix is provided. The communication apparatus can be a communication device, such as a network device or a terminal device, a component configured in the communication device, such as a circuit or a chip (e.g., a modem chip, also referred to as a baseband chip, or a system on chip (SoC) chip or a system in package (SIP) chip containing a modem core, etc.) in the communication device, a logic module or software capable of implementing part or all of the functions of the communication apparatus, etc., which are not limited in the present application.

[0008] Exemplarily, the method comprises: obtaining a first base matrix; the first base matrix comprises Q patch elements, each patch element in the Q patch elements has a first value, and the positions of the Q patch elements in the first base matrix coincide with the positions of Q elements having a second value in a second base matrix, Q being a positive integer; obtaining a check matrix from the first base matrix, the check matrix being used for LDPC encoding or LDPC decoding, the first value in the check matrix corresponding to a cyclic shift square matrix, and the second value in the check matrix corresponding to an all-zero square matrix.

[0009] It can be understood that the cyclic shift square matrix can also be referred to as a cyclic shift submatrix, and the all-zero square matrix can also be referred to as an all-zero submatrix.

[0010] Further, the method further comprises: performing LDPC encoding or LDPC decoding by using the check matrix.

[0011] Based on the above scheme, the communication apparatus can perform LDPC encoding or LDPC decoding based on the check matrix obtained from the first base matrix. Since the first base matrix has more elements having the first value than the second base matrix, that is, there are more cyclic shift square matrices in the check matrix. This is conducive to increasing the number of non-zero elements in the check matrix, reducing the existence of light columns in the check matrix, improving the decoding performance of the flat area, and improving the reliability. Thus, it can be applied to some scenarios with high reliability requirements to reduce the risk.

[0012] In combination with the first aspect, in some possible implementation manners of the first aspect, the first value is 1, and the second value is 0; or the first value is greater than or equal to 0, and the second value is -1. The specific values of the first value and the second value are not limited in the present application.

[0013] In combination with the first aspect, in some possible implementation manners of the first aspect, the obtaining of the first base matrix comprises: obtaining the first base matrix according to the second base matrix.

[0014] It should be understood that the second base matrix can be in the form of a base matrix defined in the current new radio (NR) or a base matrix obtained based on the base matrix. In a possible scenario, the second base matrix is pre-stored in the communication device, and the communication device can first obtain the second base matrix and then obtain the first base matrix according to the second base matrix, so as to reduce the storage overhead caused by pre-storing the first base matrix.

[0015] With reference to the first aspect, in some possible implementation manners of the first aspect, the Q patch elements are located in the first m b rows of the first base matrix, m b satisfies: R is a target code rate, which can be a code rate indicated by a modulation coding scheme (MCS), k b is a column number of information bits in the first base matrix, d b is a column number of punctured bits in the first base matrix, denotes rounding up.

[0016] In the LDPC code, the fewer the number of rows actually participating in encoding in the check matrix, the higher the code rate; the more the number of rows actually participating in encoding in the check matrix, the lower the code rate. If a cyclic shift submatrix is added in the first m b rows of the check matrix H, the decoding performance can be affected. Since each non-zero element in the first base matrix is a Z×Z submatrix, the first m b rows of the check matrix can correspond to the first m b rows of the first base matrix, the Q patch elements can be controlled in the first m b rows of the first base matrix. Therefore, the range of the rows in which the Q patch elements are located in the first base matrix can be determined according to the target code rate.

[0017] Therefore, the range of the rows in which the Q patch elements are located in the first base matrix is determined according to the target code rate, which is beneficial to increasing the number of elements 1 in the rows actually participating in encoding in the check matrix, so that the addition of the patch elements can obtain greater benefits.

[0018] With reference to the first aspect, in some possible implementation manners of the first aspect, the position information of the patch elements corresponding to the plurality of code rates includes the same G column indexes, and G is a positive integer.

[0019] That is, the column in which the patch elements are located does not change with the change of the code rate. The position information of the patch elements can be pre-stored in the communication device, and if the position information of the patch elements corresponding to the plurality of code rates includes the same column indexes, excessive storage overhead can be avoided.

[0020] Optionally, the G columns indicated by the G column indices satisfy the following: in the G' columns of the second base matrix, they are ranked in descending order of the statistical value of the number of error bits corresponding to each column; wherein, the statistical value of the number of error bits corresponding to the i-th column in the G' columns is a function of the number of error bits corresponding to the i-th column in each of the plurality of submatrices of the second base matrix; any one of the plurality of submatrices includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m b The value of ' corresponds to the code rate corresponding to any of the submatrices. The G' columns can be one or more predefined columns, and G' is a positive integer greater than or equal to G.

[0021] Optionally, any one of the plurality of submatrices of the second basis matrix includes the first m from the top left corner of the second basis matrix. b 'The first S columns of the row, and the m corresponding to different sized submatrices. b The values ​​of ' and S differ, and different sizes of submatrices correspond to different code rates; that is, the m values ​​of multiple submatrices... b The value of ' can correspond one-to-one with multiple code rates. For example, in BG 2 of the NR protocol, its complete base matrix (as an example of the second base matrix above) is 42×52. With 2 columns punched, the submatrix corresponding to a code rate of 0.67 is the matrix formed by the first 7 rows and first 17 columns of this base matrix (i.e., m). b '=7,S=17); the submatrix corresponding to a code rate of 0.5 is the matrix formed by the first 12 rows and first 22 columns of the base matrix (i.e., m b '=12,S=22). Where, m b The value of ' can also be called the number of rows in the submatrix, that is, the number of rows included in the submatrix. The value of S is a positive integer.

[0022] The column index of the patch element is determined based on the number of error bits in each column. In other words, patch elements are added to columns with a large number of error bits to improve decoding performance.

[0023] Optionally, the G columns indicated by the G column indices satisfy the following: among the G' columns of the second base matrix, they are ranked in ascending order of the statistical value of the number of target elements contained in each column; wherein, the statistical value of the number of target elements contained in the i-th column of the G' columns is a function of the number of target elements contained in the i-th column of each of the plurality of submatrices of the second base matrix; any one of the plurality of submatrices includes the first m columns of the G' columns of the second base matrix. b 'Okay, the m bThe value of the first value has a corresponding relationship with a code rate corresponding to the any one sub-matrix, the G' columns are predefined one or more columns, and G' is a positive integer greater than or equal to G; and the target element is an element with the first value. Optionally, the G' columns are the first G' columns, such as the first G' columns from the left top vertex, or the first G' columns in the upper left corner, in which case the plurality of sub-matrices are from the G' columns.

[0024] The number of rows of the sub-matrix and the corresponding relationship between the number of rows of the plurality of sub-matrices and the plurality of code rates can be referred to the above and will not be repeated here.

[0025] Optionally, the above function can be a weighted average value, a maximum value, etc., which is not limited here.

[0026] Since the first value can correspond to a cyclic shift sub-matrix in the check matrix, the column index of the patch element is determined according to the number of target elements contained in each column, which is equivalent to determining the column index of the patch element according to the column weight of each column in the check matrix, so that the patch element can be added to the column with lighter column weight to improve the decoding performance.

[0027] In combination with the first aspect, in some possible implementation manners of the first aspect, the position information of the patch element corresponding to each code rate in the plurality of code rates includes one or more column indexes, and the position information of the patch element corresponding to at least two code rates in the plurality of code rates includes at least one different column index.

[0028] That is, the column in which the patch element is located can also change with the change of the code rate. That is, the column index of the patch element is determined according to the code rate, which can more accurately determine the position of the patch element and be more flexible.

[0029] Optionally, the Q patch elements are located in G columns in the first base matrix, and the G columns satisfy that in a sub-matrix of the second base matrix, the first G columns are arranged in descending order of the number of error bits corresponding to each column; and the sub-matrix of the second base matrix includes the first m b rows of G' columns of the second base matrix, and the value of m b ' has a corresponding relationship with a target code rate, the G' columns are predefined one or more columns, and G' is greater than or equal to G, G' and G are positive integers.

[0030] The column index of the patch element is determined according to the number of error bits of each column, that is, the patch element is added to the column with more error bits to improve the decoding performance.

[0031] Optionally, the Q patch elements are located in G columns of the first base matrix, the G columns satisfying that in a sub-matrix of the second base matrix, the first G columns are arranged in an ascending order of the number of target elements contained in each column; wherein the sub-matrix of the second base matrix includes the first m rows of G' columns of the second base matrix, the value of m has a corresponding relationship with a target code rate, the G' columns are one or more predefined columns, and G' is greater than or equal to G, G' and G are positive integers; the target element is an element with the first value. b 'row, the value of m b 'has a corresponding relationship with a target code rate, the G' columns are one or more predefined columns, and G' is greater than or equal to G, G' and G are positive integers; the target element is an element with the first value.

[0032] Since the first value can correspond to a cyclic shift sub-matrix in the check matrix, determining the column index of the patch element according to the number of target elements contained in each column is equivalent to determining the column index of the patch element according to the column weight of each column in the check matrix, so that the patch element can be added to a column with a lighter column weight, thereby improving decoding performance.

[0033] In combination with the first aspect, in some possible implementation manners of the first aspect, the method further includes determining to use the first base matrix.

[0034] The communication device can determine whether to use or not to use the first base matrix to obtain the check matrix according to actual needs, so that different schemes can be selected flexibly to cope with different scenarios, and greater benefits can be obtained in different scenarios.

[0035] Optionally, the determining to use the first base matrix includes: determining to use the first base matrix in a case where a first condition is met.

[0036] The communication device can determine whether to use the first base matrix. Exemplarily, the first condition is related to a channel environment, a capability of the communication device, a service scenario, or the like. Therefore, the communication device can select different schemes flexibly to cope with different scenarios, and greater benefits can be obtained in different scenarios.

[0037] Further, the method further includes: sending first indication information, the first indication information being used for indicating to use the first base matrix or indicating the first base matrix.

[0038] The communication device indicates whether to use the first base matrix through the first indication information, so that another communication device in communication with the communication device can also obtain the check matrix based on the same base matrix, thereby avoiding decoding errors and improving decoding performance.

[0039] Optionally, the method further comprises: receiving second indication information, the second indication information being used for indicating to use the first base matrix or indicating the first base matrix; and the determining to use the first base matrix comprises: determining to use the first base matrix according to the second indication information.

[0040] The communication device can also determine which base matrix to use to obtain the check matrix according to an indication of another communication device in communication therewith, thereby avoiding decoding errors and improving decoding performance.

[0041] In a second aspect, a communication device is provided. The communication device can include a module corresponding to each of the methods / operations / steps / actions described in the first aspect, or include a module corresponding to each of the methods / operations / steps / actions described in the first aspect. The module can be a hardware circuit, or software, or a combination of hardware circuit and software.

[0042] In one design, the communication device can include a processing module and a communication module. The communication module can be configured to perform the transmitting and receiving actions performed by the communication device in the methods described in the first aspect, and the processing module can be configured to perform the actions related to processing performed by the communication device in the methods described in the first aspect.

[0043] In one design, the device can be a terminal, or a device, module, circuit, or chip configured to be disposed in a terminal, or a device capable of being used in matching with a terminal.

[0044] In one design, the device can be a network device, or a device, module, circuit, or chip configured to be disposed in a network device, or a device capable of being used in matching with a network device.

[0045] In a third aspect, a communication device is provided, including a processor and a storage medium, the storage medium storing instructions, which, when executed by the processor, cause the method in the first aspect or any possible implementation manner of the first aspect to be implemented.

[0046] In a fourth aspect, a device is provided, including a processing circuit, the processing circuit being configured to process data and / or information, so that the method in the first aspect or any possible implementation manner of the first aspect is implemented.

[0047] The processing circuit can include one or more processors, or all or part of a circuit for processing functions in the one or more processors.

[0048] Optionally, the apparatus can further include a memory for storing a program or instructions, and the processor is configured to execute the program or instructions to enable the method in the first aspect or any possible implementation of the first aspect to be implemented.

[0049] Optionally, the apparatus can further include the transceiver circuit, or an input / output interface.

[0050] In a fifth aspect, a chip is provided, including a processing circuit configured to execute a program or instructions to enable the method in the first aspect or any possible implementation of the first aspect to be implemented.

[0051] Optionally, the chip can further include a memory for storing the program or instructions.

[0052] Optionally, the chip can further include the transceiver circuit, or an input / output interface.

[0053] In a sixth aspect, a computer readable storage medium is provided, including instructions, which when executed by a processor, enable the method in the first aspect or any possible implementation of the first aspect to be implemented.

[0054] In a seventh aspect, a computer program product is provided, including computer program code or instructions, which when executed, enable the method in the first aspect and any possible implementation of the first aspect to be implemented.

[0055] In an eighth aspect, a communication system is provided, including the communication apparatus performing the first aspect and any possible implementation of the first aspect.

[0056] It should be understood that the second aspect to the eighth aspect of the present application correspond to the technical solution of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding possible implementation are similar, which will not be repeated. BRIEF DESCRIPTION OF DRAWINGS

[0057] FIG. 1 is a schematic diagram of a communication system suitable for the method provided by the embodiments of the present application;

[0058] FIG. 2 is a schematic diagram of several different communication scenarios suitable for the method provided by the embodiments of the present application;

[0059] FIG. 3 is a schematic diagram of a signal processing process of a physical layer provided by the embodiments of the present application;

[0060] FIG. 4 is a schematic block diagram of an apparatus for implementing physical layer processing;

[0061] FIG. 5 is an example of a Tanner graph according to an embodiment of the present application;

[0062] FIG. 6 is a structure diagram of a check matrix according to an embodiment of the present application;

[0063] FIG. 7 is a Raptor-like structure of two different dimensions according to an embodiment of the present application;

[0064] FIG. 8 is a diagram of a relationship between a base graph (BG) selection and a transport block size (TBS) and a rate according to an embodiment of the present application;

[0065] FIG. 9 is a performance simulation diagram according to an embodiment of the present application;

[0066] FIG. 10 is a diagram of a relationship between elements of a column of BG 2 and a number of error bits according to an embodiment of the present application;

[0067] FIG. 11 is a schematic flowchart of a method of obtaining a check matrix according to an embodiment of the present application;

[0068] FIG. 12 is a diagram of a first base matrix according to an embodiment of the present application;

[0069] FIG. 13 is another diagram of the first base matrix according to an embodiment of the present application;

[0070] FIG. 14 is a performance simulation diagram according to an embodiment of the present application;

[0071] FIG. 15 is a schematic block diagram of a communication device according to an embodiment of the present application;

[0072] FIG. 16 is another schematic block diagram of a communication device according to an embodiment of the present application. DETAILED DESCRIPTION

[0073] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0074] Before introducing the solutions of the present application, the following points are explained.

[0075] First, in the present application, indication includes explicit indication (also referred to as direct indication) and implicit indication (also referred to as indirect indication). Wherein, explicit indication of information A means including the information A; implicit indication of information A means indicating the information A through a correspondence between the information A and information B and direct indication of the information B, the correspondence between the information A and the information B can be predefined, pre-stored, pre-burned, or pre-configured; or, it can also mean indicating the information A through the information B and a preset rule.

[0076] Secondly, in the present application, information C used for determination of information D includes both information D determined based on information C only and information D determined based on information C and other information. In addition, information C used for determination of information D also includes the case of indirect determination, such as the case where information D is determined based on information E, and information E is determined based on information C.

[0077] Thirdly, in the present application, "at least one" means one or more, and "multiple" means two or more. The expression " / " is used to represent that the objects associated in front and back are in an "or" relationship; for example, A / B can represent: A or B. The expression "and / or" is used to represent that the objects associated in front and back can be in an "and" relationship or an "or" relationship, for example, A and / or B, which can represent: the case of A alone, the case of A and B together, and the case of B alone, where A and B can be singular or plural. The character " / " generally represents that the objects associated in front and back are in an "or" relationship, but does not exclude the case where the objects associated in front and back are in an "and" relationship. The specific meaning can be understood in combination with the context. "At least one of the following" or the like means any combination of the items, including any combination of single item or multiple items. For example, at least one of a, b, or c can represent: a, b, c; a and b; a and c; b and c; or a and b and c. Where a, b, and c can be single or multiple.

[0078] Fourthly, in the present application, the use of prefixes such as "first", "second", and the like is only for the convenience of distinguishing different objects belonging to the same name category, and does not constrain the order, size, or quantity of the objects. For example, "first indication information" and "second indication information" are only different indication information, and there is no time sequence, size relationship or priority relationship between them; for example, "first base matrix" and "second base matrix" are only different base matrices, and there is no time sequence, size relationship or priority relationship between them. It should be understood that the objects thus described can be interchanged under appropriate circumstances, so as to be able to describe schemes other than the embodiments of the present application.

[0079] Fifth, in the present application, "sending" and "receiving" represent the direction of signal transmission. For example, "sending information to XX" can be understood as that the destination of the information is XX, which can include direct sending through the air interface, and also includes indirect sending through the air interface by other units or modules. "Receiving information from YY" can be understood as that the source of the information is YY, which can include direct receiving from YY through the air interface, and also can include indirect receiving from YY through the air interface by other units or modules. "Sending" can also be understood as the "output" of the chip interface, and "receiving" can also be understood as the "input" of the chip interface. In other words, sending and receiving can be carried out between devices, such as between terminal devices and computing nodes, or can be carried out within a device, such as between components, modules, chips, software modules or hardware modules within a device through a bus, wire or interface.

[0080] Sixth, in the embodiments of the present application, "when", "if" and "whether" all refer to that the device will make corresponding processing under certain objective circumstances, and are not limited to time, and also do not require the device to have a judgment action when it is implemented, and also do not mean that there are other limitations.

[0081] Seventh, in the present application, "example", "exemplarily", "for example" or "such as" and the like are used to represent as an example, illustration or description. Any embodiment or design scheme described as "example", "exemplarily", "for example" or "such as" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "example", "exemplarily", "for example" or "such as" and the like is intended to present the relevant concept in a specific manner.

[0082] Eighth, in order to facilitate understanding of the method provided in the present application, the following describes in many places in combination with specific examples. In the examples shown below, the row index, column index and the like are numbered starting from 0, but this should not constitute any limitation on the present application. For example, these numbers can also be numbered starting from 1, or starting from other preset values. Therefore, the present application does not limit the value range of the row index, column index and the like.

[0083] The technical solutions provided in the present application can be applied to various communication systems, for example, a 5th generation (5G) or new radio (NR) system, a long term evolution (LTE) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, a wireless local area network (WLAN) system, a satellite communication system, a future communication system, or a fusion system of multiple systems, and the like. The technical solutions provided in the present application can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and an internet of things (IoT) communication system or other communication systems.

[0084] A device in a communication system can send a signal to another device or receive a signal from another device. The signal can include information, signaling, or data, and the like. The device can also be replaced by an entity, a network entity, a communication device, a communication module, a node, a communication node, and the like. The device is taken as an example for description in the present application. For example, the communication system can include at least one terminal device and at least one network device. The network device can send a downlink signal to the terminal device, and / or the terminal device can send an uplink signal to the network device. It can be understood that the terminal device in the present application can be replaced by a first communication apparatus, and the network device can be replaced by a second communication apparatus, both of which perform the corresponding communication method in the present application.

[0085] The radio access network (RAN) device in the present application is a device with wireless transceiving function. The radio access network device can provide wireless communication function service and can access terminal devices to a wireless network. The radio access network can also be referred to as an access network device or a network device. The network device in the embodiments of the present application can refer to a radio access network (RAN) node (or device) applied to a cellular network (or mobile network) to access terminal devices to a wireless network, and can also be a zigbee base station, a bluetooth master (BT master), a bluetooth low energy (BLE) master, a long range radio (Lora) base station, and a wireless fidelity (Wi-Fi) access point.

[0086] The network device can be a base station. The base station can broadly cover various names in the following or be replaced with the following names, such as: Node B (Node B), evolved Node B (eNB), next generation Node B (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), primary station, secondary station, multi-mode wireless (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. The base station can be a macro base station, a micro base station, a relay node, a donor node, or the like, or a combination thereof. The base station can also refer to a communication module, modem, or chip for setting in the aforementioned device or apparatus. The base station can also be a mobile switching center and a device assuming a base station function in D2D, V2X, M2M communication, a device assuming a base station function in a future communication system, etc. The base station can support networks of the same or different access technologies. Alternatively, the RAN node can also be a server, a wearable device, a vehicle or a vehicle-mounted device, etc. For example, the access network device in vehicle to everything (V2X) technology can be a road side unit (RSU). Embodiments of the present application do not limit the specific technology and specific device form adopted by the network device. In some deployments, the network device mentioned in the embodiments of the present application can be a device including a CU, or a DU, or a device including a CU and a DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network device can include gNB-CU-CP, gNB-CU-UP and gNB-DU.

[0087] In some deployments, wireless access is facilitated by a plurality of RAN nodes in cooperation to serve a terminal, different RAN nodes respectively implementing part of the functionalities of a base station. For example, a RAN node can be a CU, a DU, a CU-CP, a CU-UP, or a RU, etc. A CU and a DU can be separately arranged, or can also be included in the same network element, for example, in a BBU. A RU can be included in a radio frequency device or a radio frequency unit, for example, in a RRU, an AAU, or a RRH.

[0088] A RAN node can support one or more types of fronthaul interfaces, different fronthaul interfaces respectively corresponding to DUs and RUs having different functions. If the fronthaul interface between a DU and a RU is a common public radio interface (CPRI), the DU is configured to implement one or more of the baseband functions, and the RU is configured to implement one or more of the radio frequency functions. If the fronthaul interface between the DU and the RU is another interface, compared with the CPRI, part of the baseband functions of the downlink and / or the uplink, such as, for a downlink, one or more of precoding, digital beamforming (BF), or inverse fast Fourier transform (IFFT) / adding a cyclic prefix (CP), are implemented in the RU from the DU, and for an uplink, one or more of digital beamforming (BF), or fast Fourier transform (FFT) / removing the CP are implemented in the RU from the DU. In a possible implementation, the interface can be an enhanced common public radio interface (eCPRI). Under the eCPRI architecture, the splitting manner between the DU and the RU is different, corresponding to different categories (Cat) of eCPRI, such as eCPRI Cat A, B, C, D, E, F.

[0089] Taking eCPRI Cat A as an example, for downlink transmission, the DU is configured to implement layer mapping and one or more functions (i.e., one or more of encoding, rate matching, scrambling, modulation, and layer mapping) before layer mapping, and other functions (e.g., one or more of resource element (RE) mapping, digital BF, or IFFT / add CP) after layer mapping are implemented in the RU. For uplink transmission, the DU is configured to implement demapping and one or more functions (i.e., one or more of decoding, de-rate matching, de-scrambling, demodulation, inverse discrete Fourier transform (IDFT), channel equalization, and de-RE mapping) before demapping, and other functions (e.g., one or more of digital BF or FFT / CP removal) after demapping are implemented in the RU. It can be understood that the function descriptions of the DU and the RU corresponding to various types of eCPRI can refer to the eCPRI protocol, which will not be described here.

[0090] In a possible design, the processing unit in the BBU for implementing baseband functions is referred to as a base band high (BBH) unit, and the processing unit in the RRU / AAU / RRH for implementing baseband functions is referred to as a base band low (BBL) unit.

[0091] In different systems, the CU (or CU-CP and CU-UP), DU, or RU can also have different names, but those skilled in the art can understand their meanings. For example, in an open radio access network (open-RAN, O-RAN, or ORAN) system, the CU can also be referred to as an O-CU (open CU), the DU can also be referred to as an O-DU, the CU-CP can also be referred to as an O-CU-CP, the CU-UP can also be referred to as an O-CU-UP, and the RU can also be referred to as an O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module. The network device in this application can be a virtualized device, for example, implemented by general hardware and instantiated virtualization functions, or special hardware and instantiated virtualization functions. The general hardware can be a server, for example, a cloud server.

[0092] In the embodiments of the present application, the apparatus for implementing the function of the network device can be the network device, or can be an apparatus capable of supporting the network device to implement the function, such as a chip system, a hardware circuit, a software module, or a hardware circuit plus a software module. The apparatus can be installed in the network device or used in matching with the network device. In the embodiments of the present application, only the apparatus for implementing the function of the network device is taken as an example for description, and the scheme of the embodiments of the present application is not limited in this way.

[0093] The terminal device in the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent or a user apparatus.

[0094] The terminal device can be a device providing voice / data, for example, a handheld device with wireless connection function, a vehicle-mounted device, etc. At present, some examples of terminals are: mobile phone, tablet computer, notebook computer, palm computer, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, cellular phone, cordless phone, session initiation protocol (SIP) phone, wireless local loop (WLL) station, personal digital assistant (PDA), handheld device with wireless communication function, computing device or other processing device connected to a wireless modem, wearable device, terminal device in a 5G network, or terminal device in a future evolved public land mobile network (PLMN), etc., device in a zigbee network, device in a Lora network, Bluetooth slave (BT slave), Bluetooth low energy (BLE) slave, Wi-Fi station (STA), etc. The present embodiment is not limited thereto.

[0095] The terminal device can also be a terminal device in an IoT system, also known as an IoT node. IoT is an important part of future information technology development, and its main technical feature is to connect objects through communication technology and network, so as to realize the intelligent network of man-machine interconnection and object-object interconnection. Connection can be through broadband technology or narrowband technology. IoT technology can achieve mass connection, deep coverage and terminal power saving through, for example, narrowband (NB) technology. IoT technology includes reflection communication technology, spread spectrum technology, ultra wide band (UWB), etc., which will not be described here.

[0096] In addition, the terminal device can further include a smart printer, a train detector, a gas station sensor, and the like, and the main functions include collecting data (part of the terminal device), receiving control information and downlink data of a network device, and transmitting electromagnetic waves to transmit uplink data to the network device.

[0097] By way of example and not limitation, in the embodiments of the present application, the terminal device can also be a wearable device. The wearable device can also be referred to as a wearable smart device, which is a general term for devices that are designed and developed by applying wearable technology to daily wear, such as glasses, gloves, watches, clothing, and shoes. The wearable device is a portable device that is directly worn on the body or integrated into the clothes or accessories of the user. The wearable device is not only a hardware device, but also a powerful function realized through software support and data interaction and cloud interaction. The general wearable smart device includes a full function, a large size, and can realize complete or partial functions without relying on a smart phone, such as a smart watch or smart glasses, and focuses on a certain application function and needs to cooperate with other devices such as a smart phone, such as various smart wristbands and smart jewelry for monitoring vital signs.

[0098] In the embodiments of the present application, the device for realizing the function of the terminal device can be a terminal device, or a device capable of supporting the terminal device to realize the function, such as a chip system, which can be installed in the terminal device or matched with the terminal device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices. In the embodiments of the present application, only the device for realizing the function of the terminal device is taken as an example for description, and the scheme of the embodiments of the present application is not limited.

[0099] The terminal device in the present application can be a hardware device, a software function running on a special hardware, or a software function running on a general hardware, and can also be a virtualized device, such as a general hardware and an instantiated virtualization function, or a special hardware and an instantiated virtualization function. The general hardware can be a server, such as a cloud server.

[0100] The network device and / or the terminal device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can also be deployed on the water surface; and can also be deployed on an airplane, a balloon, and a satellite in the air. The present application does not limit the scenario where the network device and the terminal device are located.

[0101] FIG. 1 is a schematic diagram of an architecture of a communication system 10 to which embodiments of the present application are applied. FIG. 1 shows a schematic diagram of a possible, non-limiting architecture of the system. As shown in FIG. 1, the communication system 10 includes a radio access network (RAN) 100 and a core network 200. Optionally, the communication system 10 further includes an Internet 300. The RAN 100 can include at least one RAN node (e.g., 110a and 110b in FIG. 1) and at least one terminal device (e.g., 120a-120j in FIG. 1). The terminal devices can be connected to the RAN devices by wireless means. The terminal devices and the terminal devices, and the RAN devices and the RAN devices, can be connected to each other by wired or wireless means. The RAN node 110a or 110b is connected to the core network 200 by wireless or wired means. The core network device in the core network 200 and the RAN node 110a or 110b in the RAN 100 can be different physical devices, respectively, or can be the same physical device integrated with the logical functions of the core network and the logical functions of the radio access network.

[0102] FIG. 1 is only a schematic diagram, and the communication system 10 can further include other network devices, such as wireless relay devices and wireless backhaul devices, which are not shown in FIG. 1.

[0103] The RAN 100 can be a 3rd generation partnership project (3GPP)-related cellular system, such as a 4G, 5G mobile communication system, or a future-oriented evolved system. The RAN 100 can also be an ORAN, a cloud radio access network (CRAN), or a zigbee network system, or a wireless fidelity (Wi-Fi) system. The RAN 100 can also be a communication system in which two or more of the above systems are integrated.

[0104] The RAN node can be a base station deployed in the air, such as a satellite base station 110a, or a base station deployed indoors, such as a micro base station or an indoor station 110b. It should be understood that the present application does not limit the specific technology and specific device form of the radio access network device. For ease of description, the following describes the base station as an example of the radio access network device.

[0105] The terminal device can be a terminal device deployed in the air, such as the helicopter or the unmanned aerial vehicle 120i in FIG. 1; or a terminal device deployed on the ground, such as the mobile phone 120a, 120e, 120f, and 120j, the vehicle 120b, the computer 120g, the printer 120h, the gas station 120c, the smart home device 120d, and the like in FIG. 1.

[0106] Optionally, the terminal device can also be used to act as a RAN node. For example, the UE can act as a scheduling entity that provides sidelink signals between terminal devices in vehicle-to-everything (V2X), device-to-device (D2D), or peer to peer, and the like.

[0107] The RAN node and the terminal device can be fixed in position or movable. The RAN node and the terminal device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can be deployed on the water surface; and can also be deployed on an airplane, a balloon, and a man-made satellite in the air. Embodiments of the present application do not limit the application scenarios of the RAN node and the terminal device.

[0108] The roles of the RAN node and the terminal device can be relative. For example, the helicopter or the unmanned aerial vehicle 120i in FIG. 1 can be configured as a RAN node, and for those terminal devices 120j that access the RAN 100 through 120i, the terminal device 120i is a RAN node; but for the RAN node 110a, 120i is a terminal device, that is, 110a and 120i communicate with each other through a wireless air interface protocol. Of course, 110a and 120i can also communicate with each other through an interface protocol between RAN nodes, and in this case, 120i is also a RAN node relative to 110a. Therefore, the RAN node and the terminal device can be collectively referred to as a communication device, and 110a, 110b, and 120a-120j in FIG. 1 can be referred to as a communication apparatus having their respective functions, such as a communication device having a RAN node function or a communication device having a terminal function.

[0109] In embodiments of the present application, the functions of the RAN node can also be performed by a module (such as a chip) in the RAN node or by a control subsystem containing RAN node functions. The control subsystem containing RAN node functions herein can be a control center in the application scenarios of the above terminal devices such as smart grids, industrial control, intelligent transportation, and smart cities. The functions of the terminal device can also be performed by a module (such as a chip) in the terminal device or by a device containing terminal device functions. The present application does not limit this.

[0110] FIG. 2 is a schematic diagram of several different communication scenarios applicable to the communication method provided by the embodiments of the present application. For example, point-to-point transmission between a RAN node and a terminal or between terminals (e.g., (a) in FIG. 2 is point-to-point transmission between a RAN node and a terminal), multi-hop transmission of a RAN node and a terminal (e.g., (b) in FIG. 2, (c) in FIG. 2), dual connectivity (DC) or multi-connectivity of multiple RAN nodes and a terminal (e.g., (d) in FIG. 2), and the like. It should be noted that the above specific communication application scenarios are only examples and do not limit the application. In particular, from the perspective of services, the embodiments of the present application are applicable to many service scenarios, such as data encoding scenarios in extended reality (XR) services, uplink large capacity scenarios, and the like. In addition, FIG. 2 does not limit the network architecture applicable to the present application, and the present application does not limit uplink, downlink, access link, backhaul link, sidelink (SL), and the like.

[0111] FIG. 3 is a schematic diagram of a signal processing process of a physical layer applicable to the embodiments of the present application. The signal processing of the physical layer can be divided into downlink processing and uplink processing.

[0112] The downlink processing is a process of transmitting information data from a higher layer after physical layer processing. Exemplarily, the downlink processing includes: performing channel coding (which can be referred to as coding for short), modulation, layer mapping, precoding, framing, IFFT, and RF or IRF frequency conversion processing on information data of layer 2 (L2) to generate an air interface signal to be transmitted.

[0113] More specifically, the transmitting end of the information data can split the information data from layer 2 into multiple transport blocks (TBs) according to the size of the TBs (TBS) supported by the system, and add a cyclic redundancy check (CRC) code to each TB. If the size of the TB after adding the CRC code exceeds the maximum code block length, the TB can be segmented to obtain multiple code blocks (CBs). Each CB after segmentation can further add a CRC code to obtain a to-be-encoded input corresponding to each CB. The to-be-encoded input is a sequence of bits to be encoded, which can specifically include information bits and check bits (i.e., CRC codes) in the CB corresponding thereto. The transmitting end can perform channel coding, such as LDPC coding, on the to-be-encoded input to obtain a corresponding coded code block. Rate matching is performed on the coded code block, and the coded code block after rate matching is concatenated to form a codeword (CW). The transmitting end can scramble the codeword to generate scrambled bits. The scrambled bits are modulated to obtain modulation symbols. After resource element (RE) mapping of the modulation symbols, the modulation symbols are mapped to multiple REs, and thus values carried on each RE can be obtained. Based on the values carried on the REs, the transmitting end can generate a baseband signal. The baseband signal can be subjected to operations such as RF or IRF processing, and then transmitted by an antenna.

[0114] The uplink processing is a process of performing physical layer processing on a signal received through an air interface. For example, the uplink processing includes: performing IRF processing on the received signal to obtain a baseband signal, and then performing physical layer signal processing through FFT, de-framing, demodulation, decoding, and the like, and delivering the obtained information data to layer 2.

[0115] More specifically, the receiving end of the signal performs RF or IRF processing on the signal received from the antenna to obtain a baseband signal. Thereafter, the physical layer of the receiving end can sequentially perform RE demapping, demodulation, descrambling, rate de-matching, channel decoding, and the like on the signal, so as to obtain a bit sequence before encoding, which can specifically include information bits and check bits.

[0116] Optionally, the receiving end can perform channel equalization after completing RE demapping and before demodulation. The channel equalization is based on a channel obtained through channel estimation, and removes the influence of the channel by using an equalization algorithm, so as to ensure correct demodulation of the signal.

[0117] Optionally, the transmitter can perform layer mapping and precoding before RE mapping after modulation. For example, the transmitter can map the modulation symbols to multiple layers, and perform precoding on the modulation symbols after layer mapping to obtain precoded signals. The precoded signals are mapped to multiple REs after RE mapping. Correspondingly, the receiver can perform channel equalization before demapping after performing demapping, and then perform demodulation; or the receiver can perform demapping after performing channel equalization, and then perform demodulation; or the receiver can perform demapping after performing de-framing, and then perform channel equalization.

[0118] Since the specific implementation of each step in FIG. 3 can be implemented by existing technology or future possible solutions, please refer to the relevant chapters in the third generation partnership project (3GPP) technical specification (TS) 38.211 for details. rd Since the specific implementation of each step in FIG. 3 can be implemented by existing technology or future possible solutions, please refer to the relevant chapters in the third generation partnership project (3GPP) technical specification (TS) 38.211 for details.

[0119] The apparatus for implementing the physical layer processing described above can be a communication device, such as a network device or a terminal, or a mobile communication chip, such as a baseband chip, and the present application does not limit it. Based on different functions, the apparatus can be divided into multiple units (or modules). For example, FIG. 4 is a schematic block diagram of an apparatus for implementing physical layer processing. FIG. 4(a) and (b) respectively show apparatuses 400A and 400B. Among them, the apparatus 400A can be used to implement uplink processing, and the apparatus 400B can be used to implement downlink processing.

[0120] As shown in FIG. 4(a) and (b), the apparatuses 400A and 400B respectively include a computing unit, a control unit and a storage unit. The computing unit can be responsible for processing the logical operation of the apparatus, which can specifically include the logical operation of encoding and / or decoding. The storage unit can be responsible for storing data in the computing process, and can also be used to store information related to coding and decoding, such as base graph. The control unit can be responsible for scheduling and controlling the computing unit and storage resources.

[0121] For example, as shown in FIG. 4(a), the computing unit of the apparatus 400A can be used to perform TB CRC calculation, BG selection, code block segmentation, CB CRC calculation, LDPC encoding and code block concatenation, etc. Among them, the BG selection can be a selection from the BG stored in the storage unit.

[0122] Exemplarily, as shown in (b) of FIG. 4, the computing unit of the apparatus 400B can be configured to perform operations such as de-rate matching, hybrid automatic repeat request (HARQ) combining, LDPC decoding, CB CRC checking, TB CRC checking, and the like.

[0123] In another possible implementation, the module for implementing LDPC encoding in the apparatus 400A is an encoder. In another possible implementation, the encoder can implement not only LDPC encoding, but also pre-processing and / or post-processing of the LDPC encoding. The pre-processing of the LDPC encoding includes one or more of the following, for example: TB CRC calculation, BG selection, code block segmentation, or CB CRC calculation. The post-processing of the LDPC encoding includes code block concatenation, for example. For example, the apparatus 400A is an encoder. Of course, the encoder can also implement other functions in addition to the LDPC encoding and the pre-processing and post-processing thereof listed above, which are not limited in the present application.

[0124] In one possible implementation, the module for implementing LDPC decoding in the apparatus 400B is a decoder. In another possible implementation, the decoder can implement not only LDPC decoding, but also pre-processing and / or post-processing of the LDPC decoding. The pre-processing of the LDPC decoding includes one or more of the following, for example: de-rate matching or HARQ combining. The post-processing of the LDPC decoding includes one or more of the following, for example: CB CRC or TB CRC. For example, the apparatus 400B is a decoder. Of course, the decoder can also implement other functions in addition to the LDPC decoding and the pre-processing and post-processing thereof listed above, which are not limited in the present application.

[0125] For the convenience of understanding the embodiments of the present application, several terms involved in the present application are explained as follows.

[0126] Channel coding: encoding information transmitted through an unreliable channel in digital communication to improve the reliability of information transmission. In channel coding, the sending end can adopt a certain coding type to convert the original information (such as information bits) into a certain format of coded data and transmit it through the channel; the receiving end needs to decode the received data and restore the original information. The most critical part of channel coding is forward error correcting coding (FEC). The purpose of error correcting coding is to ensure that the receiving end can automatically correct errors occurring in data transmission through as small a redundancy overhead as possible. At the same time, the smaller the required overhead, the higher the efficiency of the coding. The coding types of traditional channel coding generally include linear block code (LBC) (such as Hamming code, Golay code, BCH code (Bose-Chaudhuri-Hocquenghem code), RS code (Reed-Solomon code), etc.), convolutional code, and concatenated code. These codes have different characteristics and performances and are suitable for different scenarios.

[0127] Code rate: the proportion of useful information in the total information in the coded data stream. In this paper, useful information is referred to as information bits, and coded data stream is referred to as coded bits, which includes information bits and check bits (or called redundant bits). For example, the information bits are K bits, and the coded bits after channel coding are N bits, and the coding rate is K / N. Among them, the number of coded bits after channel coding can also be referred to as code length. It can be understood that the higher the redundancy, the lower the coding rate, the stronger the anti-interference ability, but the lower the transmission efficiency; the lower the redundancy, the higher the coding rate, the weaker the anti-interference ability, but the higher the transmission efficiency.

[0128] LDPC code: a linear block code. Because the check matrix of this linear block code has the sparse characteristic, the proportion of elements with value 1 in the check matrix is extremely small, so it is also called LDPC code. For an LDPC code with K information bits and code length N, the dimension of the check matrix is (N-K) x N, and the corresponding code word can be defined by the check matrix H:

[0129] Among them, c represents K information bits; w represents (N+D-K) check bits; [c w] T represents a column vector with length (N+D) composed of K information bits and (N+D-K) check bits; D represents the number of puncturing bits, D is a positive integer, an example, D is 2Z c , Z crepresents the minimum value of Z, Z is a lifting size, the value of Z can be predefined, Z is an integer greater than or equal to 1.

[0130] The process of LDPC encoding based on the check matrix H, that is, the process of obtaining the encoding output [c w] based on the check matrix H and the input to be encoded c. T The process of LDPC decoding based on the check matrix H, that is, the process of recovering the input to be encoded c based on the check matrix H and the input to be decoded [c w] T .

[0131] Check matrix: can be used for LDPC encoding or LDPC decoding. In this application, the check matrix is denoted as a matrix H with a dimension of MxN. Wherein, M is the number of check bits, which can satisfy: M=N-K. Therefore, the dimension of the check matrix can also be denoted as (N-K)xN.

[0132] In the check matrix H, each row corresponds to a check equation of the LDPC code, and the (N-K) check equations correspond to the (N-K) check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and the N symbols correspond to the N variable nodes of the LDPC code. The non-zero element h m,n in the check matrix H represents the connection between the mth check node and the nth variable node, wherein m can be an integer greater than or equal to 0 and less than or equal to (M-1), and n can be an integer greater than or equal to 0 and less than or equal to (N-1). The number of non-zero elements in each row of the check matrix H is the degree of the check node, and the number of non-zero elements in each column is the degree of the variable node. If the degrees of all check nodes are equal, and the degrees of all variable nodes are equal, the LDPC code corresponding to the matrix is a regular code, otherwise it is an irregular code.

[0133] For example, the check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is as follows:

[0134] In the check matrix H, each row includes 10 variable nodes, and each column includes 5 check nodes. If c0, c1, …, c9 are used to represent the variable nodes, and p0, p1, …, p4 are used to represent the check nodes, the check matrix H can be represented by a graph model, such as Tanner graph, factor graph and tree graph, etc.

[0135] Figure 5 shows an example of a Tanner graph. The Tanner graph shown in Figure 5 corresponds to the check matrix H listed above, and the degree of a node is equal to the number of edges connected to the node in the Tanner graph. For example, h 0,0If the value of h 1,1 If the value of h

[0136] In the Tanner graph, a closed path formed by some edges connecting different vertices, which starts from one vertex, goes along edges between vertices, and returns to the same vertex, can be called a "cycle". The number of edges passed is called the length of the cycle (may be referred to as cycle length). Taking FIG. 5 as an example, starting from variable node c0, going along the edge between variable node c0 and check node p0 can reach check node p0, going along the edge between check node p0 and variable node c6 can reach variable node c6, going along the edge between variable node c6 and check node p1 can reach check node p1, and finally going along the edge between check node p1 and variable node c0 can return to variable node c0, thus forming a cycle with a length of 4 (as shown by the black thick line in FIG. 5).

[0137] In the LDPC code, since the iterative probabilistic decoding causes information to be exchanged between nodes, a cycle inevitably affects the decoding result. Information starting from a node of the cycle will be continuously transmitted along the nodes on the cycle and return to the node itself, thereby causing the information of the node itself to be continuously accumulated, and further causing the probability of decoding failure to be large. The shorter the cycle length is, the shorter the path that the information needs to take to return to itself is, the faster the error propagates in the iteration process, and the higher the probability of decoding failure is. In other words, a short cycle will seriously affect the decoding performance.

[0138] It can be seen that a cycle needs at least 4 nodes to form a cycle with a length of 4. In other words, the minimum cycle length is 4. Next are 6-cycle, 8-cycle, and so on, which are not enumerated.

[0139] It should be noted that the above is only for the convenience of understanding and description, and takes the Tanner graph as an example to illustrate a cycle. In fact, the cycle is not limited to the Tanner graph, and can also be identified in the base graph, for example, a cycle is also illustrated in the base graph in FIG. 10 below, which can be specifically seen from the dashed line in FIG. 10.

[0140] Quasi-cyclic LDPC (QC-LDPC) code: a subclass of LDPC. The parity check matrix of QC-LDPC has quasi-cyclic characteristics, and the parity check matrix can be represented in a simplified manner according to the quasi-cyclic structure. Exemplarily, for a QC-LDPC code of (N, K), the parity check matrix H can be represented as:

[0141] wherein M = mb x Z, N = n b x Z, P i,j represents a cyclic shift matrix (also referred to as a cyclic shift square matrix, a cyclic shift submatrix) of dimension Z x Z or an all-zero matrix (also referred to as an all-zero submatrix, an all-zero square matrix) of dimension Z x Z, which can be simplified by its corresponding cyclic shift coefficient V i,j . For example, the cyclic shift matrix is defined as a cyclic right shift matrix of a unit matrix, each element "1" in the unit matrix is cyclically shifted right by V i,j . When V i,j = -1, P i,j is an all-zero matrix of Z x Z; when V i,j = 0, P i,j is a unit matrix of Z x Z, that is, each element "1" in the unit matrix is cyclically shifted right by 0 (or not shifted); when V i,j ∈ [-1, Z max -1], P i,j is a matrix obtained by cyclically shifting right each element "1" in the unit matrix of Z x Z by V i,j , Z max is the maximum value of Z, Z≤Z max .

[0142] The process of converting an element P i,j in the parity check matrix H into a cyclic shift matrix or an all-zero matrix can be represented by a conversion function g(V i,j , Z) as follows:

[0143] where % represents a modulo operation; the value of V i,j may be predefined, for example, by a protocol, such as defined in Table 5.3.2-2 and Table 5.3.2-3 in the 3rd generation partnership project (3GPP) technical specification (TS) 38.212.

[0144] Taking Z = 4 and Z max = 8 as an example, the correspondence between the elements P i,j in the parity check matrix and the cyclic shift matrix or the all-zero matrix is as follows:

[0145] The element "-1" corresponds to the matrix , that is, an all-zero matrix; the elements "0" to "7" correspond to the cyclic shift matrix, wherein the elements "0" and "4" correspond to the matrix , the elements "1" and "5" correspond to the matrix Element "2" and "6" correspond to the matrix Element "3" and "7" correspond to the matrix

[0146] Base graph and base matrix: In some implementations, the base graph can also be simply represented as a table, array or sequence indicating the row and column positions of non-zero elements. In other implementations, the base graph can be identified by a base matrix.

[0147] The base graph can be represented as a base matrix with dimensions m b ×n b . The base matrix can be used to construct the parity check matrix of the QC-LDPC code. The base matrix has dimensions m b ×n b , and the corresponding parity check matrix has dimensions (m b ×Z) × (n b ×Z). It can be seen that each element in the base matrix can be replaced by a matrix with dimensions Z × Z, which can be referred to as a sub-matrix with dimensions Z × Z in the parity check matrix.

[0148] It should be noted that the matrix with dimensions Z × Z and the sub-matrix with dimensions Z × Z in the above are relative to different objects. For an independent element in the base matrix, it can be replaced by a matrix with dimensions Z × Z, and the matrix with dimensions Z × Z is only a part of the parity check matrix, and thus it can be referred to as a sub-matrix of the parity check matrix.

[0149] The base matrix can include zero elements and non-zero elements. The zero element in the base matrix can be replaced by a zero matrix with dimensions Z × Z; and the non-zero element in the base matrix can be replaced by a circulant parity check matrix P i,j , where i and j represent the row and column positions of the non-zero element in the base matrix, and P i,j Specifically, the circulant parity check matrix P i,j can be determined according to the conversion function g(V i,j , Z) above, which will not be repeated here.

[0150] In the base matrix, the zero element can be represented by 0, the non-zero element can be represented by 1, and the number of bits of the cyclic shift can be determined according to the conversion function g(V i,j , Z) above; or the zero element can be represented by -1, the non-zero element can be represented by 0, and the number of bits of the cyclic shift can be determined according to the conversion function g(V i,j , Z) above; or the zero element can be represented by -1, the non-zero element can be represented by a value greater than or equal to 0, and the number of bits of the cyclic shift can be indicated by the value of the non-zero element. The present application does not limit this.

[0151] For convenience of distinguishing and description, in this document, the value of the non-zero element of the base matrix is denoted as a first value, and the value of the zero element is denoted as a second value. Exemplarily, the first value can be 1, and the second value can be 0; or the first value can be 0, and the second value can be -1; or the first value can be greater than or equal to 0, and the second value can be -1. The first value corresponds to a circulant shift matrix in the parity check matrix, and the second value corresponds to an all-zero matrix in the parity check matrix.

[0152] Currently, two base graphs, BG 1 and BG 2, are defined in the protocol of NR. The base matrix defined by BG 1 has a dimension of 46x68, and the core matrix has a dimension of 4x26, which is mainly used in scenarios with high throughput requirements, high code rates, and long code lengths. The base matrix defined by BG 2 has a dimension of 42x52, and the core matrix has a dimension of 4x14, which is mainly used in scenarios with low throughput requirements, low code rates, and short code lengths.

[0153] FIG. 6 is a structural diagram of a parity check matrix provided by an embodiment of the present application. The structure of the parity check matrix shown in FIG. 6 is a relatively common Raptor-like structure in the current 5G. As shown in FIG. 6, the parity check matrix of the Raptor-like LDPC structure includes the following five parts:

[0154] Part A: information bit part of the core matrix;

[0155] Part B: check bit part of the core matrix, having a double diagonal structure.

[0156] Part C: all-zero matrix;

[0157] Part D: information bit part of the extension matrix;

[0158] Part E: check bit part of the extension matrix, having a single diagonal structure.

[0159] It should be understood that the descriptions of the core matrix, the all-zero matrix, the extension matrix, and the like described above are all relative to the respective parts. In the parity check matrix, the core matrix can be referred to as a core submatrix, the all-zero matrix can be referred to as an all-zero submatrix (or simply an all-zero submatrix), and the extension matrix can be referred to as an extension submatrix.

[0160] The parity check matrix includes a core matrix H core and an extension matrix H ext . The core matrix H core includes Part A and Part B in FIG. 6 (shown as a black thick line box in the figure), which is a high code rate parity check matrix and can be represented as [A B]. The dimension of the core matrix H core is M core x N core , M core ≤ M core , N core+ K. The core matrix H is based on the kernel matrix H core The extension matrix H is generated by extension ext The extension matrix H can correspond to parts D and E of FIG. 6. The extension matrix H ext The check matrix H has one more column for each added row. It should be understood that the names of the various parts above are named only for ease of differentiation and should not be construed as limiting the present application. For example, part A can also be referred to as the information column region corresponding to a high code rate, part B can also be referred to as the core check region corresponding to a high code rate, and parts D and E can also be referred to as the incremental redundancy region.

[0161] It should be noted that since the check matrix can be generated based on the base matrix, each element in the base matrix can be converted into a Z x Z matrix, and thus the dimension of the core matrix H core x N core may also correspond to a sub-matrix of the base matrix with a dimension of (M core / Z) x (N core / Z). Since part C of the check matrix is a full zero sub-matrix and part E is a single diagonal sub-matrix, both of which have relatively regular structures, when describing the check matrix or the base matrix, the A part, the B part, and the D part can also be mainly described. In the following, in order to facilitate explanation and understanding, parts C and E will not be described in detail, but those skilled in the art can understand that after the core matrix and the extension matrix are determined, the other parts can be obtained according to the structures described above, and then the complete check matrix is obtained.

[0162] It should also be noted that in some other implementations, the core matrix can also include rows and / or columns in addition to parts A and B. For example, the number of rows of the core matrix is the number of rows of the matrix [A B] + 1, and the number of columns of the core matrix is the number of columns of the matrix [A B] + 1. The core matrix is defined exemplarily for the convenience of understanding the embodiments of the present application and should not be construed as limiting the present application. The present application does not limit the dimension of the core matrix. In the following, the core matrix is still understood as [A B] unless otherwise specified.

[0163] Exemplarily, FIG. 7 is a Raptor-like structure of two different dimensions provided by the embodiments of the present application. The 5G protocol defines two different BGs: BG 1 and BG 2, as shown in (a) and (b) of FIG. 7, respectively. In the structure shown in (a) of FIG. 7, the size of BG 1 is 46 x 68, the size of the core matrix H core is 4 x 26, and it is mainly applied to a scenario with a high throughput requirement, a high code rate, and a long code length. In the structure shown in (b) of FIG. 7, the size of BG 2 is 42 x 52, the size of the core matrix H core is 4 x 14, and it is mainly applied to a scenario with a low throughput requirement, a low code rate, and a short code length.

[0164] In practical applications, which BG is used to generate the check matrix, and then used for LDPC encoding and decoding, can be determined according to the TBS and the code rate R. FIG. 8 shows an example of the relationship between BG selection and TBS and code rate. As shown in the figure, if A≤292; or A≤3824 and R≤0.67; or R≤0.25, BG 2 is selected; otherwise, BG 1 is selected. Wherein, the message block length A is the TBS excluding the CRC, R can be the code rate indicated by the MCS index, which can be understood as the code rate that is expected to be achieved, and can be referred to as the target code rate, rather than the actual code rate.

[0165] At present, when the check matrix generated by BG 1 and BG 2 is used for LDPC encoding and decoding, in a lower symbol signal-to-noise ratio interval, the BLER significantly decreases with the increase of SNR, which can be referred to as the waterfall region; and in a higher signal-to-noise ratio interval, the trend of BLER decreasing with the increase of SNR slows down, and a relatively obvious error floor appears, which can be referred to as the error floor region. This may lead to a low decoding performance in the error floor region, especially for some scenarios with high reliability requirements, which has potential risks and impacts.

[0166] FIG. 9 is a performance simulation diagram provided by an embodiment of the present application. FIG. 9 is a result of BLER performance simulation of a code rate (i.e., the aforementioned target code rate) of 0.67 and different information bit lengths K, using BG 2 of NR to generate the check matrix, and using quadrature phase shift keying (QPSK) modulation in an additive white Gaussian noise (AWGN) channel. The horizontal coordinate of FIG. 9 represents the symbol signal-to-noise ratio (Es / N0), i.e., the ratio of the energy of each symbol (Es) to the noise power spectral density (N0), and the vertical coordinate is the BLER. Wherein, Es / N0 and SNR are in a proportional relationship, for example, they have a conversion relationship as follows:

[0167] For complex signals: Es / N0 (dB) = 10log 10 (T sym / T samp )+SNR (dB);

[0168] For real signals: Es / N0 (dB) = 10log 10 (0.5T sym / T samp )+SNR (dB);

[0169] All units are in decibels (dB), T sym represents the symbol period, and T samp represents the sampling interval.

[0170] It can be seen that the greater the Es / N0, the greater the SNR; the smaller the Es / N0, the smaller the SNR. Therefore, the relationship between the SNR and the BLER can be seen from the relationship between the Es / N0 and the BLER.

[0171] It can be seen from the figure that for a fixed information bit length K, in the lower symbol SNR interval, the BLER curve drops steeply, and the decoding performance is good; but as the symbol SNR increases, the slope of the BLER curve gradually slows down, and a relatively obvious error floor appears.

[0172] The researchers further collected the number of error bits of each column that appeared in the error floor area when BG 2 was used, and the results in FIG. 10 were obtained. FIG. 10 is a graph of the corresponding relationship between the elements of BG 2 and the number of error bits obtained by statistics according to an embodiment of the present application.

[0173] Each square in FIG. 10 represents an element in the base matrix, and the square with a filling pattern represents an element in the base matrix with a first value, which can correspond to a cyclic shift submatrix in the check matrix; and the blank square represents an element in the base matrix with a second value, which can correspond to a zero submatrix in the check matrix.

[0174] It can be seen from FIG. 10 that the number of errors in different columns is not the same. Some columns have a relatively large number of error bits, and these columns generally have a light column weight. In this case, once the elements in these columns participate in the formation of the ring in the base matrix (as shown by the black dashed line in the figure), they participate in fewer check equations, so they have less external information input, and therefore are more prone to errors.

[0175] Therefore, the all-zero submatrix in the check matrix is partially replaced by a cyclic shift submatrix by adding the patch element. Thus, the number of non-zero elements in the check matrix can be increased, thereby reducing the existence of light column weight in the check matrix, improving the decoding performance in the error floor area, and improving reliability.

[0176] FIG. 11 is a schematic flowchart of a method for obtaining a check matrix according to an embodiment of the present application. The method shown in FIG. 11 can be performed by a communication apparatus, which can be a communication device such as a network device or a terminal device, a component configured in a communication device such as a circuit or a chip (e.g., a modem chip, also known as a baseband chip, or a SoC chip or a SIP chip containing a modem core, etc.) inside the communication device, a logic module or software capable of implementing part or all of the functions of the communication apparatus, etc., without limitation.

[0177] It should be understood that the check matrix obtained based on the method can be used for LDPC encoding or LDPC decoding. Therefore, the method shown in FIG. 11 can be applied to an encoding end, for example, can be performed by the apparatus 400A shown in FIG. 4, or can be applied to a decoding end, for example, can be performed by the apparatus 400B shown in FIG. 4.

[0178] The method 1100 for generating a check matrix shown in FIG. 11 can include steps 1110 to 1120. Optionally, the method 1100 further includes one or more of steps 1130 or 1140. Each step in the method 1100 shown in FIG. 11 is described in detail below.

[0179] In step 1110, a first base matrix is obtained, the first base matrix including Q patch elements.

[0180] In the present application, a patch element refers to an element with a first value. The positions of the Q patch elements in the first base matrix coincide with the positions of Q elements with a second value in the second base matrix. Here, the second base matrix can be understood as a matrix form of a base graph, or a base matrix obtained based on the base graph. The difference between the first base matrix and the second base matrix is that the values of the Q elements are different. In the second base matrix, the values of the Q elements are the second value, corresponding to an all-zero submatrix in the check matrix, while in the first base matrix, the values of the Q elements are the first value, corresponding to a cyclic shift submatrix in the check matrix.

[0181] One possible implementation of step 1110 is that the first base matrix is obtained based on the second base matrix. Accordingly, step 1110 specifically includes obtaining the first base matrix based on the second base matrix. That is, the communication apparatus can first obtain the second base matrix, and then replace the Q elements with the second value in the second base matrix with Q elements with the first value (i.e., the Q patch elements) to obtain the first base matrix.

[0182] In this implementation, the Q patch elements can be used to replace the Q elements with the second value in the second base matrix, and the first base matrix is obtained by patching the Q elements with the second value in the second base matrix or adding Q elements with the first value to the second base matrix. In this paper, it is named as patch element for the convenience of distinguishing and understanding, but it should not constitute any limitation to the present application. The patch element can also be called element, replacement element, correction element, etc., without limitation.

[0183] It should be understood that the "patch", "replace", "add" and the like described above are only descriptions for the convenience of understanding, and in the specific implementation, the actions of "patching", "replacing", "adding" and the like do not necessarily need to be performed.

[0184] It should be noted that the first base matrix includes Q patch elements, which does not mean that the first base matrix only includes Q elements with the first value. The first base matrix can also include more elements with the first value and / or one or more elements with the second value. The second base matrix can also not only include Q elements with the second value. The second base matrix can also include more elements with the second value and / or one or more elements with the first value. Since the difference between the first base matrix and the second base matrix is the above-mentioned Q elements, the Q elements are mainly described here.

[0185] Optionally, before obtaining the first base matrix according to the second base matrix, the method further includes obtaining the second base matrix.

[0186] As described above, the second base matrix can be in the form of a base graph matrix or a base matrix obtained based on the base graph. In an implementation, the first base matrix can be obtained based on the target code rate and TBS. In the protocol of NR, two base graphs, BG 1 and BG 2, are defined, and the relationship between BG selection and TBS and code rate is shown in the foregoing description in combination with FIG. 8. Therefore, the communication device can select one of BG 1 and BG 2 to use according to the target code rate and TBS. The target code rate can be determined by the MCS index.

[0187] The second base matrix can be a matrix pre-existing in the communication device. For example, in (a) or (b) of FIG. 4, the second base matrix can be a matrix pre-existing in the storage unit. The computing unit can read the second base matrix from the storage unit according to the TBS and the target code rate when there is a coding requirement.

[0188] Another possible implementation of step 1110 is to read the first base matrix from pre-stored base matrices. Illustratively, the communication device can generate a plurality of selectable base matrices in advance for different base graphs, and for different base graphs, the number and position of patch elements are defined in advance. Therefore, the plurality of selectable base matrices correspond to the base graphs, and the base matrices with patch elements are added. When there is a coding requirement, the communication device can select a corresponding base matrix as the first base matrix according to the current target code rate and TBS by using the foregoing manner of selecting a base graph.

[0189] In step 1120, a check matrix is obtained according to the first base matrix.

[0190] The process of obtaining a check matrix according to a base matrix has been described in detail in the foregoing term introduction in combination with the check matrix and the base matrix, and will not be described here again.

[0191] For the convenience of distinguishing and description, the check matrix obtained according to the first base matrix is referred to as the first check matrix, and the check matrix obtained according to the second base matrix and not obtained according to the first base matrix is referred to as the second check matrix. Since the first base matrix contains more elements with the first value than the second base matrix, the first check matrix contains more cyclic shift sub-matrices than the second check matrix. In other words, the first check matrix contains more elements with the value 1 than the second check matrix. In this way, the number of elements with the value 1 in part of the columns of the first check matrix increases, and the column weight increases.

[0192] Therefore, the check matrix obtained based on the first base matrix proposed in the embodiments of the present application has a reduced number of zero sub-matrices and an increased number of cyclic shift sub-matrices compared with the check matrix obtained based on the second base matrix. This is beneficial to increase the number of non-zero elements in the check matrix, reduce the existence of light column weight in the check matrix, improve the decoding performance of the flat area, and improve the reliability. Therefore, it can be applied to some scenarios with high reliability requirements to reduce the risk.

[0193] Optionally, the method further includes step 1130: performing LDPC encoding or LDPC decoding based on the check matrix.

[0194] As described before, the check matrix can be used for LDPC encoding or LDPC decoding. If the communication device needs to send data, LDPC encoding can be performed based on the check matrix; if the communication device receives data, LDPC decoding can be performed based on the check matrix. The following will briefly describe the flow by taking LDPC encoding and LDPC decoding as examples respectively.

[0195] LDPC encoding:

[0196] If the communication device needs to send data, the data can be encoded and then sent. Illustratively, the communication device can pre-process the data obtained from the higher layer to obtain information bits to be encoded, and encode the information bits to be encoded based on the check matrix by LDPC.

[0197] As mentioned before, the check matrix H satisfies:

[0198] where c represents the information bits to be encoded, including K information bits, denoted as c0, …, c K－1 ; w represents (N+D-K) check bits, denoted as: c K , …, c N+D－K－1 .

[0199] The process of LDPC encoding based on the check matrix H is as follows: taking K information bits c0, …, c K－1 as input, since the check matrix H is known, (N+D-K) check bits c K , …, c N+D－K－1 can be solved by calculation. Thus, the output, i.e., (N+D) encoded bits: c0, …, c K－1 , c K , …, c N+D－K－1 , can be obtained.

[0200] The encoded bits obtained by encoding can be sent out after modulation, layer mapping, precoding, framing, IFFT, IRF, etc.

[0201] More detailed descriptions of each step before and after encoding can be found in the foregoing description in connection with FIG. 3, and will not be repeated here.

[0202] LDPC decoding:

[0203] If the communication device receives data, the data can be decoded and then sent to the higher layer. Illustratively, the communication device can pre-process the signal received from the air interface, such as IRF, FFT, de-framing, de-layer mapping, channel equalization, demodulation, etc., to obtain encoded bits to be decoded, and decode the encoded bits to be decoded based on the check matrix by LDPC.

[0204] Illustratively, the communication device can use the sum-product algorithm (SPA) and its simplified Min-Sum algorithm for decoding. For convenience of distinguishing and description, the log-likelihood ratio (LLR) of the (N+D) encoded bits obtained by demodulating the signal received by the communication device is denoted as: q0, …, q N+D-1, which are also the initial values of the a posteriori information of each variable node. The SPA algorithm uses the connection relationship between the variable nodes and the check nodes of the check matrix H to iteratively update the a posteriori information q0, …, q N+D-1 Finally, the decision result of each variable node (i.e., the received coded bit) is obtained according to the a posteriori information For more detailed descriptions of the various steps before and after decoding, refer to the related descriptions in the foregoing with reference to FIG. 3, which will not be repeated here.

[0205] For the convenience of understanding, the process of data transmission is described here by taking the data interaction between the communication apparatus and another communication apparatus as an example. In the following, for the convenience of distinguishing and description, the communication apparatus is denoted as communication apparatus #1, and the other communication apparatus in communication therewith is denoted as communication apparatus #2.

[0206] The communication apparatus #1 can pre-process the information data obtained from a higher layer to obtain a bit sequence to be encoded, perform LDPC encoding on the bit sequence to be encoded based on a check matrix, and send the coded bits obtained by encoding out after modulation, layer mapping, precoding, framing, IFFT, IRF, and the like. The communication apparatus #2 can perform IRF, FFT, framing, layer demapping, channel equalization, demodulation, and the like on the received signal to obtain coded bits to be decoded after receiving the signal over the air, and then send the coded bits to be decoded to a higher layer after performing LDPC decoding thereon. The check matrix used for LDPC encoding and the check matrix used for LDPC decoding can both be the check matrix obtained based on the method described above, i.e., the check matrix obtained based on the first base matrix.

[0207] It can be understood that the communication apparatus #1 and the communication apparatus #2 in the foregoing can be swapped, i.e., the communication apparatus #2 sends data and performs LDPC encoding, and the communication apparatus #1 receives data and performs LDPC decoding. For the sake of brevity, no further details will be provided.

[0208] In the embodiments of the present application, whether the communication apparatus uses the first base matrix can be pre-configured.

[0209] For the convenience of distinguishing and description, the scheme provided by the present application, which obtains a check matrix (i.e., the first check matrix described above) based on a first base matrix and then performs LDPC encoding and decoding based on the check matrix, is denoted as scheme 1, and the scheme which obtains a check matrix (i.e., the second check matrix described above) based on BG (or in other words, based on a second base matrix) according to the definition of the current protocol and then performs LDPC encoding and decoding based on the check matrix is denoted as scheme 2.

[0210] If the communication device is pre-configured to perform Scheme 1 but not Scheme 2, such as being installed with computer programs for performing Scheme 1 but not Scheme 2, or having circuitry for performing Scheme 1 but not Scheme 2, the communication device can directly perform LDPC encoding or decoding based on the aforementioned procedure (e.g., the procedure shown in steps 1110-1130) when there is a need for encoding or decoding.

[0211] The communication device can also be configured to perform both Scheme 1 and Scheme 2, such as being installed with computer programs for performing both Scheme 1 and Scheme 2, or having circuitry for performing both Scheme 1 and Scheme 2. In this case, the communication device can determine whether to use the first base matrix before step 1110, and perform the aforementioned procedure when it is determined to use the first base matrix.

[0212] Optionally, the method further comprises step 1140 of determining whether to use the first base matrix.

[0213] Accordingly, step 1110 comprises obtaining the first base matrix when it is determined to use the first base matrix.

[0214] Since the first base matrix is a base matrix including patch elements, determining whether to use the first base matrix can be replaced by determining whether to use patch elements, or determining whether to enable patch elements, or determining whether to add patch elements, etc.

[0215] Since the check matrix obtained based on the first base matrix is referred to as the first check matrix, and the check matrix obtained based on the second base matrix is referred to as the second check matrix, determining whether to use the first base matrix can also be replaced by determining whether to use the first check matrix, or determining whether to use the second check matrix.

[0216] The communication device can determine whether to use the first base matrix by itself, or according to an indication from another communication device with which it communicates. For the convenience of distinguishing and explanation, the communication device is referred to as communication device #1, and the other communication device is referred to as communication device #2.

[0217] In a possible implementation, the step 1140 specifically includes: determining to use the first base matrix in a case where a first condition is met.

[0218] That is, the communication device 1 can determine whether to use the first base matrix according to the first condition, or whether to perform the scheme 1 or the scheme 2. Exemplarily, the first condition can be related to a channel environment, a capability of the communication device 1, a service scenario, and the like.

[0219] In an example, the first condition is related to a service scenario. The first condition can be, for example, that the first base matrix is used in an ultra reliable low latency communication (URLLC) scenario, and the first base matrix is not used in other scenarios.

[0220] In an embodiment of the present application, it is assumed that the communication device 1 is applied to the URLLC scenario, and thus it can be determined to use the first base matrix.

[0221] In another example, the first condition is related to a channel environment. The first condition can be, for example, that the first base matrix is used when a signal-to-noise ratio is greater than or equal to a threshold value, and the first base matrix is not used when the signal-to-noise ratio is less than the threshold value. The channel environment can be determined by channel state information (CSI) or the like.

[0222] In an embodiment of the present application, it is assumed that the channel environment meets the first condition, and thus it can be determined to use the first base matrix.

[0223] In yet another example, the first condition is related to a capability of the communication device. The first condition can be, for example, that the communication device is configured to perform the scheme 1 but not the scheme 2, or is configured to perform the scheme 1 and the scheme 2, and it is determined to use the first base matrix.

[0224] Optionally, the method further includes: sending first indication information, the first indication information being used to indicate the use of the first base matrix, or the first indication information being used to indicate the first base matrix.

[0225] After the communication device 1 determines to use the first base matrix, the communication device 1 can also notify a communication device 2 in communication therewith, through first indication information, whether to use the first base matrix, or directly indicate the first base matrix to be used to the communication device 2. Thus, the two ends of the transceiver can obtain the check matrix based on the same base matrix, and then perform LDPC encoding and decoding. In this way, the decoding performance can be improved.

[0226] In one example, the communication device 1 is a base station, and the communication device 2 is a terminal. The base station can indicate to the terminal whether to use the first base matrix through the first indication information. For example, the first indication information can be an indication bit in downlink control information (DCI). When the indication bit is 1, it indicates to use the first base matrix; and when the indication bit is 0, it indicates to use the second base matrix without using the first base matrix.

[0227] In another example, the communication device 1 is a terminal, and the communication device 2 is a base station. The terminal can indicate to the base station whether to use the first base matrix through the first indication information. For example, the first indication information can be an indication bit in uplink control information (UCI). When the indication bit is 1, it indicates to use the first base matrix; and when the indication bit is 0, it indicates to use the second base matrix without using the first base matrix.

[0228] In another possible implementation, the method further includes: receiving second indication information, the second indication information being used to indicate to use the first base matrix, or the second indication information being used to indicate the first base matrix; and the step 1140 specifically includes: determining to use the first base matrix according to the second indication information.

[0229] That is, the communication device 1 can also not determine whether to use the first base matrix by itself, but perform corresponding operations according to the indication of the communication device 2.

[0230] Based on the above scheme, the communication device can determine whether to use the first base matrix according to actual needs to obtain the check matrix. Thus, different schemes can be more flexibly selected to cope with different scenarios, and greater benefits can be obtained in different scenarios.

[0231] The foregoing describes in detail the specific process of the method for obtaining the check matrix provided by the embodiments of the present application in combination with the drawings. The determination of the positions of the Q patch elements will be described in detail below.

[0232] Optionally, the Q patch elements are located in the first m b 'rows of the first base matrix, m b ' satisfying: R is a target code rate, k b is the number of columns of information bits in the first base matrix, k b is a positive integer; d b is the number of columns of punctured bits (hereinafter referred to as punctured columns) in the first base matrix, d b is a non-negative integer less than or equal to k b It can be understood that the punctured columns D=d bXZ, d b 0 means no punctured column, d b greater than 0 means one or more punctured columns are set; means rounding up. It can be understood that, since the number of rows of the first base matrix is m b , m b ' is a positive integer less than or equal to m b .

[0233] For the convenience of understanding, the relationship between the number of rows of the check matrix and the code rate will be first explained in combination with BG 2 defined in the NR protocol.

[0234] The size of BG 2 in the NR protocol is 42x52, and the size of the core matrix is 4x14. Generally, the core matrix corresponding sub-matrix (such as denoted as sub-matrix H') in the check matrix H can be preferentially used for LDPC encoding, that is, the first (4xZ) rows of the check matrix H correspond to the first 4 rows in the base graph. That is, the number of rows actually participating in LDPC encoding in the check matrix is (4xZ) rows, which correspond to the first 4 rows in the base graph.

[0235] Since the size of the core matrix is 4x14, the first 10 columns are information bit parts, which are associated with the first (10xZ) information bits in the input to be encoded; the last 4 columns are check bits, which are associated with (4xZ) check bits. Assuming that the first two columns of the base graph are punctured columns, if the first (4xZ) rows (i.e., corresponding to the first 4 rows in BG 2) in the check matrix H are used for LDPC encoding, the code rate R = 10 / (10+4-2) = 0.833 can be obtained; if the first (5xZ) rows (i.e., corresponding to the first 5 rows in BG 2) in the check matrix H are used for LDPC encoding, the code rate R = 10 / (10+5-2) = 0.769 can be obtained; if the first (6xZ) rows (i.e., corresponding to the first 6 rows in BG 2) in the check matrix H are used for LDPC encoding, the code rate R = 10 / (10+5-2) = 0.714 can be obtained; if the first (7xZ) rows (i.e., corresponding to the first 7 rows in BG 2) in the check matrix H are used for LDPC encoding, the code rate R = 10 / (10+7-2) = 0.667 can be obtained; and so on, which will not be enumerated.

[0236] As can be seen, the fewer the number of rows participating in encoding in the check matrix, the higher the code rate; the more the number of rows participating in encoding in the check matrix, the lower the code rate.

[0237] It should be noted that the above uses the first (m b 'xZ) rows in the check matrix H (for BG 2, m b ' is a positive integer less than or equal to 52; for BG 1, m bThe LDPC encoding is performed on the first m b The LDPC encoding is performed on the first m b The LDPC encoding is performed on the first m b The LDPC encoding is performed on the first m

[0238] As can be seen from the relationship between the number of rows of the parity check matrix and the code rate, if the cyclic shift sub-matrix is added in the first m b The first m b The first m b Therefore, the Q patch elements can be controlled in the first m b Therefore, the positions of the Q patch elements can be determined according to the target code rate.

[0239] Suppose the first d b The code rate R satisfies:

[0240] For the input to be encoded with a known target code rate, m b The value of m

[0241] In a possible design, the relationship between the value of m b For example, the first mapping relationship can indicate a plurality of code rates and a plurality of values of m b The value of m b The value of m

[0242] Table 1 is an example of the first mapping relationship. It can be understood that the first mapping relationship can include one or more of the plurality of corresponding relationships between R and m b The following table 1 can also be represented by multiple tables.

[0243] Table 1

[0244] It should be understood that Table 1 exemplified above is merely one possible form of the first mapping relationship and should not be construed as limiting this application in any way. This application does not limit the specific form of the mapping relationship; for example, it could also be in the form of a formula, an array, or a sequence. It should also be understood that the first mapping relationship can be predefined by the protocol, calculated by the communication device itself, obtained from other devices, or indicated by other devices; this application does not limit this.

[0245] In this embodiment, the range of rows of the Q patch elements in the first base matrix can be determined according to the above... The value can be calculated using the relational formula, or it can be obtained using the first mapping relationship mentioned above. If obtained using the first mapping relationship, this first mapping relationship can be stored in the communication device in advance. When there is a need for encoding and decoding, the corresponding m can be determined according to the target code rate. b The value of '.

[0246] The patch elements identified above are located in the first m steps of the first basis matrix. b 'Row is just a broad range. This application can further provide a method for determining the row and column positions of patch elements in the first base matrix.'

[0247] For example, the positions of the Q patch elements can be described by their row and column indices in the first base matrix. That is, the position information of the Q patch elements includes their row and column indices. The determination of the row and column indices of the patch elements will be explained in detail below.

[0248] Column index:

[0249] The columns of the Q patch elements in the first base matrix can be predefined or determined based on the target bitrate.

[0250] Optionally, the location information of patch elements corresponding to multiple bitrates includes the same G column indices, where G is a positive integer. In other words, the column indices of the patch elements do not change with the bitrate. The G columns indicated by these G column indices can be determined based on the statistical value of the number of error bits in each column under multiple bitrates, or they can be determined based on the statistical value of the number of target elements contained in each column under multiple bitrates.

[0251] For ease of explanation, we assume here that the location information of the patch element includes G column indices; in other words, the patch element is located in G columns. For clarity and explanation, the G columns where the patch element is located are referred to as the G target columns. It should be understood that these G column indices refer to the column indices in the first base matrix of the G target columns (or patch elements), and can also be equivalent to the column indices in the second base matrix.

[0252] In an implementation, the m b values of the plurality of code rates, the m b values of the plurality of code rates, the m b values of the plurality of code rates. The number of rows of a sub-matrix refers to the number of rows included in the sub-matrix, and the number of rows of a sub-matrix corresponding to different code rates is different. For example, referring to Table 1, the number of rows of a sub-matrix corresponding to a code rate of 0.769 is 5 rows, i.e., the first 5 rows of the G' columns of the second base matrix; the number of rows of a sub-matrix corresponding to a code rate of 0.714 is 6 rows, i.e., the first 6 rows of the G' columns of the second base matrix; and so on, and 38 sub-matrices including the first 5 rows to the first 42 rows of the G' columns of the second base matrix are obtained, corresponding to 38 code rates. The G' columns in the second base matrix are one or more predefined columns, which can be the first G' columns of the second base matrix, can be G' columns predefined by a protocol, or can be randomly selected G' columns, which are not limited in the present application. G target columns are determined from the plurality of sub-matrices, and the G target columns can satisfy that, among the G' columns of the second base matrix, the first G columns are arranged in descending order of the statistical values of the error bit numbers corresponding to the columns. The statistical value of the error bit number corresponding to the i-th column in the G' columns is a function of the error bit number corresponding to the i-th column in each sub-matrix of the plurality of sub-matrices of the second base matrix. The error bit number corresponding to the i-th column of each sub-matrix can be obtained by simulation, for example, by selecting a higher value of Es / N0 for simulation, i.e., simulation in a flat area.

[0253] Optionally, any one of the plurality of sub-matrices includes the first m b rows and the first S columns of the upper left corner of the second base matrix, and the values of m b and S corresponding to sub-matrices of different sizes are different, and different sizes of sub-matrices correspond to different code rates, i.e., the values of m b of the plurality of sub-matrices can correspond to the plurality of code rates one by one. For example, in the BG2 of the NR protocol, the size of the complete base matrix (e.g., an example of the second base matrix) is 42x52, and in the case of puncturing 2 columns, the sub-matrix corresponding to a code rate of 0.67 is a matrix composed of the first 7 rows and the first 17 columns of the base matrix (i.e., m b = 7, S = 17); and the sub-matrix corresponding to a code rate of 0.5 is a matrix composed of the first 12 rows and the first 22 columns of the base matrix (i.e., m b = 12, S = 22). The value of m b may also be referred to as the number of rows of a sub-matrix, i.e., the number of rows included in the sub-matrix, and S is a positive integer and S = G'. In other words, the G target columns are determined from the G' columns, and one or more columns with higher error bit numbers.

[0254] For example, referring to Table 1, 38 sub-matrices corresponding to 38 code rates can be obtained, and each of the 38 sub-matrices includes the first 5 rows to the first 42 rows of the G' columns of the second base matrix G'. Based on the 38 sub-matrices, 38 check matrices with different numbers of rows can be obtained. Using the 38 check matrices, the same input to be encoded is encoded respectively, and the encoded bits obtained by encoding are decoded, and the number of error bits in each column of the G' columns is recorded. For the ith column, 38 numbers of error bits corresponding to the 38 check matrices can be recorded, and based on a predefined function, the 38 numbers of error bits are calculated to obtain a statistical value of the number of error bits corresponding to the ith column. The predefined function can be, for example, an average value, a maximum value, a weighted average value, and the like, which is not limited in the present application.

[0255] For i in the G' columns, the statistical values of the number of error bits corresponding to the G' columns can be obtained, the G' statistical values are sorted in descending order, and the G columns with the highest ranks are determined as the G target columns, and the column indexes of the G target columns are obtained.

[0256] It can be understood that the more the number of error bits, the fewer the number of correct bits. Therefore, based on the above implementation manner, the G target columns determined from the plurality of sub-matrices also satisfy that in the G' columns of the second base matrix, the G columns are ranked in front according to the statistical values of the number of correct bits in descending order.

[0257] In another implementation manner, m b The first m b rows of the G' columns of the second base matrix can be obtained, and the plurality of sub-matrices corresponding to the plurality of code rates can be obtained. The plurality of sub-matrices are the same as the plurality of sub-matrices in the previous implementation manner, and the related description is referred to the above, and will not be repeated. The G target columns are determined from the plurality of sub-matrices, and the G target columns satisfy that in the G' columns of the second base matrix, the G columns are ranked in front according to the statistical values of the number of target elements in descending order; wherein the statistical value of the number of target elements in the ith column of the G' columns is a function of the number of target elements in the ith column of the plurality of sub-matrices of the second base matrix, and the target element is an element with a first value.

[0258] For example, referring to Table 1, 38 sub-matrices corresponding to 38 code rates can be obtained, and each of the 38 sub-matrices includes the first 5 rows to the 42nd row of the second base matrix G'. For each of the 38 sub-matrices, the number of target elements contained in the ith column is counted, and the number of target elements corresponding to the 38 sub-matrices is obtained. Then, the number of target elements is calculated based on a predefined function, and the statistical value of the number of target elements contained in the ith column is obtained. The predefined function may, for example, be an average value, a maximum value, a weighted average value, or the like, which is not limited in the present application.

[0259] The statistical values of the number of target elements corresponding to the G' columns are obtained by traversing i in the G' columns. The G' statistical values are sorted in ascending order, and the G columns with the top G statistical values are determined as the G target columns. The column indexes of the G target columns are obtained.

[0260] Since the target elements are elements with the first value, that is, corresponding to the cyclic shift sub-matrices in the check matrix, the fewer the number of target elements contained in a column in the above plurality of sub-matrices, the fewer the cyclic shift sub-matrices corresponding to the Z columns in the check matrix, and the more the all-zero sub-matrices. Therefore, the column weight of the corresponding column in the check matrix is lighter. Therefore, the column weight of the corresponding column in the check matrix can be improved by adding patch elements to the G target columns.

[0261] It can be understood that the fewer the first value, the more the second value for the base matrix. Therefore, based on the above implementation manner, the G target columns determined from the plurality of sub-matrices also satisfy that the ith column in the G' columns of the second base matrix ranks first according to the statistical value of the number of target elements contained in each column in descending order. The statistical value of the number of target elements contained in the ith column in the G' columns is a function of the number of target elements contained in the ith column in the plurality of sub-matrices of the second base matrix, and the target elements are elements with the second value.

[0262] Alternatively, the columns where the patch elements corresponding to at least two code rates are different. In other words, the position information of the patch elements corresponding to at least two code rates includes at least one different column index. That is, the column index of the patch element can change with the code rate. The column index of the patch element corresponding to a certain code rate can be determined according to the statistical value of the number of error bits of each column under the code rate, or can be determined according to the statistical value of the number of target elements contained in each column under the code rate.

[0263] For ease of explanation, we assume here that the position information of the Q patch elements corresponding to the target bitrate includes G column indices; in other words, the Q patch elements are located in G columns. For clarity and explanation, the G columns containing the Q patch elements are referred to as the G target columns. It should be understood that the G column indices refer to the column indices of the G target columns (or patch elements) in the first base matrix, and can be considered equivalent to the column indices in the first base matrix.

[0264] In one implementation, the target bitrate can be targeted at m. b The value of ' is taken from the first m columns of the G' columns of the second basis matrix. b A submatrix of the second basis matrix can be obtained by 'rowsing'. The G' columns in the second basis matrix are predefined; they can be the first G' columns of the second basis matrix, G' columns predefined by the protocol, or G' columns randomly selected. This application does not impose any restrictions on this. G target columns are determined from this submatrix. These G target columns must satisfy the following condition: among the G' columns of the second basis matrix, they are ranked in descending order of the number of error bits corresponding to each column. In other words, the G target columns are determined from the G' columns, and are one or more columns with higher error bit counts.

[0265] The number of error bits in the i-th column of the G' columns is obtained through simulation, such as simulation in a flat area. Traversing i through the G' columns yields G' error bits corresponding to each column. These G' error bits are then sorted in descending order, and the top G columns are identified as the G target columns, thus yielding the column indices of the G target columns. It should be understood that these column indices refer to the column indices of the G target columns in the second base matrix, that is, in the first base matrix.

[0266] In another implementation, the target bitrate can be targeted at m. b The value of ' is taken from the first m columns of the G' columns of the second basis matrix. b Rows can be used to obtain a submatrix of the second basis matrix. From this submatrix, G target columns are determined, which satisfy the following: In the G' columns of the second basis matrix, the columns are ranked in ascending order of the number of target elements they contain; where the target element is the element with the first value. Alternatively, these G target elements can satisfy the following: In the G' columns of the second basis matrix, the columns are ranked in descending order of the number of target elements they contain; where the target element is the element with the second value.

[0267] In yet another implementation, the plurality of code rates can be divided into a plurality of groups, and each group of code rates corresponds to an interval range of code rates, and each group can include a plurality of code rates. For each interval, the G column indexes corresponding to the plurality of code rates in each interval can be determined according to the implementation provided above. For example, taking the 38 code rates shown in Table 1 as an example, the 38 code rates can be divided into 4 groups, and the corresponding interval ranges are as follows: (0, 0.4], (0.4, 0.5], (0.5, 0.6], (0.6, 1). The G column indexes corresponding to the code rates in each group can be determined according to the statistical values of the error bits corresponding to each column in the plurality of sub-matrices corresponding to the plurality of code rates in each group, or according to the statistical values of the number of target elements contained in each column in the plurality of sub-matrices corresponding to the plurality of code rates in each group, which will not be described here.

[0268] It should be understood that the implementation provided above for determining the column indexes of the patch elements is only some possible implementations, and should not constitute any limitation on the present application.

[0269] In a possible design, the relationship between the column indexes and the code rates can be indicated by a third mapping relationship. For example, the third mapping relationship can indicate the correspondence between a plurality of code rates and one or more column indexes, and each code rate corresponds to a column index used to determine the column in which the patch element is located in the first base matrix. For example, in the plurality of code rates shown in Table 1, if numbered from 0, the G column indexes can be 2, 12, 13. Since the third mapping relationship is shown in Table 2 below, it will not be described here.

[0270] The third mapping relationship can indicate the correspondence between a plurality of code rates and the same G column indexes, or the correspondence between a plurality of code rates and different one or more column indexes, which is not limited in the present application.

[0271] It should be understood that the third mapping relationship can be pre-defined by a protocol, or can be calculated by the communication device, which is not limited in the present application.

[0272] In the embodiments of the present application, the column indexes of the Q patch elements can be determined by calculation, such as the implementation provided above, or can be obtained according to the third mapping relationship. If obtained according to the third mapping relationship, the third mapping relationship can be pre-stored in the communication device, and the column indexes of the Q patch elements are determined when there is a coding requirement.

[0273] Row index:

[0274] Optionally, the row indexes of the Q patch elements in the first base matrix are determined according to the target code rate.

[0275] After determining the column indices of the Q patch elements, the communication device can further determine the row indices of these Q patch elements. For example, assume that the Q patch elements are located in G target columns. The communication device can determine one or more rows in the corresponding columns of the second base matrix based on the column indices of the G target columns, such that after adding patch elements at the positions corresponding to the determined row and column indices, the resulting matrix satisfies a predefined objective function. For ease of distinction and explanation, the rows containing the patch elements are referred to as target rows, assumed to be J rows, where J is a positive integer. As previously mentioned, the Q patch elements can be located in the first m rows of the first base matrix. b Therefore, J can be less than or equal to m in the ' rows'. b A positive integer.

[0276] For example, in the first m of the second basis matrix b In a set of G target columns and 1 row, the row index is determined at the column level. For each of the G target columns, m... b The values ​​of the elements in J rows of m rows are set to the first value, and then calculated using a predefined function. This can be understood as... b There are multiple combinations of J rows. By traversing these combinations, different function values ​​can be obtained. Then, the combination corresponding to the top-ranking function values ​​is selected. This determines the J target rows.

[0277] Taking a second value of 0 as an example, the row index of the J target rows in the i-th column can satisfy:

[0278] in, Let f(r) represent the row indices of the J target rows; f() represents a predefined function; argmin f() represents finding the minimum value of the predefined function; B represents the second basis matrix; B(r) 0,i ~r J-1,i (i) = 0 indicates that the column index is i and the row index is r0 to r1 in the second basis matrix. J-1 J elements, where each of the J row indices can be from 0 to (m). b By iterating through the values ​​in '-1), we can obtain various combinations with the J row indices. This can be understood as the row indices of the J target rows. It is one of the many combinations; G patch This represents the set of column indexes consisting of the above G column indexes; B|B(r 0,i ~r J-1,i ,i)=0 means that the r0th to rth elements in the second basis matrix B are... J-1 The element in the row and i-th column is assigned the second value (e.g., 0 in this example). Note that during the assignment process, elements in the second base matrix whose values ​​are already the second value can be avoided.

[0279] It should be understood that, in the assignment process, the elements of the r0~r J-1 row of each column can be assigned column by column, or the elements of the r0~r J-1 row of multiple columns can be assigned at the same time, and the present application does not limit this. In the case of assigning the elements of the r0~r J-1 row of multiple columns at the same time, the above formula can be simplified as:

[0280] For example, the above predefined function is a PEXIT function based on a protograph, and the row indexes of the J target rows can satisfy:

[0281] Wherein, the PEXIT function can be used to calculate a PEXIT threshold, and the smaller the threshold, the better the performance of the matrix.

[0282] In one possible design, the relationship between the row index and the code rate can be indicated by a second mapping relationship. Illustratively, the second mapping relationship can indicate a correspondence between multiple code rates and multiple row indexes, each code rate corresponding to one or more row indexes, which are used to determine the row in which the patch element is located in the first base matrix.

[0283] It should be understood that the second mapping relationship can be predefined by the protocol or calculated by the communication device itself, and the present application does not limit this.

[0284] For example, assuming that J is 1 and the column indexes of the G target columns are 2, 12, and 13, the row indexes of the target rows under different code rates can include one or more of the correspondence between the multiple code rates R and one or more columns shown in Table 2 using the above PEXIT function, wherein the one or more columns can include one or more of the following columns: column 2, column 12, and column 13. It can be understood that Table 2 can also be split into multiple tables, which are not limited herein. In addition, the correspondence between the multiple code rates R and one or more column indexes can also be represented in other forms, such as a formula, an array, or a sequence, which are not limited herein.

[0285] Table 2

[0286] It should be understood that Table 2 is only an example of the second mapping relationship, showing the correspondence between multiple code rates and multiple row indexes. As can be seen, the row indexes of the patch elements under different code rates are not necessarily the same, in other words, the row indexes of the patch elements are related to the code rate.

[0287] In fact, Table 2 also shows the same column indexes of multiple patch elements under multiple code rates, i.e., the column indexes of the patch elements are the same under different code rates, and are 2, 12 and 13. Therefore, Table 2 can also be considered as an example of the third mapping relationship.

[0288] In the embodiments of the present application, the row indexes of the Q patch elements can be determined by calculation, such as the implementation provided in the foregoing, or can be obtained according to the second mapping relationship. If obtained according to the second mapping relationship, the second mapping relationship can be pre-stored in the communication device, and the row indexes of the Q patch elements are determined when there is a coding and decoding requirement.

[0289] It should also be understood that Table 1 and Table 2 in the foregoing examples are only shown for the convenience of understanding, and do not constitute any limitation on the values in the tables (or the first mapping relationship and the second mapping relationship). In addition, Table 1 and Table 2 can also be combined into one table, or split into more tables, such as being split according to different code rates, and each table can indicate a code rate and one or more of the following corresponding to the code rate: the value of m b the row index of the patch element, or the column index of the patch element.

[0290] Based on the foregoing description of the value of m b Based on the foregoing description of the value of m

[0291] FIGS. 12 and 13 are two schematic diagrams of the first base matrix provided by the embodiments of the present application. Since the positions of the patch elements correspond to the A part, the B part and the D part of the check matrix, FIGS. 12 and 13 mainly show the elements in the first base matrix corresponding to the three parts. In FIGS. 12 and 13, each square represents an element in the base matrix, and the square with a filling pattern represents an element with a first value in the first base matrix, which can correspond to a cyclic shift submatrix in the check matrix, and in order to distinguish the patch elements from other elements with the first value, the patch elements are identified with different filling patterns; the blank square represents an element with a second value in the first base matrix, which can correspond to an all-zero submatrix in the check matrix.

[0292] In the first base matrix shown in FIG. 12, the patch elements corresponding to multiple code rates are in the same three columns, and the patch elements under the same code rate are in the same row. Specifically, when R is 0.67, the patch elements are located in column 2, column 12 and column 13, and row 6; when R is 0.5, the patch elements are located in column 2, column 12 and column 13, and row 9, which corresponds to the correspondence between the code rate and the column index and the row index shown in Table 2 (the values in the table are shown in bold) shown in the foregoing example.

[0293] In the first base matrix shown in FIG. 13, the columns in which the patch elements corresponding to different code rates are located are not completely the same, and the rows in which the patch elements corresponding to the same code rate are located are also not completely the same. Specifically, when R is 0.67, the patch elements are located at (column 2, row 6), (column 3, row 4), and (column 12, row 5); when R is 0.5, the patch elements are located at (column 2, row 9), (column 4, row 10), and (column 11, row 11).

[0294] In order to obtain better decoding performance, the present application also provides a possible design for the offset value of the patch element in the corresponding cyclic shift submatrix in the check matrix.

[0295] In the embodiments of the present application, the offset value refers to the number of bits by which the element 1 in the cyclic shift submatrix is offset, for example, when the offset value is 0, there is no offset, when the offset value is 1, there is an offset of 1 bit, and so on. The direction of the offset can be predefined as left shift or right shift, which is not limited in the present application. Since the dimension of each cyclic shift submatrix in the check matrix is ZxZ, the number of bits of the cyclic shift is not more than Z, that is, the offset value can be in the range of 0 to (Z-1).

[0296] As described previously, in the LDPC code, the shorter the ring length, the higher the probability of decoding failure, and therefore the short ring seriously affects the decoding performance. Therefore, the number of short rings can be reduced as much as possible by designing the offset. One possible method is to change the length of the original short ring by offsetting the "1" in the cyclic shift submatrix. The definition of the short ring can be defined by the ring length. For example, the short ring can include a ring with a ring length of 4 when the preset threshold is 4; for another example, the short ring can include a ring with a ring length of 4 and a ring with a ring length of 6 when the preset threshold is 6. The present application does not limit the definition of the short ring and the specific value of the preset threshold.

[0297] Based on the above-mentioned scheme, after determining the positions of the Q patch elements in the first base matrix, the corresponding ring length can be determined by setting different offset values for each patch element, and the offset value of each patch element corresponding to the case where the number of short rings is the minimum is determined as the offset value used by each patch element, so as to control the number of short rings to the minimum.

[0298] For example, assuming that Q is 1, the cyclic shift submatrix corresponding to the 1 patch element in the check matrix can be shifted according to the offset values from 0 to (Z-1), and the short ring is searched under different offset values to count the number of short rings under different offset values, and then the offset value with the minimum number of short rings is obtained. The offset value can be used to control the number of bits by which the element 1 in the cyclic shift submatrix corresponding to the patch element in the check matrix is shifted.

[0299] For example, if Q is 3, the three patch elements can be shifted according to offset values from 0 to (Z-1) in the corresponding cyclic shift sub-matrices in the parity check matrix. It can be understood that there are multiple combinations of the offset values for the three patch elements, and the combinations can be represented by an array, denoted as (a1, a2, a3), where a1, a2, and a3 can be integers from 0 to (Z-1). q a q represents an offset value of the qth patch element, q can be an integer from 1 to Q, and a q can be an integer from 0 to (Z-1). q The offset values in the combination can be used to control the number of bits of the element 1 in the cyclic shift sub-matrices corresponding to the patch elements in the parity check matrix.

[0300] The determination of the offset values is described in detail above in combination with the cases of one patch element and multiple patch elements. It should be understood that the implementation provided above is only an example, and should not constitute any limitation on the present application.

[0301] Based on the above scheme, the number of short cycles in the parity check matrix is reduced by designing the offset values, thereby further improving the decoding performance.

[0302] FIG. 14 is a performance simulation diagram provided by an embodiment of the present application. FIG. 14 shows the performance comparison in the flat region obtained by simulation under two different schemes. The two schemes are the aforementioned scheme 1 and scheme 2. It is observed that under different simulation parameters, the symbol signal-to-noise ratio (Es / N0) is improved by 0.5-1 dB when BLER=10 -7

[0303] The method provided by the embodiments of the present application is described in detail above in combination with multiple drawings. The apparatus provided by the embodiments of the present application is described below in combination with the drawings.

[0304] As an example, FIG. 15 and FIG. 16 are schematic block diagrams of possible apparatuses provided by embodiments of the present application. These apparatuses can be used to implement the functions of the communication apparatus in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0305] FIG. 15 is a schematic block diagram of a communication apparatus provided by an embodiment of the present application. The apparatus 1500 shown in FIG. 15 can include a processing module 1510 and a communication module 1520.

[0306] ​In one possible design, the apparatus 1500 can be used to implement the communication method performed by the communication apparatus in the embodiments shown in FIG. 11. For example, the processing module 1510 can be used to implement the steps of obtaining and compiling codes and other processing-related steps performed by the communication apparatus in steps 1110 to 1140 of the method 1100, and the communication module 1520 can be used to implement the steps of sending and / or receiving performed by the communication apparatus in the method 1100.

[0307] For example, the processing module 1510 can be used to obtain a first base matrix, obtain a check matrix based on the first base matrix, and perform LDPC encoding or LDPC decoding based on the check matrix.

[0308] Optionally, the processing module 1510 can also be used to determine to use the first base matrix.

[0309] Optionally, the communication module 1520 can be used to send the first indication information or receive the second indication information.

[0310] More detailed descriptions of the processing module 1510 and the communication module 1520 can be directly obtained by referring to the related descriptions in the method embodiments shown in FIG. 11, which will not be repeated here.

[0311] It should be noted that the communication module can also be referred to as a transceiver module, a transceiver unit, a transceiver, a transceiver device, or the like. The processing module can also be referred to as a processor, a processing board, a processing unit, or the like. Optionally, the communication module can be used to perform the sending and receiving operations of the first communication apparatus or the second communication apparatus in the above method, and the devices in the communication module used to implement the receiving function can be regarded as a receiving module, and the devices in the communication module used to implement the sending function can be regarded as a sending module, i.e., the communication module can include a receiving module and a sending module.

[0312] It should also be noted that, in one possible design, the foregoing processing module and / or communication module can be implemented by a virtual module, e.g., the processing module can be implemented by a software function unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. In another possible design, the processing module or the communication module can also be implemented by an entity device, e.g., if the apparatus is implemented by a chip / chip circuit, the communication module can be an input / output circuit and / or a communication interface, which performs input operations (corresponding to the foregoing receiving operations) and output operations (corresponding to the foregoing sending operations); and the processing module can be an integrated processor or a microprocessor or an integrated circuit.

[0313] The division of the modules in the embodiments of the present application is illustrative, and is merely a logical function division. In actual implementation, another division manner can be used. In addition, each function module in each example in the embodiments of the present application can be integrated in one processor, or can be physically separated, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software function module.

[0314] Fig. 16 is a structural schematic diagram of a communication apparatus provided by another embodiment of the present application. As shown in Fig. 16, the apparatus 1600 includes processing circuitry 1610 and communication circuitry 1620. The processing circuitry 1610 and the communication circuitry 1620 are coupled to each other.

[0315] It can be understood that the processing circuitry 1610 can be one or more processors, or can be all or part of the processing function of the circuit in the one or more processors.

[0316] It can be understood that the communication circuitry 1620 can be a transceiver or an input / output interface.

[0317] Optionally, the apparatus 1600 can further include a memory 1630 for storing instructions executed by the processing circuitry 1610 or storing input data required by the processing circuitry 1610 for executing instructions or storing data generated after the processing circuitry 1610 executes instructions.

[0318] It can be understood that the memory 1630 can be located outside the processing circuitry 1610, or located inside the processing circuitry 1610.

[0319] As an example, the processing circuitry 1610 is configured to implement the functions of the above-mentioned processing module 1510, and the communication circuitry 1620 is configured to implement the functions of the above-mentioned communication module 1520.

[0320] As an example, the apparatus 1600 can be a communication device, or can be a chip applied to a communication device.

[0321] When the apparatus 1600 is a communication device, the communication circuitry can be a transceiver; when the apparatus 1600 is a chip, the communication circuitry can be an input / output circuit, a bus, a pin or other types of communication interfaces, wherein the input circuit in the input / output circuit can be used for receiving, and the output interface can be used for transmitting.

[0322] In some embodiments of the present application, a computer program product is also provided, which, when running on a processor, can implement the method of obtaining the check matrix implemented by the communication apparatus in the above method embodiments.

[0323] Some embodiments of the present application further provide a computer readable storage medium, which comprises computer instructions, and the computer instructions can implement the method of obtaining the check matrix implemented by the communication device in the above method embodiments when running on a processor.

[0324] Some embodiments of the present application further provide a communication system, which comprises the above communication device, and the communication device can be used to implement the method of obtaining the check matrix implemented by the communication device in the above method embodiments.

[0325] It can be understood that the processor in the embodiments of the present application can be all or part of the circuit of the following devices or the following devices for processing functions: a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), field programmable gate arrays (FPGAs) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0326] The terms "unit", "module" and the like used in the specification can be used to represent computer-related entities, hardware, combinations of hardware and software, software, or software in execution.

[0327] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0328] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the above method embodiments, which will not be described here.

[0329] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the division of the above-described device embodiment is only a logical function division, and there can be another division manner for actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, or the logical couplings or communication connections between the different functions, can be implemented in electronic, mechanical or other forms.

[0330] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0331] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0332] In the above embodiments, the functions of the various functional units can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, the software can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the whole or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as digital video disc (DVD)), or semiconductor media (such as solid state disk (SSD)) and the like.

[0333] The functions, if implemented in the form of software functional units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part of the prior art or the part of the technical solutions of the present application can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a number of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in the embodiments of the present application. The storage medium mentioned above includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and various media that can store program codes.

[0334] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of obtaining a parity check matrix, characterized by, The method comprises: obtaining a first base matrix, wherein the first base matrix comprises Q patch elements, each patch element in the Q patch elements has a first value, and positions of the Q patch elements in the first base matrix coincide with positions of Q elements having a second value in a second base matrix, Q is a positive integer; obtaining a check matrix from the first base matrix, wherein the check matrix is used for low-density parity-check (LDPC) encoding or LDPC decoding, the first value corresponds to a cyclic shift square matrix in the check matrix, and the second value corresponds to an all-zero square matrix in the check matrix.

2. The method of claim 1, wherein, The first value is 1, and the second value is 0; or the first value is greater than or equal to 0, and the second value is -1.

3. The method of claim 1 or 2, wherein, The method further comprises: obtaining the first base matrix according to the second base matrix.

4. The method of any one of claims 1 to 3, wherein, The Q patch elements are located in the first base matrix in the first m b rows, m b satisfies: R is a target code rate, the target code rate is a code rate indicated by a modulation and coding scheme (MCS), k b is a column number of information bits in the first base matrix, d b is a column number of punctured bits in the first base matrix, denotes a ceiling.

5. The method of claim 4, wherein, The value of m b The relationship between the value of m b and the target code rate is determined according to a first mapping relationship, the first mapping relationship indicating a correspondence relationship between a plurality of code rates and a plurality of values of m , each value corresponding to a code rate being used to determine a range of rows in the first base matrix where the patch element is located, the plurality of code rates including the target code rate.

6. The method of claim 4 or 5, wherein, The positions of the patch elements corresponding to the plurality of code rates comprise the same G column indexes, and G is a positive integer.

7. The method of claim 6, wherein, The position information of the patch elements corresponding to each code rate in the plurality of code rates comprises one or more column indexes, and the position information of the patch elements corresponding to at least two code rates in the plurality of code rates comprises different at least one column index.

8. The method of claim 7, wherein, The G columns indicated by the G column indexes satisfy that, among G' columns of the second base matrix, the first G columns are arranged in descending order of statistical values of error bit numbers corresponding to the columns; a statistical value of error bit numbers corresponding to an i th column in the G' columns is a function of error bit numbers corresponding to an i th column in a plurality of sub-matrices of the second base matrix; any one of the plurality of sub-matrices comprises the first m rows of the G' columns of the second base matrix, a value of the m rows has a corresponding relationship with a code rate corresponding to the any one of the sub-matrices; and the G' columns are one or more predefined columns, and G' is a positive integer greater than or equal to G. b b ​​ 9. The method of claim 7, wherein, The G columns indicated by the G column indexes satisfy: among the G' columns of the second base matrix, the first G columns are arranged in ascending order according to statistical values of the number of target elements contained in each column; wherein the statistical value of the number of target elements contained in the i th column of the G' columns is a function of the number of target elements contained in the i th column of a plurality of sub-matrices of the second base matrix respectively; any one of the plurality of sub-matrices includes the first m rows of the G' columns of the second base matrix, and the value of the m rows has a corresponding relationship with a code rate corresponding to the any one of the sub-matrices; the G' columns are one or more predefined columns, and G' is a positive integer greater than or equal to G; and the target element is an element with the first value. b b ​​ 10. The method of claim 6, wherein, The method further comprises:

11. The method of any one of claims 1 to 6, or 10, wherein, The Q patch elements are located in G columns in the first base matrix, and the G columns satisfy: in a sub-matrix of the second base matrix, the first G columns are arranged in descending order of the number of error bits corresponding to each column; wherein the sub-matrix of the second base matrix includes the first m b rows of G' columns of the second base matrix, the value of m b has a corresponding relationship with a target code rate; the G' columns are one or more predefined columns, and G' is greater than or equal to G, G' and G are positive integers.

12. The method of any one of claims 1 to 6, or 10, wherein, The Q patch elements are located in G columns of the first base matrix, and the G columns satisfy: in a sub-matrix of the second base matrix, the first G columns are arranged in ascending order according to the number of target elements contained in each column; wherein the sub-matrix of the second base matrix includes the first m rows of G' columns of the second base matrix, the value of m has a corresponding relationship with a target code rate; the G' columns are one or more predefined columns, and G' is greater than or equal to G, G' and G are positive integers; and the target element is an element with the first value. b b ​​ 13. The method of any one of claims 1 to 12, wherein, determining to use the first base matrix. The method further comprises:

14. The method of claim 13, wherein, determining to use the first base matrix when a first condition is met. The method further comprises:

15. The method of claim 13 or 14, wherein, sending first indication information, wherein the first indication information is used to indicate to use the first base matrix or to indicate the first base matrix. The method further comprises:

16. The method of claim 13, wherein, receiving second indication information, wherein the second indication information is used to indicate to use the first base matrix or to indicate the first base matrix. The method further comprises: determining to use the first base matrix according to the second indication information. The method further comprises:

17. The method of any one of claims 1 to 16, wherein, performing LDPC encoding or LDPC decoding by using the check matrix. The method comprises a function module for implementing the method according to any one of claims 1 to 17.

18. A communications device, characterized by The method comprises:

19. A communications device, characterized by one or more processors and a communication circuit, wherein the communication circuit is used for at least one of input or output of a signal by the communication device, and the one or more processors are used to implement the method according to any one of claims 1 to 17. The communication device is a network device or a terminal device, or a chip for the network device or the terminal device.

20. The communication apparatus of claim 18 or 19, wherein, The communication device is a network device or a terminal device, or a chip for the network device or the terminal device.

Images