LDPC code-based communication method and communication apparatus

Abstract

An LDPC code-based communication method and a communication apparatus. In the method, a device can perform encoding or decoding on the basis of an LDPC matrix, wherein the LDPC matrix is determined on the basis of an LDPC base matrix, a lifting value Zc, and a shifting value of the base matrix, the shifting value of the base matrix is determined on the basis of a second row sequence, a second column sequence, and Zc, the elements of the second row sequence have one-to-one correspondence to the rows of the base matrix, the elements of the second column sequence have one-to-one correspondence to the columns of the base matrix, the second row sequence is determined on the basis of a first row sequence, the second column sequence is determined on a first column sequence, the number of elements of the first row sequence is less than the number of elements of the second row sequence, and the number of elements of the first column sequence is less than the number of elements of the second column sequence. The method allows for flexible construction of a shifting value of a base matrix, and supports a broader set of lifting values.

Description

Communication method and communication apparatus based on LDPC code

[0001] The present application claims priority to the Chinese patent application No. 202411296203.X, filed on September 14, 2024, and entitled "Communication method and communication apparatus based on LDPC code", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of coding, and more particularly, to a communication method and communication apparatus based on LDPC code. BACKGROUND

[0003] In the field of channel coding, low-density parity check (LDPC) code is one of the most mature and widely used channel coding schemes. Quasi-cyclic low density parity check (QC-LDPC) code is a structured LDPC code. Due to the unique structure of its check matrix, it can be implemented using a simple feedback shift register during encoding, which reduces the encoding complexity of the LDPC code.

[0004] The shift values given in the current protocol for QC-LDPC code (see the multiple sets of shift values shown in Table 2 in the specific embodiments) depend on random search, which cannot theoretically guarantee the girth property of the LDPC code. In addition, the shift values in the QC-LDPC code shown in Table 2 are only applicable to the set of lifting values that increases exponentially (see the multiple sets of lifting values shown in Table 1 in the specific embodiments), and are not applicable to other types of lifting value sets. SUMMARY

[0005] Embodiments of the present application provide a communication method and communication apparatus based on LDPC code, which can flexibly construct the shift values of the base matrix and support a wider set of lifting values.

[0006] In a first aspect, a communication method based on LDPC code is provided, which can be executed by a sending end device. In the absence of special description, the "sending end device" in the present application can refer to the sending end device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system, etc.) in the sending end device, or a logic module or software capable of realizing all or part of the functions of the sending end device.

[0007] The method comprises: obtaining an information bit sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC base matrix, a lifting value Zc and a shift value of the base matrix, wherein the shift value of the base matrix is determined based on a second row sequence, a second column sequence and the lifting value Zc, the second row sequence having an element number equal to a row number of the base matrix and the elements of the second row sequence corresponding to the rows of the base matrix in one-to-one manner, the second column sequence having an element number equal to a column number of the base matrix and the elements of the second column sequence corresponding to the columns of the base matrix in one-to-one manner, the second row sequence being determined based on a first row sequence, the second column sequence being determined based on a first column sequence, the first row sequence having an element number smaller than that of the second row sequence, and the first column sequence having an element number smaller than that of the second column sequence; and encoding the information bit sequence according to the LDPC matrix to obtain a codeword sequence.

[0008] The technical solution provides a method for obtaining a second row / column sequence based on a first row / column sequence and determining a shift value of a base matrix based on the second row / column sequence and a lifting value. In the method, the shift value is not dependent on random search, but can be flexibly constructed by using determined parameters, so that the girth property of the LDPC code can be theoretically guaranteed, and the method can support different types of lifting value sets, so that diversified communication requirements can be better met.

[0009] In a second aspect, a communication method is provided, which can be executed by a receiving end device. In the case where no special description is made, the receiving end device in the present application can refer to the receiving end device itself (for example, a network device or a terminal device), a component (for example, a processor, a chip or a chip system) in the receiving end device, or a logic module or software capable of realizing all or part of the functions of the receiving end device.

[0010] The method comprises: obtaining a symbol sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC base matrix, a lifting value Zc and a shift value of the base matrix, wherein the shift value of the base matrix is determined based on a second row sequence, a second column sequence and the lifting value Zc, the second row sequence having an element number equal to a row number of the base matrix and the elements of the second row sequence corresponding to the rows of the base matrix in one-to-one manner, the second column sequence having an element number equal to a column number of the base matrix and the elements of the second column sequence corresponding to the columns of the base matrix in one-to-one manner, the second row sequence being determined based on a first row sequence, the second column sequence being determined based on a first column sequence, the first row sequence having an element number smaller than that of the second row sequence, and the first column sequence having an element number smaller than that of the second column sequence; and decoding the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

[0011] The beneficial effects of the second aspect are described in the first aspect, which will not be repeated here.

[0012] In some implementations of the first or second aspect, the shift value of the 1 element in row i and column j of the basis matrix is ​​obtained by summing t first values, where t is a positive integer. The first values ​​are determined based on R(i), C(j), Zc, p and s corresponding to the first values. R(i) is the element in the second row sequence corresponding to row i, C(j) is the element in the second column sequence corresponding to column j, s is an integer between 1 and t, and p is the prime number corresponding to Zc.

[0013] In the above technical solution, in order to theoretically guarantee the loop properties of LDPC codes (such as loop performance and loop existence), the translation value of the basis matrix can be determined based on the above parameters.

[0014] In some implementations of the first or second aspect, p is a prime base of Zc, or p is the largest prime number that divides the largest lift value in the set of all lift values, or p is a prime number that divides any lift value in the set of all lift values, or p is the maximum or minimum value in the prime base corresponding to the set of all lift values.

[0015] In some implementations of the first or second aspect, the translation value SV of the 1-element in row i and column j of the basis matrix i,j Satisfy the following formula:

[0016] Where s is a positive integer, u s +v s =s+1,u s and v s All are positive integers, Z id_s It is determined based on Zc, p, and s, or, Z id_s =1,k s For p s-1 A positive integer multiple of t. For example, t = 2 or 3.

[0017] The above technical solution can theoretically guarantee properties related to cycles. Different terms in the calculation formula can guarantee different cycle properties. Among them, the aforementioned SV... i,j In the calculation formula, s=1 is to ensure that 4 loops do not exist; s=2 is to ensure that the number of 6 loops is small, and that 6 loops do not exist when Zc is large enough; s=3 is to ensure that the number of 8 loops is small, and that 8 loops do not exist when Zc is large enough, and so on. More terms with s greater than or equal to 3 are to further guarantee the loop property.

[0018] In some implementations of the first or second aspect, the translation value SV of the 1-element in row i and column j of the basis matrix i,j Satisfy the following formula:

[0019] Where, N s Let be the values ​​stored at the corresponding positions in row r1 and column c1 of table s, where row r1 is the row in table s associated with R(i), column c1 is the column in table s associated with C(j), s is a positive integer, and Z is a positive integer. id_s It is determined based on Zc, p, and s, or, Z id_s =1,k s For p s-1 A positive integer multiple of.

[0020] In the above technical solution, the parameter N for determining the translation value can be obtained by looking up a table. s The obtained translation value can theoretically guarantee the properties related to the cycle. Specifically, different values ​​of t in the calculation formula can guarantee different cycle properties. The aforementioned SV... i,j In the calculation formula, s=1 is to ensure that 4 loops do not exist; s=2 is to ensure that the number of 6 loops is small, and that 6 loops do not exist when Zc is large enough; s=3 is to ensure that the number of 8 loops is small, and that 8 loops do not exist when Zc is large enough, and so on. More terms with s greater than or equal to 3 are to further guarantee the loop property.

[0021] In some implementations of the first or second aspect, the numerical value N stored in table s s Satisfy the following formula:

[0022] Among them, u s +v s =s+1,u s and v s All are positive integers.

[0023] The above technical solution provides a predefined table s for storing numerical values ​​N. s The specific calculation method can theoretically guarantee the properties related to the loop.

[0024] In some implementations of the first or second aspect, all rows of table s correspond one-to-one with the elements in the second row sequence, and all columns of table s correspond one-to-one with the elements in the second column sequence.

[0025] In some implementations of the first or second aspect, Z id_s It is determined based on Zc, p, and s, where Z is the base value of Zc. id_s Satisfying the following formula: Z id_s =mod(mod(Zc,p) s+1 ),p s )

[0026] The above calculation method can theoretically guarantee the properties related to the loop.

[0027] In some implementations of the first aspect or the second aspect, the base matrix is determined based on a split sequence θ, where an element in the split sequence θ corresponding to a row i of the base matrix is θ(i), and θ(i) is equal to a first character indicating that the row i of the base matrix is not associated with any row of the base matrix, or otherwise, θ(i) is less than i indicating that the row i of the base matrix is associated with the row θ(i) of the base matrix, a first row sequence includes a plurality of elements corresponding to a plurality of rows of the base matrix one-to-one, the plurality of rows are all rows i of the base matrix where θ(i) is equal to the first character, an element in a second row sequence corresponding to a row i1 is equal to an element in the first row sequence corresponding to the row i1, and an element in the second row sequence corresponding to a row i2 is equal to an element in the second row sequence corresponding to a row θ(i2), where θ(i1) is equal to the first character, θ(i2) is not equal to the first character, or otherwise, the first row sequence includes a plurality of elements corresponding to a plurality of core rows of the base matrix one-to-one, an element in the second row sequence corresponding to the row i1 is equal to an element in the first row sequence corresponding to the row i1, an element in the second row sequence corresponding to a row i3 is equal to an element in the first row sequence corresponding to a row i3', and an element in the second row sequence corresponding to the row i2 is equal to an element in the second row sequence corresponding to the row θ(i2), where the row i1 is any row in the core of the base matrix, the row i3 is any row of the base matrix other than the core rows among all rows i of the base matrix where θ(i) is equal to the first character, i3' is less than i3, θ(i1) is equal to the first character, and θ(i2) is not equal to the first character.

[0028] In the above technical solution, the first sequence does not include an element corresponding to a row i where θ(i) is not equal to the first character, which has the advantage of ensuring that the translation values of the child nodes and the parent nodes are relevant, and can achieve QC-level elimination expansion.

[0029] In some implementations of the first aspect or the second aspect, the first row sequence is determined based on the split sequence, where the plurality of elements in the first row sequence are included in the split sequence, the first element in the first row sequence is the minimum value in the split sequence, and the element corresponding to a first row in the first row sequence is less than the element corresponding to a second row in the first row sequence, and the row number of the first row is less than the row number of the second row.

[0030] In the above technical solution, only the split sequence can be stored, the first row sequence can be determined based on the split sequence, and the split process can maintain the QC structure, and hardware implementation is simpler.

[0031] In some implementations of the first aspect or the second aspect, the first column sequence includes a plurality of elements corresponding to a plurality of core columns of the base matrix one-to-one, and an element in a second column sequence corresponding to a column j1 is equal to an element in the first column sequence corresponding to the column j1, and the column j1 is any column in the core columns.

[0032] In some implementations of the first aspect or the second aspect, the base matrix is a circulant-shifted space-coupled QC-LDPC base matrix, a coupling length of a sub-code of the base matrix is L, a coupling width is w, a number of rows of each base matrix block in the sub-code is m, and a number of columns of each base matrix block in the sub-code is n, the first row sequence includes (m*(w+c)) elements, the elements in the first row sequence one-to-one correspond to the first (m*(w+c)) rows of the base matrix, c is an integer, the first column sequence includes (n*(w+c)) elements, the elements in the first column sequence one-to-one correspond to the first (n*(w+c)) columns of the base matrix, the second row sequence includes (m*(L+w)) elements, the elements in the second row sequence are obtained based on the first row sequence through cyclic reuse, and the second column sequence includes (n*L) elements, the elements in the second column sequence are obtained based on the first column sequence through cyclic reuse.

[0033] In the technical solution, a specific rule for generating the shift value is provided, and the shift value of the base matrix can be obtained in the case of any number of sub-codes according to the rule.

[0034] For example, c is equal to -1, -2, 0, 1, or 1.

[0035] In a third aspect, a communication apparatus is provided. The apparatus can be configured to perform the method in any of the aspects and / or implementations of the aspects.

[0036] In an implementation, the apparatus is a sending device or a receiving device. When the apparatus is the sending device or the receiving device, the transceiver unit can be a transceiver, or an input / output interface, or a communication interface; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0037] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a sending device or a receiving device. When the apparatus is the chip, the chip system, or the circuit used in the sending device or the receiving device, the transceiver unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin, or a related circuit on the chip, the chip system, or the circuit; and the processing unit can be at least one processor, a processing circuit, or a logic circuit.

[0038] In a fourth aspect, a communication apparatus is provided. The apparatus includes a memory configured to store a program, and at least one processor configured to execute the computer program or instructions stored in the memory to perform the method in any of the aspects and / or implementations of the aspects.

[0039] In an implementation, the apparatus is a transmitting device or a receiving device.

[0040] In another implementation, the apparatus is a chip, a chip system or a circuit for a transmitting device or a receiving device.

[0041] In a fifth aspect, a communication apparatus is provided, which comprises at least one processor and a communication interface, the at least one processor being configured to acquire a computer program or instructions stored in a memory through the communication interface, so as to execute the method provided in any one of the aspects or the implementations thereof. The communication interface can be implemented by hardware or software.

[0042] In an implementation, the apparatus further comprises the memory.

[0043] In a sixth aspect, a processor is provided, which is configured to execute the method provided in the aspects.

[0044] For the transmitting and acquiring / receiving operations of the processor, if no special description is made, or if it is not contrary to the actual role or inherent logic in the related description, it can be understood as the output and receiving, input operations of the processor, or the transmitting and receiving operations performed by the radio frequency circuit and the antenna, which are not limited in the present application.

[0045] In a seventh aspect, a computer readable storage medium is provided, which stores program codes for execution by a device, and the program codes comprise codes for executing the method provided in any one of the aspects or the implementations thereof.

[0046] In an eighth aspect, a computer program product containing instructions is provided, which, when executed on a computer, causes the computer to execute the method provided in any one of the aspects or the implementations thereof.

[0047] In a ninth aspect, a chip is provided, which comprises a processor and a communication interface, the processor being configured to read instructions stored in a memory through the communication interface, and execute the method provided in any one of the aspects or the implementations thereof. The communication interface can be implemented by hardware or software.

[0048] Optionally, as an implementation, the chip further comprises the memory, the memory storing computer programs or instructions, and the processor being configured to execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, the processor is configured to execute the method provided in any one of the aspects or the implementations thereof.

[0049] When the method provided by the present application is executed by a chip, the present application does not limit the number of chips for implementing the method of the present application, for example, the method can be executed by one chip, or two or more chips. When the number of chips for implementing the method of the present application is two or more, the chip manufacturers are not limited, and can be the same manufacturer or different manufacturers.

[0050] In a tenth aspect, a computer program is provided, which, when running on a computer, causes the method provided by any one of the above aspects or the implementation manners thereof to be executed.

[0051] In an eleventh aspect, a communication system is provided, which includes at least one of the above-mentioned sending end device or receiving end device. BRIEF DESCRIPTION OF DRAWINGS

[0052] FIG. 1 is a schematic diagram of a network architecture to which the embodiments of the present application can be applied.

[0053] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0054] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0055] FIG. 4 is a schematic diagram of the structure of a check matrix.

[0056] FIG. 5 is a schematic diagram of an information transmission process.

[0057] FIG. 6 is a schematic flowchart of a communication method 600 based on an LDPC code provided by the present application.

[0058] FIG. 7 is a schematic diagram of the correspondence between a table s and a second row (column) sequence.

[0059] FIG. 8 is a schematic diagram of a shift value of a QC SC-LDPC base matrix determined based on the method proposed by the present application.

[0060] FIG. 9 is a schematic block diagram of a communication apparatus 1000 provided by the embodiments of the present application.

[0061] FIG. 10 is a schematic block diagram of a communication apparatus 1100 provided by the embodiments of the present application. DETAILED DESCRIPTION

[0062] In order to facilitate the understanding of the embodiments of the present application, the following points are explained before the embodiments of the present application are introduced.

[0063] "Indicative of" or "indicate" can include both direct and indirect indication, or "indicative of" or "indicate" can explicitly and / or implicitly indicate. The first, second, etc. various numerical designations are only for the convenience of description and do not limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc. "Predefined" can be achieved by pre-storing corresponding codes, tables or other means for indicating relevant information in the device, and the specific implementation manner is not limited in the present application. The "protocol" referred to can refer to a standard protocol in the communication field, which can include a long term evolution (LTE) protocol, a new radio (NR) protocol and a related protocol applied in a future communication system, and the present application is not limited thereto. The words "example", "for example", "exemplary", "as an example", etc. are used to indicate an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized. "At least one" refers to one or more, and "multiple" refers to two or more. "At most one" refers to one or 0. "And / or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple. The description related to the sending of messages, information or data by network element A to network element B and the receiving of messages, information or data from network element A by network element B is intended to indicate which network element the message, information or data is intended for, and does not limit whether they are directly sent or indirectly sent via other network elements. "When", "in the case of", "if" and "if" and other descriptions all refer to the objective situation in which the device will make corresponding processing, and are not limited by time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations. "Corresponding to", "correspondingly" and equivalent expressions mean that the two have a corresponding relationship, which can include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly make corresponding processing, and it is not required that the corresponding processing must follow the occurrence of the objective situation.

[0064] In addition, the network architecture and service scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, with the evolution of network architecture and the appearance of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0065] The communication system to which the embodiments of the present application can be applied will be described below.

[0066] The embodiments of the present application can be applied to various communication systems, including but not limited to: a 5th generation (5G) system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as a 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), an internet of things (IoT) communication system, a narrow band-internet of things (NB-IoT) system, or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, etc., without limitation.

[0067] The communication system applicable to the embodiments of the present application can include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device can be a terminal device, and the other can be a network device. Optionally, both the transmitting end device and the receiving end device can be terminal devices. Optionally, both the transmitting end device and the receiving end device can be network devices.

[0068] FIG. 1 is a schematic diagram of a network architecture applicable to the embodiments of the present application. As shown in FIG. 1, the embodiments of the present application can be applicable to both uplink data transmission and downlink data transmission. In FIG. 1, only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting end device herein is a terminal device, and the receiving end device is a network device; conversely, in downlink data transmission, the transmitting end device is a network device, and the receiving end device is a terminal device. In addition, the embodiments of the present application are not limited in their applicability to other communication scenarios, for example, they can also be applied to sidelink communication.

[0069] The terminal device of the present application can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a drone, a wireless communication device, a user agent or a user apparatus, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to users, and can be used to connect people, things and machines, such as handheld devices with wireless connection function, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0070] The network device of the present application can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to next generation base station (gNodeB, gNB) in 5G system, base station in sixth generation mobile communication system, base station in future mobile communication system, or access node in wireless fidelity (WiFi) system, evolved node B (eNB) in long term evolution (LTE) system, radio network controller (RNC), node B (NB), base station controller (BSC), home base station (such as home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellite, unmanned aerial vehicle, etc. In one network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a RAN device including CU node and DU node, or be a RAN device including control plane CU node and user plane CU node, and DU node, or the network device can also be a wireless controller in cloud radio access network (CRAN) scenario, relay station, vehicle-mounted device, wearable device, etc. In addition, the base station can be a macro base station, micro base station, relay node, donor node or combination thereof. The base station can also refer to a communication module, modem or chip for setting in the foregoing device or apparatus. The base station can also be a mobile switching center and a device assuming base station function in D2D, V2X, M2M communication, network side device in 6G network, device assuming base station function in future communication system, etc. The base station can support networks of the same or different access technologies, without limitation.

[0071] Unless otherwise defined, the apparatuses used in the embodiments of the present application to realize the functions of the terminal device or the network device can refer to the terminal device or the network device itself, or can refer to an apparatus capable of supporting the terminal device or the network device to realize the functions, such as a chip system or a chip, specifically, a system on a chip (SoC) or a Modem. The apparatus can be installed in the terminal device or the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0072] It should also be noted that some embodiments in the present document take the 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, the LTE system, or future communication systems, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, which is not limited in the present application.

[0073] In addition, the embodiments of the present application can be applied to various application scenarios, such as a high throughput scenario, a high reliability scenario, a low latency scenario, a high reliability low latency scenario or a low power consumption scenario. The high throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, and the high reliability low latency scenario can be, for example, an ultra reliable low latency communication (URLLC) scenario.

[0074] In order to facilitate understanding of the embodiments of the present application, several concepts or terms related to the embodiments of the present application are briefly described. The concepts or terms described below are based on the concepts or terms defined in the protocol, but do not mean that the embodiments of the present application can only be applied to the existing system. The concepts or terms related to the embodiments of the present application can be applied to future systems. And the specific names of the concepts or terms (such as the concepts or terms related to the functional description) can be adjusted with the development of future systems.

[0075] 1、LDPC code

[0076] LDPC code is a kind of linear block code. Linear block code is to divide the information sequence to be coded into groups in units of q bits, and then linearly operate the q information bits by the encoder to obtain m check bits, and then combine the q information bits and the m check bits to obtain a code word with length n=q+m. The mapping relationship from the q-bit information bits to the n-bit code word is usually represented by a corresponding check matrix H. According to the check matrix H, the code word sequence can be generated to complete the coding process. After the code word sequence is transmitted through the channel, the receiving end device decodes the received signal to determine the original information bits.

[0077] The check matrix H of LDPC is a sparse matrix. The number of zero elements in the check matrix H is much larger than the number of non-zero elements, or in other words, the row weight (or column weight) of the check matrix is much smaller than the number of elements in each row (or each column) of the LDPC matrix. The LDPC code with the information bit sequence length equal to q and the code length equal to n can be uniquely determined by its check matrix H.

[0078] Tanner represented the check matrix H in the form of a graph in 1981. This graph is now called a Tanner graph, and the Tanner graph and the check matrix correspond one-to-one. The Tanner graph is composed of two types of vertices. One type of vertex represents a code word bit, which is called a variable node. The other type of vertex is a check node, which represents a check constraint relationship. Each check node represents a check constraint relationship. The following will be described in conjunction with FIG. 2 and FIG. 3.

[0079] FIG. 2 is a schematic diagram of a check matrix H of an LDPC.

[0080] In FIG. 2, {V i} represents a set of variable nodes (VN), and {C i} represents a set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. In FIG. 2, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0081] FIG. 3 is a Tanner graph of a check matrix H of an LDPC.

[0082] As shown in FIG. 3, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H, and the m check nodes correspond to the m rows of the check matrix H. A cycle in the Tanner graph is a group of vertices connected to each other, and a cycle starts and ends at the same vertex and passes through each node only once. More specifically, a cycle in the Tanner graph refers to a closed loop formed by variable nodes, check nodes and edges. The length of a cycle is defined as the number of edges it contains, and the girth of a graph can also be referred to as the perimeter of the graph, which is defined as the minimum cycle length in the graph. As shown in FIG. 3, the girth is 4, as indicated by the black edges. The variable nodes in the Tanner graph correspond to each column of the check matrix H, i.e., each code bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the check matrix H, i.e., each check bit of the LDPC. The connection between the two types of nodes corresponds to the value of the element in the H matrix. If there is a connection between the i th check node and the j th variable node, it means that the value of the element (i, j) in the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between the variable nodes and the check nodes can also be referred to as an edge. The connection between the check nodes and the variable nodes can also be described as: the check nodes and the variable nodes have a connection or an edge. The edge relationship between the check nodes and the variable nodes can include the existence of an edge or the non-existence of an edge.

[0083] 2. QC-LDPC code

[0084] The QC-LDPC code is a structured LDPC code. Due to the unique structure of the check matrix, a simple feedback shift register can be used for encoding, reducing the encoding complexity of the LDPC code. The QC-LDPC code actually used is represented by a base graph (BG). The elements in the BG are 0 or 1. The 1 and 0 in the BG are expanded, and the check matrix H obtained after the expansion can be used for encoding or decoding. In the embodiments of the present application, the BG can be written in the form of a matrix, which can be referred to as a base matrix H BG BG ​The middle element is 0, indicating that there is no edge in the base graph, and is 1, indicating that there is an edge in the base graph (or indicating that the corresponding check is associated with the corresponding variable). The NR LDPC code involves multiple base graph selection, and the current standard stores two base graphs BG1 and BG2. When the information length is less than or equal to 292, or the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or the code rate is less than or equal to 0.25, BG2 is used, otherwise BG1 is used. The following describes the extension process of the base matrix.

[0085] Based on the base matrix and the lifting value Zc (lifting size), the base matrix can be extended to a complete check matrix for encoding or decoding. In this application, Z c It can also be referred to as an extension factor, a lifting factor, an extension value, an extension coefficient, a lifting size, etc. The extension process is to lift all elements in the base matrix to a Zc*Zc matrix, wherein 0 is lifted to a Zc*Zc 0 matrix, and 1 is lifted to a unit matrix and is cyclically shifted based on the shifting value (SV) corresponding to 1. The cyclic shift can be to the left or to the right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 unit matrix as an example, if the shifting values are 0, 1, and 3, the cyclic shift matrix after right cyclic shift is as shown in the following table:

[0086] (1) When the shifting value is 0 (i.e. remains unchanged), the corresponding matrix after cyclic shift is

[0087] (2) When the shifting value is 1, the corresponding matrix after cyclic shift is

[0088] (3) When the shifting value is 3, the corresponding matrix after cyclic shift is

[0089] It can also be understood that the complete check matrix H can be represented by an exponential matrix H b , wherein each element in H b corresponds to a Zc*Zc submatrix, and each element identifies the number of times the corresponding submatrix is cyclically shifted from the Zc*Zc unit matrix. Thus, the storage space required for the complete check matrix H is greatly reduced. The elements in the exponential matrix H b may also be referred to as QC blocks.

[0090] For example, the exponential matrix H b of the QC-LDPC code is as follows:

[0091] As can be seen, the exponential matrix H bThe size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the matrix represents a square matrix of order Zc. Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0092] For example, As shown below:

[0093] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0094] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are expanded into a Zc*Zc cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a Zc*Zc 0 matrix. After the expansion is completed, the parity check matrix is ​​obtained.

[0095] Next, the information bit sequence c can be encoded based on the parity-check matrix H to obtain a codeword sequence. The codeword sequence includes (N+2*Zc-K) parity bits w, where N is the length of the codeword sequence, K = Kb*Zc, Kb is the number of columns corresponding to the information column in the base map, and Zc is the boost value. For details on Zc, please refer to the explanation in Terminology 3. Specifically, the parity bits w are determined based on the information bit sequence c and the parity-check matrix H, where the parity bits are w = [w0, w1, w2, ..., wN+2*Zc-K-1]. T c = [c0, c1, c2, ..., c K-1 ] T The encoding process is solving equations The process of obtaining w.

[0096] 3. Lifting Size (Zc) and Shifting Value

[0097] The storage content of the 5G LDPC code regarding shift values ​​includes: (1) a list of lifting sizes; and (2) a list of shift values ​​that correspond one-to-one with the rows of the lifting size list.

[0098] For example, the list of Lifting Sizes is shown in Table 1.

[0099] Table 1

[0100] The jth row of the Lifting Size list includes where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; the row index of the Lifting Size list corresponds to the column index of the Shifting Value list, i.e., each row of the Lifting Size list corresponds to a group of Shifting Values.

[0101] For example, the Shifting Value list is shown in Table 2.

[0102] Table 2

[0103] For a fixed lifting value index, one non-zero position of the base matrix corresponds to one shifting value. For example, the element in the 0th row and the 0th column of H BG corresponds to the shifting value 211 when the lifting value index = 0, the element in the 1st row and the 6th column of H BG corresponds to the shifting value 66 when the lifting value index = 3, and the element in the 2nd row and the 9th column of H BG corresponds to the shifting value 206 when the lifting value index = 7.

[0104] It can be understood that, at present, when LDPC encoding is performed, the lifting value needs to be determined first, and then the corresponding shifting value is determined based on the selected lifting value to construct the check matrix. For example, the determined lifting value is 40, and the lifting value index corresponding to 40 in Table 1 is 2, and then the check matrix can be constructed based on the shifting values in the column corresponding to the lifting value index = 2 in Table 2.

[0105] 4. Structure of the base matrix

[0106] FIG. 4 is a schematic diagram of the structure of the check matrix.

[0107] As shown in (a) of FIG. 4, the check matrix can include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region can include the A and B parts shown in (b) of FIG. 4, where the A part corresponds to information bits (or information bits, system bits, etc.), and the B part is a square matrix and corresponds to core check bits (or core check bits), where the core check can be a check corresponding to the highest code rate, or can be a check with a degree greater than or equal to 2, or can be a check node corresponding to a row set with a maximum row weight (a row weight significantly / higher than other rows). The all-zero region can correspond to the C part of (b) of FIG. 4, which is an all-zero matrix. The incremental redundancy region can correspond to the D part of (b) of FIG. 4. The raptor-like region can correspond to the E part of (b) of FIG. 4, which can be a unit matrix and corresponds to check bits for low rate extension. The B part and the E part are both check parts, the B part is defined as a core check region, and the feature can be a non-lower triangular encoding part (i.e., a value above the diagonal is non-all 0), or an encoding part with a column weight greater than 1, and the E part is defined as an extension check region, and the feature can be a lower triangular encoding part (i.e., a value above the diagonal is all 0), or a diagonal matrix.

[0108] The check matrix of the LDPC code shown in FIG. 4 adopts a "raptor-like" structure and can be gradually extended to a low code rate from a high code rate core matrix. In actual use, as shown in (a) of FIG. 4, the first X rows and the first Y columns of the check matrix can be intercepted, and as the code rate gradually decreases from high to low, X and Y gradually increase, and the area of the matrix used also gradually expands.

[0109] It should be noted that the check matrix can be represented by an LDPC base matrix, and therefore the structure of the LDPC base matrix is similar to that of the check matrix, which will not be described in detail here.

[0110] 5. Information columns and check columns

[0111] The columns of the LDPC base matrix are composed of information columns and check columns.

[0112] Information columns: correspond to information bits (or information bits, system bits, etc.), and are the columns corresponding to the A part.

[0113] Parity Check Column: A column corresponding to a parity bit (or parity bit, etc.), a column corresponding to the B part and the C part, which can include a core parity column and an extended parity column. Among them, the core parity column is the column corresponding to the B part, and the extended parity column is the column corresponding to the C part or the E part. The extended parity column can also be referred to as a raptor-like column. Alternatively, the core parity column is a parity column with more than one column in the B part (1 element above and below the diagonal line in the B part), and the extended parity column is the remaining column in the parity column except the core parity column.

[0114] 6、Core Row, Core Column, Core Matrix

[0115] Core Row: A core row of an LDPC base matrix corresponding to a core parity bit. In other words, the core row is a row corresponding to a high code rate region, or a row corresponding to the A part, the B part, or the C part.

[0116] Core Column: Can include all information columns and all core parity columns. In other words, the core column is a column corresponding to a high code rate region, or a column corresponding to the A part + the B part.

[0117] Core Matrix (Kernel Matrix): A matrix region composed of all core rows and all core columns of the LDPC base matrix. In other words, the core matrix is a high code rate region of the LDPC base matrix, or a part composed of the A part and the B part.

[0118] 7、Traditional Extension and Split Extension

[0119] Traditional Extension: Also known as normal extension, it refers to a way of low code rate extension based on a traditional way, in which a row of a storage matrix is read as a row of an LDPC base matrix.

[0120] Split Extension: Unlike the traditional extension, it is necessary to use a newly added row to eliminate a certain row before the newly added row in the LDPC base matrix while reading a row of the storage matrix as a newly added row of the LDPC base matrix. The eliminated row and the newly added row are orthogonal except for the extension node. It can also be understood that the eliminated row is split into the newly added row and the row after elimination; or the row after elimination and the newly added row are orthogonal except for the extension node; or the eliminated row contains all rows in the newly added row except for the extension parity node. The eliminated row can correspond to a parent node, and the newly added row or the eliminated row can correspond to a child node.

[0121] 8、Spatially Coupled-Low Density Parity Check (SC-LDPC) Code

[0122] An SC-LDPC code is constructed by coupling L disjoint sub-codes, where L is the coupling length, and the parity check matrix H of the SC-LDPC code has the following form:

[0123] where H i is a parity check matrix of size M x N, w is the coupling width, is a sub-code, L is the coupling length, i.e., the number of in H.

[0124] A quasi-cyclic SC-LDPC (QC SC-LDPC) code is a special type of SC-LDPC code, whose parity check matrix H can be obtained by lifting its corresponding base matrix B. When the lifting value is Z c , the base matrix B of a QC SC-LDPC code has the following form:

[0125] where B i is a base matrix block of size m x n, m = M / Z c , n = N / Z c , w is the coupling width, and L is the coupling length.

[0126] 9. Information transmission process

[0127] FIG. 5 is a schematic diagram of an information transmission process suitable for the present application. As shown in FIG. 5, information is transmitted from a source to a sink through source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, and source recovery. The upper layer of FIG. 5 shows the processing (including source encoding, channel encoding, and modulation) performed at the sending end device, and the lower layer of FIG. 5 shows the processing (including demodulation, channel decoding, and source recovery) performed at the receiving end device. Embodiments of the present application mainly relate to source encoding, channel encoding, channel decoding, and source recovery.

[0128] Based on the description in the background art, the present application proposes a communication method based on an LDPC code, which can effectively solve the above technical problems. The method proposed by the present application is described in detail below.

[0129] FIG. 6 is a schematic flowchart of a communication method 600 based on an LDPC code according to the present application. The method includes the following steps.

[0130] It can be understood that the method 600 can be executed by a sending end device and a receiving end device, and the "sending end device" or the "receiving end device" can refer to the sending end device or the receiving end device itself, or can refer to an apparatus capable of supporting the sending end device or the receiving end device to implement the function, and for the convenience of description, the sending end device and the receiving end device are used to describe below. The sending end device can be a terminal device or a network device, and the receiving end device can be a terminal device or a network device.

[0131] S610, the sending end device acquires an information bit sequence.

[0132] It can be understood that if the sending end device needs to communicate with the receiving end device, i.e., the sending end device needs to send a signal to the receiving end device, the sending end device needs to acquire an information bit sequence corresponding to the signal to be sent to the receiving end device.

[0133] The sending end device acquiring the information bit sequence can refer to that the sending end device source encodes a source symbol to generate the information bit sequence, or the sending end device acquiring the information bit sequence can also refer to that the sending end device receives the information bit sequence from other communication apparatuses, and the application does not limit the way of acquiring the information bit sequence.

[0134] S620, the sending end device determines an LDPC matrix.

[0135] The LDPC matrix is determined based on an LDPC base matrix (hereinafter referred to as a base matrix), a lifting value Zc and a shift value of the base matrix, wherein the shift value of the base matrix is determined based on a second row sequence R, a second column sequence C and the lifting value Zc, the number of elements of the second row sequence R is equal to the number of rows of the base matrix, and the elements of the second row sequence correspond to the rows of the base matrix one by one, the number of elements of the second column sequence C is equal to the number of columns of the base matrix, and the elements of the second column sequence correspond to the columns of the base matrix one by one, the second row sequence is determined based on a first row sequence, the second column sequence is determined based on a first column sequence, the number of elements of the first row sequence is less than the number of elements of the second row sequence, and the number of elements of the first column sequence is less than the number of elements of the second column sequence.

[0136] For example, the base matrix can be a base matrix of a QC-LDPC code, or can also be a base matrix of a QC SC-LDPC code.

[0137] For example, the first row sequence can correspond to at least one second row sequence, and similarly, the first column sequence can also correspond to at least one second column sequence. If there are multiple second row (column) sequences, the second row (column) sequence to be finally used can be determined according to the lifting value Zc, and the shift value of the base matrix is determined based on the determined second row (column) sequence.

[0138] For example, the correspondence between the elements in the second row (column) sequence and the rows (columns) of the base matrix can be sequential correspondence, i.e., the ith element in the second row (column) sequence corresponds to the ith row (column) of the base matrix, or the correspondence can be reverse sequential correspondence, or the correspondence can also be specific sequential correspondence.

[0139] For example, the first row (column) sequence can be obtained based on Zc or the lifting value index lookup table corresponding to Zc, or the first row (column) sequence can be obtained based on pre-stored sequence calculation, and the application does not limit the obtaining manner of the first row (column) sequence.

[0140] First, the possible implementation of determining the translation value of the base matrix based on the second row sequence R, the second column sequence C and the lifting value Zc is described in detail.

[0141] Optionally, the translation value of the 1 element in the base matrix can be determined based on the following manner: the translation value of the 1 element located at row i and column j in the base matrix is obtained based on the summation of t first values, t is a positive integer, wherein the first value is determined based on R(i), C(j), Zc, p and the s corresponding to the first value, R(i) is the element in the second row sequence R corresponding to row i, C(j) is the element in the second column sequence C corresponding to column j, s is an integer between 1 and t, and p is the prime number corresponding to Zc.

[0142] For example, the s corresponding to any first value in the t first values is different, i.e., the t s corresponding to the t first values are t different integers between 1 and t.

[0143] For example, p can be the prime base of Zc, or can be the maximum value or minimum value in the prime base corresponding to all lifting value sets, or can be the largest prime number that can divide the maximum lifting value in all lifting value sets, or can be a prime number that can divide any lifting value in all lifting value sets.

[0144] The following illustrates p with specific sets of lifting values. For example, there is a set of lifting values that is not exponentially increasing as shown in Table 2, and the set of lifting values corresponds to three sets of lifting values, all of the lifting values in the first set of lifting values satisfy the first expression 7n, n is a positive integer (for example, the first set of lifting values includes lifting values 7, 14, 21), all of the lifting values in the second set of lifting values satisfy the second expression 11n (for example, the second set of lifting values includes lifting values 11, 22, 33), and all of the lifting values in the third set of lifting values satisfy the third expression 13n (for example, the third set of lifting values includes lifting values 13, 26, 39). For example, if Zc is a lifting value in the second set of lifting values, then p is 11. For example, if p is the maximum value in the prime bases corresponding to the three sets of lifting values, then p is 13. For example, if p is the minimum value in the prime bases corresponding to the three sets of lifting values, then p is 7. Here, the above examples are not repeated one by one.

[0145] The following gives two ways to determine SV i,j .

[0146] Method one

[0147] Wherein, mod represents the modulo operation, and the following explains the parameters in the above formula.

[0148] (1) s is a positive integer, t is an integer greater than or equal to 1, u s +v s = s + 1, u s and v s are positive integers.

[0149] For example, t = 2 or 3.

[0150] For example, s = 3, there are the following possible values: u s = 1, v s = 3, or u s = 2, v s = 2, or u s = 3, v s = 1.

[0151] For example, u s = 1, v s = s, then

[0152] For example, u s = s, v s = 1, then

[0153] It can be understood that mod((R(i)*C(j) s ), (Zid_s * p) * k s It can be regarded as an example of one of the above t first values.

[0154] (2) As to p, refer to the description above, which will not be repeated here.

[0155] (3) Z id_s is determined based on Zc, p and s, or, Z id_s = 1.

[0156] In one possible implementation mode, Z id_s = mod(mod(Zc, p s+1 ), p s ), where there are two pieces of modulo, the two pieces of modulo are Zc modulo parameters related to p, and the object of the first piece of modulo is p times the object of the second piece of modulo.

[0157] For example, based on this implementation mode, Z id_1 = mod(mod(Zc, p 2 ), p), Z id_2 = mod(mod(Zc, p 3 ), p 2 ), Z id_3 = mod(mod(Zc, p 4 ), p 3 ), and the specific expression of Z id_s corresponding to s greater than 3 is by analogy, which will not be repeated here.

[0158] Optionally, Z id_s corresponding to all s from 1 to t is determined based on Zc, p and s.

[0159] Optionally, Z id_s corresponding to all s from 1 to t is 1.

[0160] Optionally, Z id_s corresponding to part of s from 1 to t is determined based on Zc, p and s, and Z id_s corresponding to the remaining s is 1.

[0161] (4) k s is a positive integer multiple of p s-1 .

[0162] Specifically, k1 is an integer multiple of 1, k2 is an integer multiple of p, k3 is an integer multiple of p 2 , and so on, which will not be repeated here.

[0163] For example, the positive integer multiple here is 1 times, that is, k s equals ps-1 .

[0164] Based on the description corresponding to Fig. 3, in the Tanner graph, the definition of a cycle is a structure starting from a vertex, along the non-repeated edges, through the non-repeated vertices, and finally returning to the starting point. Since the Tanner graph is a bipartite graph, the length of the cycle can only be an even number greater than 2, such as 4, 6, 8, etc. The shorter cycle has a great harm to the LDPC code, so in the design of the LDPC code, it is necessary to avoid short cycles as much as possible. The above given SV i,j calculation formula can guarantee the cycle characteristics in theory. Different terms of the calculation formula can guarantee different cycle properties. For example, in the above SV i,j calculation formula, s = 1 is to guarantee that the 4-cycle does not exist, s = 2 is to guarantee that the number of 6-cycles is small, and in the case of a large enough Zc, it can also guarantee that the 6-cycle does not exist; s = 3 is to guarantee that the number of 8-cycles is small, and in the case of a large enough Zc, it guarantees that the 8-cycle does not exist, and so on. More terms of s greater than or equal to 3 are to further guarantee the cycle properties.

[0165] Optionally, a fixed constant can be added or subtracted from the above SV i,j calculation formula, and the constant does not change with the positions i and j. At this time, the overall cycle properties do not change.

[0166] Method two

[0167] In this method, s = 1 to t correspond to mod(N s , (Z id_s *p))*k s can be understood as the above t first values. Adding the t first values can obtain the SV i,j . Wherein, each first value corresponds to N s can be obtained by looking up a table.

[0168] It can be understood that the above formula is only an example, and the meanings of the parameters are described in method one, which will not be described here. In this method, the process of obtaining N s by looking up a table is mainly introduced.

[0169] Wherein, N s is obtained based on R(i), C(j) and a pre-stored table s, wherein each row and each column in the table s stores a value corresponding to the position of the table s. N sa value stored in a position corresponding to row r1 and column c1 of table s, where row r1 is a row in table s associated with R(i) and column c1 is a column in table s associated with C(j). For example, as shown in the table on the right side of FIG. 7, element 3 in the second row sequence corresponding to the 2nd row of the base matrix is associated with the (3+1)th row (an example of row r1) of table s, and element 7 in the second column sequence corresponding to the 8th column of the base matrix is associated with the (7+1)th column (an example of column c1) of table s, thus, the shifted value of the 1 element in the 2nd row and 8th column of the base matrix is the value 5 stored in the position corresponding to the 4th row and 8th column of table s.

[0170] It can be understood that N s is obtained based on R(i), C(j) and table s, and when s = 1 to t, the corresponding N s is obtained based on R(i), C(j) and t tables respectively, specifically, N1 is obtained based on R(i), C(j) and table 1, N2 is obtained based on R(i), C(j) and table 2, and so on, which will not be described herein.

[0171] The above describes a manner of obtaining N s by table lookup, and the following still takes table s as an example to describe a possible manner of determining the values stored in table s.

[0172] In a possible implementation, the values N s stored in table s satisfy the following formula:

[0173] where u s +v s = s+1, u s and v s are positive integers.

[0174] In another possible implementation, the values N s stored in table s satisfy the following formula:

[0175] The following describes the correspondence between the rows in table s and the second row sequence, and the correspondence between the columns in table s and the second column sequence.

[0176] In a possible implementation, all rows of table s correspond to all elements in the second row sequence one by one, and all columns of table s correspond to all elements in the second column sequence one by one. For example, R(i) is associated with row i in table s, and C(j) is associated with row j in table s.

[0177] In another possible implementation, the elements in the second row sequence and the second column sequence are elements in a finite field, which can also be called a Galois field, and the number of elements in the finite field is a prime power, which is an algebraic structure that can be added, subtracted, multiplied and divided, and the number of elements in the finite field set is p. For example, p = 13, and the finite field set can be {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}, and the table s is shown in Table 3, all rows of the table s correspond to elements in the finite field, and all columns of the table s correspond to elements in the finite field, specifically, the first column can be regarded as corresponding to a finite field element for each row, and the first row can be regarded as corresponding to a finite field element for each column.

[0178] Table 3

[0179] For example, the elements in the first row sequence and the first column sequence can also be elements in the finite field set.

[0180] For example, R(i) is associated with the row mod((R(i) + a), p) in the table s, and C(j) is associated with the row mod((C(j) + b), p) in the table s.

[0181] For example, a = b. Further, a = b = 0 or a = b = 1 or -1. Wherein, the advantage of a = b = 0 is simple expression, and the advantage of a = b = 1 or -1 is corresponding to the finite field element and easy to calculate and hardware implementation.

[0182] For example, p = 13, the finite field set can be {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}, a = b = -1, the second row sequence is {2, 4, 5, 7, 8, 9}, and the second column sequence is {0, 2, 3, 5, 6, 10}, for example, 5 in the second row sequence is associated with the row 4 in the table s, and for example, 0 in the second column sequence is associated with the column 11 in the table s, and then N s is the value stored in the position corresponding to the row 4 and the column 11 in the table s.

[0183] It can be understood that the formulas in the first mode and the second mode are only examples, for example, Z id_s in the above formula can be replaced by the quotient of Zc divided by the base of Zc, for example, Zc = 33, and the base of Zc is 11, then Z id_s = 3.

[0184] In a possible implementation, the second row sequence and the second column sequence are determined based on the third sequence. For example, the second row sequence can be obtained by intercepting a corresponding number of elements in the third sequence based on the number of rows of the base matrix, and the second column sequence can be obtained by intercepting a corresponding number of elements in the third sequence based on the number of columns of the base matrix.

[0185] Secondly, the possible implementation of determining the second row sequence based on the first row sequence and determining the second column sequence based on the first column sequence is described in detail below by taking two scenarios of the base matrix being a QC-LDPC base matrix and a QC SC-LDPC base matrix as examples.

[0186] In the first scenario, the base matrix is a QC-LDPC base matrix, and the base matrix is determined based on a split sequence θ, and the second row sequence is determined based on the first row sequence and the split sequence θ.

[0187] The split sequence is introduced below. The base matrix is determined based on a split sequence θ, and the split sequence θ includes m elements, m being equal to the number of rows of the base matrix, where the m elements correspond to the m rows of the base matrix in a one-to-one manner. It can be understood that the element corresponding to the i-th row of the base matrix in the m elements is θ(i).

[0188] For example, if the row numbers of the base matrix are numbered from 1, the value of the element θ(i) in the split sequence can be a first character or a positive integer, and the first character is not equal to any positive integer. When θ(i) is a positive integer, it indicates that the i-th row of the base matrix is associated with the row θ(i) of the base matrix, and θ(i) is less than i, that is, the value of θ(i) is less than the row number of the current row. When θ(i) is the first character, it indicates that the i-th row of the base matrix is not associated with any row of the base matrix. The first character can be a number, a letter, or a symbol, and the like, which is not limited in the application. For example, the first character can be 0 in this example, and the split sequence θ indicates the expansion mode of the LDPC storage matrix. When θ(i) is not equal to 0, it indicates that the i-th row needs to be associated with the θ(i)-th row for elimination when the i-th row is expanded (θ(i) can be referred to as the parent node of i, and i can be referred to as the child node of θ(i)). When θ(i) is 0, it indicates that the i-th row is normally expanded.

[0189] For example, if the row numbers of the base matrix are numbered from 0, the first character cannot be 0, and can be other characters such as -1, -2, and the like. The first character is not equal to a natural number (that is, not equal to 0 and a positive integer). Similarly, when θ(i) is a natural number, it indicates that the i-th row of the base matrix is associated with the row θ(i) of the base matrix, and θ(i) is less than i, that is, the value of θ(i) is less than the row number of the current row. When θ(i) is the first character, it indicates that the i-th row of the base matrix is not associated with any row of the base matrix. The expansion mode is the same as above, and details are not repeated here.

[0190] For the convenience of description, the following description is made with the row number and the column number of the base matrix (storage matrix) numbered from 1, and the first character is 0, i.e. the value of the element θ(i) in the split sequence is 0 or a positive integer. The split sequence θ is exemplified. The base matrix includes m = 17 rows, and the split sequence θ includes 17 elements, θ = {0, 0, 0, 0, 0, 0, 0, 3, 1, 4, 0, 0, 0, 0, 2, 7, 6}, and the 17 elements correspond to the 1st to 17th rows of the base matrix one by one. Among them, θ(i) in the split sequence corresponding to the rows i = 1, 2, 3, 4, 5, 6, 7, 11, 12, 13, 14 of the base matrix is 0, θ(8) corresponding to the 8th row of the base matrix is 3 < 8, and θ(9) corresponding to the 9th row of the base matrix is 1 < 9.

[0191] Two specific ways of determining the second row sequence based on the first row sequence are given below.

[0192] In the first way, the first row sequence is composed of multiple elements, the multiple elements correspond to multiple rows of the base matrix one by one, and the multiple rows of the base matrix are all rows i with θ(i) equal to 0. Then, the element corresponding to the row i1 in the second row sequence is equal to the element corresponding to the row i1 in the first row sequence, and the element corresponding to the row i2 in the second row sequence is equal to the element corresponding to the row θ(i2) in the second row sequence, where θ(i1) is equal to 0, θ(i2) is a positive integer, and θ(i2) is less than i2.

[0193] For example, the multiple elements in the first row sequence are all different from each other, and the elements corresponding to the rows i1 in the second row sequence are all different from each other.

[0194] Take Table 4 and Table 5 as examples. It can be understood that the storage matrix has the same number of rows as the base matrix, and the matrix in Table 4 to Table 6 is a storage matrix. As shown in Table 4, the split sequence θ is {0, 0, 0, 3, 2, 1, 0}, and the 7 elements in the split sequence θ correspond to the 1st row to the 7th row of the base matrix one by one. The first row sequence is {0, 3, 1, 2}, and the 4 elements in the first row sequence correspond to the 1st row, the 2nd row, the 3rd row and the 7th row of the base matrix one by one. Then, as shown in Table 5, the element corresponding to the row i1 in the second row sequence, i.e. the elements corresponding to the 1st row, the 2nd row, the 3rd row and the 7th row in the second row sequence are {0, 3, 1, 2}. In addition, the element corresponding to the row i2 in the second row sequence, i.e. the element corresponding to the 4th row in the second row sequence is equal to the element corresponding to the θ(4)th row in the second row sequence, since θ(4) = 3, the element corresponding to the 4th row in the second row sequence is equal to the element corresponding to the 3rd row in the second row sequence, i.e. equal to 1. Similarly, the element corresponding to the 5th row in the second row sequence is equal to the element corresponding to the θ(5)th row (i.e. the 2nd row) in the second row sequence, i.e. equal to 3, and the element corresponding to the 6th row in the second row sequence is equal to the element corresponding to the θ(6)th row (i.e. the 1st row) in the second row sequence, i.e. equal to 0. Therefore, the determined second row sequence is {0, 3, 1, 1, 3, 0, 2}.

[0195] Table 4

[0196] Table 5

[0197] In the second mode, the first row sequence is composed of a plurality of elements, and the plurality of elements correspond to a plurality of rows of the base matrix one by one, and the plurality of rows are rows corresponding to θ(i) equal to 0 in the core region of the base matrix. Then, the element corresponding to the row i1 in the second row sequence is equal to the element corresponding to the row i1 in the first row sequence, the element corresponding to the row i3 in the second row sequence is equal to the element corresponding to the row i3' in the first row sequence, and the element corresponding to the row i2 in the second row sequence is equal to the element corresponding to the row θ(i2) in the second row sequence, wherein the row i1 is any row in the plurality of rows, the row i3 is any row in the remaining rows except the plurality of rows in all rows where θ(i) is equal to 0, i3' is less than i3, wherein θ(i1) is equal to 0, θ(i2) is a positive integer, and θ(i2) is less than i2.

[0198] For example, the row i3' is any row in the rows with a common adjacent point number less than or equal to 1 with the row i3. For example, the elements in the corresponding positions of column c in row a and row b in the storage matrix are both 1, and the number of column c in the storage matrix satisfying the above condition can be understood as the common adjacent point number of row a and row b.

[0199] Take Table 4 and Table 6 as examples. As shown in Table 4, the split sequence θ is {0, 0, 0, 3, 2, 1, 0}, and the 7 elements in the split sequence θ correspond to the 1st to 7th rows of the base matrix respectively. The first row sequence is {0, 3, 1}, and the 3 elements in the first row sequence correspond to the 1st, 2nd and 3rd rows of the base matrix respectively. As shown in Table 6, the elements corresponding to the 1st, 2nd and 3rd rows of the base matrix in the second row sequence are {0, 3, 1} respectively. The element corresponding to the 7th row of the base matrix in the second row sequence can be equal to the element corresponding to the 1st, 2nd or 3rd row of the base matrix in the first row sequence. In the example, the row with the number of common collocated points with the 7th row of the storage matrix less than or equal to 1 is selected. It can be seen that only the 1st row of the storage matrix satisfies the condition that the number of common collocated points with the 7th row is less than or equal to 1. Therefore, the element corresponding to the 7th row of the base matrix in the second row sequence is equal to the element corresponding to the 1st row of the base matrix in the first row sequence, i.e. equal to 0. In addition, the element corresponding to the 4th row in the second row sequence is equal to the element corresponding to the θ(4)th row in the second row sequence. Since θ(4) = 3, the element corresponding to the 4th row in the second row sequence is equal to the element corresponding to the 3rd row in the second row sequence, i.e. equal to 1. Similarly, the element corresponding to the 5th row in the second row sequence is equal to the element corresponding to the θ(5)th row (i.e. the 2nd row) in the second row sequence, i.e. equal to 3. The element corresponding to the 6th row in the second row sequence is equal to the element corresponding to the θ(6)th row (i.e. the 1st row) in the second row sequence, i.e. equal to 0. Therefore, the determined second row sequence is {0, 3, 1, 1, 3, 0, 0}.

[0200] Table 6

[0201] It can be seen that the first sequence does not contain the element corresponding to the row i with θ(i) not equal to the first character. This has the advantage of ensuring the correlation of the translation values of the child nodes and the parent nodes, and can achieve the elimination expansion of the QC level.

[0202] Optionally, the first row sequence can be determined based on the split sequence, wherein the plurality of elements in the first row sequence are included in the split sequence, the first element in the first row sequence is the minimum value in the split sequence, and the element corresponding to the first row in the first row sequence is less than the element corresponding to the second row. The row number of the first row is less than the row number of the second row. It can also be understood that for the row i with θ(i) = 0, the first row sequence selects a minimum element not currently appearing in the first row sequence as the element corresponding to the row i according to the elements in the split sequence in ascending order, i.e. the selected element corresponding to the row i is not equal to the element in the first row sequence corresponding to the row i' (i' < i); for the row i with θ(i) > 0, the value of the first row sequence of the row i does not need to be considered.

[0203] For example, the split sequence is {0, 0, 0, 3, 2, 1, 0}, the first row sequence is {0, 1, 2, 3}, and the four elements in the first row sequence correspond to the first row, the second row, the third row and the seventh row of the base matrix respectively.

[0204] For example, the split sequence can be a pre-stored sequence.

[0205] The following describes a manner of determining the second column sequence based on the first column sequence.

[0206] Optionally, the first column sequence includes a plurality of elements, the plurality of elements correspond to core columns of the base matrix one by one, and an element corresponding to column j1 in the second column sequence is equal to an element corresponding to column j1 in the first column sequence, where column j1 is any column in the core columns.

[0207] For example, elements corresponding to all columns except the core columns in the base matrix in the second column sequence are natural numbers. For example, the elements corresponding to the remaining columns in the second column sequence can all be the same, for example, 0 or 1, or the elements corresponding to the remaining columns in the second column sequence can not be the same, for example, can be filled in a 01 or 10 cycle, and the present application does not limit this.

[0208] Scenario two: the base matrix is a QC SC-LDPC base matrix, and the base matrix is in the form of matrix B:

[0209] wherein the coupling length of the subcode of the base matrix is L, the coupling width is w, the number of rows of each base matrix block B i in the subcode is m, and the number of columns is n.

[0210] In a possible implementation, the first row sequence includes (m*(w+1)) elements, and one base matrix block B i corresponds to m rows, so that each m elements in the first row sequence can be regarded as corresponding to B0,..., B w in order respectively. In addition, the rule of obtaining the second row sequence based on the first row sequence is that the second row sequence obtained by cyclic reuse based on the first row sequence includes (m*(L+w)) elements, because the base matrix includes a total of (m*(L+w)) rows.

[0211] In a possible implementation, the first column sequence can include (n*(w+1)) elements, and one base matrix block B iCorresponding to n columns, it can be seen that each n elements in the first column sequence are respectively in one-to-one correspondence with (w+1) B0s in order. In addition, the rule for obtaining the second column sequence based on the first column sequence is that the second column sequence obtained based on the cyclic reuse of the first column sequence includes (n*L) elements, because the base matrix includes a total of (n*L) columns.

[0212] An example of cyclic reuse of the sequence is described. For example, the base matrix includes a total of 10 rows, the first row sequence is {0, 3, 1, 2}, and the second row sequence is {0, 3, 1, 2, 0, 3, 1, 2, 0, 3}.

[0213] It can be understood that (w+1) in the above description is a parameter related to the coupling width w. Alternatively, (w+1) can be replaced by (w+c), and the corresponding first row / column sequence and the second row / column sequence are as follows: the first row sequence includes (m*(w+c)) elements, the elements in the first row sequence are in one-to-one correspondence with the first (m*(w+c)) rows of the base matrix, c is an integer, the first column sequence includes (n*(w+c)) elements, the elements in the first column sequence are in one-to-one correspondence with the first (n*(w+c)) columns of the base matrix. The second row sequence includes (m*(L+w)) elements, the elements in the second row sequence are obtained based on the cyclic reuse of the first row sequence, and the second column sequence includes (n*L) elements, the elements in the second column sequence are obtained based on the cyclic reuse of the first column sequence.

[0214] For example, c is equal to -1, -2, 0, 1, or 1. The advantage of this mode is that the cyclic property can be guaranteed as much as possible, and flexible lifting values are supported.

[0215] It can also be understood that the elements in the second row sequence corresponding to all the rows in the base matrix are obtained based on the cyclic reuse of the first row sequence, and similarly, the elements in the second column sequence corresponding to all the columns in the base matrix are obtained based on the cyclic reuse of the first column sequence. Therefore, as long as the shift values corresponding to each 1 element in region #1 in the base matrix are calculated, where region #1 is a region composed of the first (2*m*(w+c)-1) rows and the first (n*(w+c)) columns of the base matrix, the shift values of the remaining positions in the base matrix can be obtained based on the cyclic reuse of the shift values of the region.

[0216] For example, n = m = 1, w = 4, L = 10, as shown in FIG. 8, the base matrix is a 14-row 10-column matrix, only the positions of the 1 elements in the base matrix are shown, and the elements in the remaining positions are all 0 elements. For example, if c = 1, the first row sequence includes 5 elements, the first column sequence includes 5 elements, the second row sequence and the second column sequence are obtained by cyclic shift based on the first row sequence and the first column sequence, the second row sequence includes 14 elements, which correspond to the 14 rows of the base matrix one by one respectively, and the second column sequence includes 10 elements, which correspond to the 10 columns of the base matrix one by one respectively. As shown in FIG. 8, as long as the shift value of the 1 element in the region #1 of the base matrix is determined, the region #1 is a region composed of the first 9 rows and the first 5 columns of the base matrix, then the shift values of the remaining positions in the base matrix can be obtained by cyclic reuse based on the shift value of the region, as shown in FIG. 8.

[0217] In another possible implementation, the length of the first row sequence is (w + c1) * m, and the length of the first column sequence is (w + c2) * n, where c is an integer, and c1 < c2, then the second row sequence obtained by cyclic reuse of the first row sequence includes (m * (L + w)) elements, and the second column sequence obtained by cyclic reuse of the first column sequence includes (n * L) elements. Then, the shift values of the base matrix are determined based on the second row sequence and the second column sequence. It can be understood that the elements corresponding to all the rows of the base matrix in the second row sequence are obtained by cyclic reuse of the first row sequence, and the elements corresponding to all the columns of the base matrix in the second column sequence are obtained by cyclic reuse of the first column sequence. Therefore, as long as the shift value corresponding to each 1 element in the region #1 of the base matrix is calculated, where the region #1 is a region composed of the first (2 * m * (w + c1) - 1) rows and the first (n * (w + c2)) columns of the base matrix, the shift values of the remaining positions in the base matrix can be obtained by cyclic reuse based on the shift values of the region.

[0218] Optionally, in the process of cyclic reuse of the first row (column) sequence to obtain the second row (column) sequence, permutation can be performed on the first row (column) sequence in each round of cyclic reuse. Taking the first row sequence as sequence #1 for example, the second row sequence is {{sequence #1}, p1{sequence #1}, p2{sequence #1}…}, where p i All are permutations of the sequence #1. For example, the base matrix includes 10 rows in total, the first row sequence is {0, 3, 1, 2}, and the second row sequence can be {{0, 3, 1, 2}, {3, 1, 0, 2}, {3, 0}}.

[0219] It can be understood that the LDPC matrix can be obtained by lifting and shifting the elements in the base matrix. In this application, the LDPC matrix can also be referred to as an LDPC encoding matrix. For example, the LDPC matrix can be an LDPC check matrix or an LDPC generator matrix. The LDPC check matrix or the LDPC generator matrix is a matrix obtained by lifting and shifting the elements in all regions of the base matrix, and the LDPC generator matrix and the LDPC check matrix correspond to each other.

[0220] In S630, the sending device encodes the information bit sequence according to the LDPC matrix, and outputs a codeword sequence.

[0221] For the encoding process, refer to the description above, which will not be repeated here.

[0222] In S640, the sending device determines a symbol sequence based on the codeword sequence.

[0223] It can be understood that the symbol sequence can be a sequence after rate matching and modulation. For example, the sending device performs rate matching on the codeword sequence, then modulates the sequence after rate matching to obtain a symbol sequence, and maps the modulated symbol sequence to a physical resource for transmission.

[0224] In S650, the sending device sends the symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the sending device.

[0225] It can be understood that the symbol sequence #1 sent by the sending device and the symbol sequence #2 received by the receiving device can be different due to the introduction of channel noise signals in the transmission process of the symbol sequence.

[0226] In S660, the receiving device decodes the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

[0227] The LDCP matrix used by the receiving device for decoding is the same as the LDPC matrix used by the sending device for encoding. The specific manner in which the receiving device determines the LDPC matrix can refer to the description on the sending device side, which will not be described in detail here.

[0228] It can be understood that the steps in the above figures are only exemplary and are not strictly limited. In addition, the size of the serial number of the above processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the application.

[0229] It can also be understood that some optional features in the embodiments of the application can not depend on other features in some scenarios, or can be combined with other features in some scenarios, without limitation.

[0230] It should also be understood that the methods implemented by the devices (the sending device or the receiving device) in the above various method embodiments can also be implemented by components (such as chips or circuits) of the devices, without limitation.

[0231] The method embodiments provided by the present application are described in detail above in combination with FIG. 1 to FIG. 8. The device embodiments of the present application will be described below in combination with FIG. 9 and FIG. 10. It can be understood that, in order to implement the functions in the above embodiments, the devices in FIG. 9 and FIG. 10 include corresponding hardware structures and / or software modules for performing various functions. Those skilled in the art should easily realize that, in combination with the units and method steps of the examples described in the embodiments disclosed in the present application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. It can be understood that the technical features described in the above method embodiments are also applicable to the following device embodiments.

[0232] FIG. 9 and FIG. 10 are structural schematic diagrams of possible devices provided by the embodiments of the present application. These devices can be used to implement the functions of the sending device or the receiving device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0233] FIG. 9 is a schematic block diagram of a communication device 1000 provided by the embodiments of the present application. As shown in FIG. 9, the device 1000 can include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside, and the processing unit 1020 is used for data processing. The communication unit 1010 can also be referred to as a communication interface or a transceiver unit.

[0234] In a possible design, the device 1000 can implement steps or procedures corresponding to those performed by the sending device in the above method embodiments, in which the processing unit 1020 is configured to perform processing-related operations of the sending device in the above method embodiments, and the communication unit 1010 is configured to perform sending-related operations of the sending device in the above method embodiments.

[0235] In another possible design, the device 1000 can implement steps or procedures corresponding to those performed by the receiving device in the above method embodiments, in which the communication unit 1010 is configured to perform receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is configured to perform processing-related operations of the receiving device in the above method embodiments.

[0236] It should be appreciated that the apparatus 1000 herein is embodied in the form of functional units. The term "unit" herein can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (for example, a shared processor, a dedicated processor, or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combination of logic circuitry and / or other suitable components that support the described functions. In an optional example, those skilled in the art can understand that the apparatus 1000 can be embodied in the form of the sending device in the above-described embodiments, and can be used to execute the respective processes and / or steps corresponding to the sending device in the above-described method embodiments, or the apparatus 1000 can be embodied in the form of the receiving device in the above-described embodiments, and can be used to execute the respective processes and / or steps corresponding to the receiving device in the above-described method embodiments. To avoid repetition, details are not described herein.

[0237] The apparatus 1000 of each of the above-described schemes has a function of implementing the respective steps performed by the sending device in the above-described methods, or the apparatus 1000 of each of the above-described schemes has a function of implementing the respective steps performed by the receiving device in the above-described methods. The function can be implemented by hardware, or can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions; for example, the communication unit can be replaced by a transceiver (for example, the sending unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor, which respectively performs the transceiving operations and related processing operations in each of the method embodiments.

[0238] In addition, the communication unit can also be a transceiving circuit (for example, can include a receiving circuit and a sending circuit), and the processing unit can be a processing circuit. In the embodiments of the present application, the apparatus in FIG. 9 can be the receiving device or the sending device in the above-described embodiments, or can be a chip or a chip system, for example, a system on chip (SoC). The communication unit can be an input / output circuit, a communication interface; and the processing unit can be a processor or a microprocessor integrated on the chip or an integrated circuit. Details are not limited herein.

[0239] FIG. 10 is a schematic block diagram of a communication apparatus 1100 provided by the embodiments of the present application. The apparatus 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is configured to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0240] Optionally, the apparatus 1100 further includes a memory 1130, which is in communication with the processor 1110 and the transceiver 1120 via the internal connection path. The memory 1130 is used to store instructions, which the processor 1110 can execute. In one possible implementation, the apparatus 1100 is configured to implement the procedures and steps corresponding to the transmitting end device in the above-described method embodiments. In another possible implementation, the apparatus 1100 is configured to implement the procedures and steps corresponding to the receiving end device in the above-described method embodiments.

[0241] Optionally, the memory 1130 can be integrated in the processor 1110.

[0242] In one possible scenario, the apparatus 1100 includes at least one processor integrated with a memory, and other memory in addition to the memory integrated in the processor.

[0243] It can be understood that the apparatus 1100 can be specifically the transmitting end device or the receiving end device in the above-described embodiments, or a chip or chip system. Correspondingly, the transceiver 1120 can be a transceiver circuit of the chip, which is not limited here. Specifically, the apparatus 1100 can be configured to execute the procedures and steps corresponding to the transmitting end device or the receiving end device in the above-described method embodiments.

[0244] Optionally, the memory 1130 can include a read-only memory and a random access memory, and provide instructions and data for the processor. The memory can include a non-volatile random access memory. For example, the memory can also store device type information. The processor 1110 can be configured to execute the instructions stored in the memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to execute the procedures and steps of the above-described method embodiments corresponding to the transmitting end device or the receiving end device.

[0245] In the implementation process, the procedures of the above-described method can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The procedures of the method disclosed in the embodiments of the present application can be directly embodied as being completed by a hardware processor, or completed by a combination of hardware and software modules in the processor. The software modules can be located in the random access memory, the flash memory, the read-only memory, the programmable read-only memory, the electrically erasable programmable memory, the register, or other mature storage media in the field. The storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the procedures of the above-described method. To avoid repetition, it will not be described in detail here.

[0246] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with a signal processing capability. In the implementation process, the steps of the method embodiments described above can be completed by an integrated logic circuit or an instruction in the form of software in the processor. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The processor in the embodiments of the present application can realize or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or be executed by a combination of hardware and software modules in the code processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the storage, and the processor reads the information in the storage, and combines the hardware to complete the steps of the above method.

[0247] It is to be appreciated that the memory in the embodiments of the application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Where the nonvolatile memory is, for example, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. The volatile memory, which can be used as external cache, can be, for example, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), or direct rambus RAM (DR RAM). It is to be appreciated that the memory described herein is intended to include, among other things, these and any other memory suitable for storing or providing program code or instructions to a processor or other system.

[0248] Optionally, the memory (e.g., 1130) in the embodiments of the application can be integrated in the processor (e.g., 1110).

[0249] In addition, the application also provides a computer readable storage medium, the computer readable storage medium stores computer instructions, when the computer instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0250] The application also provides a computer program product, the computer program product includes computer program code or instructions, when the computer program code or instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0251] Further, the application provides a chip including a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are performed.

[0252] Further, the chip can further include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can further include a memory.

[0253] Further, the application provides a communication system including the sending device and the receiving device in the embodiments of the application.

[0254] It should be further noted that the memory described herein is intended to include, but not limited to, these and any other suitable types of memory.

[0255] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form. The units described as separate components can be or can not be physically separate, and the components shown as units can be or can not be physical units, i.e. can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the functional units in each embodiment of the application can be integrated in one processing unit, or each unit can be physically present, or two or more units can be integrated in one unit.

[0256] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0257] It can be understood that the "embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0258] It can also be understood that in the present application, "when", "if" and "when" all refer to the case that the network element will make corresponding processing under certain objective circumstances, not the time limit, and it is not required that the network element must have a judgment action when it is implemented, nor does it mean that there are other limitations.

[0259] It can also be understood that in the embodiments of the present application, "A corresponding B" means that B is associated with A, and B can be determined according to A. However, it can also be understood that determining B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

Claims

1. A communication method based on a low-density parity-check (LDPC) code, characterized by, The method comprises: obtaining an information bit sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC base matrix, a lifting value Zc and a shift value of the base matrix, wherein the shift value of the base matrix is determined based on a second row sequence, a second column sequence and the lifting value Zc, the second row sequence having a number of elements equal to a number of rows of the base matrix and the elements of the second row sequence corresponding to the rows of the base matrix one by one, the second column sequence having a number of elements equal to a number of columns of the base matrix and the elements of the second column sequence corresponding to the columns of the base matrix one by one, the second row sequence being determined based on a first row sequence, the second column sequence being determined based on a first column sequence, the first row sequence having a number of elements less than that of the second row sequence, and the first column sequence having a number of elements less than that of the second column sequence; encoding the information bit sequence according to the LDPC matrix to obtain a codeword sequence.

2. A communication method based on a low-density parity-check (LDPC) code, comprising: obtaining a symbol sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC base matrix, a lifting value Zc and a shift value of the base matrix, wherein the shift value of the base matrix is determined based on a second row sequence, a second column sequence and the lifting value Zc, the second row sequence having a number of elements equal to a number of rows of the base matrix and the elements of the second row sequence corresponding to the rows of the base matrix one by one, the second column sequence having a number of elements equal to a number of columns of the base matrix and the elements of the second column sequence corresponding to the columns of the base matrix one by one, the second row sequence being determined based on a first row sequence, the second column sequence being determined based on a first column sequence, the first row sequence having a number of elements less than that of the second row sequence, and the first column sequence having a number of elements less than that of the second column sequence; decoding the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The shift value of a 1 element located at row i and column j in the base matrix is obtained by summing t first values, t being a positive integer, wherein the first value is determined based on R(i), C(j), the Zc, p and s corresponding to the first value, R(i) being an element in the second row sequence corresponding to the row i, C(j) being an element in the second column sequence corresponding to the column j, s being an integer between 1 and t, and p being a prime number corresponding to the Zc.

4. The method according to claim 3, wherein the p is a prime base of the Zc, or the p is a largest prime number that can divide a largest lifting value in a set of lifting values, or the p is a prime number that can divide any lifting value in the set of lifting values, or the p is a largest value or a smallest value in prime bases corresponding to the set of lifting values.

5. The method according to claim 3 or 4, characterized in that, Shift value SV of the 1 element in the base matrix located at row i column j i,j satisfies the following equation: wherein s is a positive integer, u s v s = s + 1, u s and v s are positive integers, The Z id_s is determined based on the Zc, the p, and the s, or, the Z id s = 1,​ The k s is a positive integer multiple of p s-1 .

6. The method according to claim 3 or 4, characterized in that, Shift value SV of the 1 element in the base matrix located at row i column j i,j satisfies the following equation: wherein The N s a value stored in a position corresponding to a row r1 and a column c1 of a table s, the row r1 being a row of the table s associated with the R(i), the column c1 being a column of the table s associated with the C(j), the s being a positive integer, The Z id_s is determined based on the Zc, the p, and the s, or, the Z id_s = 1, The k s is a positive integer multiple of p s-1 .

7. The method of claim 6, wherein, The values N stored in the table s s satisfy the following equation: wherein u s v s = s + 1, said u s and said v s are positive integers.

8. The method according to claim 6 or 7, wherein all rows of the table s correspond to elements in the second row sequence one by one, and all columns of the table s correspond to elements in the second column sequence one by one.

9. The method according to any one of claims 5 to 8, characterized in that, The Z id_s determined based on the Zc, the p, and the s, the Z id_s satisfies the following equation: Z id_s = mod(mod(Zc, p s+1 ), p s ).

10. The method according to any one of claims 1 to 9, characterized in that, The base matrix is determined based on a split sequence θ, an element corresponding to a row i of the base matrix in the split sequence θ is θ(i), wherein the θ(i) is equal to a first character, indicating that the row i of the base matrix is not associated with any row of the base matrix, otherwise, indicating that the row i of the base matrix is associated with the row θ(i) of the base matrix, and the θ(i) is less than the i, The first row sequence consists of a plurality of elements, the plurality of elements correspond to a plurality of rows of the base matrix one by one, the plurality of rows are all rows i in which the θ(i) is equal to the first character, an element corresponding to a row i1 in the second row sequence is equal to an element corresponding to the row i1 in the first row sequence, an element corresponding to a row i2 in the second row sequence is equal to an element corresponding to a row θ(i2) in the second row sequence, wherein θ(i1) is equal to the first character, θ(i2) is not equal to the first character, Or, The first row sequence consists of a plurality of elements, the plurality of elements correspond to a plurality of rows of the base matrix one by one, the plurality of rows are all rows i in which the θ(i) is equal to the first character, an element corresponding to a row i1 in the second row sequence is equal to an element corresponding to the row i1 in the first row sequence, an element corresponding to a row i3 in the second row sequence is equal to an element corresponding to a row i3' in the first row sequence, an element corresponding to a row i2 in the second row sequence is equal to an element corresponding to a row θ(i2) in the second row sequence, wherein the row i1 is any row in a core of the base matrix, the row i3 is any row remaining except the core row among all rows in which the θ(i) is equal to the first character, the i3' is less than the i3, θ(i1) is equal to the first character, θ(i2) is not equal to the first character.

11. The method of claim 10, wherein, The first row sequence is determined based on the split sequence, wherein the plurality of elements in the first row sequence are all included in the split sequence, a first element in the first row sequence is a minimum value in the split sequence, and an element corresponding to a first row in the first row sequence is less than an element corresponding to a second row, a row number of the first row is less than a row number of the second row.

12. The method according to any one of claims 1 to 11, characterized in that, The first column sequence includes a plurality of elements, the plurality of elements correspond to a plurality of core columns of the base matrix one by one, an element corresponding to a column j1 in the second column sequence is equal to an element corresponding to the column j1 in the first column sequence, the column j1 is any column in the core columns.

13. The method of any one of claims 1 to 9, wherein, The base matrix is a cyclic shift space coupled low density parity check QCSC-LDPC base matrix, a coupling length of a subcode of the base matrix is L, a coupling width is w, a number of rows of each base matrix block in the subcode is m, and a number of columns is n, The first row sequence consists of (m*(w+c)) elements, the elements in the first row sequence one-to-one correspond to the first (m*(w+c)) rows of the base matrix, and the c is an integer, The first column sequence consists of (n*(w+c)) elements, the elements in the first column sequence one-to-one correspond to the first (n*(w+c)) columns of the base matrix, The second row sequence consists of (m*(L+w)) elements, the elements in the second row sequence are obtained based on cyclic reuse of the first row sequence, The second column sequence consists of (n*L) elements, the elements in the second column sequence are obtained based on cyclic reuse of the first column sequence.

14. The method of claim 13, wherein, The c is equal to -1, -2, 0, 1, or 1.

15. A communications device, characterized by The communication device comprises at least one processor and interface circuitry for receiving signals from other communication devices outside the communication device and transmitting signals to the processor or sending signals from the processor to other communication devices outside the communication device, and the processor is configured to implement the method according to any one of claims 1 to 14 by means of logic circuitry or executing code instructions.

16. The communication apparatus according to claim 15, wherein The communication device is a chip or a chip system.

17. A computer readable storage medium characterized by: The storage medium stores a computer program or instructions, and when the computer program or instructions are executed, the method according to any one of claims 1 to 14 is implemented.

18. A computer program product, characterised in that, The computer program is configured to implement the method according to any one of claims 1 to 14 when the computer program is executed.

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