Array substrate, display panel, and display device
By segmenting the slit electrode into multiple branch electrodes and connecting them to the main electrode, the problems of high risk of interrupted lines and low luminous efficiency in TFT-LCDs are solved, achieving higher light transmittance and luminous efficiency.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2024-09-23
- Publication Date
- 2026-05-15
AI Technical Summary
The slit electrode structure in existing thin-film transistor liquid crystal displays (TFT-LCDs) results in large dark fields and poor light efficiency at the edges of the pixel structure. Furthermore, the large size of individual pixels leads to excessively long slit electrodes, increasing the risk of line breakage.
The slit electrode is segmented into multiple branch electrodes and connected by a main electrode to reduce electrode length and lower the risk of wire breakage. At the same time, multiple main electrodes are set to optimize the electric field distribution, reduce edge dark field, and improve light efficiency.
It reduces the risk of wire breakage, increases light transmittance, improves luminous efficiency, and achieves higher overall transmittance and better electrical connection.
Smart Images
Figure CN2024120491_15052026_PF_FP_ABST
Abstract
Description
Array substrate, display panel and display device Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology
[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.
[0003] Summary of the Invention
[0004] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:
[0005] On one hand, embodiments of this disclosure provide an array substrate, including:
[0006] Substrate;
[0007] Multiple electrodes are located on the substrate; the electrodes include a first main electrode, a second main electrode, multiple first branch electrodes, multiple second branch electrodes, and multiple third branch electrodes; wherein...
[0008] The plurality of first branch electrodes extend along a first direction and are arranged along a second direction;
[0009] The plurality of second branch electrodes extend along a third direction and are arranged along the second direction, wherein the first direction, the second direction, and the third direction intersect.
[0010] The plurality of third branch electrodes extend along the first direction and are arranged along the second direction on one side of the plurality of first branch electrodes;
[0011] The first main electrode is located between the columns containing the plurality of first branch electrodes and the columns containing the plurality of second branch electrodes, and the first main electrode is connected to the plurality of first branch electrodes and the plurality of second branch electrodes;
[0012] The second main electrode is located on the side of the plurality of third branch electrodes away from the first main electrode, and the second main electrode is connected to the plurality of third branch electrodes.
[0013] In some embodiments, in the array substrate provided in the present disclosure, the electrode further includes a first common branch electrode, which extends along the first direction between the plurality of first branch electrodes and the plurality of third branch electrodes, and is connected between the first main electrode and the second main electrode.
[0014] In some embodiments, in the array substrate provided in this disclosure, the electrodes further include a third main electrode and a plurality of fourth branch electrodes; wherein,
[0015] The plurality of fourth branch electrodes extend along the third direction on one side of the plurality of second branch electrodes and are arranged along the second direction;
[0016] The third main electrode is located on the side of the plurality of fourth branch electrodes away from the first main electrode, and the third main electrode is connected to the plurality of fourth branch electrodes.
[0017] In some embodiments, in the array substrate provided in the present disclosure, the electrode further includes a second common branch electrode, which extends along the third direction between the plurality of second branch electrodes and the plurality of fourth branch electrodes, and is connected between the first main electrode and the third main electrode.
[0018] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first branch electrodes and the plurality of second branch electrodes are connected to the same first main electrode.
[0019] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first branch electrodes and the plurality of second branch electrodes are arranged along a fourth direction, and the plurality of third branch electrodes and the plurality of fourth branch electrodes are arranged along the fourth direction, which is substantially perpendicular to the second direction.
[0020] In some embodiments, the array substrate provided in this disclosure further includes transistors;
[0021] The electrode also includes a block electrode located at the end of the second main electrode away from the first common branch electrode, and the block electrode is electrically connected to the first electrode of the transistor.
[0022] In some embodiments, the array substrate provided in this disclosure further includes multiple data lines, and the second electrode of the transistor is electrically connected to the data lines;
[0023] The second electrode of the transistor is "m-shaped", with the opening of the "m-shaped" electrode facing the electrode corresponding to the transistor. The first electrode of the transistor includes two sub-electrodes extending from the "m-shaped" opening, and the two sub-electrodes converge at the block electrode.
[0024] In some embodiments, the array substrate provided in this disclosure further includes multiple common electrode lines, multiple transition electrodes, and multiple common electrodes;
[0025] The electrode includes a clearance structure located at the corner of the side where the third main electrode is located, and the common electrode line is electrically connected to the common electrode through the adapter electrode within the area where the clearance structure is located.
[0026] In some embodiments, in the array substrate provided in the present disclosure, the electrodes further include a fourth main electrode, a third common branch electrode, a fourth common branch electrode, a plurality of fifth branch electrodes, and a plurality of sixth branch electrodes; wherein...
[0027] The third common branch electrode extends along the first direction on the side of the plurality of third branch electrodes away from the first common branch electrode, and the third common branch electrode is connected between the second main electrode and the fourth main electrode.
[0028] On the side of the third common branch electrode away from the plurality of third branch electrodes, the plurality of fifth branch electrodes extend along the first direction and are arranged along the second direction;
[0029] The fourth common branch electrode extends along the third direction on the side of the plurality of fourth branch electrodes away from the second common branch electrode, and the fourth common branch electrode is connected between the third main electrode and the fourth main electrode.
[0030] On the side of the fourth common branch electrode away from the plurality of fourth branch electrodes, the plurality of sixth branch electrodes extend along the third direction and are arranged along the second direction;
[0031] The fourth main electrode is located between the plurality of fifth branch electrodes and the plurality of sixth branch electrodes, and the plurality of fifth branch electrodes are electrically connected to the plurality of sixth branch electrodes through the fourth main electrode.
[0032] In some embodiments, in the array substrate provided in the present disclosure, the linewidth of the fourth main electrode is approximately the same as the linewidth of the first main electrode.
[0033] The linewidth of the third common branch electrode and the linewidth of the fifth branch electrode are approximately the same as the linewidth of the first branch electrode.
[0034] The linewidth of the fourth common branch electrode and the linewidth of the sixth branch electrode are approximately the same as the linewidth of the second branch electrode.
[0035] The spacing between adjacent fifth branch electrodes, the spacing between the third common branch electrode and adjacent third branch electrodes, and the spacing between the third common branch electrode and adjacent fifth branch electrodes are approximately equal to the spacing between adjacent first branch electrodes;
[0036] The spacing between adjacent sixth branch electrodes, the spacing between the fourth common branch electrode and adjacent fourth branch electrodes, and the spacing between the fourth common branch electrode and adjacent sixth branch electrodes are approximately equal to the spacing between adjacent second branch electrodes.
[0037] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first branch electrodes and the plurality of fourth branch electrodes are arranged along a fourth direction, the plurality of third branch electrodes and the plurality of second branch electrodes are arranged along the fourth direction, the first trunk electrode connected to the plurality of first branch electrodes and the first trunk electrode connected to the plurality of second branch electrodes are staggered along the fourth direction, and the fourth direction is substantially perpendicular to the second direction.
[0038] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first branch electrodes and the plurality of second branch electrodes are connected to different first main electrodes;
[0039] The third branch electrode, which is furthest from the first common branch electrode, is connected to the fourth branch electrode, which is furthest from the second common branch electrode.
[0040] In some embodiments, in the array substrate provided in the present disclosure, the linewidth of the second main electrode and the linewidth of the third main electrode are approximately the same as the linewidth of the first main electrode.
[0041] The linewidth of the first common branch electrode and the linewidth of the third branch electrode are approximately the same as the linewidth of the first branch electrode.
[0042] The linewidth of the second common branch electrode and the linewidth of the fourth branch electrode are approximately the same as the linewidth of the second branch electrode.
[0043] The spacing between adjacent third branch electrodes, the spacing between the first common branch electrode and adjacent first branch electrodes, and the spacing between the first common branch electrode and adjacent third branch electrodes are approximately equal to the spacing between adjacent first branch electrodes.
[0044] The spacing between adjacent fourth branch electrodes, the spacing between the second common branch electrode and adjacent second branch electrodes, and the spacing between the second common branch electrode and adjacent fourth branch electrodes are approximately equal to the spacing between adjacent second branch electrodes.
[0045] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first branch electrodes and the plurality of second branch electrodes are symmetrical about the central axis of the electrodes along the second direction.
[0046] In some embodiments, in the array substrate provided in the present disclosure, the angle between the first branch electrode and the central axis of the electrode along the second direction is not equal to the angle between the second branch electrode and the central axis of the electrode along the second direction.
[0047] In some embodiments, in the array substrate provided in the present disclosure, the angle between the first branch electrode and the central axis of the electrode along the second direction, and the angle between the second branch electrode and the central axis of the electrode along the second direction, are both 5° to 15°.
[0048] In some embodiments, in the array substrate provided in the present disclosure, the linewidth of the first branch electrode is approximately the same as the linewidth of the second branch electrode, and the spacing between adjacent first branch electrodes is approximately the same as the spacing between adjacent second branch electrodes.
[0049] In some embodiments, in the array substrate provided in the present disclosure, the linewidth of the first main electrode is 1.5 μm to 4 μm, the linewidth of the first branch electrode is 2 μm to 6 μm, and the spacing between adjacent first branch electrodes is 2 μm to 6 μm.
[0050] In some embodiments, the array substrate provided in this disclosure includes gate lines and data lines arranged in a cross-layer configuration;
[0051] The ratio of the size of the electrode in the direction of the gate line extension to the size of the electrode in the direction of the data line extension is (0.8 to 1.2):1, or 1:(0.8 to 1.2).
[0052] In some embodiments, the array substrate provided in the present disclosure includes gate lines and data lines arranged in a cross-layer configuration, wherein the second direction is the extension direction of the gate lines or the extension direction of the data lines.
[0053] In some embodiments, in the array substrate provided in the present disclosure, the electrode is a pixel electrode.
[0054] On the other hand, embodiments of this disclosure provide an array substrate, including:
[0055] Substrate;
[0056] Multiple electrodes are located on the substrate; the electrodes include a first main electrode, multiple first branch electrodes, and multiple second branch electrodes; wherein...
[0057] The plurality of first branch electrodes extend along a first direction and are arranged along a second direction;
[0058] The plurality of second branch electrodes extend along a third direction and are arranged along the second direction, wherein the first direction, the second direction, and the third direction intersect.
[0059] The first main electrode is located between the columns containing the plurality of first branch electrodes and the columns containing the plurality of second branch electrodes, and the first main electrode is connected to the plurality of first branch electrodes and the plurality of second branch electrodes;
[0060] The angle between the first branch electrode and the central axis of the electrode along the second direction is not equal to the angle between the second branch electrode and the central axis of the electrode along the second direction.
[0061] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.
[0062] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel, the backlight module including red LEDs, green LEDs and blue LEDs. Attached Figure Description
[0063] Figure 1 is a schematic diagram of a "convex" electrode provided in an embodiment of this disclosure;
[0064] Figure 2 is a layout of the electrode region shown in Figure 1, defined by gate lines and data lines;
[0065] Figure 3 shows the layout of the gate metal layer in Figure 2;
[0066] Figure 4 shows the layout of the active layer in Figure 2;
[0067] Figure 5 shows the layout of the source and drain metal layers in Figure 2;
[0068] Figure 6 is the layout of the via layer in Figure 2;
[0069] Figure 7 is the layout of the common electrode layer in Figure 2;
[0070] Figure 8 is the layout of the electrode layer in Figure 2;
[0071] Figure 9 is a schematic structural diagram of the "double horse-shaped" electrode provided by the embodiment of the present disclosure;
[0072] Figure 10 is a schematic structural diagram of the "卍-shaped" electrode provided by the embodiment of the present disclosure;
[0073] Figure 11 is a schematic structural diagram of the "middle-shaped" electrode provided by the embodiment of the present disclosure;
[0074] Figure 12 is another schematic structural diagram of the "convex-shaped" electrode provided by the embodiment of the present disclosure;
[0075] Figure 13 is another schematic structural diagram of the "convex-shaped" electrode provided by the embodiment of the present disclosure;
[0076] Figure 14 is a schematic structural diagram of the "丰-shaped" electrode provided by the embodiment of the present disclosure;
[0077] Figure 15 is a schematic structural diagram of the "fishbone-shaped" electrode provided by the embodiment of the present disclosure;
[0078] Figure 16 is another schematic structural diagram of the "丰-shaped" electrode provided by the embodiment of the present disclosure;
[0079] Figure 17 is a schematic structural diagram of the display panel provided by the embodiment of the present disclosure;
[0080] Figure 18 is a schematic structural diagram of the display device provided by the embodiment of the present disclosure. Detailed implementation manners
[0081] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the following description will be made in conjunction with the accompanying drawings of the embodiments of this disclosure. For clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shapes in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shapes of the regions or reflect true proportions, but are only intended to illustrate the content of this disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0082] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0083] In the following description, when an element or layer is referred to as "on" another element or layer or "connected" to another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" another element or layer" or "directly connected" to another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items. The various embodiments of this disclosure may be combined and integrated with each other without conflict.
[0084] A Field-Sequential Color LCD has a three-color backlight source that is lit separately in sequence. The liquid crystal screen controls the color and brightness of the transmitted light according to the displayed information to achieve additive color mixing in time. It does not require a color filter film, and the number of pixels becomes 1 / 3 of that of a conventional transmissive LCD, making it easier to achieve high-capacity and large-screen displays. It may become the development trend of LCDs, and both its color gamut and brightness far exceed those of conventional LCD TVs. The delicate skin tones, moist green leaves, and vast landscapes in the picture can create an immersive feeling. The panel production of the colorless film technology will bring a revolutionary impact and is also the most important application of LED backlight in the LCD field. In addition to cost reduction, the simplification of the manufacturing process also plays an important role in reducing related costs (such as production and labor) and improving production efficiency.
[0085] In some embodiments, the pixels of a Field-Sequential Color LCD can be formed by combining the RGB sub-pixels of a conventional LCD including a color film. However, the inventors found that in this pixel structure, the slit electrodes are surrounded by frames on all sides, resulting in a large dark field at the edge of the pixel structure, poor light efficiency, and due to the relatively large size of a single pixel, the single-strip electrode of the slit electrode contained in the pixel is too long, and the risk of disconnection is high.
[0086] To at least improve the above technical problems, the embodiments of the present disclosure provide an array substrate. FIG. 1 is a schematic structural diagram of a "convex-shaped" electrode provided by the embodiments of the present disclosure. FIG. 2 is a layout of the electrode region shown in FIG. 1 defined by gate lines and data lines. FIG. 3 is a layout of the gate metal layer in FIG. 2. FIG. 4 is a layout of the active layer in FIG. 2. FIG. 5 is a layout of the source-drain metal layer in FIG. 2. FIG. 6 is a layout of the via layer in FIG. 2. FIG. 7 is a layout of the common electrode layer in FIG. 2. FIG. 8 is a layout of the electrode layer in FIG. 2. FIG. 9 is a schematic structural diagram of a "double-horse-shaped" electrode provided by the embodiments of the present disclosure. FIG. 10 is a schematic structural diagram of a "wan-shaped" electrode provided by the embodiments of the present disclosure. FIG. 11 is a schematic structural diagram of a "middle-shaped" electrode provided by the embodiments of the present disclosure. FIG. 12 is another schematic structural diagram of a "convex-shaped" electrode provided by the embodiments of the present disclosure. FIG. 13 is another schematic structural diagram of a "convex-shaped" electrode provided by the embodiments of the present disclosure. As shown in FIGS. 1, 8 to 13, an array substrate provided by the embodiments of the present disclosure may include:
[0087] A substrate 101, optionally, the substrate 101 is a substrate that allows visible light to pass through, such as made of glass, quartz, plastic, etc.
[0088] Multiple electrodes 102 are located on the substrate 101, for example, multiple electrodes 102 are arranged in an array on the substrate 101; the material of the electrodes 102 may include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO).
[0089] In some embodiments, electrode 102 may include a first main electrode M1, a second main electrode M2, a plurality of first branch electrodes B1, a plurality of second branch electrodes B2, and a plurality of third branch electrodes B3; wherein, the plurality of first branch electrodes B1 extend along a first direction D and are arranged along a second direction Y, optionally, the second direction Y is the extension direction of the gate line 108 or the extension direction of the data line 104; the plurality of second branch electrodes B2 extend along a third direction D' and are arranged along the second direction Y, the first direction D, the second direction Y, and the third direction D' intersect; the plurality of third branch electrodes B3 extend along the first direction D and are arranged along the second direction Y on one side of the plurality of first branch electrodes B1; the first main electrode M1 is located between the column where the plurality of first branch electrodes B1 are located and the column where the plurality of second branch electrodes B2 are located, and the first main electrode M1 is connected to the plurality of first branch electrodes B1 and the plurality of second branch electrodes B2; the second main electrode M2 is located on the side of the plurality of third branch electrodes B3 away from the first main electrode M1, and the second main electrode M2 is connected to the plurality of third branch electrodes B3.
[0090] In the array substrate provided in the embodiments of this disclosure, the longer strip electrodes in the relevant slit electrodes are segmented into first branch electrodes B1 and second branch electrodes B2, thereby reducing the length and lowering the risk of wire breakage. The third branch electrode B3, which is in the same row as the first branch electrode B1, is also shorter, and the risk of wire breakage is also lower. At the same time, this disclosure provides a first main electrode M1 between the column where the first branch electrode B1 is located and the column where the second branch electrode B2 is located, and uses the first main electrode M1 to connect the first branch electrode B1 and the second branch electrode B2, thereby ensuring the electrical connection relationship between the first branch electrode B1 and the second branch electrode B2. Therefore, it is not necessary to set a frame around the first branch electrode B1 and the second branch electrode B2 to realize the electrical connection between the first branch electrode B1 and the second branch electrode B2, thereby reducing the edge dark field caused by the frame and improving the light efficiency.
[0091] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG1, FIG8 to FIG13, may further include a first common branch electrode S1, a second common branch electrode S2, a plurality of third branch electrodes B3, and a plurality of fourth branch electrodes B4; wherein, the first common branch electrode S1 extends along a first direction D between the plurality of first branch electrodes B1 and the plurality of third branch electrodes B3, and the first common branch electrode S1 is connected between a first main electrode M1 and a second main electrode M2; the second common branch electrode S2 extends along a third direction D', and the second common branch electrode S2 is connected between the first main electrode M1 and the third main electrode M3; on the side of the second common branch electrode S2 away from the plurality of second branch electrodes B2, the plurality of fourth branch electrodes B4 extend along a third direction D' and are arranged along a second direction Y; on the side away from the electrode 102 along the central axis MN of the second direction Y, the plurality of fourth branch electrodes B4 are connected to the third main electrode M3.
[0092] The introduction of the first main electrode M1 can cause electric field disturbances in its vicinity, resulting in dark lines. This disclosure addresses this by providing a second main electrode M2 and / or a third main electrode M3 at a portion of the edge of electrode 102. This effectively balances the small dark fields at the edges and in the center, ensuring good overall pixel light efficiency. Compared to LCDs with color filters, this disclosure improves overall transmittance by 5% to 20%. Furthermore, the third branch electrode B3 connected to the second main electrode M2 and the fourth branch electrode B4 connected to the third main electrode M3 are disconnected in the middle of the pixel. Therefore, the lengths of the third branch electrode B3 and the fourth branch electrode B4 are smaller than those of the strip electrodes in the relevant slit electrodes, reducing the risk of line breakage.
[0093] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 1, 8, and 10 to 13, a plurality of first branch electrodes B1 and a plurality of second branch electrodes B2 can be connected to the same first main electrode M1. Alternatively, as shown in Figure 9, a plurality of first branch electrodes B1 and a plurality of second branch electrodes B2 can also be connected to different first main electrodes M1. Optionally, in Figure 10, the first main electrode M1 connected to the plurality of first branch electrodes B1 and the first main electrode M1 connected to the plurality of second branch electrodes B2 are staggered along a fourth direction X. The fourth direction X can be substantially perpendicular to the second direction Y. Optionally, the second direction Y is the extension direction of the data line 104 and the fourth direction X is the extension direction of the gate line 108, or the second direction Y is the extension direction of the gate line 108 and the fourth direction X is the extension direction of the data line 104. Due to limitations in process conditions or the influence of other factors such as measurement, the "approximately perpendicular" of this disclosure may be exactly perpendicular or may have some deviation (e.g., a deviation of ±5%). Therefore, as long as the "approximately perpendicular" relationship between related features meets the allowable error, it falls within the protection scope of this disclosure.
[0094] Referring to Figures 1, 8, and 10 to 13, multiple first branch electrodes B1, multiple second branch electrodes B2, a first main electrode M1, a first common branch electrode S1, a second main electrode M2, multiple third branch electrodes B3, a second common branch electrode S2, a third main electrode M3, and multiple fourth branch electrodes B4 constitute an electrically conductive electrode 102. To ensure that each part of the electrode 102 shown in Figure 9 is electrically conductive while minimizing the risk of wire breakage, this disclosure connects the third branch electrode B3, which is furthest from the first common branch electrode S1, to the fourth branch electrode B4, which is furthest from the second common branch electrode S2. Since Figures 1, 8, and 11 to 13 are electrically conductive electrodes 102, the third branch electrode B3, which is farthest from the first common branch electrode S1, and the fourth branch electrode B4, which is farthest from the second common branch electrode S2, may or may not be connected; this disclosure does not impose any limitations on this. In Figure 10, the third branch electrode B3 and the fourth branch electrode B4 are offset along the second direction Y, making them difficult to connect.
[0095] In some embodiments, in the array substrate provided in the embodiments of this disclosure, as shown in Figures 1, 8, 9, and 11 to 13, a plurality of first branch electrodes B1 and a plurality of second branch electrodes B2 are arranged along the fourth direction X, a plurality of third branch electrodes B3 and a plurality of fourth branch electrodes B4 are arranged along the fourth direction X, and the first main electrode M1 is a linear electrode between the plurality of first branch electrodes B1 and the plurality of second branch electrodes B2. In other embodiments, as shown in Figure 10, a plurality of first branch electrodes B1 and a plurality of fourth branch electrodes B4 are arranged along the fourth direction X, a plurality of third branch electrodes B3 and a plurality of second branch electrodes B2 are arranged along the fourth direction X, the plurality of first branch electrodes B1 and the plurality of third branch electrodes B3 constitute one column of branch electrodes, the plurality of second branch electrodes B2 and the plurality of fourth branch electrodes B4 constitute another column of branch electrodes, and the first main electrode M1 is a zigzag electrode located between the two columns of branch electrodes.
[0096] In some embodiments, as shown in Figures 1 and 8 to 12, the first common branch electrode S1 of this disclosure can be an electrode structure with a linewidth approximately the same as that of the first branch electrode B1, and the second common branch electrode S2 can also be an electrode structure with a linewidth approximately the same as that of the second branch electrode B2. In other embodiments, as shown in Figure 13, the first common branch electrode S1 of this disclosure can also be two adjacent electrode structures with a linewidth approximately the same as that of the first branch electrode B1, and the two first common branch electrodes S1, together with the first main electrode M1 and the second main electrode M2, form a closed loop structure; in some embodiments, the gap between the two first common branch electrodes S1 shown in Figure 13 can be filled with electrode material to form a thicker branch electrode structure to prevent wire breakage. Referring again to Figure 13, the second common branch electrode S2 of this disclosure can be two adjacent electrode structures with approximately the same linewidth as the second branch electrode B2, and the two second common branch electrodes S2, together with the first main electrode M1 and the third main electrode M3, form a closed loop structure. In some embodiments, the gap between the two second common branch electrodes S2 shown in Figure 13 can be filled with electrode material to form a thicker branch electrode structure to prevent wire breakage. Due to limitations in process conditions or the influence of other factors such as measurement, the "approximately the same" in this disclosure may be exactly the same, or there may be some deviation (e.g., a deviation of ±10%). Therefore, as long as the "approximately the same" relationship between related features meets the allowable error, it falls within the protection scope of this disclosure.
[0097] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 2 to 8, may further include a transistor 103. Optionally, the electrode 102 is a pixel electrode, and the electrode 102 further includes a block electrode P located at the end of the second main electrode M2 away from the first common branch electrode S1. The block electrode P is electrically connected to the first electrode d of the transistor 103. Specifically, the block electrode P and the first electrode d of the transistor 103 are electrically connected through a first via V1 penetrating the insulating layer between them. The block electrode P covers the first via V1, resulting in a larger contact area between the electrode 102 and the transistor 103, and a better electrical connection effect.
[0098] It should be noted that the electrode 102 in this disclosure can also be a common electrode, and when the electrode 102 is a common electrode, a connection structure is provided between adjacent common electrodes so that the common electrodes are connected into a whole. This disclosure illustrates the example of the electrode 102 being a pixel electrode.
[0099] In some embodiments, as shown in Figures 2 to 8, the array substrate provided in this disclosure may further include multiple data lines 104, and the second electrode s of transistor 103 may be electrically connected to the data lines 104. Optionally, the second electrode s of transistor 103 is "m-shaped," with the opening of the "m-shaped" electrode facing the electrode 102 corresponding to transistor 103. The first electrode d of transistor 101 includes two sub-electrodes extending from the "m-shaped" opening, and the two sub-electrodes converge at the block electrode P. Transistor 103 with this structure has a larger current output capability, which is beneficial for improving pixel charging rate.
[0100] In some embodiments, the array substrate provided in the present disclosure, as shown in Figures 2 to 8, may further include multiple common electrode lines 105, multiple transition electrodes 106, and multiple common electrodes 107. Optionally, the common electrode lines 105 and gate lines 108 are disposed in the same layer and made of the same material. The linewidths of the common electrode lines 105 and gate lines 108 decrease at their intersections with the data lines 104, and the linewidths of the data lines 104 also decrease at their intersections with the common electrode lines 105 and gate lines 108, in order to reduce the parasitic capacitance between the data lines 104 and the common electrode lines 105 and gate lines 108. In some embodiments, the orthographic projection of the common electrode line 105 on the substrate 101 overlaps with the orthographic projection of the edge of the electrode 102 where the end of the first main electrode M1 is located on the substrate 101. The transfer electrode 106 is disposed on the same layer and made of the same material as the electrode 102. The orthographic projection of the transfer electrode 106 on the substrate 101 extends along the data line 104 and crosses the orthographic projection of the gate line 108 on the substrate 101. The electrode 102 may include a clearance structure C located at the corner of the side where the third main electrode M3 is located. The orthographic projection of the common electrode 107 on the substrate 101 can cover the slit of the electrode 102 and the orthographic projection of the clearance structure C on the substrate 101, and does not overlap with the orthographic projection of the block electrode P on the substrate 101. The common electrode line 105 can be electrically connected to the common electrode 107 through the transfer electrode 106 in the area where the clearance structure C is located, thereby improving the uniformity of the common voltage.
[0101] In some embodiments, as shown in Figures 2 to 8, the common electrode 107 and the transition electrode 106 are electrically connected through a second via V2 penetrating the insulating layer between them, and the common electrode line 105 and the transition electrode 106 are electrically connected through a third via V3 penetrating the insulating layer between them. Additionally, this disclosure may provide a connecting electrode 109 at the location of the second via V2 in the layer where the gate line 108 is located, so that the common electrode 107, the connecting electrode 109, and the transition electrode 106 are sequentially electrically connected, thereby reducing the contact resistance between the transition electrode 106 and the common electrode 107 and enhancing the electrical connection effect. The common electrode line 105 may have a widened portion 106' provided at the third via V3 to improve its electrical connection with the transition electrode 106.
[0102] In some embodiments, as shown in FIG11, the array substrate provided in this disclosure may further include a fourth main electrode M4, a third common branch electrode S3, a fourth common branch electrode S4, a plurality of fifth branch electrodes B5, and a plurality of sixth branch electrodes B6; wherein, the third common branch electrode S3 may extend along a first direction D on the side of the plurality of third branch electrodes B3 away from the first common branch electrode S1, and the third common branch electrode S3 is connected between the second main electrode M2 and the fourth main electrode M4; on the side of the third common branch electrode S3 away from the plurality of third branch electrodes B3, the plurality of fifth branch electrodes B5 extend along a first direction D. The electrodes extend in direction D and are arranged along the second direction Y; the fourth common branch electrode S4 extends along the third direction D' on the side of the plurality of fourth branch electrodes B4 away from the second common branch electrode S2, and the fourth common branch electrode S4 is connected between the third main electrode M3 and the fourth main electrode M4; on the side of the fourth common branch electrode S4 away from the plurality of fourth branch electrodes B4, the plurality of sixth branch electrodes B6 extend along the third direction D' and are arranged along the second direction Y; the fourth main electrode M4 is located between the plurality of fifth branch electrodes B5 and the plurality of sixth branch electrodes B6, and the plurality of fifth branch electrodes B5 are electrically connected to the plurality of sixth branch electrodes B6 through the fourth main electrode M4. This allows for a smaller edge dark field and a smaller middle dark field, achieving ultra-high transmittance, while also reducing the risk of line breakage.
[0103] In some embodiments, in the array substrate provided in the present disclosure, in order to achieve better light efficiency and reduce the risk of line breakage, the linewidth of the second main electrode M2, the linewidth of the third main electrode M3, and the linewidth of the fourth main electrode M4 can be set to be approximately the same as the linewidth of the first main electrode M1, for example, 1.5μm to 4μm, specifically 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, etc. The linewidths of the first common branch electrode S1, the second common branch electrode S2, the third common branch electrode S3, the fourth common branch electrode S4, the second branch electrode B2, the third branch electrode B3, the fourth branch electrode B4, the fifth branch electrode B5, and the sixth branch electrode B6 are approximately the same as the linewidth of the first branch electrode B1, for example, 2μm to 6μm, specifically 2μm, 3μm, 4μm, 5μm, 6μm, etc. The spacing between adjacent second branch electrodes B2, adjacent third branch electrodes B3, adjacent fourth branch electrodes B4, adjacent fifth branch electrodes B5, adjacent sixth branch electrodes B6, the spacing between the first common branch electrode S1 and adjacent first branch electrode B1, the spacing between the first common branch electrode S1 and adjacent third branch electrode B3, the spacing between the second common branch electrode S2 and adjacent second branch electrode B2, the spacing between the second common branch electrode S2 and adjacent fourth branch electrode B4, the spacing between the third common branch electrode S3 and adjacent third branch electrode B3, the spacing between the third common branch electrode S3 and adjacent fifth branch electrode B5, the spacing between the fourth common branch electrode S4 and adjacent fourth branch electrode B4, and the spacing between the fourth common branch electrode S4 and adjacent sixth branch electrode B6 are approximately equal to the spacing between adjacent first branch electrodes B1, for example, 2μm to 6μm, specifically 2μm, 3μm, 4μm, 5μm, 6μm, etc.
[0104] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1, FIG8 to FIG11 and FIG13, in order to reduce the risk of left-right color shift and achieve true color, the electrode 102 of the present disclosure can be a left-right symmetrical structure. Specifically, in FIG1, FIG8, FIG9 and FIG13, a plurality of first branch electrodes B1 and a plurality of second branch electrodes B2 are symmetrical about the central axis MN of the electrode 102 along the second direction Y, and a plurality of third branch electrodes B3 and a plurality of fourth branch electrodes B4 are symmetrical about the central axis MN; in FIG10, a plurality of first branch electrodes B1 and a plurality of fourth branch electrodes B4 are symmetrical about the central axis MN, and a plurality of third branch electrodes B3 and a plurality of second branch electrodes B2 are symmetrical about the central axis MN; in FIG11, a plurality of first branch electrodes B1 and a plurality of second branch electrodes B2 are symmetrical about the central axis MN, a plurality of third branch electrodes B3 and a plurality of fourth branch electrodes B4 are symmetrical about the central axis MN, and a plurality of fifth branch electrodes B5 and a plurality of sixth branch electrodes B6 are symmetrical about the central axis MN.
[0105] In field-sequential color LCD products, since a color image is sequentially divided into three RGB frames over time, and these frames are then switched at high speed to form a single color image, the key to achieving field-sequential display technology lies in significantly improving the response speed of the existing LCD. Considering gray-to-gray response time (GTG) optimization, this disclosure allows the left and right branch electrodes to be configured as an asymmetrical structure, such that the angle between the first branch electrode B1 and electrode 102 along the central axis MN of the second direction Y is not equal to the angle between the second branch electrode B2 and electrode 102 along the central axis MN of the second direction Y. In some embodiments, the angles between the first branch electrode B1 and the central axis MN, and the angles between the second branch electrode B2 and the central axis MN, are both 5° to 15°. For example, the angle between the first branch electrode B1 and the central axis MN is 7°, and the angle between the second branch electrode B2 and the central axis MN is 11°. Because the branch electrodes extending in the range of 5° to 15° increase the component of the electric field acting on the liquid crystal along the liquid crystal deflection direction, the liquid crystal experiences increased electric field force, and the deflection speeds up, thus reducing the GTG (Gross Transmission Gaussian Gap) and achieving an ultra-fast response. Compared to LCDs with color filters, the response speed of this disclosure is improved by 10% to 20%. After the LCD field sequence response speed is improved, the backlight duty cycle is increased, the overall brightness is improved, and the overall power consumption can be greatly reduced.
[0106] In some embodiments of the present disclosure, in the array substrate provided above, unlike the conventional pixel dimension ratio of 1 / 3 in the extension direction of the gate line 108 to the extension direction of the data line 104, the dimension ratio of the electrode 102 in the extension direction of the gate line 108 to the extension direction of the data line 104 can be (0.8 to 1.2):1, or 1:(0.8 to 1.2), for example, 1:1.
[0107] In some embodiments, FIG. 14 shows a schematic structural diagram of the "丰字型" electrode provided by an embodiment of the present disclosure. As can be seen from FIG. 14, the electrode 102 in the embodiment of the present disclosure may only include a first main electrode M1, a plurality of first branch electrodes B1 and a plurality of second branch electrodes B2 separated on the left and right sides of the first main electrode M1, and the extension direction of the first branch electrode B1 (for example, 7°) may be different from the extension direction of the second branch electrode B2 (for example, 11°). Of course, in some embodiments, the plurality of first branch electrodes B1 and the plurality of second branch electrodes B2 may also be symmetrically arranged in the electrode 102, such as the "fishbone type" structure symmetrically arranged up and down shown in FIG. 15, and the "丰字型" structure symmetrically arranged left and right shown in FIG. 16.
[0108] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel. As shown in FIG. 17, it includes an array substrate 001 and a counter substrate 002 disposed opposite to each other, wherein the array substrate 001 is the above-mentioned array substrate 001 provided by an embodiment of the present disclosure. Since the principle of solving problems of this display panel is similar to that of the above-mentioned array substrate, therefore, the implementation of this display panel provided by an embodiment of the present disclosure can refer to the implementation of the above-mentioned array substrate provided by an embodiment of the present disclosure, and the repeated parts will not be elaborated here.
[0109] In some embodiments, in the display panel provided by an embodiment of the present disclosure, as shown in FIG. 17, it may further include a liquid crystal layer 003 between the array substrate and the counter substrate, a first polarizer 004 on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 on the side of the counter substrate 002 away from the array substrate 001, and the polarization directions of the first polarizer 004 and the second polarizer 005 are perpendicular to each other. Other essential components in the display panel are understood to be possessed by those of ordinary skill in the art, and will not be elaborated here, nor should it be regarded as a limitation to the present disclosure.
[0110] Based on the same inventive concept, an embodiment of the present disclosure provides a display device. As shown in FIG. 18, it includes the above-mentioned display panel PNL provided by an embodiment of the present disclosure, and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU includes red light beads, green light beads and blue light beads, and the red light beads, green light beads and blue light beads are sequentially lit in different time periods of one frame time to achieve the display of a frame of color picture. In some embodiments, the backlight module BLU is a side-entry type backlight module, and the side-entry type backlight module may further include a reflective sheet, a light guide plate, a diffusion sheet, a prism group, etc. stacked, and the light bar formed by the red light beads, green light beads and blue light beads may be located on one side in the thickness direction of the light guide plate. The red light beads, green light beads and blue light beads may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).
[0111] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.
[0112] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0113] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.
Claims
1. An array substrate, wherein, include: Substrate; Multiple electrodes are located on the substrate; the electrodes include a first main electrode, a second main electrode, multiple first branch electrodes, multiple second branch electrodes, and multiple third branch electrodes; wherein... The plurality of first branch electrodes extend along a first direction and are arranged along a second direction; The plurality of second branch electrodes extend along a third direction and are arranged along the second direction, wherein the first direction, the second direction, and the third direction intersect. The plurality of third branch electrodes extend along the first direction and are arranged along the second direction on one side of the plurality of first branch electrodes; The first main electrode is located between the columns containing the plurality of first branch electrodes and the columns containing the plurality of second branch electrodes, and the first main electrode is connected to the plurality of first branch electrodes and the plurality of second branch electrodes; The second main electrode is located on the side of the plurality of third branch electrodes away from the first main electrode, and the second main electrode is connected to the plurality of third branch electrodes.
2. The array substrate as claimed in claim 1, wherein, The electrode further includes a first common branch electrode, which extends along the first direction between the plurality of first branch electrodes and the plurality of third branch electrodes, and is connected between the first main electrode and the second main electrode.
3. The array substrate as described in claim 2, wherein, The electrode also includes a third main electrode and multiple fourth branch electrodes; wherein... The plurality of fourth branch electrodes extend along the third direction on one side of the plurality of second branch electrodes and are arranged along the second direction; The third main electrode is located on the side of the plurality of fourth branch electrodes away from the first main electrode, and the third main electrode is connected to the plurality of fourth branch electrodes.
4. The array substrate as claimed in claim 3, wherein, The electrode further includes a second common branch electrode, which extends along the third direction between the plurality of second branch electrodes and the plurality of fourth branch electrodes, and is connected between the first main electrode and the third main electrode.
5. The array substrate as claimed in claim 4, wherein, The plurality of first branch electrodes and the plurality of second branch electrodes are connected to the same first main electrode.
6. The array substrate as claimed in claim 5, wherein, The plurality of first branch electrodes and the plurality of second branch electrodes are arranged along a fourth direction, and the plurality of third branch electrodes and the plurality of fourth branch electrodes are arranged along the fourth direction, which is substantially perpendicular to the second direction.
7. The array substrate as claimed in claim 6, wherein, It also includes transistors; The electrode also includes a block electrode located at the end of the second main electrode away from the first common branch electrode, and the block electrode is electrically connected to the first electrode of the transistor.
8. The array substrate as claimed in claim 7, wherein, It also includes multiple data lines, with the second terminal of the transistor electrically connected to the data lines; The second electrode of the transistor is "m-shaped", with the opening of the "m-shaped" electrode facing the electrode corresponding to the transistor. The first electrode of the transistor includes two sub-electrodes extending from the "m-shaped" opening, and the two sub-electrodes converge at the block electrode.
9. The array substrate according to any one of claims 6 to 8, wherein, It also includes multiple common electrode lines, multiple adapter electrodes, and multiple common electrodes; The electrode includes a clearance structure located at the corner of the side where the third main electrode is located, and the common electrode line is electrically connected to the common electrode through the adapter electrode within the area where the clearance structure is located.
10. The array substrate as claimed in claim 6, wherein, The electrode further includes a fourth main electrode, a third common branch electrode, a fourth common branch electrode, multiple fifth branch electrodes, and multiple sixth branch electrodes; wherein... The third common branch electrode extends along the first direction on the side of the plurality of third branch electrodes away from the first common branch electrode, and the third common branch electrode is connected to the second main... Between the dry electrode and the fourth main electrode; On the side of the third common branch electrode away from the plurality of third branch electrodes, the plurality of fifth branch electrodes extend along the first direction and are arranged along the second direction; The fourth common branch electrode extends along the third direction on the side of the plurality of fourth branch electrodes away from the second common branch electrode, and the fourth common branch electrode is connected between the third main electrode and the fourth main electrode. On the side of the fourth common branch electrode away from the plurality of fourth branch electrodes, the plurality of sixth branch electrodes extend along the third direction and are arranged along the second direction; The fourth main electrode is located between the plurality of fifth branch electrodes and the plurality of sixth branch electrodes, and the plurality of fifth branch electrodes are electrically connected to the plurality of sixth branch electrodes through the fourth main electrode.
11. The array substrate as claimed in claim 10, wherein, The linewidth of the fourth main electrode is approximately the same as that of the first main electrode. The linewidth of the third common branch electrode and the linewidth of the fifth branch electrode are approximately the same as the linewidth of the first branch electrode. The linewidth of the fourth common branch electrode and the linewidth of the sixth branch electrode are approximately the same as the linewidth of the second branch electrode. The spacing between adjacent fifth branch electrodes, the spacing between the third common branch electrode and adjacent third branch electrodes, and the spacing between the third common branch electrode and adjacent fifth branch electrodes are approximately equal to the spacing between adjacent first branch electrodes; The spacing between adjacent sixth branch electrodes, the spacing between the fourth common branch electrode and adjacent fourth branch electrodes, and the spacing between the fourth common branch electrode and adjacent sixth branch electrodes are approximately equal to the spacing between adjacent second branch electrodes.
12. The array substrate as claimed in claim 5, wherein, The plurality of first branch electrodes and the plurality of fourth branch electrodes are arranged along the fourth direction, the plurality of third branch electrodes and the plurality of second branch electrodes are arranged along the fourth direction, the first main electrode connected to the plurality of first branch electrodes and the first main electrode connected to the plurality of second branch electrodes are staggered along the fourth direction, and the fourth direction is approximately perpendicular to the second direction.
13. The array substrate as claimed in claim 4, wherein, The plurality of first branch electrodes and the plurality of second branch electrodes are connected to different first main electrodes; The third branch electrode, which is furthest from the first common branch electrode, is connected to the fourth branch electrode, which is furthest from the second common branch electrode.
14. The array substrate according to any one of claims 4 to 13, wherein, The linewidth of the second main electrode and the linewidth of the third main electrode are approximately the same as the linewidth of the first main electrode. The linewidth of the first common branch electrode and the linewidth of the third branch electrode are approximately the same as the linewidth of the first branch electrode. The linewidth of the second common branch electrode and the linewidth of the fourth branch electrode are approximately the same as the linewidth of the second branch electrode. The spacing between adjacent third branch electrodes, the spacing between the first common branch electrode and adjacent first branch electrodes, and the spacing between the first common branch electrode and adjacent third branch electrodes are approximately equal to the spacing between adjacent first branch electrodes. The spacing between adjacent fourth branch electrodes, the spacing between the second common branch electrode and adjacent second branch electrodes, and the spacing between the second common branch electrode and adjacent fourth branch electrodes are approximately equal to the spacing between adjacent second branch electrodes.
15. The array substrate according to any one of claims 1 to 14, wherein, The plurality of first branch electrodes and the plurality of second branch electrodes are symmetrical about the central axis of the electrodes along the second direction.
16. The array substrate according to any one of claims 1 to 14, wherein, The angle between the first branch electrode and the central axis of the electrode along the second direction is not equal to the angle between the second branch electrode and the central axis of the electrode along the second direction.
17. The array substrate as claimed in claim 15 or 16, wherein, The angle between the first branch electrode and the central axis of the electrode along the second direction, and the angle between the second branch electrode and the central axis of the electrode along the second direction, are both 5° to 15°.
18. The array substrate according to any one of claims 1 to 17, wherein, The linewidth of the first branch electrode is approximately the same as that of the second branch electrode, and the spacing between adjacent first branch electrodes is approximately the same as that between adjacent second branch electrodes.
19. The array substrate as claimed in claim 18, wherein, The linewidth of the first main electrode is 1.5 μm to 4 μm, the linewidth of the first branch electrode is 2 μm to 6 μm, and the spacing between adjacent first branch electrodes is 2 μm to 6 μm.
20. The array substrate according to any one of claims 1 to 19, wherein, This includes gate lines and data lines that are arranged in a cross-layer configuration; The ratio of the size of the electrode in the direction of the gate line extension to the size of the electrode in the direction of the data line extension is (0.8 to 1.2):1, or 1:(0.8 to 1.2).
21. The array substrate according to any one of claims 1 to 20, wherein, It includes gate lines and data lines arranged in different layers, and the second direction is the extension direction of the gate lines or the extension direction of the data lines.
22. The array substrate according to any one of claims 1 to 21, wherein, The electrode is a pixel electrode.
23. An array substrate, wherein, include: Substrate; Multiple electrodes are located on the substrate; the electrodes include a first main electrode, multiple first branch electrodes, and multiple second branch electrodes; wherein... The plurality of first branch electrodes extend along a first direction and are arranged along a second direction; The plurality of second branch electrodes extend along a third direction and are arranged along the second direction, wherein the first direction, the second direction, and the third direction intersect. The first main electrode is located between the columns containing the plurality of first branch electrodes and the columns containing the plurality of second branch electrodes, and the first main electrode is connected to the plurality of first branch electrodes and the plurality of second branch electrodes; The angle between the first branch electrode and the central axis of the electrode along the second direction is not equal to the angle between the first branch electrode and the central axis of the electrode along the second direction. The angle between the second branch electrode and the central axis of the electrode along the second direction.
24. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 23.
25. A display device, wherein, The display panel as described in claim 24, and a backlight module located on the light-incident side of the display panel, the backlight module comprising red LEDs, green LEDs and blue LEDs.