Method for preparing TBC solar cell having polished isolation region structure

Abstract

The present invention relates to the field of solar cells, and discloses a method for preparing a TBC solar cell having a polished isolation region structure. Firstly, in the present invention, a conventional isolation region structure having a pyramid suede is improved into a polished isolation region structure protruding from the back of a silicon wafer, which can increase the reflection of incident light in a silicon substrate, thus improving the Isc of the cell, and also, because the initial isolation region is protected by a mask layer and is subsequently not damaged by wet corrosion, and the height difference between the isolation region and the boron / phosphorus diffusion layer is small, which is conducive to lateral transmission of carriers in the silicon substrate and improvement of FF. Secondly, in the present invention, by optimizing the process steps, the TBC solar cell can be obtained by depositing an intrinsic polysilicon layer once, which can effectively improve the performance and yield of the product and can also significantly reduce the production cost.

Description

Preparation method of TBC solar cell with polished isolation region structure TECHNICAL FIELD

[0001] The present application relates to the field of solar cells, in particular to a preparation method of TBC solar cell with polished isolation region structure. BACKGROUND

[0002] IBC solar cell is a cross-finger back contact cell, which has no metal grid line on the cell front surface, and the emitter and back field and corresponding positive and negative metal electrodes are integrated in the back surface of the cell in a cross-finger shape. This structure can avoid the shading of the metal grid electrode to the light, can fully utilize the incident light, reduce the optical loss, has higher short-circuit current, and thus effectively improves the photoelectric conversion efficiency of the cell. Among them, TBC solar cell is one of IBC solar cells.

[0003] In order to avoid short circuit, the n region (phosphorus diffusion region) and the p region (boron diffusion region) on the back surface of the TBC solar cell are both provided with an insulating isolation region. At present, the structure of the isolation region of the TBC solar cell is usually in a groove type (i.e. the height of the isolation region is lower than the phosphorus diffusion layer and the boron diffusion layer), and a pyramid texture is usually provided on the surface of the silicon wafer in the isolation region, as shown in Figure 9. The applicant found that the formation of the pyramid texture on the surface of the isolation region on the back surface of the silicon wafer is not conducive to increasing the reflection of the incident light in the silicon substrate, thereby limiting the I sc .

[0004] In addition, the current preparation of TBC solar cell usually needs to first deposit an intrinsic polysilicon layer on the back surface of the silicon wafer, then convert it into a boron diffusion layer through a boron diffusion process, then deposit an intrinsic polysilicon layer again, and then convert it into a phosphorus diffusion layer through a phosphorus diffusion process. The disadvantage of the above method is that in the process of depositing the intrinsic polysilicon layer twice, uneven thermal stress distribution is easy to occur, thereby causing the silicon wafer to warp, fragment, etc., which will significantly affect the performance and yield of the product. And depositing the intrinsic polysilicon layer twice will also greatly increase the consumption of special gas, thereby increasing the cost.

[0005] In summary, it is of great significance to further optimize the structure of the cell isolation region to further improve the I sc of the cell, and to simplify the preparation process of the cell to improve the performance of the cell, improve the yield, and reduce the cost. SUMMARY

[0006] In order to solve the above technical problems, the present application provides a preparation method of TBC solar cell with polished isolation region structure. First, the present application improves the conventional isolation region structure with a pyramid texture to a polished isolation region structure which protrudes from the back surface of the silicon wafer, which can increase the reflection of the incident light in the silicon substrate, thereby improving the I scMeanwhile, since the initial isolation region is protected by the mask layer, the subsequent isolation region is not damaged by wet etching, the height difference between the isolation region and the boron / phosphorus diffusion layer is small, which is beneficial to the lateral transmission of the carrier in the silicon substrate and improves the FF; secondly, the TBC solar cell is obtained by single deposition of the intrinsic polycrystalline silicon layer through the optimization of the process steps, the performance and yield of the product can be effectively improved, and the production cost is also significantly reduced.

[0007] The specific technical scheme of the present application is as follows: the present application provides a preparation method of a TBC solar cell with a polished isolation region structure, comprising the following steps: S1, double-sided polishing of a silicon wafer.

[0008] S2, forming a tunneling oxide layer, an intrinsic polycrystalline silicon layer and a mask layer on the back surface.

[0009] The purpose of setting the intrinsic polycrystalline silicon layer is to provide a basis for subsequent boron diffusion and phosphorus diffusion, and the purpose of setting the mask layer is to block the doping atoms from entering the intrinsic polycrystalline silicon layer at the bottom during the subsequent boron diffusion and phosphorus diffusion process.

[0010] S3, slotting to remove the mask layer of the boron diffusion design region.

[0011] The pre-designed boron diffusion region is slotted, and after removing the mask layer of the region, boron atoms can diffuse into the intrinsic polycrystalline silicon layer of the region during the subsequent boron diffusion process.

[0012] S4, alkali cleaning to remove the residual mask layer of the slotted region to fully expose the intrinsic polycrystalline silicon layer of the region.

[0013] S5, boron diffusion, so that the inner layer and the surface layer of the intrinsic polycrystalline silicon layer of the boron diffusion design region are respectively converted into a boron diffusion layer and a BSG layer.

[0014] During the above boron diffusion process, the S3 unslotted region can effectively block boron atoms from entering the intrinsic polycrystalline silicon layer due to the protection of the mask layer, and only the inner layer and the surface layer of the intrinsic polycrystalline silicon layer exposed in the boron diffusion region are respectively converted into a boron diffusion layer and a BSG layer.

[0015] S6, retaining the mask layer of the isolation region design region and slotting to remove the mask layer of the phosphorus diffusion design region.

[0016] The pre-designed phosphorus diffusion region is slotted, and after removing the mask layer of the region, phosphorus atoms can diffuse into the intrinsic polycrystalline silicon layer of the region during the subsequent phosphorus diffusion process, so that it is converted into a phosphorus diffusion layer. The purpose of retaining the mask layer of the isolation region design region is to lay the foundation for the subsequent formation of the polished isolation region structure protruding from the back surface of the silicon wafer, in addition, the BSG layer formed by S5 boron diffusion can also effectively block the phosphorus atoms from entering the bottom boron diffusion layer during the phosphorus diffusion process.

[0017] S7, the alkali cleaning removes the residual mask layer in the slotting area of S6 to expose the intrinsic polysilicon layer in the area.

[0018] S8, phosphorus diffusion, the inner layer and the surface layer of the intrinsic polysilicon layer in the phosphorus diffusion design area are converted into phosphorus diffusion layer and PSG layer respectively.

[0019] In the above phosphorus diffusion process, the surface of the intrinsic polysilicon layer in the boron diffusion layer and the isolation area is protected by the BSG layer and the mask layer respectively, so that the phosphorus atoms cannot diffuse into the intrinsic polysilicon layer, and only the inner layer and the surface layer of the intrinsic polysilicon layer exposed in the phosphorus diffusion design area are converted into phosphorus diffusion layer and PSG layer respectively.

[0020] S9, removing the wrap layer on the front and side surfaces of the silicon wafer.

[0021] S10, wet cleaning and front texturing, forming a pyramid textured surface on the front surface of the silicon wafer, and removing the residual mask layer, PSG layer and BSG layer by pickling to form a polished isolation area protruding from the back surface of the silicon wafer.

[0022] In the above S10 process, since the front surface of the silicon wafer has been removed from the wrap layer without the existence of the oxidation area, an effective light trapping textured surface (i.e. pyramid textured surface) can be formed during the texturing process; and for the whole area of the back surface of the silicon wafer, the PSG layer / mask layer / BSG layer exists, which can block the corrosion of the alkali and prevent it from being damaged. After cleaning and texturing, the residual mask layer, PSG layer and BSG layer on the back surface of the silicon wafer are removed by pickling to form a boron diffusion layer and a phosphorus diffusion layer with a cross contact structure, and a polished isolation area protruding from the back surface of the silicon wafer. The polished isolation area is the intrinsic polysilicon layer between the boron diffusion layer and the phosphorus diffusion layer, which plays an insulating role, and the surface of the isolation area is a polished plane. Compared with the conventional pyramid textured isolation area, the polished isolation area can increase the reflection of incident light in the silicon substrate, improve the I sc of the solar cell, and the initial isolation area is protected by the mask layer, which is not damaged by subsequent wet etching, so that the height difference between the isolation area and the boron / phosphorus diffusion layer is small, which is beneficial to the lateral transmission of carriers in the silicon substrate and improves the FF.

[0023] S11, double-sided film plating, after double-sided film plating, a passivation and anti-reflection layer is formed on the front / back surface of the silicon wafer.

[0024] S12, screen printing, sintering and light injection to obtain a TBC solar cell.

[0025] In summary, first, the conventional isolation area structure with a pyramid textured surface is improved to a polished isolation area structure protruding from the back surface of the silicon wafer, which can increase the reflection of incident light in the silicon substrate, thereby improving the I sc .

[0026] Secondly, the application realizes the TBC solar cell by optimizing the process step and depositing intrinsic polycrystalline silicon layer once, so that the problems such as product performance and yield reduction caused by uneven thermal stress distribution due to multiple deposition of intrinsic polycrystalline silicon layer can be avoided; in addition, the use of one-time intrinsic polycrystalline silicon layer deposition can greatly reduce the amount of special gas and production cost.

[0027] As preferred, in S2, the mask layer is formed by PECVD, and the conditions are as follows: the reaction gas is N2O and SiH4, the reaction temperature is 400-500 DEG C, the flow rate of N2O is 9000-11000 sccm, the flow rate of SiH4 is 1000-5000 sccm, the power is 3000-20000 W, the deposition time is 100-3000 s, and the thickness of the mask layer is 30-300 nm.

[0028] As preferred, in S2, the mask layer can also be formed by ultraviolet oxidation laser treatment: first, an embryonic mask layer is generated under the conditions of oxygen concentration of 20-40%, ultraviolet laser wavelength of 300-400 nm; and then a denser mask layer is formed under the conditions of oxygen concentration of 50-90%, ultraviolet laser wavelength of 200-300 nm.

[0029] In the previous test, it is found that the density of the mask layer obtained by using conventional PECVD or conventional one-step ultraviolet laser oxidation process is not ideal, which increases the risk of boron atoms and phosphorus atoms diffusing into the intrinsic polycrystalline silicon layer during subsequent boron diffusion and phosphorus diffusion, thereby causing battery leakage or performance degradation. Therefore, the application designs the above-mentioned special two-step differential ultraviolet laser oxidation process, and the principle is that different laser wavelengths penetrate to different depths in the silicon, the wavelength is larger in the first step of the above-mentioned process, the penetration depth is deeper, and a relatively thick embryonic mask layer can be initially formed; the wavelength is shorter in the second step, the penetration depth is shallower, and the embryonic mask layer can become denser in texture without changing the thickness; at the same time, different oxygen concentration treatment environments can make the formed mask layer more effectively block the internal diffusion of boron atoms and phosphorus atoms.

[0030] Further preferably, in S2, the conditions of the ultraviolet oxidation laser treatment are as follows: first, an embryonic mask layer is generated under the conditions of O2 flow rate of 10-100 sccm, environmental oxygen concentration of 20-40%, ultraviolet laser wavelength of 300-400 nm, power of 10-500 W, and processing time of 1-30 s; and then a denser mask layer is formed under the conditions of O2 flow rate of 100-500 sccm, environmental oxygen concentration of 50-90%, ultraviolet laser wavelength of 200-300 nm, power of 2-50 W, and processing time of 1-30 s; and the thickness of the mask layer is 30-300 nm.

[0031] As preferred, in S2, the deposition condition of the tunneling oxide layer is: O2 flow rate 10000-80000sccm, reaction temperature 400-800℃, time 200-1000s, and the thickness of the tunneling oxide layer is 2-10nm.

[0032] As preferred, in S2, the deposition condition of the intrinsic polysilicon layer is: SiH4 flow rate 300-2000sccm, reaction temperature 500-700℃, time 2-4h, working pressure 100-500mTorr, and the thickness of the intrinsic polysilicon layer is 100-300nm.

[0033] As preferred, in S3, the mask layer of the boron diffusion design area is removed by laser patterning and slotting.

[0034] As preferred, in S5, the boron diffusion condition is: temperature 800-950℃, diffusion time 5-50min, BCl3 flow rate 50-500sccm, O2 flow rate 500-2000sccm; oxidation advancing temperature 900-1050℃, O2 flow rate 5000-30000sccm, advancing time 30-80min, and a BSG layer with a thickness of 30-70nm is generated.

[0035] As preferred, in S6, the mask layer of the phosphorus diffusion design area is removed by laser patterning and slotting.

[0036] As preferred, in S8, the phosphorus diffusion condition is: temperature 750-850℃, diffusion time 5-30min, POC13 carried by nitrogen flow rate 500-1200sccm, O2 flow rate 500-1000sccm; oxidation advancing temperature 850-950℃, O2 flow rate 1000-10000sccm, advancing time 20-60min, and a PSG layer with a thickness of 30-70nm is generated. sc Meanwhile, since the initial isolation area is protected by the mask layer, it is not damaged by the subsequent wet etching, and the height difference between the isolation area and the boron / phosphorus diffusion layer is small, which is beneficial to the lateral transmission of the carriers in the silicon substrate and improves the FF.

[0037] (2) The present application realizes the single deposition of the intrinsic polysilicon layer to obtain a TBC solar cell, effectively improves the performance and yield of the product, and significantly reduces the production cost. BRIEF DESCRIPTION OF DRAWINGS

[0038] Fig. 1 is a schematic structural diagram of a silicon wafer after double-side polishing.

[0039] Figure 2 is a schematic diagram of the structure of a silicon wafer after deposition of a tunneling oxide layer / intrinsic polysilicon layer / mask layer.

[0040] Figure 3 is a schematic diagram of the structure of a silicon wafer after laser one-time patterning of the slot mask layer + cleaning.

[0041] Figure 4 is a schematic diagram of the structure of a silicon wafer after boron diffusion.

[0042] Figure 5 is a schematic diagram of the structure of a silicon wafer after laser two-time patterning of the slot mask layer + cleaning.

[0043] Figure 6 is a schematic diagram of the structure of a silicon wafer after phosphorus diffusion.

[0044] Figure 7 is a schematic diagram of the structure of a silicon wafer after cleaning and texturing.

[0045] Figure 8 is a schematic diagram of the structure of a TBC solar cell.

[0046] Figure 9 is a schematic diagram of the structure of a solar cell prepared in Comparative Example 1.

[0047] The reference signs are: N-type monocrystalline silicon wafer 1; tunneling oxide layer 2; intrinsic polysilicon layer 3; mask layer 4; boron diffusion layer 5; BSG layer 6; phosphorus diffusion layer 7; PSG layer 8; pyramid texturing 9; passivation anti-reflection layer 10; electrode layer 11. DETAILED DESCRIPTION

[0048] The application is further described below in conjunction with examples.

[0049] A preparation method of a TBC solar cell having a polished isolation region structure, comprising the following steps: S1, polishing both sides of a silicon wafer.

[0050] In some specific embodiments, an N-type monocrystalline silicon wafer 1 is selected after being cut by a diamond wire, the thickness is about 150 μm, and the size is 182.2 mm x 186.7 mm. The silicon wafer is placed into an alkali polishing tank, the temperature is maintained at 75-85 °C, and the time for polishing both sides is 6-8 min, the polishing thickness is 3-7 μm, and the thinning amount is 0.35-0.45 g, as shown in Figure 1.

[0051] S2, sequentially forming a tunneling oxide layer 2 (adopting an LPCVD method), an intrinsic polysilicon layer 3 (adopting an LPCVD method), and a mask layer 4 on the back of the silicon wafer, as shown in Figure 2.

[0052] In some specific embodiments, the deposition conditions of the tunneling oxide layer are as follows: O2 flow rate 10000-80000 sccm, reaction temperature 400-800 °C, time 200-1000 s, and tunneling oxide layer thickness 2-10 nm.

[0053] In some embodiments, the intrinsic polysilicon layer is deposited under the following conditions: SiH4 flow rate 300-2000 sccm, reaction temperature 500-700 °C, time 2-4 h, working pressure 100-500 mTorr, and intrinsic polysilicon layer thickness 100-300 nm.

[0054] In some embodiments, the mask layer is formed by PECVD under the following conditions: reaction gas N2O and SiH4, reaction temperature 400-500 °C, N2O flow rate 9000-11000 sccm, SiH4 flow rate 1000-5000 sccm, power 3000-20000 W, deposition time 100-3000 s, and mask layer thickness 30-300 nm.

[0055] In some preferred embodiments, the mask layer can also be formed by ultraviolet oxidation laser treatment: first, under the conditions of oxygen concentration 20-40% and ultraviolet laser wavelength 300-400 nm, a mask layer prototype is formed; and then, under the conditions of oxygen concentration 50-90% and ultraviolet laser wavelength 200-300 nm, a denser mask layer is formed.

[0056] Further preferably, in S2, the conditions of the ultraviolet oxidation laser treatment are as follows: first, under the conditions of O2 flow rate 10-100 sccm, ambient oxygen concentration 20-40%, ultraviolet laser wavelength 300-400 nm, power 10-500 W, and treatment time 1-30 s, a mask layer prototype is formed; and then, under the conditions of O2 flow rate 100-500 sccm, ambient oxygen concentration 50-90%, ultraviolet laser wavelength 200-300 nm, power 2-50 W, and treatment time 1-30 s, a denser mask layer is formed; and the mask layer thickness is 30-300 nm.

[0057] S3, laser one-time patterning and slotting to remove the mask layer of the boron diffusion design region. The pre-designed boron diffusion region is slotted, and the mask layer of the region is removed, so that in the subsequent boron diffusion process, boron atoms can diffuse to the intrinsic polysilicon layer of the region.

[0058] In some embodiments, the picosecond laser is used for one-time patterning and slotting under the following conditions: laser wavelength 400-600 nm, frequency 500-700 KHz, marking speed 40000-50000 mm / s, power 10-50 W, and treatment time 1-5 s.

[0059] S4, alkali cleaning to remove residual mask layer in the slotted region to fully expose the intrinsic polysilicon layer of the region, as shown in FIG. 3.

[0060] In some specific embodiments, the silicon wafer is placed in an alkaline solution for cleaning at a temperature of 75-85°C. During the experiment, different cleaning times and other parameters are adjusted, and the thickness of the mask layer after cleaning is tested by an ellipsometer. The mask layer in the grooved area can be accurately removed without excessive removal of the intrinsic polysilicon layer at the bottom during the alkaline cleaning process.

[0061] S5, boron diffusion, the inner layer and the surface layer of the intrinsic polysilicon layer 3 in the boron diffusion design area are converted into a boron diffusion layer 5 and a BSG layer 6, respectively. During the above boron diffusion process, the S3 un-grooved area is effectively blocked from boron atoms entering the intrinsic polysilicon layer 3 due to the protection of the mask layer 4, and only the inner layer and the surface layer of the intrinsic polysilicon layer 3 exposed in the boron diffusion area are converted into a boron diffusion layer 5 and a BSG layer 6, respectively, as shown in FIG. 4.

[0062] In some specific embodiments, the conditions for boron diffusion are: temperature 800-950°C, diffusion time 5-50min, BCl3 flow rate 50-500sccm, O2 flow rate 500-2000sccm; oxidation promotion temperature 900-1050°C, O2 flow rate 5000-30000sccm, promotion time 30-80min. The thickness of the BSG layer is 30-70nm.

[0063] S6, the mask layer in the isolation area design area is retained, and the mask layer in the phosphorus diffusion design area is removed by laser secondary patterning and grooving. After the pre-designed phosphorus diffusion area is grooved and the mask layer in this area is removed, phosphorus atoms can diffuse into the intrinsic polysilicon layer in this area during the subsequent phosphorus diffusion process, causing it to be converted into a phosphorus diffusion layer. The purpose of retaining the mask layer in the isolation area design area is to lay the foundation for the subsequent formation of a polished isolation area structure that protrudes from the back surface of the silicon wafer. In addition, the BSG layer formed by S5 boron diffusion can effectively block phosphorus atoms from entering the bottom boron diffusion layer during the phosphorus diffusion process.

[0064] In some specific embodiments, picosecond laser is used for secondary patterning and grooving, and the conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0065] S7, alkaline cleaning to remove the residual mask layer 4 in the grooved area to fully expose the intrinsic polysilicon layer 3 in this area. The boron diffusion layer area and the deposited layer at the bottom of the isolation area design area are protected by the BSG layer 6 and the mask layer 4, respectively, which can avoid being corroded and damaged by the alkali, as shown in FIG. 5.

[0066] S8, phosphorus diffusion, the inner layer and the surface layer of the intrinsic polysilicon layer 3 in the phosphorus diffusion design area are respectively converted into the phosphorus diffusion layer 7 and the PSG layer 8. In the above phosphorus diffusion process, since the surface of the intrinsic polysilicon layer 3 in the boron diffusion layer 5 and the isolation area is respectively protected by the BSG layer 6 and the mask layer 4, the phosphorus atoms cannot diffuse into the boron diffusion layer 5 and the isolation area, and only the inner layer and the surface layer of the intrinsic polysilicon layer 3 exposed in the phosphorus diffusion design area are respectively converted into the phosphorus diffusion layer 7 and the PSG layer 8, as shown in FIG. 6.

[0067] In some specific embodiments, the conditions of the phosphorus diffusion are as follows: the temperature is 750-850°C, the diffusion time is 5-30 min, the flow rate of POCl3 carried by nitrogen is 500-1200 sccm, and the flow rate of O2 is 500-1000 sccm; the oxidation advancing temperature is 850-950°C, the flow rate of O2 is 1000-10000 sccm, and the advancing time is 20-60 min. The thickness of the PSG layer is 30-70 nm.

[0068] S9, removing the boron diffusion layer and the phosphorus diffusion layer around the front surface and the side surface of the silicon wafer.

[0069] In some specific embodiments, the silicon wafer is removed by a chain machine (acid corrosion) to remove the boron diffusion layer and the phosphorus diffusion layer around the front surface and the side surface of the silicon wafer.

[0070] S10, wet cleaning and front surface texturing, the front surface of the silicon wafer forms a pyramid texturing surface 9, and the residual mask layer 4, the PSG layer 8 and the BSG layer 6 are removed by acid washing to form a polished isolation area protruding from the back surface of the silicon wafer, as shown in FIG. 7.

[0071] In the above S10 process, since the front surface of the silicon wafer has been removed from the oxidation area without the boron diffusion layer and the phosphorus diffusion layer, an effective light trapping texturing surface (i.e. the pyramid texturing surface) can be formed in the texturing process; and for the back surface of the silicon wafer, the PSG layer / mask layer / BSG layer exists in the whole area, which can block the corrosion of the alkali and prevent the isolation area from being damaged. After cleaning and texturing, the residual mask layer, the PSG layer and the BSG layer on the back surface of the silicon wafer are removed by acid washing to form the boron diffusion layer and the phosphorus diffusion layer with a cross-contact structure, and the polished isolation area protruding from the back surface of the silicon wafer. The polished isolation area is the intrinsic polysilicon layer between the boron diffusion layer and the phosphorus diffusion layer, which is not converted and has an insulating effect. The surface of the isolation area is a polished plane, which can increase the reflection of incident light in the silicon substrate compared with the conventional pyramid texturing surface, thereby improving the I sc At the same time, since the initial isolation area is protected by the mask layer, it is not damaged by subsequent wet etching, and the height difference between the isolation area and the boron / phosphorus diffusion layer is small, which is beneficial to the lateral transmission of carriers in the silicon substrate and improves the FF.

[0072] In some specific embodiments, the de-wound plated silicon wafer is put into an alkali texturing tank for wet cleaning and texturing integrated processing, wherein the temperature is maintained at 75-85℃, and the time is 6-12 min.

[0073] S11, double-sided coating: after double-sided coating, a passivation anti-reflection layer 10 is formed on the front / back surface of the silicon wafer.

[0074] S12, screen printing and sintering to form an electrode layer 11, light injection, to obtain a TBC solar cell, as shown in the specific embodiments and comparative examples of FIG. 8.

[0075] Embodiment 1: a preparation method of a TBC solar cell with a polished isolation region structure, comprising the following steps: S1, double-sided polishing of a silicon wafer: select an N-type monocrystalline silicon wafer 1 after diamond wire cutting, with a thickness of 150μm and a size of 182.2mm×186.7mm. Put the silicon wafer into an alkali polishing tank, maintain the temperature at 75℃, and polish for 6 min to obtain a double-sided polished silicon wafer with a polishing thickness of 4μm and a thinning amount of 0.42g, as shown in FIG. 1.

[0076] S2, sequentially form a tunneling oxide layer 2 (using an LPCVD method), an intrinsic polysilicon layer 3 (using an LPCVD method), and a mask layer 4 (using a PECVD method) on the back surface of the silicon wafer, as shown in FIG. 2. The deposition conditions of the tunneling oxide layer are as follows: O2 flow rate 40000sccm, reaction temperature 600℃, time 600s, and the thickness of the tunneling oxide layer is about 3nm.

[0077] The deposition conditions of the intrinsic polysilicon layer are as follows: SiH4 flow rate 920sccm, reaction temperature 550℃, time 3.3h, working pressure 300mTorr, and the thickness of the intrinsic polysilicon layer is about 290nm.

[0078] The PECVD deposition conditions of the mask layer are as follows: the reaction gas is N2O and SiH4, the reaction temperature is 440℃, the flow rate of N2O is 9500sccm, the flow rate of SiH4 is 2700sccm, the power is 7000W, the deposition time is 650s, and the thickness of the mask layer is about 52nm.

[0079] S3, laser one-time patterning and slotting to remove the mask layer of the boron diffusion layer design area, with the following conditions: laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / s, power 25W, and processing time 2.7s.

[0080] S4, the residual mask layer 4 in the grooving area is removed by alkali cleaning to fully expose the intrinsic polysilicon layer 3 in the area, as shown in FIG. 3. The specific steps are as follows: the silicon wafer is placed in an alkali solution for cleaning, the temperature is 75°C, and during the experiment, different cleaning times and other parameters are adjusted to correspond to the ellipsometer test of the mask layer thickness after cleaning, so that the mask layer in the grooving area can be accurately removed without excessive removal of the intrinsic polysilicon layer at the bottom during the alkali cleaning process.

[0081] S5, boron diffusion, the inner layer and the surface layer of the exposed intrinsic polysilicon layer are respectively converted into a boron diffusion layer and a BSG layer. The conditions for boron diffusion are as follows: temperature 850°C, diffusion time 10 min, BCl3 flow rate 200 sccm, O2 flow rate 1200 sccm; oxidation promotion temperature 950°C, O2 flow rate 7000 sccm, promotion time 30 min. The thickness of the BSG layer is about 45 nm. During the above boron diffusion process, the S3 un-grooving area is effectively blocked from boron atoms entering the intrinsic polysilicon layer 3 due to the protection of the mask layer 4, and only the inner layer and the surface layer of the exposed intrinsic polysilicon layer 3 are respectively converted into a boron diffusion layer 5 and a BSG layer 6, as shown in FIG. 4.

[0082] S6, the mask layer in the design area of the isolation area is retained, and the mask layer in the phosphorus diffusion design area is removed by laser secondary patterning grooving. The conditions are as follows: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0083] S7, the residual mask layer 4 in the grooving area of S6 is removed by alkali cleaning to fully expose the intrinsic polysilicon layer 3 in the area. The boron diffusion layer area and the deposited layer at the bottom of the design area of the isolation area are protected by the BSG layer 6 and the mask layer 4 respectively, so as to avoid being corroded and damaged by alkali, as shown in FIG. 5. The specific steps are as follows: the silicon wafer is placed in an alkali solution for cleaning, the temperature is 75°C, and during the experiment, different cleaning times and other parameters are adjusted to correspond to the ellipsometer test of the mask layer thickness after cleaning, so that the mask layer in the grooving area can be accurately removed without excessive removal of the intrinsic polysilicon layer at the bottom during the alkali cleaning process.

[0084] S8, phosphorus diffusion, the inner layer and the surface layer of the intrinsic polysilicon layer 3 in the phosphorus diffusion design area are respectively converted into the phosphorus diffusion layer 7 and the PSG layer 8. The conditions of the phosphorus diffusion are: temperature 790℃, diffusion time 20min, POCI3 carried by nitrogen flow at 1100sccm, O2 flow 700sccm; oxidation promotion temperature 890℃, O2 flow 3000sccm, promotion time 40min. The thickness of the PSG layer is about 42nm. In the above phosphorus diffusion process, since the surface of the intrinsic polysilicon layer 3 in the boron diffusion layer 5 and the isolation area is respectively protected by the BSG layer 6 and the mask layer 4, the phosphorus atoms cannot diffuse into the boron diffusion layer 5 and the isolation area, and only the inner layer and the surface layer of the intrinsic polysilicon layer 3 exposed in the phosphorus diffusion design area are respectively converted into the phosphorus diffusion layer 7 and the PSG layer 8, as shown in Figure 6.

[0085] S9, removing the front and side wrap layers of the silicon wafer: the silicon wafer is removed by using a chain machine (acid etching) to remove the boron diffusion layer and the phosphorus diffusion layer and other wrap layers on the front and side of the silicon wafer.

[0086] S10, wet cleaning and front texturing, the silicon wafer is subjected to wet cleaning and front texturing treatment under alkaline conditions, the temperature is maintained at 82℃, and the time is 7min. The front of the silicon wafer forms a pyramid texture 9, and the residual mask layer 4, PSG layer 8 and BSG layer 6 are removed by acid washing to form a polished isolation area protruding from the back of the silicon wafer, as shown in Figure 7.

[0087] In the above S10 process, since the front of the silicon wafer has been removed from the wrap layer and the non-oxidized area exists, an effective light trapping texture (i.e. the pyramid texture 9) can be formed during the texturing process; and for the whole area of the back of the silicon wafer, the PSG layer / mask layer / BSG layer exists, which can block the corrosion of the alkali and is not damaged. After cleaning and texturing, the residual mask layer, PSG layer and BSG layer on the back of the silicon wafer are removed by acid washing to form the boron diffusion layer and the phosphorus diffusion layer with a cross-contact structure, and the polished isolation area protruding from the back of the silicon wafer. The polished isolation area is the intrinsic polysilicon layer between the boron diffusion layer and the phosphorus diffusion layer which is not transformed, which plays an insulating role, and the surface of the isolation area is a polished plane. Compared with the conventional isolation area with a pyramid textured surface, the polished isolation area can increase the reflection of incident light in the silicon substrate and improve the I sc ; at the same time, since the initial isolation area is protected by the mask layer, it is not damaged by subsequent wet etching, which can make the height difference between the isolation area and the boron / phosphorus diffusion layer smaller, which is beneficial to the lateral transmission of carriers in the silicon substrate and improves the FF.

[0088] S11, double-sided film plating: after double-sided film plating, a passivation anti-reflection layer 10 is formed on the front / back of the silicon wafer. Specifically, AlO xThe thin film is formed by reacting Al(CH3)3 with water vapor, and the thickness is 8 nm, and the process temperature is controlled at 250°C. Then, a tube PECVD device is used to deposit SiN x film on the front side of the silicon wafer x The thickness of the thin film is about 82 nm, and the refractive index is 2.1; the back side SiN x The thickness of the thin film is about 90 nm, and the refractive index is 2.0; the reaction gas in the tube cavity is SiH4, NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440°C, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10 min.

[0089] S12, the coated silicon wafer is subjected to screen printing on the back side to form a metal contact, and then sintered at 770°C to form an Ag-Si ohmic contact (electrode layer 11), and finally subjected to photo injection repair to obtain a TBC solar cell, as shown in FIG. 8.

[0090] Example 2 The difference between Example 2 and Example 1 is that the mask layer in S2 is formed by one-step ultraviolet laser oxidation treatment: first generate a mask layer with a thickness of about 52 nm under the conditions of O2 flow rate 50 sccm, ambient oxygen concentration 26% (volume concentration), ultraviolet laser wavelength 355 nm, power 12 W, and processing time 10 s.

[0091] Example 3 The difference between Example 3 and Example 1 is that the mask layer in S2 is formed by two-step ultraviolet laser oxidation treatment: first generate a mask layer with a thickness of about 52 nm under the conditions of O2 flow rate 50 sccm, ambient oxygen concentration 26% (volume concentration), ultraviolet laser wavelength 355 nm, power 12 W, and processing time 10 s; then form a denser mask layer under the conditions of O2 flow rate 200 sccm, ambient oxygen concentration 60% (volume concentration), ultraviolet laser wavelength 266 nm, power 3 W, and processing time 18 s.

[0092] Comparative Example 1 The difference between Comparative Example 1 and Example 1 is that in S6, the mask layer of the isolation region and the mask layer of the phosphorus diffusion design region are removed by laser secondary patterning slotting at the same time, and the surface of the isolation region of the finally obtained TBC solar cell has a pyramid suede structure, as shown in FIG. 9.

[0093] The preparation method of Comparative Example 1 specifically includes: S1-S5 of Example 1.

[0094] S6, laser secondary patterning slotting is used to remove the mask layers of the phosphorus diffusion design region and the isolation design region, and the conditions are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0095] S7-S8 same as example 1.

[0096] S9, laser three times patterning groove removes BSG layer and PSG layer at the junction of boron diffusion layer and phosphorus diffusion layer (i.e. isolation region), and loosens the bottom of each deposited layer. Conditions: laser wavelength is 532 nm, frequency is 600 KHz, marking speed is 45000 mm / s, power is 50 W, and processing time is 3 s.

[0097] S10 same as example 1.

[0098] S11, the silicon wafer after complete removal of the winding plating is put into an alkali texturing tank for backside laser grooving area wet cleaning and texturing integration treatment, the temperature is maintained at 82℃, the time is 7 min, the weight loss is 0.36 g, and cleaning and texturing are performed. Since the front surface of the silicon wafer has been completely removed from the winding plating layer and there is no oxidized area, an effective light-trapping textured surface (i.e. pyramid textured surface) can be formed during the texturing process; while in the isolation region of the back surface of the silicon wafer, the alkali solution can effectively corrode the bottom deposited layer, so that the back surface of the silicon wafer in this region is exposed, and a pyramid textured surface is formed during the texturing process. Subsequently, the subsequent self-contained acid cleaning tank of the texturing tank can further remove the residual PSG layer and BSG layer of the silicon wafer, as shown in FIG. 9.

[0099] S12-S13 same as example 1.

[0100] Comparative example 2 (using two intrinsic polycrystalline silicon layer deposition processes) S1, select N-type monocrystalline silicon wafer cut by diamond wire, thickness is 150 μm, size is 182.2 mm x 186.7 mm. Put the cut silicon wafer into an alkali polishing tank, maintain the temperature at 75℃, polish both sides for 6 min, the polishing thickness is 4 μm, and the thinning amount is 0.42 g.

[0101] S2, then grow a tunneling oxide layer on the back surface of the polished silicon wafer by LPCVD method, the gas flow of O2 is 40000 sccm, the temperature is 600℃, and the time is 600 s, the thickness of the grown tunneling oxide layer is about 3 nm; then grow an intrinsic polycrystalline silicon layer on the basis of the tunneling oxide layer, wherein the gas flow of SiH4 is 920 sccm, the temperature is 550℃, the time is 3.3 h, the working pressure is 300 mTorr, and the thickness of the intrinsic polycrystalline silicon layer is about 290 nm.

[0102] S3, then use high-temperature boron diffusion method to convert the inner layer and surface layer of the intrinsic polycrystalline silicon layer into boron diffusion layer and BSG layer, respectively, the boron diffusion temperature is 850℃, the diffusion time is 10 min, the BCl3 gas flow is 200 sccm, the O2 gas flow is 1200 sccm, the oxidation advancing temperature is 950℃, the O2 flow is 7000 sccm, the advancing time is 30 min, and the thickness of the BSG layer is about 45 nm.

[0103] S4, using picosecond laser to pattern groove BSG layer, the laser wavelength is 532 nm, the frequency is 600 KHZ, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.

[0104] S5, the silicon wafer after laser patterning groove is put into an alkali solution for cleaning, the temperature is 75 DEG C, the time is 360 s, and the etching depth is 1.7 μm.

[0105] S6, then the back surface of the silicon wafer is secondarily grown with a tunnel oxide layer by LPCVD, the gas flow of O2 is 30000 sccm, the temperature is 600 DEG C, and the time is 450 s, and the thickness of the grown tunnel oxide layer is about 2.5 nm; then the intrinsic polysilicon layer is grown again on the basis of the tunnel oxide layer, wherein the gas flow of SiH4 is 920 sccm, the temperature is 550 DEG C, the time is 1.5 h, and the working pressure is 300 mTorr, and the thickness of the intrinsic polysilicon layer is about 180 nm.

[0106] S7, the inner layer and the surface layer of the intrinsic polysilicon layer are converted into phosphorus diffusion layer and PSG layer by phosphorus diffusion method, the phosphorus diffusion temperature is 790 DEG C, the diffusion time is 15 min, the flow rate of POCl3 carried by nitrogen is 1000 sccm, the flow rate of O2 is 650 sccm, the oxidation advancing temperature is 890 DEG C, the flow rate of O2 is 3000 sccm, the advancing time is 20 min, and the thickness of the PSG layer is about 39 nm.

[0107] S8, then the PSG layer is secondarily patterned and grooved by picosecond laser, so that the PSG layer at the bottom of the boron diffusion layer and the junction area between the p region and the n region is loosened, the laser wavelength is 532 nm, the frequency is 600 KHz, the marking speed is 45000 mm / s, the power is 25 W, and the processing time is 2.7 s.

[0108] S9, the above silicon wafer is removed by a chain machine to remove the boron diffusion layer and the phosphorus diffusion layer on the front surface and the side surface of the silicon wafer.

[0109] S10, the silicon wafer after the plating is put into an alkali texturing tank for back laser grooving area wet cleaning and texturing integrated processing, the temperature is maintained at 82 DEG C, the time is 7 min, the weight loss is 0.36 g, and the cleaning and texturing are performed. Since the front surface of the silicon wafer has been removed from the plating layer and there is no oxidation area, an effective light trapping textured surface can be formed during the texturing process; and the alkali solution can effectively etch the bottom deposition layer in the laser patterned processing area on the back surface, so as to form an isolated insulating structure. Then, the subsequent acid cleaning tank of the texturing tank can further remove the residual PSG layer and BSG layer of the silicon wafer.

[0110] S11, AlOx The thin film is generated by reacting Al(CH3)3 with water vapor, and the thickness is 8 nm, and the process temperature is controlled at 250°C. Then, a tube PECVD device is used to deposit SiN on both sides of the film x The film is SiN on the front side x The thickness of the thin film is about 82 nm, and the refractive index is 2.1; the back side is SiN x The thickness of the thin film is about 90 nm, and the refractive index is 2.0; the reaction gas in the tube cavity is SiH4, NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440°C, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10 min.

[0111] S12, the coated wafer is screen printed on the back side to form a metal contact, then sintered at 770°C to form an Ag-Si ohmic contact, and finally repaired by light injection to obtain a final TBC finished product battery.

[0112] Performance comparison table 1: different battery performance data From the above table data, it can be seen that: (1) The TBC solar cells prepared in Examples 1-3 all have a polished isolation zone structure, compared with the isolation zone surface of the TBC solar cell obtained in Comparative Example 1 which has a pyramid suede structure, the reflection of incident light in the silicon substrate can be increased, thereby improving the I sc sc of the battery; at the same time, since the initial isolation zone is protected by the mask layer, it is not damaged by subsequent wet etching, and the height difference between the isolation zone and the boron / phosphorus diffusion layer is small, which is beneficial to the lateral transmission of carriers in the silicon substrate and improves the FF.

[0113] (2) Since Examples 1-3 all use a one-step deposition of intrinsic polysilicon layer process, while Comparative Example 2 uses a conventional two-step deposition of intrinsic polysilicon layer process, the poly-Si parasitic absorption of the battery is lower, because it has a higher short-circuit current density (J sc ).

[0114] (3) The difference between Examples 1-3 is the preparation method of the mask layer. Specifically: Example 1 uses a more traditional PECVD process, Example 2 uses a one-step ultraviolet laser oxidation process, and Example 3 uses a two-step differential ultraviolet laser oxidation process. The results show that the performance of the product prepared by the PECVD process is not as good as that of the ultraviolet laser oxidation process. At the same time, the oxidation barrier layer formed by the one-step ultraviolet laser oxidation process in Example 2 is often not ideal in density, which can easily increase the risk of boron and phosphorus atoms diffusing into the bottom intrinsic polysilicon layer during subsequent boron and phosphorus diffusion processes, thereby causing the battery performance to decline or to leak. The two-step differential ultraviolet laser oxidation process used in Example 3 can make the oxidation barrier layer denser in texture without significantly increasing the thickness, so it can more effectively block the subsequent diffusion of boron and phosphorus atoms, thereby improving the battery performance.

[0115] The raw materials and equipment used in the present application are conventional raw materials and equipment in the art unless otherwise specified; the methods used in the present application are conventional methods in the art unless otherwise specified.

[0116] The above is only a preferred embodiment of the present application, and does not limit the present application in any way. Any simple modification, change, and equivalent transformation of the above embodiment based on the technical essence of the present application are still within the protection scope of the technical solution of the present application.

Claims

1. A method for producing a TBC solar cell having a polished isolation region structure, characterized by The method comprises the following steps: S1, polishing both sides of a silicon wafer; S2, forming a tunneling oxide layer, an intrinsic polysilicon layer and a mask layer on the back side of the silicon wafer; S3, removing the mask layer in the boron diffusion design area by slotting; S4, alkali cleaning; S5, boron diffusion, converting the intrinsic polysilicon layer in the boron diffusion design area into a boron diffusion layer and a BSG layer; S6, retaining the mask layer in the isolation area design area and removing the mask layer in the phosphorus diffusion design area by slotting; S7, alkali cleaning; S8, phosphorus diffusion, converting the intrinsic polysilicon layer in the phosphorus diffusion design area into a phosphorus diffusion layer and a PSG layer; S9, removing the plating layer; S10, wet cleaning and front side texturing, acid cleaning to remove the residual mask layer, PSG layer and BSG layer, and forming a polishing isolation area protruding from the back side of the silicon wafer; S11, double-side film plating; S12, screen printing, sintering and photo injection.

2. The method of claim 1, wherein: In S2, the mask layer is formed by PECVD, and the conditions are as follows: the reaction gas is N2O and SiH4, the reaction temperature is 400-500°C, the flow rate of N2O is 9000-11000sccm, the flow rate of SiH4 is 1000-5000sccm, the power is 3000-20000W, the deposition time is 100-3000s, and the thickness of the mask layer is 30-300nm.

3. The method of claim 1, wherein: In S2, the mask layer can also be formed by ultraviolet oxidation laser treatment: firstly, generating a mask layer prototype under the conditions of an oxygen concentration of 20-40% and an ultraviolet laser wavelength of 300-400nm; secondly, forming a denser mask layer under the conditions of an oxygen concentration of 50-90% and an ultraviolet laser wavelength of 200-300nm.

4. The method of claim 3, wherein: In S2, the conditions of the ultraviolet oxidation laser treatment are as follows: firstly, generating a mask layer prototype under the conditions of an O2 flow rate of 10-100sccm, an environmental oxygen concentration of 20-40%, an ultraviolet laser wavelength of 300-400nm, a power of 10-500W and a processing time of 1-30s; secondly, forming a denser mask layer under the conditions of an O2 flow rate of 100-500sccm, an environmental oxygen concentration of 50-90%, an ultraviolet laser wavelength of 200-300nm, a power of 2-50W and a processing time of 1-30s; the thickness of the mask layer is 30-300nm.

5. The method of claim 1, wherein: In S2, the deposition conditions of the tunneling oxide layer are as follows: an O2 flow rate of 10000-80000sccm, a reaction temperature of 400-800°C, a time of 200-1000s, and a thickness of the tunneling oxide layer of 2-10nm.

6. The method of claim 1, wherein: In S2, the deposition conditions of the intrinsic polysilicon layer are as follows: an SiH4 flow rate of 300-2000sccm, a reaction temperature of 500-700°C, a time of 2-4h, a working pressure of 100-500mTorr, and a thickness of the intrinsic polysilicon layer of 100-300nm.

7. The method of claim 1, wherein: In S3, the mask layer in the boron diffusion design area is removed by laser patterning and slotting.

8. The method of claim 1, wherein: In S5, the boron diffusion conditions are: temperature 800-950℃, diffusion time 5-50min, BCl3 flow rate 50-500sccm, O2 flow rate 500-2000sccm; oxidation advancing temperature 900-1050℃, O2 flow rate 5000-30000sccm, advancing time 30-80min, to generate a BSG layer with thickness 30-70nm.

9. The method of claim 1, wherein: In S6, laser patterning is used to groove and remove the mask layer in the phosphorus diffusion design area.

10. The method of claim 1, wherein: In S8, the phosphorus diffusion conditions are: temperature 750-850℃, diffusion time 5-30min, POC13 carried by nitrogen with flow rate 500-1200sccm, O2 flow rate 500-1000sccm; oxidation advancing temperature 850-950℃, O2 flow rate 1000-10000sccm, advancing time 20-60min, to generate a PSG layer with thickness 30-70nm.

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