Back contact cell, cell module and photovoltaic system

Abstract

The present disclosure relates to the technical field of solar cells, and provides a back contact cell, a cell module and a photovoltaic system. The back face of a silicon substrate of the back contact cell has a plurality of polished regions and a plurality of textured regions; a first passivation layer and a first polarity doped layer are successively stacked in each polished region; a second passivation layer and a second polarity doped layer are successively stacked in each textured region and at least cover the textured region; first transparent conductive films are provided on the first polarity doped layers, and second transparent conductive films are provided on the second polarity doped layers, the thickness of the portions of the second transparent conductive films corresponding to the textured regions being less than the thickness of the first transparent conductive films. In this way, the thickness of the portions of the second transparent conductive films in the textured regions is configured to be relatively small. When back-face light rays enter, parasitic absorption at the textured regions can be reduced, increasing the bifaciality factor of the back contact cell. In addition, configuring some of regions on the back face as textured faces can further reduce the reflectivity of the back-face light rays, thereby further increasing the bifaciality factor.

Description

Back contact cell, cell assembly and photovoltaic system

[0001] Cross-reference to Related Applications

[0002] The present disclosure claims priority to the Chinese patent application No. 202411330365.0, filed on September 20, 2024, with the title of “Back contact cell, cell assembly and photovoltaic system”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of solar cells, in particular to a back contact cell, a cell assembly and a photovoltaic system. BACKGROUND

[0004] Currently, in solar cells, a hybrid back contact cell is a cell in which both emitter and base contact electrodes are placed on the back surface (non-light receiving surface) of the cell. The light receiving surface of the cell is not blocked by any metal electrode, thereby effectively increasing the short-circuit current of the cell.

[0005] In order to improve the efficiency of the back contact cell, one of the doped layers of the back contact cell can be set as a polysilicon layer, and the other doped layer can be set as an amorphous silicon layer or a microcrystalline silicon layer or other different types of doped layers, and then a transparent conductive film layer such as TCO is set, thereby forming a hybrid back contact cell, that is, HBC (Hybrid Back Contact) technology. However, the double-sided rate of the hybrid back contact cell in the related art is low, and therefore, how to improve the double-sided rate of the hybrid back contact cell has become a technical problem for technical personnel to study. SUMMARY

[0006] The present disclosure provides a back contact cell, a cell assembly and a photovoltaic system.

[0007] The present disclosure is implemented in this way. The back contact cell of the embodiment of the present disclosure comprises:

[0008] a silicon substrate, the silicon substrate having opposite front and back surfaces, the back surface comprising a plurality of polished regions and a plurality of textured regions arranged alternately along a first direction, the polished regions and the textured regions both extending along a second direction, the second direction intersecting the first direction;

[0009] a first passivation contact structure, the first passivation contact structure comprising a first passivation layer and a first polarity doped layer which are sequentially stacked on the polished regions;

[0010] a second passivation contact structure, the second passivation contact structure comprising a second passivation layer and a second polarity doped layer which are sequentially stacked on the textured regions, the second passivation layer and the second polarity doped layer covering at least the textured regions; and

[0011] The first transparent conductive film and the second transparent conductive film, the first transparent conductive film is laminated on the first polarity doped layer and covers at least part of the area of the first polarity doped layer, the second transparent conductive film is laminated on the second polarity doped layer and covers at least part of the area of the part of the second polarity doped layer corresponding to the textured area, the second transparent conductive film is insulated and spaced apart from the first transparent conductive film, and the thickness of the part of the second transparent conductive film corresponding to the textured area is less than the thickness of the first transparent conductive film.

[0012] In some embodiments, the first passivation layer is a tunneling oxide layer, and the first polarity doped layer is a doped polysilicon layer.

[0013] The second passivation layer is at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer, and the second polarity doped layer is at least one of a doped amorphous silicon layer and a doped microcrystalline silicon.

[0014] In some embodiments, the thickness of the part of the second transparent conductive film corresponding to the textured area is 75-85 nm.

[0015] In some embodiments, the thickness of the first transparent conductive film is 90-155 nm.

[0016] In some embodiments, the ratio between the thickness of the first transparent conductive film and the thickness of the part of the second transparent conductive film corresponding to the textured area is 1.2-1.8.

[0017] In some embodiments, the first polarity doped layer and the second polarity doped layer are adjacent in the first direction; or the first polarity doped layer and the second polarity doped layer are spaced apart in the first direction.

[0018] In some embodiments, the first transparent conductive film is only laminated on the first polarity doped layer, the second passivation layer and the second polarity doped layer are only laminated on the textured area, and the second transparent conductive film is only laminated on the second polarity doped layer.

[0019] In some embodiments, the first polarity doped layer is a base doped layer, the second polarity doped layer is an emitter doped layer, and the sum of the orthographic projection areas of all the second polarity doped layers on the silicon substrate is greater than the sum of the orthographic projection areas of all the first polarity doped layers on the silicon substrate.

[0020] In some embodiments, the ratio between the sum of the orthographic projection areas of all the second polarity doped layers on the silicon substrate and the area of the back surface is 65%-85%.

[0021] In some embodiments, at the preset position of the at least partial second passivation contact structure, the second passivation layer has a passivation extension extending to cover a partial region of the first polarity doped layer, and the second polarity doped layer has a doped extension extending to cover the passivation extension, so as to form a stack structure of the first passivation layer, the first polarity doped layer, the passivation extension and the doped extension in sequence on the partial polishing region.

[0022] The second transparent conductive film has a film extension extending to at least a partial region of the doped extension, and the first transparent conductive film is at least layer-stacked on the region of the first polarity doped layer which is not covered by the passivation extension and the doped extension.

[0023] In some embodiments, the thickness of the film extension is greater than the thickness of the portion of the second transparent conductive film corresponding to the textured region.

[0024] In some embodiments, the thickness of the film extension is the same as the thickness of the first transparent conductive film.

[0025] The present disclosure also provides a battery assembly, which comprises a plurality of the back contact battery of any one of the above.

[0026] The present disclosure also provides a photovoltaic system, which comprises the battery assembly of the above.

[0027] In the back contact battery, the battery assembly and the photovoltaic system of the embodiments of the present disclosure, the back surface of the silicon substrate has a plurality of polishing regions and a plurality of textured regions, the first passivation layer and the first polarity doped layer are layer-stacked in sequence on the polishing regions, the second passivation layer and the second polarity doped layer are layer-stacked in sequence on the textured regions and cover at least the textured regions, the first transparent conductive film is arranged on the first polarity doped layer, and the second transparent conductive film is arranged on the second polarity doped layer, which are insulated and spaced apart. The thickness of the portion of the second transparent conductive film corresponding to the textured region is less than the thickness of the first transparent conductive film. In this way, the thickness of the portion of the second transparent conductive film on the textured region is set to be small, which can reduce the parasitic absorption at the textured region when the light enters the back surface, and improve the bifaciality of the back contact battery. Meanwhile, the partial region of the back surface is set to be textured, which can further reduce the reflectivity of the light on the back surface, thereby further improving the bifaciality.

[0028] Additional aspects and advantages of the present disclosure will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1 is a schematic diagram of a module of a photovoltaic system according to an embodiment of the present disclosure;

[0030] FIG. 2 is a schematic diagram of a module of a battery assembly according to an embodiment of the present disclosure;

[0031] Fig. 3 is a schematic cross-sectional view of a back contact cell according to an embodiment of the present disclosure;

[0032] Fig. 4 is another schematic cross-sectional view of a back contact cell according to an embodiment of the present disclosure;

[0033] Fig. 5 is a schematic plan view of a back contact cell according to an embodiment of the present disclosure;

[0034] Fig. 6 is still another schematic cross-sectional view of a back contact cell according to an embodiment of the present disclosure.

[0035] Main element symbol explanation: photovoltaic system 1000, cell assembly 200, back contact cell 100, silicon substrate 10, front surface 11, back surface 12, polished region 121, textured region 122, first passivation contact structure 20, first passivation layer 21, first polarity doped layer 22, second passivation contact structure 30, second passivation layer 31, second polarity doped layer 32, pre-set position 320, doped extension 321, first transparent conductive thin film 40, second transparent conductive thin film 50. DETAILED DESCRIPTION

[0036] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and cannot be understood as a limitation on the present disclosure. In addition, it should be understood that the specific embodiments described herein are only used to explain the present disclosure and cannot be used to limit the present disclosure.

[0037] In the description of the present disclosure, it should be understood that the terms "length", "width", "upper", "lower", "lateral", "longitudinal" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0038] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0039] In the description of the present disclosure, it is necessary to point out that, unless explicitly defined and limited otherwise, the terms "mount", "connect", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0040] In the present disclosure, unless explicitly defined and limited otherwise, the "upper" or "lower" of the first feature to the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "upper", "above" and "on" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The "below", "under" and "under" of the first feature to the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0041] The following disclosure provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the disclosure of the present disclosure, the components and arrangements of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeatedly refer to at least one of reference numerals and reference letters in different examples, and such repetition is for the purpose of simplification and clarity, which does not indicate the relationship between at least one of the various embodiments and arrangements discussed. In addition, the present disclosure provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and the use of at least one of other materials.

[0042] Please refer to FIG. 1-2, the photovoltaic system 1000 in the embodiment of the present disclosure can include the battery assembly 200 in the embodiment of the present disclosure, the battery assembly 200 in the embodiment of the present disclosure can include a plurality of back contact cells 100 in the embodiment of the present disclosure.

[0043] In the embodiment of the present disclosure, the plurality of back contact cells 100 in the battery assembly 200 can be connected in series to form a plurality of cell strings, and the manner of realizing the current bus output of each cell string can be one of the following: series connection, parallel connection, series-parallel combination, for example, the connection between each cell piece can be realized by welding the welding strip, and the connection between each cell string can be realized by the bus bar. In some embodiments, each cell string can form a cell piece array, and then be packaged together by the front plate, the front adhesive film, the rear adhesive film and the back plate to form the battery assembly 200.

[0044] Referring to FIG. 3, the back contact cell 100 in the embodiment of the present disclosure can include a silicon substrate 10, a first passivation contact structure 20, a second passivation contact structure 30, a first transparent conductive film 40, and a second transparent conductive film 50.

[0045] The silicon substrate 10 has opposite front and back surfaces 11 and 12, and the back surface 12 includes a plurality of polished regions 121 and a plurality of textured regions 122. The plurality of polished regions 121 and the plurality of textured regions 122 are alternately arranged along a first direction, and the polished regions 121 and the textured regions 122 each extend along a second direction, which is perpendicular to the first direction.

[0046] Specifically, as shown in FIG. 3, the polished regions 121 and the textured regions 122 can be alternately arranged along a transverse direction of the silicon substrate 10 and each extend along a longitudinal direction, that is, the first direction can be a transverse direction of the back contact cell 100, and the second direction can be a transverse direction of the back contact cell 100, which are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, the two can be diagonal directions of the silicon substrate 10, which are not specifically limited here.

[0047] The first passivation contact structure 20 can include a first passivation layer 21 and a first polarity doped layer 22 which are sequentially stacked on the polished regions 121 (each polished region 121 is provided with the first passivation contact structure 20, and the number of the two corresponds one-to-one), that is, the first passivation layer 21 is stacked on the polished regions 121, and the first polarity doped layer 22 is stacked on the first passivation layer 21.

[0048] The second passivation contact structure 30 can include a second passivation layer 31 and a second polarity doped layer 32 which are sequentially stacked on the textured regions 122 (each textured region 122 is provided with the second passivation contact structure 30, and the number of the two corresponds one-to-one), and the second passivation layer 31 and the second polarity doped layer 32 at least cover the textured regions 122.

[0049] For example, in some embodiments, the first polarity doped layer 22 only covers the polished regions 121, and the second polarity doped layer 32 at least covers at least part of the textured regions 122, and the part of the second polarity doped layer 32 corresponding to the textured regions 122 can be textured away from the surface of the silicon substrate 10. That is, in the second passivation contact structure 30, the second passivation layer 31 is disposed on the textured regions 122, and the second polarity doped layer 32 is stacked on the second passivation layer 31, and the back surface of the part of the second polarity doped layer 32 corresponding to the textured regions 122 can be textured.

[0050] As shown in FIG. 3, the first transparent conductive film 40 is laminated on the first polarity doped layer 22 and covers at least part of the area of the first polarity doped layer 22, and the second transparent conductive film 50 is laminated on the second polarity doped layer 32 and covers at least part of the area of the part of the second polarity doped layer 32 corresponding to the textured area 122, and the second transparent conductive film 50 is insulated and spaced apart from the first transparent conductive film 40.

[0051] In the embodiment of the present disclosure, the thickness of the part of the second transparent conductive film 50 corresponding to the textured area 122 is less than the thickness of the first transparent conductive film 40, that is, the thickness of the part of the second transparent conductive film 50 located at the textured area 122 is less than the thickness of the first transparent conductive film 40.

[0052] It should be noted that in the present disclosure, the covering or laminating of a film layer on part or all of an area of a surface or a film layer means that the film layer is directly laminated on the surface or the film layer, or other film layers are arranged between the film layer and the surface or the film layer, and the covering only means to define the specific arrangement range of the film layer.

[0053] In addition, in the present disclosure, the part of a film layer corresponding to an area or a layer structure means the part of the film layer overlapping the area or the other layer structure in the thickness direction, for example, the part of the second transparent conductive film 50 corresponding to the textured area 122 means the area of the second transparent conductive film 50 covering the textured area 122, and the similar description in the following can also be referred to.

[0054] In the back contact cell 100, the cell assembly 200 and the photovoltaic system 1000 in the embodiment of the present disclosure, the back surface 12 of the silicon substrate 10 has a plurality of polished areas 121 and a plurality of textured areas 122, the first passivation layer 21 and the first polarity doped layer 22 are sequentially laminated on the polished areas 121, the second passivation layer 31 and the second polarity doped layer 32 are sequentially laminated on the textured areas 122 and cover at least the textured areas 122, the first transparent conductive film 40 is arranged on the first polarity doped layer 22, the second transparent conductive film 50 is arranged on the second polarity doped layer 32, and the two are insulated and spaced apart. The thickness of the part of the second transparent conductive film 50 corresponding to the textured area 122 is less than the thickness of the first transparent conductive film 40. In this way, the thickness of the part of the second transparent conductive film 50 located on the textured area 122 is set to be small, which can reduce the parasitic absorption at the textured area 122 when the light enters the back surface 12, and improve the bifaciality of the back contact cell 100. At the same time, part of the back surface 12 is set to be textured, which can further reduce the reflectivity of the light on the back surface 12, thereby further improving the bifaciality.

[0055] That is to say, in the present disclosure, part of the back surface 12 is set as the textured area 122, and the thickness of the second transparent conductive film 50 corresponding to the part of the textured area 122 is set to be smaller. Through such an optimized design, the bifaciality of the back contact cell 100 can be improved.

[0056] Specifically, in the embodiments of the present disclosure, the silicon substrate 10 can be an N-type silicon substrate or a P-type silicon substrate, and the specific type is not limited herein. The first polarity doped layer 22 can be an N-type doped layer, and the second polarity doped layer 32 can be a P-type doped layer, or the first polarity doped layer 22 is a P-type doped layer, and the second polarity doped layer 32 is a P-type doped layer, and the specific type is not limited herein, as long as the two are of opposite polarity. In addition, in the back contact cell of the present disclosure, a first electrode (not shown in the figure) can be further arranged on the first transparent conductive film 40, and a second electrode (not shown in the figure) can be further arranged on the second transparent conductive film 50, and the current collection, confluence and output can be realized through the first electrode and the second electrode.

[0057] The first transparent conductive film 40 and the second transparent conductive film 50 can both be a film layer with both light transmission and conductivity, such as a TCO film layer, and the specific type is not limited herein, which can be a single film layer or a multi-layer composite film layer.

[0058] In the present disclosure, the back contact cell 100 can be a hybrid back contact cell, the first passivation layer 21 can be a tunneling oxide layer, for example, a tunneling silicon oxide layer, and the first polarity doped layer 22 can be a doped polysilicon layer. The second passivation layer 31 can be at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer (for example, a tunneling silicon oxide layer), and the second polarity doped layer 32 can be at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer.

[0059] In this case, the first passivation contact structure 20 is a tunneling passivation contact structure, and the second passivation contact structure 30 is a heterojunction passivation contact structure. In this way, by designing the first polarity doped layer 22 as a doped polysilicon layer and the second polarity doped layer 32 as at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer, a hybrid back contact cell 100 can be formed, and the efficiency of the back contact cell 100 can be improved.

[0060] At the same time, the region corresponding to the doped polysilicon is set as the polished area 121, which can avoid the passivation effect of the region corresponding to the doped polysilicon being greatly reduced and affecting the efficiency, while the passivation effect of at least one of the doped amorphous silicon and the doped microcrystalline silicon is better, and the region corresponding to the doped amorphous silicon or the doped microcrystalline silicon is set as the textured area, which can improve the antireflection effect of the back surface 12 and further improve the bifaciality of the back contact cell 100. That is to say, in this case, the bifaciality of the back contact cell 100 can be further improved while ensuring the passivation effect of the region corresponding to the first polarity doped layer 22.

[0061] In some embodiments, the first polarity doped layer 22 can be a P-type doped polysilicon layer, and the second polarity doped layer 32 can be at least one of an N-type doped amorphous silicon layer and an N-type doped microcrystalline silicon layer. Of course, in other embodiments, the first polarity doped layer 22 can be an N-type doped polysilicon layer, and the second polarity doped layer 32 can be at least one of a P-type doped amorphous silicon layer and a P-type doped microcrystalline silicon layer, which is not limited herein specifically.

[0062] In some embodiments, the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122 can be 75-85 nm.

[0063] In this way, by setting the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122 within this reasonable range, the difficulty of manufacturing the portion of the second transparent conductive thin film 50 corresponding to the textured region 122 can be avoided due to its too small thickness, and the passivation effect of the second polarity doped layer 32 can be avoided due to its too small thickness, while the cost can be avoided due to its too large thickness. That is, by setting the thickness within the above reasonable range, the parasitic absorption of the back surface can be reduced, and the bifaciality can be improved, while reducing the process difficulty, ensuring the passivation effect, and controlling the cost.

[0064] Specifically, in such embodiments, the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122 can be, for example, one of 75 nm, 76 nm, 77 nm, 78 nm, 79 nm, 80 nm, 81 nm, 82 nm, 83 nm, 84 nm, and 85 nm, which is not limited herein specifically.

[0065] In some embodiments, the thickness of the first transparent conductive thin film 40 can be 90-155 nm.

[0066] In this way, by setting the thickness of the first transparent conductive thin film 40 within this reasonable range, the difficulty of manufacturing the portion of the first transparent conductive thin film 40 corresponding to the polished region 121 can be avoided due to its too small thickness, and the passivation effect of the first polarity doped layer 22 can be avoided due to its too small thickness, while the cost can be avoided due to its too large thickness.

[0067] Specifically, in such embodiments, the thickness of the portion of the first transparent conductive thin film 40 corresponding to the polished region 121 can be, for example, one of 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, and 155 nm, which is not limited herein specifically.

[0068] In some embodiments, the ratio between the thickness of the first transparent conductive thin film 40 and the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured area 122 is 1.2-1.8.

[0069] In this way, by setting the ratio between the thickness of the first transparent conductive thin film 40 and the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured area 122 within this reasonable range, the parasitic absorption and passivation effects of the back surface 12 can be optimally matched.

[0070] Specifically, in such embodiments, the ratio between the two can be, for example, one of the following: 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, and 1.8, etc., without being particularly limited here.

[0071] Referring to FIG. 3, in some embodiments, the first polarity-doped layer 22 and the second polarity-doped layer 32 are adjacent in the first direction. That is, the polished area 121 and the textured area 122 are continuous and adjacent in the first direction, and the first polarity-doped layer 22 and the second polarity-doped layer 32 are in contact.

[0072] In this way, the area of the back surface 12 of the silicon substrate 10 that is not covered by the first polarity-doped layer 22 and the second polarity-doped layer 32 (i.e., the area of the undoped region) can be reduced as much as possible, thereby improving the efficiency of the back contact cell 100.

[0073] Specifically, in such embodiments, the first polarity-doped layer 22 can be a doped polysilicon layer, and the second polarity-doped layer 32 can be at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer, which have poor lateral conductivity. Therefore, in order to improve the efficiency, the first polarity-doped layer 22 and the second polarity-doped layer 32 can be arranged to be adjacent.

[0074] Of course, as shown in FIG. 4, in other embodiments, the first polarity-doped layer 22 and the second polarity-doped layer 32 can also be arranged to be spaced apart in the first direction, and can have a spacing area therebetween or be separated by other intermediate film layers, without being particularly limited here.

[0075] Further, referring to FIGS. 3 and 4, in some embodiments, the first transparent conductive thin film 40 can be arranged to be stacked only on the first polarity-doped layer 22, the second passivation layer 31 and the second polarity-doped layer 32 can be arranged to be stacked only on the textured area 122, and the second transparent conductive thin film 50 can be arranged to be stacked only on the second polarity-doped layer 32.

[0076] In this way, the insulation performance between the first transparent conductive thin film 40 and the second transparent conductive thin film 50 can be improved, and electrical leakage can be avoided.

[0077] Specifically, in such embodiments, as shown in FIG. 3, when the first polarity doped layer 22 and the second polarity doped layer 32 are adjacent, the first transparent conductive film 40 can cover most of the area of the first polarity doped layer 22, and the second transparent conductive film 50 can completely cover the second polarity doped layer 32 or cover most of the area of the second polarity doped layer 32, in which case, the spacing between the two transparent conductive films can be controlled by controlling the size of the area covered by the two transparent conductive films, thereby ensuring the insulation performance of the two.

[0078] As shown in FIG. 4, when the first polarity doped layer 22 and the second polarity doped layer 32 are spaced apart, the first transparent conductive film 40 can completely cover the first polarity doped layer 22 or cover most of the area of the first polarity doped layer 22, and the second transparent conductive film 50 can completely cover the second polarity doped layer 32 or cover most of the area of the second polarity doped layer 32, in which case, the spacing between the two transparent conductive films can be controlled by controlling the size of the area covered by the two adjacent first polarity doped layers 22 and second polarity doped layers 32, thereby ensuring the insulation performance of the two.

[0079] In some embodiments, the first polarity doped layer 22 can be a base region doped layer, and the second polarity doped layer 32 can be an emitter doped layer, and the sum of the areas of the orthogonal projections of all the second polarity doped layers 32 on the silicon substrate 10 is greater than the sum of the areas of the orthogonal projections of all the first polarity doped layers 22 on the silicon substrate 10.

[0080] In this way, the area of the emitter in the back contact cell 100 can be increased, thereby improving the efficiency of the back contact.

[0081] Specifically, in such embodiments, when the silicon substrate 10 is an N-type silicon substrate 10, the first polarity doped layer 22 is an N-type doped layer, and the second polarity doped layer 32 is a P-type doped layer, and when the silicon substrate 10 is a P-type silicon substrate 10, the first polarity doped layer 22 is a P-type doped layer, and the second polarity doped layer 32 is an N-type doped layer.

[0082] Further, in such embodiments, the ratio of the sum of the areas of the orthogonal projections of all the second polarity doped layers 32 on the silicon substrate 10 to the area of the back surface 12 is 65%-85%, and the ratio of the sum of the areas of the orthogonal projections of all the first polarity doped layers 22 on the silicon substrate 10 to the area of the back surface 12 is 15%-35%.

[0083] In this way, by setting the area ratio of the first polarity doped layer 22 and the second polarity doped layer 32 within the above reasonable range, the area of the emitter region can be increased while ensuring the area ratio of the base region, thereby further optimizing the efficiency of the back contact cell 100.

[0084] Specifically, in such embodiments, the ratio of the sum of the areas of the positive projections of all the second-polarity doped layers 32 on the silicon substrate 10 to the area of the back surface 12 can be, for example, one of the following: 65%, 70%, 75%, 80%, and 85%, etc., without being particularly limited here. The ratio of the sum of the areas of the positive projections of all the first-polarity doped layers 22 on the silicon substrate 10 to the area of the back surface 12 can be, for example, one of the following: 15%, 20%, 25%, 30%, and 35%, etc., without being particularly limited here.

[0085] It can be understood that, in such embodiments, when the first-polarity doped layers 22 completely cover the polished regions 121 and the second-polarity doped layers 32 completely cover the textured regions 122, the sum of the areas of all the textured regions 122 is greater than the sum of the areas of all the polished regions 121. In such cases, the ratio of the sum of the areas of all the textured regions 122 to the area of the back surface 12 is 65%-85%, and the ratio of the sum of the areas of all the polished regions 121 to the area of the back surface 12 is 15%-35%.

[0086] Referring to FIGS. 5 and 6, in some embodiments, at the preset positions 320 of at least part of the second passivation contact structures 30, the second passivation layer 31 has a passivation extension 311 extending to cover part of the area of the first-polarity doped layer 22, and the second-polarity doped layer 32 has a doped extension 321 extending to cover the passivation extension 311, so as to form a stack structure 60 of the first passivation layer 21, the first-polarity doped layer 22, the passivation extension 311, and the doped extension 321 in sequence on part of the polished region 121.

[0087] The second transparent conductive film 50 has a film extension 51 extending to cover at least part of the area of the doped extension 321, and the first transparent conductive film 40 is at least arranged in layers on the area of the first-polarity doped layer 22 that is not covered by the passivation extension 311 and the doped extension 321.

[0088] In this way, by the extension of the stack structure 60 and the second transparent conductive film 50, the back contact cell 100 can form a leakage channel at the position of the stack structure 60, thereby forming a leakage point in the thickness direction, reducing the reverse breakdown voltage when the back contact cell 100 is shaded, and thus improving the hot spot resistance of the back contact cell 100 and reducing the risk of hot spots of the cell module 200.

[0089] Specifically, the doped extension 321 forms a leakage contact with the first-polarity doped layer 22 at the stack structure 60, and the stack structure 60 is a leakage contact structure. On the doped extension 321, the area covered by the film extension 51 is an effective leakage area, and the area not covered by the second transparent conductive film 50 is an ineffective leakage area. In the back contact cell 100, only the effective leakage area can function to improve the hot spot resistance.

[0090] In such embodiments, the first polarity doped layer 22 is a doped polysilicon layer, preferably an N-type doped polysilicon layer, and the second polarity doped layer 32 is at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer, preferably at least one of a P-type doped amorphous silicon layer and a P-type doped microcrystalline silicon layer.

[0091] In addition, as shown in FIG. 5, in embodiments of the present disclosure, in the back contact cell 100, all of the second polarity doped layers 32 can have a preset position 320, that is, all of the second polarity doped layers can have a doped extension 321 extending onto the first polarity doped layer 22 at the preset position 320, or only part of the second polarity doped layers 32 can have a doped extension 321 extending onto the first polarity doped layer 22 at the preset position 320, which is not limited herein and only needs to ensure that the leakage contact area formed by the doped extension 321 and the first polarity doped layer 22 does not cause a significant reduction in the efficiency of the back contact cell 100.

[0092] In addition, for a single second polarity doped layer 32, the single second polarity doped layer 32 can have multiple doped extensions 321, thereby forming multiple stacked structures 60 on a single polishing region 121. When a single second polarity doped layer 32 has multiple doped extensions 321, the multiple doped extensions 321 can be arranged at intervals along the second direction, which is not limited herein.

[0093] In addition, in some embodiments, for a single second polarity doped layer 32, the doped extension 321 can be formed on only one side or on both sides, which is not limited herein. FIG. 5 shows that the second polarity doped layer 32 has a doped extension 321 on both sides, and FIG. 6 shows that the second polarity doped layer 32 has a doped extension 321 on only one side, but this is not limited in the present disclosure.

[0094] In some embodiments, the thickness of the thin film extension 51 is greater than the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122. Preferably, the thickness of the thin film extension 51 can be the same as the thickness of the first transparent conductive thin film 40.

[0095] In this way, the thickness of the first transparent conductive thin film 40 and the thin film extension 51 located on the first polarity doped layer 22 is set to be relatively thick, which can improve the passivation effect of the corresponding region of the first polarity doped layer 22, and the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122 is set to be relatively thin, which can reduce parasitic absorption while efficiently passivating the corresponding region of the doped amorphous silicon or doped microcrystalline silicon, thereby improving the bifaciality.

[0096] Referring to FIG. 3, in some embodiments, the length L1 of the doped extension 321 in the first direction can be 10 μm-600 μm, and the length L2 of the doped extension 321 in the second direction can be 10 μm-5000 μm.

[0097] In this way, by properly setting the length of the doped extension 321 in each direction, the area of the doped extension 321 can be controlled to be within a reasonable range, so as to control the effective leakage contact area of a single doped extension 321 within a reasonable range, avoid the leakage contact area being too small to cause the anti-hot spot performance to fail to achieve the expected effect, and also avoid the leakage contact area being too large to cause excessive loss of efficiency, that is, such a setting can balance the relationship between the anti-hot spot performance and the efficiency, so as to achieve a relatively optimal matching effect.

[0098] Specifically, in such embodiments, the length L1 of the doped extension 321 in the first direction can be, for example, one of the following: 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, and 600 μm, etc.

[0099] The length L2 of the doped extension 321 in the second direction can be, for example, one of the following: 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, 800 μm, 850 μm, 900 μm, 950 μm, 1000 μm, 1500 μm, 2000 μm, 2500 μm, 3000 μm, 3500 μm, 4000 μm, 4500 μm, and 5000 μm, etc.

[0100] Further, in such embodiments, the length L1 of the doped extension 321 in the first direction is preferably 10 μm-150 μm, and the length L2 of the doped extension 321 in the second direction is preferably 20 μm-500 μm.

[0101] In some embodiments, the length of the thin film extension 51 in the first direction is greater than or equal to 10 μm.

[0102] In this way, the extension length of the thin film extension 51 can be avoided to be too small to cause poor anti-hot spot performance.

[0103] Further, in such embodiments, the ratio between the length of the thin film extension 51 in the first direction and the length of the doped extension 321 in the first direction is greater than 90%, for example any one of the following: 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, and 99%, etc.

[0104] In this way, by setting the ratio between the length of the thin film extension 51 and the length of the doped extension 321 in the range of greater than 90%, the anti-hot spot performance can be effectively improved while ensuring the conversion efficiency.

[0105] Specifically, as described above, in some embodiments, the length of the doped extension 321 in the first direction is 10 μm-600 μm, preferably 10 μm-150 μm, then in the present embodiments, the minimum value of the length of the portion of the second transparent conductive thin film 50 extending onto the doped extension 321 in the first direction is greater than 9 μm, and the maximum value can be greater than 540 μm and less than or equal to 600 μm, preferably greater than 135 μm and less than 150 μm.

[0106] Referring to FIG. 5, in some embodiments, on a single second-polarity doped layer 32, the number of doped extensions 321 can be multiple, and the multiple doped extensions 321 are arranged at intervals in the second direction. That is, on one side of the second-polarity doped layer 32 in the second direction, there are multiple doped extensions 321 arranged at intervals.

[0107] In this way, by arranging multiple isolated doped extensions 321 on the second-polarity doped layer 32, the excessive contact area of the leakage current on a single second-polarity doped layer 32 can be avoided, and the excessive loss of efficiency can be avoided.

[0108] It can be understood that, in some embodiments, when the second-polarity doped layer 32 forms a leakage current contact with both of the adjacent first-polarity doped layers 22, the second-polarity doped layer 32 forms a doped extension 321 on both sides thereof in the first direction, and when the second-polarity doped layer 32 forms a leakage current contact with only one first-polarity doped layer 22, the second-polarity doped layer 32 forms a doped extension 321 on only one side thereof in the first direction.

[0109] Further, as shown in FIG. 5, in some embodiments, in the second direction, the distance H1 between the adjacent two doped extensions 321 is 1 cm-10 cm.

[0110] In this way, the excessive concentration of the leakage current points due to the too small distance H1 between the adjacent two doped extensions 321 can be avoided, and the excessive heat generated by the excessive concentration of the leakage current points can be dissipated in time, so that the temperature does not rise sharply.

[0111] Specifically, in such embodiments, the distance H1 between two adjacent doping extensions 321 can be, for example, one of the following: 1 cm, 1.5 cm, 2 cm, 2.5 cm, 3 cm, 3.5 cm, 4 cm, 4.5 cm, 5 cm, 5.5 cm, 6 cm, 6.5 cm, 7 cm, 7.5 cm, 8 cm, 8.5 cm, 9 cm, 9.5 cm, and 10 cm, etc.

[0112] Further, in such embodiments, in the second direction, the distance H1 between two adjacent doping extensions 321 is preferably greater than or equal to 2 cm and less than 4 cm.

[0113] In this way, through the research and demonstration of the present inventor, by setting the distance within this preferred range, the heat can be most avoided from being too concentrated when the number of doping extensions 321 is set to be relatively large, that is, the balance between the heat spot resistance and the heat being too concentrated can be achieved to the optimal matching effect.

[0114] Specifically, in such embodiments, the distance H1 between two adjacent doping extensions 321 can be, for example, one of the following: 2 cm, 2.2 cm, 2.4 cm, 2.6 cm, 2.8 cm, 3 cm, 3.1 cm, 3.2 cm, 3.3 cm, 3.4 cm, 3.5 cm, 3.6 cm, 3.7 cm, 3.9 cm, and 3.95 cm.

[0115] In some embodiments, in the back contact cell 100, the distribution density of the doping extensions 321 is 0.01 2 -1.5 / cm 2 In this way, by reasonably controlling the distribution density of the doping extensions 321, it can avoid the leakage points from being too concentrated.

[0116] In such embodiments, the distribution density of the doping extensions 321 refers to the ratio between the sum of the number of the doping extensions 321 on the back contact cell 100 and the area of the back surface 12 of the back contact cell 100. Specifically, the distribution density of the doping extensions 321 can be, for example, one of the following: 0.01 2 / cm 2 , 0.1 2 / cm 2 , 0.2 2 / cm 2 , 0.3 2 / cm 2 , 0.4 2 / cm 2 , 0.5 / cm , 0.6 / cm , 0.7 / cm , 0.8 / cm , 0.9 / cm , and 1.0 / cm , etc.0.9 / cm 2 1 / cm 2 1.1 / cm 2 1.2 / cm 2 1.3 / cm 2 1.4 / cm 2 and 1.5 / cm 2 and so on.

[0117] In some embodiments, in the single doped extension 321, the area of the thin film extension 51 is 100 μm 2 - 50000 μm 2 .

[0118] In this way, by controlling the area of the thin film extension 51 to be within this reasonable range, the heat spot resistance can be improved while ensuring that the efficiency loss is not too large.

[0119] Specifically, in such embodiments, the area of a single thin film extension 51 can be, for example, one of: 100 μm 2 , 200 μm 2 , 300 μm 2 , 350 μm 2 , 400 μm 2 , 450 μm 2 , 480 μm 2 , 500 μm 2 , 600 μm 2 , 700 μm 2 , 800 μm 2 , 900 μm 2 , 1000 μm 2 , 1100 μm 2 , 1200 μm 2 , 1300 μm 2 , 1400 μm 2 , 1500 μm 2 , 2000 μm 2 , 3000 μm 2 , 4000 μm 2 , 5000 μm 2 , 6000 μm 2 , 7000 μm 2 , 8000 μm 2 , 9000 μm 2 , 10000 μm 2 , 15000 μm 2 , 20000 μm 2 , 25000 μm 2 , 30000 μm 235000 pm 2 40000 pm 2 45000 pm 2 and 50000 pm 2 etc.

[0120] In some embodiments, in the back contact cell 100, the ratio of the sum of the areas of all the thin film extensions 51 (i.e. the sum of the effective leakage areas on the respective doped extensions 321 in the back contact cell 100) to the area of the back surface 12 is 1.5*10 -8 -1.5*10 -5 .

[0121] In this way, by setting the ratio of the sum of the areas of all the thin film extensions 51 to the area of the back surface 12 within this reasonable range, the area ratio of the leakage contact can be prevented from being too large to seriously affect the efficiency of the back contact cell 100, i.e. the efficiency of the back contact cell 100 can be ensured while the anti-hot spot performance is ensured.

[0122] Specifically, in such embodiments, the area ratio of the two can be, for example, one of the following: 1.5*10 -8 , 2*10 -8 , 2.5*10 -8 , 3.5*10 -8 , 4.5*10 -8 , 4.5*10 -8 , 5*10 -8 , 6*10 -8 , 7*10 -8 , 8*10 -8 , 9*10 -8 , 1*10 -7 , 1*10 -6 , 1*10 -5 and 1.5*10 -5 , etc., without being specifically limited thereto. In some embodiments, the ratio between the two can be preferably greater than 1.5*10 -8 and less than 4.5*10 -8 .

[0123] In the description of the present specification, the description referring to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments or examples.

[0124] In addition, the above only describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A back contact cell, comprising: a silicon substrate having opposite front and back surfaces, the back surface comprising a plurality of polished regions and a plurality of textured regions arranged alternately along a first direction, the polished and textured regions each extending along a second direction intersecting the first direction; a first passivated contact structure comprising a first passivation layer and a first polarity doped layer stacked successively on the polished regions; a second passivated contact structure comprising a second passivation layer and a second polarity doped layer stacked successively on the textured regions, the second passivation layer and the second polarity doped layer covering at least the textured regions; and a first transparent conductive film stacked on and covering at least part of the first polarity doped layer, and a second transparent conductive film stacked on and covering at least part of the second polarity doped layer corresponding to the textured regions, the second transparent conductive film being spaced apart from the first transparent conductive film, the second transparent conductive film corresponding to the textured regions having a thickness smaller than that of the first transparent conductive film.

2. The back contact cell of claim 1, wherein, The first passivation layer is a tunneling oxide layer, and the first polarity doped layer is a doped polysilicon layer. The second passivation layer is at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer, and the second polarity doped layer is at least one of a doped amorphous silicon layer or a doped microcrystalline silicon layer.

3. The back contact cell of claim 1, wherein, The second transparent conductive film corresponding to the textured regions has a thickness of 75-85 nm.

4. The back contact cell of claim 1, wherein, The first transparent conductive film has a thickness of 90-155 nm.

5. The back contact cell of claim 1, wherein, The ratio between the thickness of the first transparent conductive film and the thickness of the second transparent conductive film corresponding to the textured regions is 1.2-1.

8.

6. The back contact cell of claim 1, wherein, The first polarity doped layer and the second polarity doped layer are adjacent in the first direction; or The first polarity doped layer and the second polarity doped layer are spaced apart in the first direction.

7. The back contact cell of claim 6, wherein, The first transparent conductive film is stacked only on the first polarity doped layer, and the second passivation layer and the second polarity doped layer are stacked only on the textured regions, and the second transparent conductive film is stacked only on the second polarity doped layer.

8. The back contact cell of claim 1, wherein, The first polarity doped layer is a base doped layer, and the second polarity doped layer is an emitter doped layer, the sum of the areas of the orthographic projections of all the second polarity doped layers on the silicon substrate being greater than the sum of the areas of the orthographic projections of all the first polarity doped layers on the silicon substrate.

9. The back contact cell of claim 8, wherein, The ratio between the sum of the areas of the orthographic projections of all the second polarity doped layers on the silicon substrate and the area of the back surface is 65-85%.

10. The back contact cell of claim 1, wherein, At a preset position of at least part of the second passivation contact structure, the second passivation layer has a passivation extension extending over part of the area of the first polarity doped layer, and the second polarity doped layer has a doped extension extending over the passivation extension, thereby forming a stack structure of the first passivation layer, the first polarity doped layer, the passivation extension and the doped extension in sequence on part of the polished area; The second transparent conductive film has a film extension extending over at least part of the area of the doped extension, and the first transparent conductive film is at least layer-stacked on the area of the first polarity doped layer not covered by the passivation extension and the doped extension.

11. The back contact cell of claim 10, wherein, The thickness of the film extension is greater than the thickness of the part of the second transparent conductive film corresponding to the textured area.

12. The back contact cell of claim 10, wherein, The thickness of the film extension is the same as the thickness of the first transparent conductive film.

13. A battery assembly comprising a plurality of back contact cells according to any one of claims 1-12.

14. A photovoltaic system comprising the battery assembly according to claim 13.

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