Rear-surface-passivated CIGS single-junction cell and interconnected cells thereof and preparation method therefor, and CIGS / PVK double-junction tandem cell and preparation method therefor

Abstract

Provided in the present invention are a rear-surface-passivated CIGS single-junction cell and interconnected cells thereof and a preparation method therefor, and a CIGS / PVK double-junction tandem cell and a preparation method therefor. The CIGS single-junction cell comprises a substrate, and a back electrode, an absorption layer, a buffer layer, a high barrier layer, a front electrode and grid lines which are sequentially formed, wherein a discontinuous passivation layer is deposited between the back electrode and the absorption layer. The preparation method for the CIGS single-junction cell comprises: depositing a back electrode on a substrate; forming a suspension from nanoparticles, coating the suspension onto the back electrode to form a wet film, and conducting annealing, so as to form a passivation layer; and sequentially depositing an absorption layer, a buffer layer, a high barrier layer, a front electrode layer and grid lines on the passivation layer. The CIGS / PVK double-junction tandem cell comprises a bottom CIGS single-junction cell and a top perovskite cell, the two forming an integral body by means of the interconnection of two or four internal ends thereof. Further provided in the present invention is a passivation method for interconnected CIGS single-junction cells. P1, P2 and P3 scribe lines are arranged inside the CIGS single-junction cell. The rear-surface-passivated cell provided by the present invention reduces rear surface recombination and improves photoelectric efficiency.

Description

A back interface passivated CIGS single-junction cell, an interconnected cell and a preparation method thereof, and a CIGS / PVK double-junction stacked cell and a preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cell manufacturing, in particular to a back interface passivated CIGS single-junction cell and an interconnected method and a preparation method thereof, and a CIGS / PVK double-junction stacked cell and a preparation method thereof. BACKGROUND

[0002] Interface passivation has been widely used in crystalline silicon cells, mainly through laser sintering to prepare micron to tens of microns of pattern structure, and different passivation schemes are controlled to develop different component technologies, which have been widely used in industrialization. Thin film cells. Because the carrier lifetime is short and the diffusion distance is short, point contact passivation technology in the sub-micron to nanometer range is needed, mainly including nanoimprint and electron beam etching, which has high cost, and there is no back interface passivation technology that can be used for commercialization.

[0003] CN 112786713B realizes point contact between the CIGS absorber layer and the back electrode through the hole structure on the passivation layer, improves the conversion efficiency, and it is difficult to control the coverage or spacing of the point contact, and the low-melting-point metal diffuses to the CIGS layer, introduces new components, which is not easy to control and may have adverse effects on the crystallinity of the absorber layer.

[0004] CN115911141A sets a low-resistance layer between the n+ type layer and the p type layer to prevent the n+ type layer and the p type layer from forming a reverse junction; an interface passivation layer is arranged on the p type layer; the surface of the n+ type layer is treated to remove surface contaminants, thereby improving the open-circuit voltage Voc and the fill factor FF of the stacked cell as a whole, improving the overall performance of the stacked cell, and improving the conversion efficiency. However, the back electrode layer of the bottom cell and the low-resistance layer below the P-type layer of the top cell are not provided with a back field point contact passivation structure, which cannot reduce the carrier recombination at the interface, thereby limiting the photoelectric performance of the cell. SUMMARY

[0005] In order to solve the problem of the photoelectric performance of the cell in the prior art, the present application provides a back interface passivated CIGS single-junction cell and an interconnected method and a preparation method thereof, and a CIGS / PVK double-junction stacked cell and a preparation method thereof.

[0006] In order to achieve the purpose of the present application, the technical scheme adopted by the present application is as follows:

[0007] In a first aspect, the present application provides a back interface passivated CIGS single-junction cell, which comprises a substrate and a back electrode, an absorber layer, a buffer layer, a high-resistance layer, a front electrode and a gate line formed in sequence on the substrate;

[0008] wherein a passivation layer is deposited between the back electrode and the absorber layer, the passivation layer is a discontinuous passivation layer formed by nanoparticles, the coverage of the passivation layer on the back electrode is 5% to 75%, preferably 8% to 65%. For example, 20%, 30%, 40%, 50%, 60%.

[0009] In some specific embodiments, the nanoparticles forming the passivation layer are selected from Al2O3, SiO2, SrO2 or MoO x .

[0010] The second aspect of the present application provides a method for preparing the above-mentioned back interface passivated CIGS single-junction cell, comprising:

[0011] (1) depositing a back electrode on a substrate;

[0012] (2) dispersing nanoparticles into a solvent to form a suspension, coating the suspension onto the back electrode to form a wet film, and forming a passivation layer after annealing and drying;

[0013] (3) sequentially depositing an absorber layer, a buffer layer, a high resistance layer and a front electrode layer on the passivation layer to obtain the back interface passivated CIGS single-junction cell;

[0014] wherein the size of the nanoparticles in the suspension is 5 to 1000 nm, preferably 50 to 500 nm, and the concentration is 0.1 to 200 mg / ml, preferably 0.3 to 10 mg / ml.

[0015] In some specific embodiments, in step (1), a back electrode is deposited on a substrate by using a magnetron sputtering process or an evaporation process, and the thickness of the back electrode is 100 to 1000 nm.

[0016] Preferably, the substrate is glass, ceramic, metal foil or polymer material, specifically, the metal foil is, for example, stainless steel foil, titanium foil, and the polymer material is, for example, PI, PEN or PET; and the material of the back electrode is Mo, ITO, AZO or FTO.

[0017] In some specific embodiments, in step (2), the suspension is coated onto the back electrode by using a spin coating, spray coating or slot coating method.

[0018] Preferably, the solvent is selected from an alcohol solvent or water.

[0019] Preferably, the annealing temperature is 80°C to 300°C.

[0020] In some specific embodiments, in step (3), the absorbing layer is deposited on the passivation layer by a thermal evaporation process; preferably, the thickness of the absorbing layer is 0.9-2.5 μm; more preferably, the absorbing layer is Cu x (In 1-y Ga y )Se2, wherein x is 0.5-0.99, preferably 0.7-0.95, and y is 0-1, preferably 0.1-0.5;

[0021] The buffer layer is deposited by a water bath or a magnetron sputtering process; preferably, the thickness of the buffer layer is 10-70 nm; more preferably, the buffer layer is CdS or Zn(O, S);

[0022] The high-resistance layer and the front electrode layer are deposited by a magnetron sputtering process; preferably, the thickness of the high-resistance layer is 10-50 nm, and the thickness of the front electrode layer is 20-500 nm; more preferably, the high-resistance layer is intrinsic ZnO or ZnMgO, and the front electrode layer is ITO, IZO or AZO;

[0023] The grid lines are prepared by a screen printing process, and the thickness of the grid lines is 0.5-100 μm, the line width is 15-120 μm, and the material is Cu, Al or Ag.

[0024] In a third aspect, the present application provides a back interface passivated CIGS / PVK double-junction tandem cell, which comprises a bottom cell selected from the above CIGS single-junction cell and a perovskite top cell, and the bottom cell and the top cell are integrated by internal two-terminal interconnection or four-terminal interconnection;

[0025] The top cell comprises, in sequence, a hole transport layer, an interface modification layer, a perovskite absorbing layer, an electron transport layer, an electron buffer layer, a front electrode layer and grid lines;

[0026] A passivation layer is deposited between the front electrode of the bottom cell and the hole transport layer of the top cell, and the passivation layer is a discontinuous passivation layer formed by nanoparticles, and the coverage of the passivation layer on the back electrode is 5%-75%, preferably 8%-65%.

[0027] In a fourth aspect, the present application provides a preparation method of a back interface passivated CIGS / PVK double-junction tandem cell, which comprises: using the above preparation method to prepare a CIGS single-junction cell as a bottom cell, and

[0028] (4) dispersing the nanoparticles into a solvent to form a suspension, coating the suspension onto the front electrode of the bottom cell to form a wet film, and forming a passivation layer after annealing and drying;

[0029] (5) depositing a hole transport layer, an interface modification layer, a perovskite absorption layer, an electron transport layer, an electron buffer layer, a front electrode layer and a grid line on the passivation layer formed in step (4) in sequence to obtain the interface-passivated CIGS / PVK double-junction stacked cell;

[0030] wherein the size of the nanoparticles in the suspension prepared in step (4) is 5-1000 nm, preferably 50-500 nm, and the concentration is 0.1-200 mg / ml, preferably 0.3-10 mg / ml.

[0031] In some specific embodiments, in step (4), the suspension is coated on the front electrode of the bottom cell by spin coating, spray coating or slot coating;

[0032] Preferably, the solvent is selected from alcohol solvents or water.

[0033] Preferably, the annealing temperature is 80-300°C.

[0034] In some specific embodiments, in step (5), the hole transport layer is deposited on the passivation layer by coating or thermal evaporation process, preferably, the thickness of the hole transport layer is 5-50 nm, and the hole transport layer is NiOx.

[0035] Preferably, the interface modification layer is deposited by spin coating, slot coating or spray coating process, preferably, the interface modification layer is a monolayer of SAM molecules.

[0036] Preferably, the perovskite absorption layer is deposited by one or more of thermal evaporation, slot coating and / or spray coating process, preferably, the thickness of the perovskite absorption layer is 200-1200 nm, more preferably, the perovskite absorption layer is Cs x (FA 1-y MA y ) 1-x Pb(I 1-z-i Br z Cl i )3, wherein x is 0.01-0.25, y is 0.05-0.35, z is 0-0.35, and i is 0-0.35.

[0037] Preferably, the electron transport layer is deposited by coating or thermal evaporation process, preferably, the thickness of the electron transport layer is 5-50 nm, more preferably, the electron transport layer is C60 or PCBM.

[0038] Preferably, the electron buffer layer is deposited by atomic layer deposition or coating process, preferably, the thickness of the electron buffer layer is 5-50 nm, more preferably, the electron buffer layer is SnO2 or BCP.

[0039] Preferably, the front electrode layer is deposited by a magnetron sputtering process, preferably, the thickness of the front electrode layer is 20-200 nm, more preferably, the front electrode layer is ITO, IZO or AZO;

[0040] Preferably, the gate line is prepared by a screen printing process, the thickness of the gate line is 0.5-100 μm, the line width is 15-100 μm, and the material is Cu, Al or Ag.

[0041] The fifth aspect of the present application provides a back interface passivation method of a CIGS single-junction interconnection cell, wherein the CIGS single-junction cell is the CIGS single-junction cell described above or the CIGS single-junction cell prepared by the preparation method described above.

[0042] The P1 scribe line, the P2 scribe line and the P3 scribe line are respectively arranged in the CIGS single-junction cell, the P1 scribe line, the P2 scribe line and the P3 scribe line are respectively formed by laser scribing, and the interconnection method comprises the following steps:

[0043] (1) after depositing the back electrode on the substrate, the back electrode is processed by laser for the first time to form the P1 scribe line by using laser scribing;

[0044] (2) the nanoparticles are dispersed into a solvent to form a suspension, the suspension is coated on the back electrode with the processed P1 scribe line to form a wet film, and after annealing and drying, a passivation layer is formed;

[0045] (3) the absorption layer, the buffer layer and the high-resistance layer are sequentially deposited on the passivation layer which has been solidified, the P2 scribe line is formed by laser processing for the second time on the high-resistance layer;

[0046] (4) the front electrode layer is deposited on the high-resistance layer with the processed P2 scribe line, and the P3 scribe line is formed by laser processing for the third time on the front electrode layer, and then the interconnection processing process is completed.

[0047] In some specific embodiments, in step (1), the width of the P1 scribe line formed is 60-100 μm;

[0048] Preferably, the first laser is a pulsed laser with a wavelength of 245-1064 nm, preferably a laser with a wavelength of 532 nm or 1064 nm, the scanning speed is 20-2000 mm / sec, preferably 800-1000 mm / sec, the adjusting frequency is 30-80 KHz, preferably 50-60 KHz;

[0049] More preferably, the laser pulse width used by the first laser is picosecond laser.

[0050] In some specific embodiments, in step (2), the size of the nanoparticles in the suspension is 5-1000 nm, preferably 50-500 nm, and the concentration is 0.1-200 mg / ml, preferably 0.3-10 mg / ml.

[0051] More preferably, the suspension is coated on the back electrode with the P1 line by spin coating, spray coating or slot coating.

[0052] In some specific embodiments, in step (3), the width of the P2 line is 40-300 μm, preferably 50-60 μm.

[0053] Preferably, the second laser is a pulsed laser with a wavelength of 245-1064 nm, preferably 1030 nm, a scanning speed of 30-2000 mm / sec, preferably 800-1000 mm / sec, and a modulation frequency of 30-80 KHz, preferably 50-60 KHz.

[0054] More preferably, the second laser uses a picosecond laser.

[0055] Further preferably, the distance between the P1 line and the P2 line is 20-400 μm.

[0056] In some specific embodiments, in step (4), the width of the P3 line is 30-100 μm, preferably 50-60 μm.

[0057] Preferably, the third laser is a pulsed laser with a wavelength of 245-1064 nm, preferably 532 nm, a scanning speed of 20-2000 mm / sec, preferably 800-1000 mm / sec, and a modulation frequency of 30-80 KHz, preferably 50-60 KHz.

[0058] More preferably, the third laser uses a picosecond laser.

[0059] Further preferably, the distance between the P2 line and the P3 line is 20-100 μm.

[0060] The above technical solution has the following technical effects:

[0061] The application provides a back interface passivated CIGS single-junction cell, which coats nanoparticles on the contact surface of CIGS and the back electrode in the cell, controls the coverage of the passivation layer on the back electrode to be between 5% and 75%, reduces the back interface recombination, enhances long-wave absorption, and improves the photoelectric efficiency.

[0062] The application also provides a back interface passivated CIGS / PVK double junction stacked cell, which passivates the back interface of CIGS and perovskite in the passivated stacked cell (CIGS / PVK) by point contact passivation, reduces the back interface recombination, and improves the photoelectric efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0063] Fig. 1 shows a structure schematic diagram of a CIGS single junction cell in an embodiment;

[0064] Fig. 2 shows a structure schematic diagram of a CIGS / PVK double junction stacked cell in an embodiment;

[0065] Fig. 3 shows a structure schematic diagram of a CIGS single junction interconnected cell in an embodiment;

[0066] Fig. 4 shows a structure schematic diagram of a CIGS / PVK double junction stacked cell in another embodiment;

[0067] Fig. 5 shows an SEM cross-sectional view of a CIGS single junction cell in an embodiment;

[0068] Fig. 6 shows an atomic force two-dimensional surface scanning diagram (upper) and its corresponding 8bit pixel extraction diagram (lower) after coating nanoparticles on the back electrode;

[0069] Fig. 7 shows an SEM cross-sectional view of a CIGS single junction cell in another embodiment;

[0070] Fig. 8 shows an external quantum efficiency curve of a CIGS single junction cell;

[0071] Fig. 9 shows an IV curve of a CIGS single junction cell. DETAILED DESCRIPTION

[0072] The specific embodiments of the application are described in detail below. It should be understood that the specific embodiments described herein are merely illustrative and explanatory and are not intended to limit the application.

[0073] The back interface passivated CIGS single junction cell provided by the application includes a substrate and a back electrode, an absorption layer, a buffer layer, a high resistance layer and a front electrode formed on the substrate in sequence; a discontinuous nanoparticle passivation island, i.e., a passivation layer, is formed by coating a nanoparticle suspension on the back electrode, and the coverage of the nanoparticles on the back electrode can reach 5% to 75%, such as 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65% or 70% by controlling the concentration of the nanoparticles and the coating times.

[0074] The CIGS single-junction cell provided by the application introduces a passivation layer structure between its absorption layer and back electrode, chemically passivates the interface between the absorption layer and back electrode, reduces the number of defect states in the Au-semiconductor contact interface, promotes carrier separation, and reduces the recombination of minority carriers. Meanwhile, the passivation layer structure plays a role in limiting light and increasing light absorption. In some specific embodiments, the nanoparticles are selected from Al2O3, SiO2, SrO2, or MoO x .

[0075] The application provides a preparation method of the back interface passivated CIGS single-junction cell, which comprises the following steps:

[0076] (1) depositing a back electrode on a substrate;

[0077] (2) dispersing nanoparticles into a solvent to form a suspension, coating the suspension onto the back electrode to form a wet film, and forming a passivation layer after annealing and drying;

[0078] (3) sequentially depositing an absorption layer, a buffer layer, a high-resistance layer, a front electrode layer, and a gate line on the passivation layer to obtain the back interface passivated CIGS single-junction cell;

[0079] In the suspension, the size of the nanoparticles is 5-1000 nm, preferably 50-500 nm, and the concentration is 0.1-200 mg / ml, preferably 0.3-10 mg / ml.

[0080] In step (1) of the preparation method, a prior art such as a magnetron sputtering process or a thermal evaporation process can be used to deposit a 300-1000 nm back electrode on the substrate. In some specific embodiments, the material of the substrate can be selected from glass, ceramic, metal foil, or polymer material, and specifically, the metal foil is, for example, stainless steel foil or titanium foil, and the polymer material is, for example, PI, PEN, or PET; and the material of the back electrode is Mo, ITO, AZO, or FTO.

[0081] In step (2) of the preparation method, the nanoparticles are ultrasonically dispersed into a solvent (deionized water or alcohol) to form a suspension, and the suspension is coated onto the substrate with the deposited back electrode by means of spin coating, spray coating, or slot coating to form a wet film; and after annealing and drying at 80-300°C, a passivation layer with non-continuous nanoparticle islands is obtained.

[0082] In step (3) of the preparation method, a thermal evaporation process is used to deposit a 0.9-2.5 μm absorption layer on the passivation layer; in some preferred embodiments, the absorption layer is Cu x (In 1-y Ga ySe2, wherein x is in the range of 0.5 to 0.99, preferably 0.7 to 0.95, such as 0.8, 0.9, and y is in the range of 0 to 1, preferably 0.1 to 0.5, such as 0.3.

[0083] In the specific preparation process of the application, a buffer layer with a thickness of 10-70 nm is deposited on the absorption layer by water bath or magnetron sputtering process; in some preferred embodiments, the buffer layer is CdS or Zn(O, S).

[0084] In the specific preparation process of the application, a high-resistance layer with a thickness of 10-50 nm and a front electrode layer with a thickness of 20-150 nm are sequentially deposited on the buffer layer by magnetron sputtering process; preferably, the high-resistance layer is intrinsic ZnO or ZnMgO, and the front electrode layer is ITO, IZO or AZO.

[0085] In some specific embodiments, the gate line is prepared by a screen printing process, the thickness of the gate line is 0.5-100 μm, the line width is 15-120 μm, and the material is Cu, Al or Ag.

[0086] The CIGS / PVK double-junction tandem cell provided by the application comprises a bottom cell of the above CIGS single-junction cell and a perovskite top cell, and the bottom cell and the top cell are integrated by internal two-end interconnection or four-end interconnection;

[0087] The top cell comprises, in sequence, a hole transport layer, an interface modification layer, a perovskite absorption layer, an electron transport layer, an electron buffer layer, a front electrode layer and a gate line;

[0088] A passivation layer is deposited between the front electrode of the bottom cell and the hole transport layer of the top cell, the passivation layer is a discontinuous passivation layer formed by nanoparticles, and the coverage of the passivation layer on the back electrode is 5% to 75%, preferably 8% to 65%, such as 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55% or 60%.

[0089] The CIGS / PVK double-junction tandem cell provided by the application increases the short-circuit current and the fill factor of the tandem cell by introducing nanoparticles at the back interface of the bottom cell and the top cell, thereby improving the photoelectric conversion efficiency of the cell.

[0090] In the method for preparing the CIGS / PVK double-junction tandem cell with passivated back interface, after the CIGS single-junction cell is prepared as a bottom cell according to the above method, the following operation steps are continued on the front electrode layer of the CIGS single-junction cell:

[0091] (4) dispersing the nanoparticles into water or alcohol solvent to form a suspension, coating the suspension onto the front electrode of the bottom cell by spin coating, spray coating or slot coating to form a wet film, and forming a passivation layer after annealing and drying;

[0092] (5) sequentially depositing a hole transport layer, an interface modification layer, a perovskite absorption layer, an electron transport layer, an electron buffer layer, a front electrode layer and a grid line on the passivation layer formed in step (4) to obtain the interface-passivated CIGS / PVK double-junction stacked cell;

[0093] In step (4), the size of the nanoparticles in the suspension is 5-1000 nm, preferably 50-500 nm, such as 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, and the concentration is 0.1-200 mg / ml, preferably 0.3-10 mg / ml.

[0094] In some specific embodiments, a 5-50 nm thick hole transport layer is deposited on the passivation layer by coating or magnetron sputtering process, preferably the hole transport layer is NiOx;

[0095] In some specific embodiments, the interface modification layer is deposited by spin coating, slot coating or spray coating process, preferably the interface modification layer is a monolayer of SAM molecules;

[0096] In some specific embodiments, a 100-1000 nm thick perovskite absorption layer is deposited by one or more of the processes of thermal evaporation, slot coating and / or spray coating, preferably the perovskite absorption layer is Cs x (FA 1-y MA y ) 1-x Pb(I 1-z-i Br z Cl i )3, wherein x is 0.01-0.25, such as 0.1, 0.2, y is 0.05-0.35, such as 0.1, 0.2, 0.3, z is 0-0.35, such as 0.1, 0.2, 0.3; i is 0-0.35, such as 0.1, 0.2, 0.3.

[0097] The electron transport layer is deposited by coating or thermal evaporation process, preferably the thickness of the electron transport layer is 5-50 nm, more preferably the electron transport layer is C60 or PCBM.

[0098] In some specific embodiments, the electron buffer layer is deposited by an atomic layer deposition or coating process, preferably, the thickness of the electron buffer layer is 5-50 nm, more preferably, the electron buffer layer is SnO2 or BCP.

[0099] In some specific embodiments, the front electrode layer is deposited by a magnetron sputtering process, preferably, the thickness of the front electrode layer is 20-200 nm, more preferably, the front electrode layer is ITO, IZO or AZO.

[0100] In some specific embodiments, the gate line is prepared by a screen printing process, the thickness of the gate line is 0.5-100 μm, the line width is 15-100 μm, and the material is Cu, Al or Ag.

[0101] In the back interface passivation method of the CIGS single-junction interconnected battery, the CIGS single-junction battery is the above-mentioned CIGS single-junction battery or the CIGS single-junction battery prepared by the above-mentioned preparation method.

[0102] The P1 scribe line, the P2 scribe line and the P3 scribe line are arranged in the CIGS single-junction battery, respectively, the P1 scribe line, the P2 scribe line and the P3 scribe line are formed by laser scribing, and the interconnection method comprises the following steps.

[0103] (1) After depositing the back electrode on the substrate, the back electrode is subjected to first laser processing by laser scribing to form the P1 scribe line;

[0104] (2) The nanoparticles are dispersed into a solvent to form a suspension, the suspension is coated on the back electrode with the processed P1 scribe line to form a wet film, and after annealing and drying, a passivation layer is formed;

[0105] (3) The absorption layer, the buffer layer and the high-resistance layer are sequentially deposited on the solidified passivation layer, and second laser processing is performed on the high-resistance layer to form the P2 scribe line;

[0106] (4) The front electrode layer is deposited on the high-resistance layer with the processed P2 scribe line, and after third laser processing is performed on the front electrode layer to form the P3 scribe line, the interconnection processing process is completed.

[0107] The back interface passivation method of the CIGS single-junction interconnected battery provided by the application can increase the interface scattering of light, reduce the recombination of carriers at the interface, improve the short-circuit current and the fill factor of the battery, and thus improve the photoelectric conversion efficiency of the battery.

[0108] In the following specific embodiment of the preparation step (1), the width of the P1 scribe line formed is 60-100 μm (according to insulation requirements, the P1 width of a CIGS cell is generally above 90 μm); preferably, the first laser is a pulsed laser with a wavelength of 245-1064 nm, preferably a laser with a wavelength of 532 nm or 1064 nm, the scanning speed is 20-2000 mm / sec, preferably 800-1000 mm / sec, and the modulation frequency is 30-80 KHz, preferably 50-60 KHz.

[0109] In some more preferred embodiments, the laser pulse width used by the first laser is picosecond laser.

[0110] In the specific embodiment of the preparation step (2), the size of the nanoparticles in the suspension is 5-1000 nm, preferably 50-500 nm, and the concentration is 0.1-200 mg / ml, preferably 0.3-10 mg / ml; in some more preferred embodiments, the suspension is coated onto the back electrode of the processed P1 scribe line by spin coating, spray coating or slot coating.

[0111] In the specific embodiment of the preparation step (3), the width of the P2 scribe line formed is 40-300 μm, preferably 50-60 μm, taking into account the dead zone and the conductive requirement; preferably, the second laser is a pulsed laser with a wavelength of 245-1064 nm, preferably a laser with a wavelength of 1030 nm, the scanning speed is 30-2000 mm / sec, preferably 800-1000 mm / sec, and the modulation frequency is 30-80 KHz, preferably 50-60 KHz.

[0112] More preferably, the laser pulse width used by the second laser is generally picosecond laser, and further preferably, the distance between the P1 scribe line and the P2 scribe line is 20-400 μm, and the smaller the distance is, the better, provided that the P1 scribe line and the P2 scribe line do not overlap.

[0113] In the specific embodiment of the preparation step (4), the width of the P3 scribe line formed is 30-100 μm, preferably 50-60 μm; preferably, the third laser is a pulsed laser with a wavelength of 245-1064 nm, preferably a laser with a wavelength of 532 nm, the scanning speed is 20-2000 mm / sec, preferably 800-1000 mm / sec, and the modulation frequency is 30-80 KHz, preferably 50-60 KHz.

[0114] More preferably, the laser pulse width used by the third laser is picosecond laser, and further preferably, the distance between the P2 scribe line and the P3 scribe line is 20-100 μm, and the smaller the distance is, the better, provided that the P2 scribe line and the P3 scribe line do not overlap.

[0115] The present invention will be further illustrated below with specific examples, but it should not be construed as the present invention being limited to these examples.

[0116] Where specific experimental steps or conditions are not specified in the examples, they can be performed according to the corresponding conventional experimental steps or conditions in this technical field. Reagents whose manufacturers are not specified are all conventional reagents already available in this field.

[0117] The testing methods used in the following examples are as follows:

[0118] Battery efficiency: Tested using a 3A Newport simulator and a Keithley 2420 source meter under AM1.5 standard illumination conditions and a temperature of 25°C, in accordance with GB / T 6495.1-1996, "Photovoltaic Devices - Part 1: Measurement of Photovoltaic Current-Voltage Characteristics".

[0119] Example 1

[0120] (1) A Mo back electrode was deposited to 500 nm on a glass substrate (thickness of 500 nm) using a magnetron sputtering process;

[0121] (2) Al2O3 nanoparticles were ultrasonically dispersed in isopropanol to form a suspension, and different particle concentrations (3 mg / ml) were prepared; wherein, the size of the nanoparticles was controlled in the range of 5 to 1000 nm, and the average particle size was 212 nm.

[0122] The suspension was coated onto the substrate with the deposited Mo back electrode using a spin coating process to form a wet film, and then annealed at 120°C for 5 minutes to form a passivation layer. The ratio of the area of ​​Al2O3 nanoparticles to the area of ​​the back electrode was calculated by obtaining a distribution map of the nanoparticles and performing image processing on the distribution map, and the coverage rate was found to be 14.6%, as shown in Figure 6.

[0123] (3) The absorption layer is prepared by evaporation process, the buffer layer is prepared by water bath, the high resistance layer and the front electrode layer are deposited by magnetron sputtering process, and the grid line is prepared by evaporation process to obtain a single-junction CIGS cell with complete back interface passivation. The specific cell structure is shown in Figure 1, and the SEM cross-section of the cell is shown in Figure 7.

[0124] Specifically, the above-mentioned absorption layer is Cu x (In 1-y Ga y Se2, x is 0.9, y is 0.32, and the thickness is 2μm; the buffer layer is CdS with a thickness of 50nm; the high-resistivity layer is intrinsic ZnO with a thickness of 50nm; the front electrode 1 is ITO with a thickness of 100nm; the gate line is Al with a thickness of 4μm and a linewidth of 80μm.

[0125] Example 2

[0126] The embodiment adopts the same preparation method as that of Embodiment 1, except that the concentration of the Al2O3 nanoparticle suspension prepared in step (2) is 5 mg / mL; after coating and annealing treatment, an Al2O3 nanoparticle passivation layer is formed, and the area ratio of the passivation layer to the back electrode is calculated to be 26.8% by obtaining the distribution map of the nanoparticles and performing image processing on the distribution map.

[0127] Embodiment 3

[0128] (1)-(3), CIGS single-junction cells are prepared according to the method described in Embodiment 1, except that in step (1), the particle concentration of the Al2O3 nanoparticle suspension is 3 mg / ml, and after depositing the front electrode layer 1 (material: ITO, thickness: 30 nm) in step (3), no grid lines are formed.

[0129] The area ratio of the Al2O3 nanoparticles to the back electrode in step (2) is calculated to be 15% by obtaining the distribution map of the nanoparticles and performing image processing on the distribution map.

[0130] (4) A 3 mg / mL alumina suspension (212 nm) is spin-coated on the front electrode layer 1 to form a wet film, and a passivation layer is formed by annealing at 85°C for 5 minutes; the area ratio of the Al2O3 nanoparticles to the back electrode is calculated to be 20% by obtaining the distribution map of the nanoparticles and performing image processing on the distribution map.

[0131] (5) A hole transport layer, an interface modification layer, and a perovskite absorption layer are sequentially deposited on the passivation layer formed in step (4) using a spin-coating process, and an electron transport layer is prepared using an evaporation method, an electron buffer layer, a front electrode layer 2, and grid lines are prepared using atomic layer deposition, to obtain a CIGS / PVK double-junction stacked cell with an interface passivation;

[0132] The hole transport layer is NiOx with a thickness of 10 nm; the interface modification layer is a monolayer of SAM molecules (Me-4PACz); the perovskite absorption layer has a thickness of 600 nm and is Cs x (FA 1-y MA y ) 1-x Pb(I 1-z-i Br z Cl i )3, where x is 0.05, y is 0.15, z is 0.15, and i is 0.05; the electron transport layer is C60 with a thickness of 20 nm; the electron buffer layer is SnO2 with a thickness of 15 nm; the front electrode layer 2 is IZO or AZO, and the grid lines are Ag with a thickness of 100 nm. The specific structure is shown in FIG. 2.

[0133] Example 4

[0134] (1) After depositing Mo back electrode on the substrate, the back electrode was first laser processed using laser scribing to form P1 scribe; the first laser had a pulse laser wavelength of 532 nm, a scanning speed of 900 mm / sec, an adjusting frequency of 50-60 KHz, and the width of P1 scribe was 90 μm.

[0135] (2) Al2O3 nanoparticles were ultrasonically dispersed into isopropyl alcohol to form a suspension, the size of the Al2O3 nanoparticles was controlled in the range of 5-1000 nm, and the average particle size was 212 nm. The suspension was coated onto the back electrode with processed P1 scribe to form a wet film, and a passivation layer was formed by annealing at 120°C for 5 minutes. The area ratio of Al2O3 nanoparticles to the area of the back electrode was obtained by obtaining a distribution map of the nanoparticles and calculating the coverage of the image processing map to be 15%.

[0136] (3) The absorption layer was prepared on the passivation layer which had been solidified by using evaporation process, the buffer layer was prepared by water bath method, and the high resistance layer was deposited by magnetron sputtering process; wherein the absorption layer was Cu x (In 1-y Ga y )Se2, x was 0.9, y was 0.32, and the thickness was 2 μm; the buffer layer was CdS, and the thickness was 50 nm; the high resistance layer was intrinsic ZnO, and the thickness was 50 nm.

[0137] The second laser processing was performed on the high resistance layer to form P2 scribe; the second laser had a pulse laser wavelength of 1030 nm, a scanning speed of 800 mm / sec, an adjusting frequency of 50-60 KHz, and the width of P2 scribe was 50 μm; the distance between the second groove P2 and the first groove P1 was 30 μm.

[0138] (4) The front electrode layer (ITO, thickness of 100 nm) was deposited on the high resistance layer with processed P2 scribe, the third laser processing was performed on the front electrode layer to form P3 scribe, and the inline processing process was completed. The third laser had a pulse laser wavelength of 532 nm, a scanning speed of 900 mm / sec, an adjusting frequency of 50-60 KHz, and the width of P3 scribe was 60 μm; the distance between the second groove P3 and the first groove P2 was 35 μm, and the details were shown in the attached Figure 3.

[0139] Comparative Example 1 (CIGS / PVK double-junction stacked cell passivation)

[0140] (1)-(3), the CIGS single-junction cell was prepared according to the method described in Example 1, except that in step (3), after depositing the front electrode layer 1 (material was ITO, thickness was 30 nm), no grid line was formed.

[0141] (4) On the electrode layer 1, a hole transport layer and an interface modification layer are sequentially deposited by a spin coating process, a wet film is formed on the interface modification layer by spin coating 3 mg / mL of aluminum oxide suspension (size of 212 nm), and a passivation layer is formed by annealing at 85°C for 5 minutes; the ratio of the area of Al2O3 nanoparticles to the area of the back electrode is obtained by obtaining a distribution map of the nanoparticles and calculating the coverage of the image processing to be 20%;

[0142] (5) A perovskite absorption layer is sequentially deposited on the passivation layer formed in step (4), an electron transport layer is prepared by evaporation, an electron buffer layer, a front electrode layer 2 and a grid line are prepared by atomic layer deposition, to obtain a CIGS / PVK double-junction stacked battery; wherein the hole transport layer is NiOx, with a thickness of 10 nm; the interface modification layer is a monolayer of SAM molecules (Me-4PACz); the perovskite absorption layer has a thickness of 600 nm and is Cs x (FA 1-y MA y ) 1-x Pb(I 1-z-i Br z Cl i )3, wherein x is 0.05, y is 0.15, z is 0.15, and i is 0.05; the electron transport layer is C60, with a thickness of 20 nm; the electron buffer layer is SnO2, with a thickness of 15 nm; the front electrode layer 2 is IZO or AZO, and the grid line is Ag, with a thickness of 100 nm. The specific structure is shown in FIG. 4.

[0143] Comparative Example 2

[0144] (1) A Mo back electrode is deposited on a glass substrate (thickness of 500 nm) by a magnetron sputtering process to 500 mm;

[0145] (2) An absorption layer is prepared on the Mo back electrode by an evaporation process, a buffer layer is prepared by a water bath method, a high resistance layer and a front electrode layer are deposited by a magnetron sputtering process, and a grid line is prepared by evaporation, to obtain a single-junction CIGS battery.

[0146] Specifically, the above-mentioned absorption layer is Cu x (In 1-y Ga y )Se2, x is 0.9, y is 0.32, and the thickness is 2 μm; the buffer layer is CdS, with a thickness of 50 nm; the high resistance layer is intrinsic ZnO, with a thickness of 50 nm; the front electrode 1 is ITO, with a thickness of 100 nm; and the grid line is Al, with a thickness of 4 μm and a line width of 80 μm.

[0147] Comparative Example 3

[0148] (1) using magnetron sputtering process to deposit Mo back electrode on glass substrate (thickness of 500 nm) to 500 nm;

[0149] (2) ultrasonic dispersion of Al2O3 nanoparticles into isopropyl alcohol to form a suspension, and prepare different particle concentrations (1 mg / ml); wherein, the size of the nanoparticles is controlled in the range of 5-1000 nm, and the average particle size is 212 nm;

[0150] The suspension is coated on the substrate with deposited Mo back electrode by spin coating process to form a wet film, and annealed at 120°C for 5 minutes to form a passivation layer; the ratio of the area of Al2O3 nanoparticles to the area of the back electrode is calculated by obtaining the distribution map of the nanoparticles and image processing the distribution map, and the coverage is 4.2%.

[0151] (3) sequentially using evaporation process to prepare the absorption layer, water bath method to prepare the buffer layer, magnetron sputtering process to deposit the high resistance layer and the front electrode layer, and evaporation process to prepare the gate line, to obtain a complete back interface passivated single-junction CIGS cell, and the specific cell structure is shown in FIG. 1, and the SEM cross-sectional view of the cell is shown in FIG. 5.

[0152] Specifically, the above-mentioned absorption layer is Cu x (In 1-y Ga y )Se2, x is 0.9, y is 0.32, and the thickness is 2 μm; the buffer layer is CdS, and the thickness is 50 nm; the high resistance layer is intrinsic ZnO, and the thickness is 50 nm; the front electrode 1 is ITO, and the thickness is 100 nm; and the gate line is Al, and the thickness is 4 μm, and the line width is 80 μm.

[0153] The cell obtained in the above embodiment is subjected to performance test, and the specific structure is shown in Table 1:

[0154] Table 1

[0155] The back field passivated CIGS cell prepared in Example 1 and the CIGS cell prepared in Comparative Example 2 are compared in terms of external quantum efficiency (EQE) at wavelengths of 900-1080 nm, and it can be seen from FIG. 8 that the cell prepared in Example 1 has an average increase of about 7% in external quantum efficiency (EQE) at wavelengths of 900-1080 nm, and the absorption at long wavelengths is obviously increased; in combination with the IV curve in FIG. 9, the absolute efficiency of the cell containing the passivation layer provided by the application can be increased by 1.1%, and the open circuit voltage is increased by about 15 mV, and the gain of the photoelectric performance of the CIGS cell with the passivation layer is significant.

Claims

1. A back interface passivated CIGS single junction cell, characterized in that, The CIGS single-junction cell comprises a substrate and a back electrode, an absorption layer, a buffer layer, a high-resistance layer, a front electrode and a grid line formed on the substrate in sequence; The back electrode and the absorption layer are deposited with a passivation layer, which is a discontinuous passivation layer formed by nanoparticles, and the coverage of the passivation layer on the back electrode is 5% to 75%, preferably 8% to 65%.

2. The CIGS single junction cell of claim 1, wherein, The nanoparticles forming the passivation layer are selected from AI2O3, SiO2, SrO2or MoO x .

3. A method of producing a back interface passivated CIGS single junction cell as claimed in claim 1 or 2, characterised in that, The method comprises: (1) depositing a back electrode on a substrate; (2) dispersing nanoparticles in a solvent to form a suspension, coating the suspension on the back electrode to form a wet film, and forming a passivation layer after annealing and drying; (3) depositing an absorption layer, a buffer layer, a high-resistance layer, a front electrode layer and a grid line on the passivation layer in sequence to obtain the CIGS single-junction cell with back interface passivation; The size of the nanoparticles in the suspension is 5 to 1000 nm, preferably 50 to 500 nm, and the concentration is 0.1 to 200 mg / ml, preferably 0.3 to 10 mg / ml.

4. The preparation method according to claim 3, characterized in that, In step (1), a back electrode is deposited on the substrate by magnetron sputtering or evaporation process, and the thickness of the back electrode is 100 to 1000 nm; Preferably, the substrate is glass, ceramic, metal foil or polymer material, and the material of the back electrode is Mo, ITO, AZO or FTO.

5. The preparation method according to claim 4, characterized in that, In step (2), the suspension is coated on the back electrode by spin coating, spraying or slot coating; Preferably, the solvent is selected from alcohol solvents or water; Preferably, the annealing temperature is 80 to 300℃.

6. The preparation method according to claim 5, characterized in that, In step (3), the absorbing layer is deposited on the passivation layer by a thermal evaporation process; preferably, the thickness of the absorbing layer is 0.9-2.5 μm; more preferably, the absorbing layer is Cu x (In 1-y Ga y )Se2, wherein x is 0.5-0.99, preferably 0.7-0.95, and y is 0-1, preferably 0.1-0.

5. The buffer layer is deposited by water bath or magnetron sputtering process; preferably, the thickness of the buffer layer is 10 to 70 nm; more preferably, the buffer layer is CdS or Zn(O,S); The high-resistance layer and the front electrode layer are deposited by magnetron sputtering process; preferably, the thickness of the high-resistance layer is 10 to 50 nm, and the thickness of the front electrode layer is 20 to 500 nm; more preferably, the high-resistance layer is intrinsic ZnO or ZnMgO, and the front electrode layer is ITO, IZO or AZO; The grid line is prepared by screen printing process, and the thickness of the grid line is 0.5 to 100 μm, the line width is 15 to 120 μm, and the material is Cu, Al or Ag.

7. A back interface passivated CIGS / PVK tandem dual junction solar cell characterized by, It comprises a CIGS single-junction cell as a bottom cell and a perovskite top cell selected from the CIGS single-junction cell of claim 1 or 2, and the bottom cell and the top cell are interconnected by internal two ends or four ends to become one; The top cell comprises a hole transport layer, an interface modification layer, a perovskite absorption layer, an electron transport layer, an electron buffer layer, a front electrode layer and a grid line in sequence; The front electrode of the bottom cell and the hole transport layer of the top cell are deposited with a passivation layer, which is a discontinuous passivation layer formed by nanoparticles, and the coverage of the passivation layer on the back electrode is 5% to 75%, preferably 8% to 65%.

8. A method of fabricating a back interface passivated CIGS / PVK tandem cell according to claim 7, characterized in that, The method comprises: The CIGS single-junction cell is prepared by the preparation method of any one of claims 3 to 6 as a bottom cell, and (4) dispersing the nanoparticles into a solvent to form a suspension, coating the suspension onto the front electrode of the bottom cell to form a wet film, and forming a passivation layer after annealing and drying; (5) sequentially depositing a hole transport layer, an interface modification layer, a perovskite absorption layer, an electron transport layer, an electron buffer layer, a front electrode layer, and a grid line on the passivation layer formed in step (4) to obtain the interface-passivated CIGS / PVK double-junction tandem cell; In step (4), the size of the nanoparticles in the suspension is 5-1000 nm, preferably 50-500 nm, and the concentration is 0.1-200 mg / ml, preferably 0.3-10 mg / ml.

9. The production method according to claim 8, characterized by, In step (4), the suspension is coated onto the front electrode of the bottom cell by spin coating, spraying, or slot coating. Preferably, the solvent is selected from an alcohol solvent or water. Preferably, the annealing temperature is 80-300°C.

10. The method of claim 9, wherein, In step (5), the hole transport layer is deposited on the passivation layer by coating or thermal evaporation process, preferably the thickness of the hole transport layer is 5-50 nm, and the hole transport layer is NiOx. Preferably, the interface modification layer is deposited by spin coating, slot coating, or spraying process, and the interface modification layer is a monolayer of SAM molecules. Preferably, the perovskite absorber layer is deposited by one or more of the processes of thermal evaporation, slot-die coating and / or spray coating, preferably the perovskite absorber layer has a thickness of 200-1200 nm, more preferably the perovskite absorber layer is Cs x (FA 1-y MA y ) 1-x Pb(I 1-z-i Br z Cl i )3, wherein x has a value of 0.01-0.25, y has a value of 0.05-0.35, z has a value of 0-0.35, and i has a value of 0-0.

35. Preferably, the electron transport layer is deposited by coating or thermal evaporation process, preferably the thickness of the electron transport layer is 5-50 nm, and more preferably the electron transport layer is C60 or PCBM. Preferably, the electron buffer layer is deposited by atomic layer deposition or coating process, preferably the thickness of the electron buffer layer is 5-50 nm, and more preferably the electron buffer layer is SnO2 or BCP. Preferably, the front electrode layer is deposited by magnetron sputtering process, preferably the thickness of the front electrode layer is 20-200 nm, and more preferably the front electrode layer is ITO, IZO, or AZO. Preferably, the grid line is prepared by screen printing process, the thickness of the grid line is 0.5-100 μm, the line width is 15-100 μm, and the material is Cu, Al, or Ag.

11. A method of passivating the back interface of a CIGS single-junction interconnect cell, characterized in that, The CIGS single-junction cell is the CIGS single-junction cell of claim 1 or 2 or prepared by the preparation method of claims 3-6. The P1 scribe line, P2 scribe line, and P3 scribe line are formed by laser scribing, and the inline method comprises the following steps: (1) after depositing the back electrode on the substrate, the back electrode is subjected to first laser processing by laser scribing to form a P1 scribe line; (2) dispersing the nanoparticles into a solvent to form a suspension, coating the suspension onto the back electrode with the processed P1 scribe line to form a wet film, and forming a passivation layer after annealing and drying; (3) sequentially depositing an absorption layer, a buffer layer, and a high-resistance layer on the solidified passivation layer, and performing second laser processing on the high-resistance layer to form a P2 scribe line; (4) depositing a front electrode layer on the high-resistance layer of the processed P2 scribe line, and performing a third laser processing to form a P3 scribe line on the front electrode layer to complete the inline processing procedure.

12. The back interface passivation method of claim 11, wherein, In step (1), the width of the P1 scribe line formed is 60-100 μm; Preferably, the first laser is a pulsed laser with a wavelength of 245-1064 nm, preferably a laser with a wavelength of 532 nm or 1064 nm, a scanning speed of 20-2000 mm / sec, preferably 800-1000 mm / sec, and a modulation frequency of 30-80 KHz, preferably 50-60 KHz. More preferably, the first laser uses a laser pulse width of picosecond laser.

13. The back interface passivation method of claim 12, wherein, In step (2), the size of the nanoparticles in the suspension is 5-1000 nm, preferably 50-500 nm, and the concentration is 0.1-200 mg / ml, preferably 0.3-10 mg / ml. More preferably, the suspension is coated on the back electrode of the processed P1 scribe line by spin coating, spray coating or slot coating.

14. The back interface passivation method of claim 13, wherein, In step (3), the width of the P2 scribe line formed is 40-300 μm, preferably 50-60 μm. Preferably, the second laser is a pulsed laser with a wavelength of 245-1064 nm, preferably a laser with a wavelength of 1030 nm, a scanning speed of 30-2000 mm / sec, preferably 800-1000 mm / sec, and a modulation frequency of 30-80 KHz, preferably 50-60 KHz. More preferably, the second laser uses a laser pulse width of picosecond laser. Further preferably, the distance between the P1 scribe line and the P2 scribe line is 20-400 μm.

15. The back interface passivation method of claim 14, wherein, In step (4), the width of the P3 scribe line formed is 30-100 μm, preferably 50-60 μm. Preferably, the third laser is a pulsed laser with a wavelength of 245-1064 nm, preferably a laser with a wavelength of 532 nm, a scanning speed of 20-2000 mm / sec, preferably 800-1000 mm / sec, and a modulation frequency of 30-80 KHz, preferably 50-60 KHz. More preferably, the third laser uses a laser pulse width of picosecond laser. Further preferably, the distance between the P2 scribe line and the P3 scribe line is 20-100 μm.

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