A 3D vertical magnetic memory device

Abstract

This disclosure relates to a 3D magnetic memory device, which comprises a stack comprising a plurality of dielectric and silicon-based layers alternatingly arranged one on the other, and a magnetic channel extending through each layer of the stack. Pinning sites defined by the layers of the stack are formed in the magnetic channel, each pinning site configured to store one or more magnetic bits. A first metallic layer is arranged on a first end of the magnetic channel and a top layer of the stack, and a magnetic tunnel junction (MTJ) and a first electrode are arranged on the first metallic layer at a distance to another. Either the first metallic layer is configured as SOT track, or a second metallic layer is configured as a SOT track and is arranged on a second end of the magnetic channel and a bottom layer of the stack.

Description

[0001] IMEC VZW

[0002] PA 2023 / 359 PCT1

[0003] P61984 / WO

[0004] A 3D VERTICAL MAGNETIC MEMORY DEVICE

[0005] TECHNICAL FIELD

[0006] The present disclosure relates to magnetic memory devices. The disclosure presents a new kind of three-dimensional (3D) magnetic memory device that may achieve high memory density (bit density). The magnetic memory device may be referred to as a 3D vertical magnetic (3DVMAG) memory device. The magnetic memory device is based on a spin orbit torque (SOT) and / or spin transfer torque (STT) magnetic random access memory (MRAM) device architecture.

[0007] BACKGROUND

[0008] In the field of computing devices, a very large variety of memory architectures have been developed over the last decades depending on various technical constraints, for instance, depending on speed requirements, memory requirements, density requirements, and application type. For example, the static random-access memory (SRAM) architecture has been exploited for its high operating speed, but with the drawback related to its areal density. By contrast, the dynamic randomaccess memory (DRAM) architecture allows for a high capacity working memory, but at lower speed. Moreover, (3D) NAND provides cheap high capacity, but is extremely slow compared to the other memory types. More recent advances introduced the spin-transfer torque magnetic random-access memory (STT- MRAM) architecture, a non-volatile resistive memory exploiting a magnetic tunnel junction (MTJ).

[0009] STT-MRAM is seen as an embedded memory (built on the same die as logic), because of its relatively fast operation speeds (down to a few nanoseconds), robust endurance, and compatibility with advanced complementary metal-oxide semiconductor (CMOS) voltages. It also offers non-volatility by storing bits in a magnetic state, and therefore presents an improvement in leakage power compared to alternatives in SRAM and DRAM. IMEC VZW

[0010] PA 2023 / 359 PCT1

[0011] P61984 / WO

[0012] Various flavors of magnetic memories exist, with STT-MRAM being the most advanced, but also SOT-MRAM and voltage controlled MRAM being potential next generation candidates with possibilities for even faster speeds and / or lower power operation. Nevertheless, all of these magnetic memories are based on the MTJ technology. Since the MRAM stack itself is often a complex collection of over 20 individual ultra-thin layers, the use of physical vapor deposition (PVD) is needed which implies a planar configuration.

[0013] While the MRAM technologies described above make good candidates for SRAM replacement or on-chip memory, the planar configuration ultimately limits the achievable memory density, thus limiting their application to embedded memory technology, where the current density offering is limited. To target other parts of the memory pyramid, MRAM would have to exploit the third dimension, in order to potentially increase the memory density by a factor of about 100, while ideally preserving and controlling the known advantages of MRAM regarding speed and endurance.

[0014] Moreover, to provide a memory device and interface that can be exploited in computing applications, memory cells often have to be arranged in an array, and have to be integrated in a proper circuit. For instance, typical components of a memory device are the (array of) memory cells, word lines, bit lines, address decoder, sense amplifiers, and buffer. The memory cells store information, and the word lines and bit lines are connected to the memory cells and provide a coordinate system to perform operations in a given memory cell. The address decoder locates and provides an address for each memory cell. The sense amplifiers amplify changes of voltage, and convert them into logic level output signals to support read operations. The buffer provides memory capacity for the output signals.

[0015] SUMMARY

[0016] The present disclosure aims to provide a new kind of magnetic memory device that is based on MRAM. An objective is to exploit all three spatial dimensions, i.e., to depart from the planar configuration and to design a 3D magnetic memory array IMEC VZW

[0017] PA 2023 / 359 PCT1

[0018] P61984 / WO and device. An ultimate objective is thereby to significantly increase the achievable memory density for storing more information in the magnetic memory device. Another objective is to provide a memory array configuration.

[0019] These and other objectives are achieved by the solutions described in the independent claims. Advantageous implementations are described in the dependent claims.

[0020] The magnetic memory device presented in this disclosure is based on a recent technology, which is referred to as 3DVMAG technology. To be able to exploit such a magnetic memory device in computing applications, an objective of this disclosure is also to address the arrangement of connections with transistors in the hardware. Thereby, one of the challenges is that a current line for a specific operation is needed.

[0021] In addition, to gain space and make a more compact device, the number of connections and transistors should be minimized as much as possible. Also, the design of the memory array should be as compact as possible, to increase storage density or create a smaller memory device. Moreover, because reading large amounts of data distributed in the memory device may take considerable time, parallelism in the reading process should be enabled, in order to enhance the performance of the magnetic memory device.

[0022] As mentioned above, the magnetic memory device of this disclosure may employ SOT. In this respect, efficiency and reliability of magnetic bit switching by SOT are important parameters, to allow control of the memory device and ensure reproducible and deterministic results for actual applications. This includes avoiding a too weak stabilization of a magnetic bit written into the magnetic channel. Moreover, a delay between subsequent SOT operations should be minimized.

[0023] In general, memory technologies that use MTJs (e.g., STT-MRAM or SOT-MRAM) require a relatively large current to provide enough torque to switch the magnetic state of their memory cells. However, it would be preferable if lower currents could IMEC VZW

[0024] PA 2023 / 359 PCT1

[0025] P61984 / WO be used. Ideally, the aim would be to reduce the necessary current in the magnetic memory device of this disclosure to 100 pA or below. Besides the reduction in power to operate the magnetic memory device, this would allow reducing its size, which facilitates the prospect of scaling down. The lower the current, the smaller selectors maybe, which maybe used to control the current flowing in the magnetic memory device, and thus the higher the achievable bit density may be. In any case, when injecting current into the magnetic memory device, there is a risk that the current takes another route (a sneak path) and interacts with other components along the way, and it is thus an objective to avoid such issues.

[0026] A first aspect of this disclosure provides a 3D magnetic memory device, the magnetic memory device comprising a stack comprising a plurality of dielectric layers and silicon-based layers, which are alternatingly arranged one on the other; a magnetic channel comprising magnetic material and extending through each layer of the stack; wherein a plurality of pinning sites defined by the plurality of layers of the stack is formed in the magnetic channel, each pinning site being configured to store one or more magnetic bits; a first metallic layer arranged respectively on a first end of the magnetic channel and a top layer of the stack; a MTJ arranged on the first metallic layer; and a first electrode arranged on the first metallic layer at a distance to the MTJ; wherein either the first metallic layer is configured as a SOT track, or a second metallic layer of the magnetic memory device is configured as a SOT track and is arranged on respectively a second end of the magnetic channel and a bottom layer of the stack.

[0027] The magnetic channel may comprise ferromagnetic material. The magnetic channel may constitute one or more memory cells. For example, the magnetic channel maybe considered being a memory cell of the 3D magnetic memory device of the first aspect as a whole, as it is individually addressable. The magnetic channel may, however, also be considered comprising a plurality of memory cells, as each pinning site in the magnetic channel is able to store a plurality of magnetic bits. The magnetic channel may in this way store the plurality of magnetic bits along its length, for example, one or more magnetic bits for each layer of the stack. The magnetic channel may accordingly store a bit sequence. The magnetic memory device may comprise multiple such magnetic channels formed in one or multiples IMEC VZW

[0028] PA 2023 / 359 PCT1

[0029] P61984 / WO stacks in the same way as described above, in order to implement multiple memory cells of the magnetic memory device. The multiple magnetic channels may thereby be arranged in parallel to each other and / or may be arranged in an array of magnetic channels, for instance, an array comprising a plurality of rows and columns. That is, the magnetic channels may be arranged in a 2D array and may extend along the third dimension (along the stacking direction of the layers of the stack, typically referred to as vertical direction). Thus, the 3D magnetic memory device of the first aspect can exploit all three dimensions, and depart from the usual planar configuration. Consequently, the magnetic memory device of the first aspect may have a significantly increased memory density, and can store more information that a conventional, planar magnetic memory device.

[0030] The pinning sites in the magnetic channel may be generated by the alternating layers and their interfaces. The pinning sites are locations where magnetic domains (or more specifically, the domain walls that separate these magnetic domains) are "pinned" or stabilized. Thus, each pinning site is configured to stabilize (and thus configured to store) a particular magnetic state in the magnetic channel, the state representing at least one (magnetic) bit of information. Domain walls may nucleate in the magnetic channel like in any magnetic material, once it becomes energetically unfavorable to keep a single uniform domain, and may form multiple magnetic domains that expand to minimize the internal energy. The domain walls may be interfaces separating two magnetic domains and acting as a continuous transition across a finite distance between different magnetic moments, which may have an angular displacement of 90° or 180°. The stability of the magnetic domains may be ensured by the overall minimization of both the overall anisotropy energy (including magneto-crystalline and shape effects) and the exchange energy at the interfaces between the domains. Each new domain then has its own orientation, different from its neighbor domains. It could be antiparallel or even pointing toward a different direction depending on the configuration.

[0031] It is possible to have multiple magnetic domains in the magnetic channel, which are oriented along a given axis. This may be achieved by having a long magnetic channel, since that provides a high shape anisotropy that incites the magnetization IMEC VZW

[0032] PA 2023 / 359 PCT1

[0033] P61984 / WO to align along the channel’s longitudinal axis. By exploiting geometric features (e.g., notches, sharp angles, discontinuities), the propagation of magnetic domains may be prevented beyond each domain wall. Deliberately fabricating the pinning sites, by at least using the alternating layers of the stack, may shape the energy landscape and allow for the control of the position of the magnetic domain walls.

[0034] The magnetic memory device of the first aspect can employ SOT for writing information into the magnetic channel, and can employ TMR using the MTJ to read out information from the magnetic channel. SOT is a phenomenon wherein an electrical current flowing through the SOT track - where the SOT track may be a bi-layer consisting of a heavy metal layer and a magnetic layer - gives rise to a change in magnetization direction in the magnetic channel. Specifically, a combined interaction between SOT and the Dzyaloshinskii-Moriya interaction (DMI) leads to the nucleation and stabilization of a magnetic domain with a given magnetic orientation and to an asymmetric domain wall motion, wherein the direction of movement of the domain wall depends on these two effects. The DMI is an exchange interaction, which is antisymmetric and arises due to spin-orbit coupling (SOC) in structures with broken inversion symmetry, and will be explained in more detail later.

[0035] The magnetic memory device of the first aspect can also employ STT for writing information into the magnetic channel. STT is a phenomenon wherein the magnetization direction of a magnetic layer such as the magnetic channel is modified by a spin-polarized current. Usually, current is 50% spin up and 50% spin down electrons, but polarization can be obtained, for example, by passing the current through a thick magnetic layer.

[0036] Information can be moved in the magnetic channel by a push current, and thus moving magnetic bits stored in the magnetic channel from one pinning site to the next. The pinning sites are enabled by the periodicity of the layer stack, and are able to stabilize a magnetic domain, for instance, within a single layer height. Hence, the height of a magnetic bit can be defined by said periodicity. To overcome those pinning sites, a supplementary magnetic field or a spin-polarized current may be applied. Each domain wall provides an energy well that requires some IMEC VZW

[0037] PA 2023 / 359 PCT1

[0038] P61984 / WO threshold driving force to overcome the potential barrier. For example, for a spin- polarized current running through the magnetic channel, the interaction (in particular the s-d exchange coupling) between the spin angular momentum of the itinerant electrons and the magnetization of the material may lead to a possible displacement of the domain wall to the next pinning point through a domain pushing force called STT, and thereby a change of magnetization in that portion of the wire.

[0039] The magnetic channel may also be referred to as a magnetic wire or magnetic pillar, and may constitute together with the SOT track, the MTJ and one or more electrodes a 3DVMAG element (or short “3DVMAG”) of the magnetic memory device.

[0040] In an implementation of the first aspect, the 3D magnetic memory device further comprises a write line connected to the SOT track; and at least one write selector connected to the write line; wherein the at least one write selector is controllable to pass a write current through the write line and the SOT track.

[0041] The write line can be used for writing information into the magnetic channel of a 3DVMAG.

[0042] In an implementation of the first aspect, the 3D magnetic memory device further comprises a second electrode arranged on or below the second end of the magnetic channel.

[0043] In an implementation of the first aspect, the 3D magnetic memory device further comprises a push line connected to one of the first electrode and the second electrode; wherein the push line is configured to provide a push current from one of the first and the second electrode through the magnetic channel to the other one of the first and the second electrode.

[0044] The push line can be used for pushing information along the magnetic channel of a 3DVMAG. IMEC VZW

[0045] PA 2023 / 359 PCT1

[0046] P61984 / WO

[0047] In an implementation of the first aspect, the 3D magnetic memory device further comprises at least one push selector connected to the push line; wherein the at least one push selector is controllable to pass the push current through the push line and the magnetic channel.

[0048] In an implementation of the first aspect, for writing a bit into the magnetic channel, the magnetic memory device is configured to control the at least one write selector, in order to select a magnetic state of the magnetic bit, and to control the at least one push selector, in order to push the magnetic bit to the pinning site closest to the SOT track.

[0049] In an implementation of the first aspect, the 3D magnetic memory device further comprises a read line connected to the MTJ; and at least one read selector connected to the read line; wherein the at least one read selector is controllable to pass a read current through the read line and the MTJ.

[0050] The read line can be used for reading information from the magnetic channel of a 3DVMAG.

[0051] The magnetic memory device of the first aspect can be integrated with only the above-described three lines - which results in a 3D architecture - contrary to some other technologies. The three lines may be used to write, read, or push magnetic bits in the magnetic channel. How the write line, read line, and push line are disposed may depend on the disposition of the SOT track and the MTJ. For example, the MTJ could be disposed on top of the magnetic channel (first end), or at the bottom (second end). The SOT track could be on the same side of the magnetic channel as the MTJ, or they could be arranged on opposite sides. Hence, there are at least four configurations: the MTJ and the SOT track on top of the magnetic channel, the MTJ and the SOT track below the magnetic channel, the MTJ on top and the SOT track below the magnetic channel, or the MTJ below and the SOT track on top of the magnetic channel. Additionally, one or the other of the two elements could be replicated on the opposite side of the magnetic channel, in order to increase the number of possibilities. Thus, there may even be an MTJ IMEC VZW

[0052] PA 2023 / 359 PCT1

[0053] P61984 / WO and / or a SOT track both on top of and below the magnetic channel. The position and number of lines is dependent on these configurations.

[0054] In any case, the read line can be directly connected to the MTJ, and can be activated with a read selector (e.g., a MOSFET), the write line can be directly connected to the SOT track and can be activated with a write selector, and the push line can be connected to the other extremity of the magnetic channel and can be activated with a push selector. The magnetic channel may work as a Last In First Out (LIFO), if the MTJ and the SOT track are on the same side of the magnetic channel. The magnetic channel may work as a First In First Out (FIFO), if the MTJ and SOT track are on opposite sides of the magnetic channel. The write, read, and push operations could be performed as follows.

[0055] For an exemplary write operation, the push selector can be turned ‘ON’ and a push current can be sent through the magnetic channel and the SOT track, from the side where the push selector is located to the side where the write selector is located, or in the opposite direction. The write selector is turned ‘ON’ and a write current is sent through the write line and through the SOT track, from the side where the write selector is located to the other side. The read selector is turned ‘OFF’. Those two combined currents result in an STT assistance for bit level selection (i.e., the access of individual bit of data), a low SOT write current and energy required, and improved write error rate (WER).

[0056] For an exemplary push operation, a push current can be sent through the push line, then going through the magnetic channel, and finally through the write line, or the other way around. The push selector is turned ‘ON’ and the write selector is turned ‘ON’. The push current is sent through the magnetic channel from the side where the write selector is located to the side where the push Selector is located. The read selector is turned ‘OFF’.

[0057] For an exemplary read operation, the push selector is turned ‘OFF’. The write selector is turned ‘ON’ and the read selector is turned ‘ON’. A read current is sent through the MTJ and SOT track, from the side where the write selector is located IMEC VZW

[0058] PA 2023 / 359 PCT1

[0059] P61984 / WO to the side where the read selector is located. The bit value / state (o or 1) that the MTJ reads depends on the total resistance of the path that the current follows.

[0060] The magnetic memory device may comprise one selector per line. However, other possibilities may be considered depending on a desired set of performances. Configurations with various numbers and positioning of write and push selectors are possible. For example, instead of having a single write selector, having two write selectors on opposite sides of the SOT track may help in reducing the push current by splitting it into two halves. Since the size of the selectors depends on the amount of current it needs to control, lowering the current allows for smaller selectors. Furthermore, since bit density has been mainly limited by the selectors’ sizes, it means that this type of configuration can potentially greatly improve bit density.

[0061] Further, the entire push current may flow through the push selector, unlike the write selector where it can be split into two halves. Consequently, a large push selector may be needed to meet the push current requirements. One way to improve the density is to eliminate the usage of the push selector altogether, which is possible. Using single push selector per magnetic channel may lead to a better density than having two selectors or three selectors, respectively. It is important to note, however, that this density gain may come at the expense of complex read, write, and push operations.

[0062] In an implementation of the first aspect, the 3D magnetic memory device further comprises a third electrode arranged on the first metallic layer in a distance to respectively the first electrode and the MTJ.

[0063] The third electrode may be used to support write and push operations.

[0064] In an implementation of the first aspect, the magnetic channel is one of a cylindrical channel; a macaroni channel; a sidewall channel.

[0065] Generally, a myriad of different configurations may be considered for implementing the magnetic channel. Without being limiting, the main families of IMEC VZW

[0066] PA 2023 / 359 PCT1

[0067] P61984 / WO magnetic channels presented in this disclosure are a (full) cylindrical channel, a macaroni channel where the core of magnetic material is removed and may be optionally replaced by a non-conductive material, and a sidewall channel that is a magnetic channel formed on a sidewall of a trench or other long narrow cavity, which may be optionally filled with a non-conductive material. The advantage of the sidewall and the macaroni channel is that the current consumption required to operate the magnetic memory device is decreased, since their respective cross- sectional surface areas are decreased compared to a full cylindrical channel. This also decreases the dependence on the overall scale of the magnetic memory device, allowing for less challenging manufacturing. The stability of the magnetic domains is also increased, due to the increased anisotropy of the pinning sites.

[0068] In an implementation of the first aspect, the 3D magnetic memory device further comprises a trench that extends through each layer of the stack; wherein the sidewall channel is formed by magnetic material arranged on a first sidewall of the trench.

[0069] This implementation is directed to the sidewall channel. The sidewall channel allows for a reduction of the active surface through which current has to run. Thanks to that, a current reduction without needing to scale the magnetic memory device down can be achieved.

[0070] In an implementation of the first aspect, the 3D magnetic memory device further comprises a second sidewall channel; wherein the second sidewall channel is formed by magnetic material arranged on a second sidewall of the trench.

[0071] In an implementation of the first aspect, the trench is rectangular; and the first sidewall and the second sidewall are opposite sidewalls of the rectangular trench.

[0072] In an implementation of the first aspect, the trench is filled with a dielectric material. IMEC VZW

[0073] PA 2023 / 359 PCT1

[0074] P61984 / WO

[0075] In an implementation of the first aspect, the trench has a first width where it extends through a silicon-based layer of the stack, and a second width where it extends through a dielectric layer of the stack.

[0076] This may be achieved, for example, by creating recesses in every other layer of the stack (whether dielectric or silicon-based is not crucial). In this case, those recesses play a role of pinning points between magnetic domains. Therefore, this configuration has nearly point -like pinning instead of layer pinning, and each individual layer in the magnetic channel can be exploited.

[0077] In an implementation of the first aspect, the trench has a constant width where it extends through a silicon-based layer of the stack, and a varying width where it extends through a dielectric layer of the stack, or vice versa.

[0078] In an implementation, the macaroni channel comprises a hollow cylinder made of magnetic material, and dielectric material that fills the hollow cylinder.

[0079] This implementation is directed to the macaroni channel. The macaroni channel provides advantages compared to a magnetic memory device that has a full magnetic channel, for example, with varying diameter.

[0080] This is, because in a magnetic memory device with full magnetic channel, the shape anisotropy of the magnetic channel is what forces the magnetization to align along the axis of the magnetic channel, as it extends through the stack (e.g., the vertical axis). An aspect ratio t / CD between an individual thickness t of the layers of the stack and a critical dimension (CD), which can guarantee this, is at least 2-3, i.e., t > 2~3*CD. Normally the overall shape anisotropy helps to make sure that all magnetization remains perpendicular, even if the individual bit t / CD ratio is much smaller. For instance, CD maybe in the range of 30-50 or 30-80 nm, while t may be in a range of 15-50 nm. However, there is a risk that different bit sequences written into the magnetic channel (e.g. {111111} vs. {1010101} vs. {000001}, for example) could contribute at different degrees to the alteration of the shape anisotropy effect, which may lead to a weakening of that effect for some of those IMEC VZW

[0081] PA 2023 / 359 PCT1

[0082] P61984 / WO configurations. However, scaling further the device (for example, down to 20 nm CD) remains challenging, as it is costly, requires intensive lithography steps, and meets limitations due to the high aspect ratio, in particular for etching.

[0083] Another issue is that the magnetic domain pinning may occur only in every other layer in this magnetic memory device with full magnetic channel, instead of between each of the layers. Therefore, magnetic information may only be storable every bi-layer, which would limit the total amount of information that the magnetic channel can bear. This could halve the potential of the 3D magnetic memory device.

[0084] The magnetic macaroni channel reduces the active magnetic channel diameter, which leads to a lower pushing current. Moreover, the magnetic channel allows for a more relaxed CD while keeping low current. This enables a cheaper fabrication, or an easier manufacturing in terms of CD control. In addition, the magnetic domains have reinforced magnetic anisotropy, which makes the memory device more stable. Potentially, the memory device may lead up to a doubling of the bit density, because magnetic bits are stored adjacent to all layers of the stack.

[0085] In an implementation, the hollow cylinder is a stepped hollow cylinder and / or has a constant outer diameter along its length through the layers of the stack.

[0086] In an implementation, the stepped hollow cylinder has a constant wall thickness.

[0087] In an implementation, at the first end of the magnetic channel, an inner core of the hollow cylinder has a diameter of up to 200 nm, or a diameter in a range of 10-80 nm.

[0088] This facilitates reading of the magnetic bit stored closest to the MTJ.

[0089] In an implementation, the magnetic channel is made of a plurality of different metallic material layers. IMEC VZW

[0090] PA 2023 / 359 PCT1

[0091] P61984 / WO

[0092] In an implementation, the plurality of metallic material layers comprises a first layer and second layer, which are made of opposite sign spin Hall angle materials.

[0093] The magnetic channel may benefit from a multilayer configuration. In one exemplary configuration, the magnetic channel may be composed of three layers, the first and last being made of a heavy metal material of opposite SHA, while the intermediate one is made of a ferromagnetic or ferrimagnetic and / or conductive material. This configuration allows achieving a lower required current to operate the magnetic memory device.

[0094] In an implementation, the 3D magnetic memory device further comprises a third layer, which is arranged between the first layer and the second layer and is made of a spin orbit generating and / or conductive material.

[0095] In an implementation, a length of the magnetic channel along its extension direction through the layers of the stack is in a range of 5-150 nm times the number of layers of the stack.

[0096] In an implementation, the magnetic channel has a first diameter where it extends through a silicon-based layer, and a second diameter where it extends through a dielectric layer of the stack.

[0097] That is, in this disclosure, in some implementations the boundaries of the magnetic channel may be straight and smooth, so that the magnetic channel has constant cross-sectional dimensions (strictly cylindrical channel). However, the cross- sectional dimensions of the magnetic channel may also vary along its length and depending on whether the channel section is embedded in a dielectric or silicon- based layer of the stack (which does not matter). This may be implemented, in order to adjust magnetic domain pinning properties. For example, there may be recesses on either the dielectric or silicon-based layers, leading to larger channel dimensions with the former and smaller for the latter, or the other way around. Moreover, even within a given type of layer, the dimensions do not necessarily have to be constant. For example, in some implementations the recesses maybe tapered along the stacking direction or against the stacking direction of the stack. IMEC VZW

[0098] PA 2023 / 359 PCT1

[0099] P61984 / WO

[0100] The different diameters may allow adjusting the pinning strength of the respective pinning sites in the magnetic channel. Thus, also the performance of the magnetic memory device, for instance, regarding its retention and latency, can be tailored.

[0101] In an implementation, the first diameter is larger or smaller than the second diameter and / or wherein a ratio between the first diameter and the second diameter is respectively in a range of 1.1:1 to 2:1 or in a range of 1:1.1 to 1:2.

[0102] A smaller ratio may be used to favor latency, while a larger ratio may be used to favor retention time of the magnetic memory device.

[0103] In an implementation, transitions between the first diameter and the second diameter are aligned with interfaces between the alternatingly arranged layers of the stack.

[0104] In an implementation, the magnetic channel is made of a ferromagnetic or ferrimagnetic material and / or a conductive material, for example, is made of cobalt, iron, nickel, or an alloy thereof, or any of the former in addition to boron.

[0105] In an implementation, a thickness of the silicon-based layers and the dielectric layers along their stacking direction in the stack is respectively in range of 5-150 nm.

[0106] In an implementation, the stack has a length that is smaller than its width; or the stack has a width that is smaller than its length.

[0107] This may be used to scale the bulk of the magnetic channel either horizontally or vertically, to enhance particular properties. While horizontal scaling helps in reducing a required power to operate the magnetic memory device, vertical scaling increases the bit density and leads to a smaller stray field making the magnetic memory device more reliable. In extreme cases, the working principle of those configurations with high aspect ratio is altered, as interfacial effects and interfacial interactions become more predominant, leading for example to magnetic IMEC VZW

[0108] PA 2023 / 359 PCT1

[0109] P61984 / WO orientations becoming in-plane rather than out-of-plane. In an example, the stack may take the form of an annulus, a geometry which may have, in the scope of this disclosure and in extreme cases, a layer thickness in the order of a few nanometers. The stack may in another example also include a horizontally scaled channel, where the channel takes the form of a shell, a geometry which may have, in the scope of this disclosure and in extreme cases, a wall thickness in the order of a few nanometers (e.g., 1-3 nm).

[0110] In an implementation, the layer of the stack, which is closest to the SOT track, has different dimensions and / or has a different shape than the other layers of the stack.

[0111] That is, an additional alteration may be having one or multiple layers having a different geometry than the rest of the stack. For instance, the first layer could be altered to enable more efficient switching of the magnetic domain, increase reliability, or reduce the required current to operate the device. For example, a thinner and wider first layer may be formed.

[0112] In an implementation, the SOT track is a single layer.

[0113] In an implementation, the SOT track is a bi-layer, or is a tri-layer, or is a multilayer.

[0114] In an implementation, the SOT track comprises a first layer and a second layer, which are made of opposite sign spin Hall angle materials.

[0115] In an implementation, the SOT track comprises a thinner first layer made of a spin orbit generating material, and a thicker second layer made of an orbital torque generating material.

[0116] In an implementation, the SOT track comprises a third layer arranged between the MTJ and the first or second layer of the SOT track.

[0117] That is, according to the above, the SOT track may be a single-layered conductive structure allowing spin current to reach the magnetic channel. However, in some IMEC VZW

[0118] PA 2023 / 359 PCT1

[0119] P61984 / WO implementations, additional layers may be added to enhance the SOT track’s performance. Therefore, the SOT track may take the form of a bi-layer, or even a tri-layer. In one implementation, the SOT track comprises two layers made of materials having opposite signs for the spin Hall angle (SHA), for example, titanium or tungsten (negative SHA) and platinum (positive SHA). This implementation is advantageous for switching quicker the magnetization in the writing process. In another implementation, the first layer is a spin-orbit generating layer, i.e. a layer of material that can generate a spin current through spin Hall effect or similar mechanisms due to spin-orbit coupling (such as tantalum nitride, tungsten nitride, tantalum, platinum, hafnium, etc.), while the second layer is an orbital torque generating layer, i.e. a layer of material that can generate an orbital angular momentum through orbital Hall effect which can exert a magnetic torque in an adjacent magnetic layer. This second layer is made of a conductive material, such as copper, and has a larger thickness, and therefore helps in significantly reducing the SOT track’s resistance. A third layer may be additionally added on top and below the MTJ to stabilize the MTJ readings. Those layers do not necessarily need to have the same dimensions and coverage, as they may individually be patterned. For instance, a macaroni channel could be combined with a bi-layer or with a tri-layer. The third layer may be shorter than the two other layers, as its purpose is strictly tied to the MTJ.

[0120] Notably, spin-orbit coupling (SOC), or spin-orbit effect or spin-orbit interaction, refers to the interaction between the spin of a particle (e.g., an electron) and its orbital angular momentum, such as that induced by the electromagnetic field generated by a nucleus, or other ions. The interaction of the electrons with the potential or electromagnetic field, with the fact that the electrons move at relativistic speeds, cause them to experience relativistic effects where an effective magnetic field appears in their frame of reference and interacts with the electrons’ spin, causing precession or rotation of the spin orientation as the electrons move through the potential or electromagnetic field.

[0121] The spin Hall effect (SHE) is a phenomenon where an electric current flowing through a material induces a transverse spin current perpendicular to the direction of the charge current. One leading phenomenon that could explain why it could IMEC VZW

[0122] PA 2023 / 359 PCT1

[0123] P61984 / WO occur is when the electrons moving through the material experiences strong SOC, where theirs spins become correlated with their motion. The electrons with different spin orientations experience slightly different effective magnetic fields and therefore different forces. As a consequence, they are deflected differently and undergo different trajectories as they move through the material. That results in a transverse spin current in the direction perpendicular to the charge current as opposite spins accumulate on the opposite sides of the material.

[0124] The orbit Hall effect (OHE) is a similar but distinct phenomenon involving an electric current in a material, causing electrons to separate based on their orbital angular momentum, how they are distributed over the orbitals and possibly also SOC (in particular due to the angular dependence of the d orbitals), and not based on charge (classical Hall Effect) nor on SHE. Due to the electric field, they experience an effective magnetic field affecting their motion, even in the absence of an external magnetic field, which leads to a transverse flow of orbital momentum in the material and eventually a transverse voltage. In short, the OHE is driven by the orbital motion of electrons due to the interaction between an applied electric field and the intrinsic properties of their orbitals.

[0125] The previously mentioned DMI is an exchange interaction that is antisymmetric (i.e., swapping entities that are interacting will inverse the sign of any effect) and that arises due to SOC in structures with broken inversion symmetry (i.e., in a structure that does not look identical, when every part of it is inverted through a point, e.g., at an interface or surface, or in zinc-blende structure). The DMI plays an important role in the formation of complex magnetic textures and effects, such as those involving magnetic skyrmions and fast domain wall motions induced by spin-orbit torques. For instance, the DMI may arise at an interface between a ferromagnetic metal and a heavy nonmagnetic metal with large SOC. This allows for a coupling term in the Hamiltonian (quantum operator corresponding to the total energy of the system) of the form of a mixed product D ■ where SLand Sj are neighboring spins and D is the Dzyaloshinskii-Moriya vector that dictates the direction and strength of the DMI, leading to a preference for the spins IMEC VZW

[0126] PA 2023 / 359 PCT1

[0127] P61984 / WO to align and stabilize at a fixed angle (other than simply parallel or antiparallel, as in ferromagnetic and antiferromagnetic interactions).

[0128] In an implementation, the MTJ is arranged on the SOT track.

[0129] In an implementation, the 3D magnetic memory device further comprises a further MTJ located at an opposite side of the stack than the MTJ.

[0130] In an implementation, the MTJ is arranged directly above the first end of the magnetic channel on the first metallic layer, or is arranged offset from the first end of the magnetic channel on the first metallic layer.

[0131] In an implementation, a width or diameter of the MTJ is larger or smaller than, respectively, a width or diameter of the magnetic channel.

[0132] For all the implementations discussed in this disclosure, the MTJ’s dimensions and position is independent of those of the magnetic channel, and those can be varied to adjust the performances of the magnetic memory device. For example, the MTJ may appear smaller than, the same size as, or larger than the magnetic channel.

[0133] In an implementation, the MTJ comprises a magnetic free layer having a coercivity of equal to or less than 2omT, or a coercivity in a range of 1-3 mT.

[0134] Thus, the stray magnetic field of the pinning site closest to the MTJ may determine the orientation of the free layer.

[0135] The MTJ may comprise at least the free layer, a reference layer, and a tunnel barrier layer, so that it enables measuring TMR as known from conventional MRAM. In an example, the MTJ consists of two ferromagnetic layers (e.g., CoFeB) sandwiching a thin dielectric layer (e.g., MgO) through which a current can tunnel. One of the ferromagnetic layers is called the fixed layer, whereas the other is called the free layer. IMEC VZW

[0136] PA 2023 / 359 PCT1

[0137] P61984 / WO

[0138] In an implementation, the 3D magnetic memory device further comprises multiple magnetic channels each comprising magnetic material; wherein the multiple magnetic channels are arranged in a sub-array comprising rows and columns.

[0139] Notably, it is alternatively or additionally possible to superpose magnetic channels, one on top of the other, and bonding them together through, for example, wafer- to-wafer techniques or wafer-to-die techniques. This maybe considered to increase the height of the stack and the bit density of the magnetic memory device, and to further enhance the capabilities of the 3DVMAG technology. It is also not excluded that this process may be achieved with different 3DVMAG configurations, e.g., different types of magnetic channels can be combined, this being also true for an arrangement of magnetic channels in a sub-array.

[0140] In an implementation, the 3D magnetic memory device comprises a plurality of SOT tracks, a plurality of write lines, a plurality of push lines, a plurality of write selectors, and a plurality of push selectors; wherein each SOT track is connected to one write line and is associated with the magnetic channels of one row of the subarray; wherein each push line is associated with the magnetic channels of one row of the sub-array; wherein each write line is connected to a write selector controllable to pass a write current through the SOT track connected to the write line; and wherein each push line is connected to multiple push selectors, each being controllable to pass a push current through one of the magnetic channels associated with the push line.

[0141] In an implementation, the 3D magnetic memory device comprises a plurality of SOT tracks, a plurality of write lines, a plurality of push lines, and a plurality of write selectors and a plurality of push selectors; wherein each SOT track is connected to one write line and is associated with the magnetic channels of one column of the sub-array; wherein each push line is associated with the magnetic channels of one row of the sub-array; wherein each write line is connected to a write selector controllable to pass a write current through the SOT track connected to the write line; and wherein each push line is connected to a push selector controllable to pass a push current through the magnetic channels associated with the push line. IMEC VZW

[0142] PA 2023 / 359 PCT1

[0143] P61984 / WO

[0144] In an implementation, the 3D magnetic memory device further comprises a plurality of read lines; and a plurality of read selectors; wherein each read line is associated with the magnetic channels of one column of the sub-array; and wherein each read line is connected to a read selector controllable to pass a read current through the MTJs related to the magnetic channels associated with the read line.

[0145] In an implementation, the 3D magnetic memory device comprises a plurality of the sub-arrays; wherein the magnetic channels of each sub-array are individually addressable using respective write lines, push lines, and read lines.

[0146] Density improvements in the magnetic memory device can be achieved by the above implementations by incorporating more than one magnetic channel. A best density may be achieved with a design that eliminates push selectors. Moreover, the absence of push selectors allows for tighter spacing between the magnetic channels, unconstrained by selector design limitations. Consequently, additional magnetic channels can be added within the given length of an SOT track, significantly enhancing the bit density. The above implementations provide different configurations of the sub-array, including different arrangement of the write, read, and push lines.

[0147] A sub-array of the magnetic memory device may also be referred to as a tile. Such a tile is a set of magnetic channels arranged in a pattern such as a grid-like structure with rows and columns, their respective MTJs, selectors, and connections and other related components that are grouped together. The magnetic channels may share connections, e.g. common SOT track, and / or common write lines, and / or common read lines, allowing each of the memory cells to be accessed efficiently to store or retrieve data. The form a tile may depend on the memory components that compose it. Various configuration having varying number, dimensions and positions of connections, selectors, MTJs, magnetic channels, etc., are possible. Those characteristics impacts the compactness and arrangement of the components and shared connections and therefore they impact how the tile looks like but also its performance overall. IMEC VZW

[0148] PA 2023 / 359 PCT1

[0149] P61984 / WO

[0150] In an example, the memory device comprises multiple magnetic channels placed along rows to form a working block of memory (referred to as a tile). Current lines are shared between magnetic channels from the same row or from the same column. For example, in the first configuration, the write line of a row of memory channels is shared and controlled by the same write selector. Similarly, the read line of a column of magnetic channels is shared and controlled by the same read selector.

[0151] An action maybe performed in a given magnetic channel by activating a given line and a transverse line in such a way that their intersection leads to the magnetic channel. That mechanism is akin to the use of word lines and bit lines in e.g., SRAM. The push selector may individually select and affect a given magnetic channel. Thus, for write lines in this example, each write selector can control the current going through the SOT track shared by the memory channels aligned in a row, and the SOT tracks are grounded together. For push lines, the push selectors (one per magnetic channel) may control the current going through the respective magnetic channel. For read lines, each read selector (one per column) can control the current reading of the MTJs aligned in a column. They may also be connected to respective column multiplexers and sense amplifiers. The current of a write operation goes from a write selector to a vertical ground contact at an end of its associated SOT track. This path has low resistance. The current of a push operation goes from the push selector to the write selector or the other way around. This path has higher resistance. The current of a read operation goes from the read Selector to the write selector or the other way around. This path may avoid going through the magnetic channel, and has therefore lower resistance

[0152] In an implementation of the 3D magnetic memory device, at least one of the first metallic layer and the second metallic layer is made of tantalum nitride, tungsten nitride, tungsten, tantalum, platinum, hafnium, molybdenum, molybdenum nitride, or alloys thereof, or is made of a topological insulator.

[0153] These materials may allow using either the first metallic layer or the second metallic layer as an SOT track. That is, this enables sending an SOT current IMEC VZW

[0154] PA 2023 / 359 PCT1

[0155] P61984 / WO through the first or second metallic layer, in order to write a magnetic bit into the magnetic channel of the memory cell.

[0156] A second aspect of this disclosure provides a method of operating the 3D magnetic memory device of any one of the first aspect and its implementations, wherein the method comprises writing a magnetic state into the magnetic channel by passing a write current through the SOT track; and pushing the magnetic state to the first pinning site in the magnetic channel, which is closest to the SOT track, by passing a first push current through the first electrode and the magnetic channel.

[0157] In an implementation, writing the magnetic state comprises selecting a first magnetic state of the magnetic bit by passing the write current along a first direction through the SOT track, or selecting a second magnetic state of the magnetic bit by passing the write current along an opposite second direction through the SOT track.

[0158] In particular, writing a bit in the magnetic channel can be done by nucleating and growing a magnetic domain having a given orientation (magnetic state) with a current, be it with SOT, STT, or a combination thereof, which may be followed by a second current to push the magnetic domain down the magnetic channel. That may be achieved by using the SOT track, which may comprise tantalum nitride, tungsten nitride, tantalum, platinum, hafnium, molybdenum, molybdenum nitride, or alloys thereof, or a topological insulator

[0159] In an implementation, the method further comprises pushing magnetic bits along the magnetic channel, respectively from one pinning site to the next pinning site, by passing a second push current through the first electrode and the magnetic channel.

[0160] In an implementation, the method further comprises reading a magnetic bit from the magnetic channel by passing a current through the MTJ, and thereby determining a tunnel-magnetoresistance, wherein the magnetic bit stored in the pinning site in the magnetic channel closest to the MTJ is read. IMEC VZW

[0161] PA 2023 / 359 PCT1

[0162] P61984 / WO

[0163] In particular, reading can be performed by pulling out the bit to read with a current, so that the magnetic orientation may be read by the MTJ. Depending on the configurations, reading and writing may be performed on the same side of the magnetic channel, or on opposite sides. One may be performed on one side of the magnetic channel e.g. the top side (first end), while the other maybe performed on the other side e.g. the bottom side (second end), which maybe closer to a substrate, or both maybe either performed on top or on the bottom side. To allow this, the SOT track and the MTJ may be on the same side of the magnetic channel, or alternatively, the MTJ may be formed on one side while the SOT track is formed on the other side, e.g. top and bottom side or the other way around. Another possibility is to have both SOT track and MTJ on both sides of the magnetic channel.

[0164] In an implementation, the magnetic memory device comprises the second electrode, and pushing the magnetic bits along the magnetic channel comprises sending the current from the second electrode to the first electrode; or the magnetic memory device does not comprise the second electrode but comprises the second metallic layer, and pushing the magnetic bits along the magnetic channel comprises sending the current from the second metallic layer to the first electrode; or the magnetic memory device comprises the second electrode and the first metallic layer is configured as the SOT track, and pushing the magnetic bits along the magnetic channel comprises sending a bi-polar current from the second metallic layer to the first electrode.

[0165] The above implementation provides different ways of performing the push operation with the magnetic memory device of the first aspect.

[0166] In an implementation, when pushing the magnetic bits stored in the magnetic channel, the magnetic bit stored in the pinning site in the magnetic channel that is closest to the first metallic layer is destructed, and the method further comprises re-writing the destructed magnetic bit into the magnetic channel or storing the information corresponding to the destructed magnetic bit in a memory. IMEC VZW

[0167] PA 2023 / 359 PCT1

[0168] P61984 / WO

[0169] The method of the second aspect provide allows to perform a write operation, a read operation, or a push operation, with the magnetic memory device of the first aspect, particularly, in the memory cell of the magnetic memory device comprising the magnetic material channel. Similar operations can be performed, subsequently or in parallel, on different memory cells of the magnetic memory device.

[0170] The method of the second aspect achieves the same advantages as the device of the first aspect and may be extended by respective implementations as described above for the device of the first aspect.

[0171] A third aspect of this disclosure provides a method of fabricating a 3D magnetic memory device, wherein the method may comprise: forming a stack of a plurality of dielectric layers and silicon-based layers, which are alternatingly arranged one on the other; forming a hole through the stack, wherein the hole extends through the layers of the stack; filling a magnetic material into the etched hole to form a magnetic channel, wherein a plurality of stacked pinning sites defined by the plurality of layers of the stack is formed in the magnetic material channel, each pinning site being configured to store one magnetic bit; forming a first metallic layer on respectively a first end of the magnetic channel and a top layer of the stack; forming a MTJ on the first metallic layer; and forming a first electrode on the first metallic layer at a distance to the MTJ; wherein either the first metallic layer is configured as a SOT track, or the method further comprises forming a second metallic layer configured as a SOT track on respectively a second end of the magnetic channel and a bottom layer of the stack.

[0172] The method of the third aspect may have a variety of implementations, adding method steps to fabricate the various implementations of the magnetic channel. For example, fabricating a cylindrical channel, macaroni channel, or trench channel. For a cylindrical channel with varying diameter the method may comprise steps of selectively etching from within the hole, in order to recess either the dielectric layers or the silicon-based layers so as to partially broaden the hole, then filling the magnetic material into the etched hole to form a magnetic material channel, which has a first diameter here it extends through a silicon-based layer of the stack and a second diameter where it extends through a dielectric layer of the IMEC VZW

[0173] PA 2023 / 359 PCT1

[0174] P61984 / WO stack. For a macaroni channel the method may comprise steps of depositing a magnetic material onto the sidewalls of the hole, in order to form a hollow cylinder made of the magnetic material, and then filling the hollow cylinder with a dielectric material, in order to form a magnetic channel comprising the hollow cylinder and the dielectric material. For a sidewall channel, the method may comprise steps of forming the hole as a trench, e.g. rectangular trench, which extends through each layer of the stack, and forming the sidewall channel by magnetic material deposited on a first sidewall of the trench.

[0175] The method of the third aspect may lead to the same advantages as described above for the magnetic memory device of the first aspect.

[0176] A fourth aspect of this disclosure provides a 3D magnetic memory device, the magnetic memory device comprising a stack comprising a plurality of dielectric layers and silicon-based layers, which are alternatingly arranged one on the other; a trench that extends through each layer of the stack; a magnetic channel comprising magnetic material and extending through each layer of the stack, wherein the magnetic channel is a sidewall channel formed by the magnetic material being arranged on a first sidewall of the trench; wherein a plurality of pinning sites defined by the plurality of layers of the stack is formed in the magnetic channel, each pinning site being configured to store one or more magnetic bits; a first metallic layer arranged respectively on a first end of the magnetic channel and a top layer of the stack; a MTJ arranged on the first metallic layer; and a first electrode arranged on the first metallic layer at a distance to the MTJ; wherein either the first metallic layer is configured as a SOT track, or a second metallic layer of the magnetic memory device is configured as a SOT track and is arranged on respectively a second end of the magnetic channel and a bottom layer of the stack.

[0177] This aspect is directed to a sidewall channel configuration of the magnetic memory device. The sidewall channel allows for a small active surface through which current has to run. Thanks to that, a low operating current without needing to scale the device down can be achieved. IMEC VZW

[0178] PA 2023 / 359 PCT1

[0179] P61984 / WO

[0180] In an implementation of the fourth aspect, the 3D magnetic memory device further comprises a second sidewall channel; wherein the second sidewall channel is formed by magnetic material arranged on a second sidewall of the trench.

[0181] In an implementation of the fourth aspect, the trench is rectangular; and the first sidewall and the second sidewall are opposite sidewalls of the rectangular trench.

[0182] In an implementation of the fourth aspect, the trench is filled with a dielectric material.

[0183] In an implementation of the fourth aspect, the trench has a first width where it extends through a silicon-based layer of the stack, and a second width where it extends through a dielectric layer of the stack.

[0184] This maybe achieved, for example, by recesses on every other layer of the stack. In this case, those recesses play a role of pinning points between magnetic domains. Therefore, this configuration has nearly point-like pinning instead of layer pinning, and each individual layer in the magnetic channel can be exploited.

[0185] In an implementation of the fourth aspect, the trench has a constant width where it extends through a silicon-based layer of the stack, and a varying width where it extends through a dielectric layer of the stack, or vice versa.

[0186] In summary of the above, the memory architecture proposed in this disclosure is a sequential read / write structure, in which magnetic bits are vertically stacked in the form of oriented magnetic domains inside the magnetic channel made of a ferromagnetic or ferrimagnetic and / or conductive material (e.g., cobalt, nickel, iron, alloys thereof, or any of the former with the addition of boron). Domain pinning for high retention is achieved by embedding the vertical magnetic channel in the stack of the dielectric and silicon-based layers, which are alternately arranged one on top of the other along the stacking direction. The morphology of the stack can be tuned to enhance / r educe pinning. For example, the height ratio between the two types of layers may be varied, and / or different magnetic channel diameters may be formed in each type of layer. The magnetic memory device of IMEC VZW

[0187] PA 2023 / 359 PCT1

[0188] P61984 / WO this disclosure combines features of previous technologies like SOT-MRAM or 3D- NAND.

[0189] To properly exploit the 3D magnetic memory device, this disclosure provides a detailed description of the magnetic channels, the array and its various configurations, the connections, the selectors and the applied biases that are necessary to perform reading, pushing and writing operations on data within a magnetic channel cell and an array made of such bit cells. The various components and connections are made as compact as possible to achieve the highest density. This allows the creation of a new generation of 3D data storage system.

[0190] Notably, in this disclosure, individual implementations can be combined with each other arbitrarily, as long as they do not exclude each other. For example, each type of magnetic channel (cylindrical, macaroni, sidewall, constant or varying width or diameter) may be combined with each type of SOT track (first metallic layer, second metallic layer, top side and / or bottom side), and / or each arrangement of the MTJ (offset, centered, top side and / or bottom side), and / or each selection of electrodes (first, second, third electrodes), and / or each writing mechanism (SOT, STT, SOT plus STT), and / or each possible material combination. The combinations among the above are arbitrary.

[0191] BRIEF DESCRIPTION OF THE DRAWINGS

[0192] The above described aspects and implementations are explained in the following description of embodiments with respect to the enclosed drawings:

[0193] FIG. 1 shows a magnetic memory device according to this disclosure, with a cylindrical channel, the SOT track on the bottom side of the magnetic channel, and the MTJ on the top side of the magnetic channel.

[0194] FIG. 2 shows a magnetic memory device according to this disclosure, with a cylindrical channel, the SOT track on the top side of the magnetic channel, and the MTJ on the top side of the magnetic channel on the SOT track. IMEC VZW

[0195] PA 2023 / 359 PCT1

[0196] P61984 / WO

[0197] FIG. 3 shows a magnetic memory device according to this disclosure, with a cylindrical channel, the SOT track on the bottom side of the magnetic channel, MTJs on both sides of the magnetic channel, and a pushing operation via the SOT track.

[0198] FIG. 4 shows a magnetic memory device according to this disclosure, with a cylindrical channel, the SOT track on the bottom side of the magnetic channel, the MTJ on the top side of the magnetic channel, and a pushing operation via the second electrode on the SOT track.

[0199] FIG. 5 shows a magnetic memory device according to this disclosure, with a connection of write, read, and push lines, and an indication of the related current flows.

[0200] FIG. 6 shows a first exemplary array of magnetic channels, with rows of magnetic channels sharing a SOT track.

[0201] FIG. 7 shows a second exemplary array of magnetic channels, with columns of magnetic channels sharing a SOT track.

[0202] FIG. 8 shows a magnetic memory device according to this disclosure, with a cylindrical channel having varying diameter, the SOT track on the bottom side of the magnetic channel, and the MTJ on the top side of the magnetic channel.

[0203] FIG. 9 shows a magnetic memory device according to this disclosure, with more than one magnetic channel in the stack, exemplarily both of varying diameter.

[0204] FIG. 10 shows a magnetic memory device according to this disclosure, with two sidewall channels, the SOT track on the bottom side of the magnetic channels, and the MTJs on the top side of the magnetic channels. IMEC VZW

[0205] PA 2023 / 359 PCT1

[0206] P61984 / WO

[0207] FIG. 11 shows a magnetic memory device according to this disclosure, with two sidewall channels, the SOT track on the top side of the magnetic channels, and the MTJs on the top side of the magnetic channels on the SOT track.

[0208] FIG. 12 shows a magnetic memory device according to this disclosure, with two sidewall channels, two SOT tracks on the top side of the magnetic channels, and the MTJs on the top side of the magnetic channels on the SOT tracks.

[0209] FIG. 13 shows a magnetic memory device according to this disclosure, with two sidewall channels with offset magnetic material, two SOT tracks on the top side of the magnetic channels, and the MTJs on the top side of the magnetic channels on the SOT tracks.

[0210] FIG. 14 shows a magnetic memory device according to this disclosure, with two sidewall channels with offset and partly tapered magnetic material, two SOT tracks on the top side of the magnetic channels, and the MTJs on the top side of the magnetic channels on the SOT tracks.

[0211] FIG. 15 shows a magnetic memory device according to this disclosure, with two sidewall channels with offset and partly tapered magnetic material, a filled trench, two SOT tracks on the top side of the magnetic channels, and the MTJs on the top side of the magnetic channels on the SOT tracks.

[0212] FIG. 16 shows magnetic memory device according to this disclosure, with respectively two sidewall channels, but with different aspect ratios between width and height of the stack. IMEC VZW

[0213] PA 2023 / 359 PCT1

[0214] P61984 / WO

[0215] FIG. 17 shows a magnetic memory device according to this disclosure, with a macaroni channel, the SOT track on the bottom side of the magnetic channel, and the MTJ on the top side of the magnetic channel.

[0216] FIG. 18 shows a magnetic memory device according to this disclosure, with a macaroni channel having varying diameter, the SOT track on the bottom side of the magnetic channel, and the MTJ on the top side of the magnetic channel.

[0217] FIG. 19 shows a magnetic memory device according to this disclosure, with a multi-layered macaroni channel, the SOT track on the bottom side of the magnetic channel, and the MTJ on the top side of the magnetic channel.

[0218] FIG. 20 shows exemplary implementations for stabilizing a SOT / DMI based writing of a bit into the magnetic channel.

[0219] FIG. 21 shows exemplary operations of a magnetic memory device according to this disclosure.

[0220] FIG. 22 shows exemplary operations of a magnetic memory device according to this disclosure.

[0221] FIG. 23 shows a flow-diagram of a method of operating a magnetic memory device according to this disclosure.

[0222] FIG. 24 shows a flow-diagram of additional operations in the method of operating a magnetic memory device according to this disclosure.

[0223] FIG. 25 illustrates a writing of a bit in a magnetic channel of a magnetic memory device according to this disclosure.

[0224] FIG. 26 illustrates a pushing of bits in a magnetic channel of a magnetic memory device according to this disclosure. IMEC VZW

[0225] PA 2023 / 359 PCT1

[0226] P61984 / WO

[0227] DETAILED DESCRIPTION OF EMBODIMENTS

[0228] FIG. 1 shows an example of a 3D magnetic memory device 10 according to this disclosure. As in all figures of a magnetic memory device 10 in this disclosure, a cress-sectional side view is shown, here in FIG. 1(a). Additionally, as in only some figured of a magnetic memory device 10 in this disclosure, also a cross-sectional top view is shown, here in FIG. 1(b).

[0229] Like all examples of the 3D magnetic memory devices 10 presented in this disclosure, the 3D magnetic memory device 10 of FIG. 1 comprises a layer stack 11, which comprises a plurality of dielectric layers 11a (e.g., oxide layers or silicon (oxide) layers) and a plurality of silicon-based layers 11b (e.g., silicon nitride layers or silicon germanium layers), which are alternatingly arranged one on the other. The dielectric layers 11a are different from the silicon-based layers 11b. The layers 11a, 11b are stacked along a stacking direction, which is the vertical direction in FIG. 1. Through this stack 11, a magnetic channel 12 is formed. The magnetic channel 12 extends through each layer 11a, 11b of the stack 11. The magnetic channel 12 may extend along a first direction, which corresponds to a stacking direction of the layers 11a, 11b of the stack 11. This first direction may be referred to as the ‘vertical direction’, as it is oriented in FIG. 1. The magnetic channel 12 may thus extend perpendicular to the surfaces of the layers 11a, 11b of the stack 11. However, it is also possible that the magnetic channel 12 extends in an angle to the surfaces of the layers 11a, 11b. The magnetic channel 12 in FIG. 1 is, as example, illustrated to be a cylindrical channel. Moreover, the cylindrical channel 12 has in FIG. 1 a constant diameter along its length through the stack 11. However, the magnetic channel 12 could also be a macaroni channel or sidewall channel, which are explained later, or could have a varying diameter along its length.

[0230] The magnetic memory device 10 of each example in this disclosure, as is shown in FIG. 1, further comprises a first metallic layer 13, which is arranged on a first end of the magnetic channel 12 and on the top (or last) layer of the stack 11. Whether the top layer of the stack is a dielectric or silicon-based layer is not crucial. The ‘top layer’ relates to the arrangement of the layers along the stacking direction of the IMEC VZW

[0231] PA 2023 / 359 PCT1

[0232] P61984 / WO layers 11a, 11b during the fabricating the stack 11, from a bottom or first layer of the stack to the top or last layer of the stack 11. On the first metallic layer 13, a MTJ 14 is arranged. In addition, a first electrode 15 (also referred to as ‘top electrode’) is arranged on the first metallic layer 13 at a distance to the MTJ 14. The MTJ 14 comprises at least a free layer, a reference layer, and a tunnel barrier layer, so that it enables measuring TMR as known from conventional MRAM. Advantageously, the MTJ 14 may comprises a magnetic free layer having a coercivity of equal to or less than 20 mT, or in a range of 1-3 mT.

[0233] As shown for the example of FIG. 1, the MTJ 14 maybe arranged directly above the first end of the magnetic channel 12 on the first metallic layer 13. In another example, it may be arranged offset from the first end, which will be shown later.

[0234] As also shown for the example of FIG. 1, the magnetic memory device 10 may comprise a second metallic layer 16, which is configured as an SOT track and is arranged on the second end of the magnetic channel 12 and a bottom layer of the stack 11. Whether the bottom layer of the stack 11 is a dielectric or silicon-based layer is not crucial. That is, the second end of the magnetic channel 12 and the bottom (or first) layer of the stack 11 are arranged on the second metallic layer 16 in this case. Being configured as an SOT track means that the second metallic layer 16 may be made of a certain material, may have a certain thickness, and may be connected to suitable electrodes, in order to allow passing an SOT current (ISOT) - also referred to as write current in this disclosure - through the second metallic layer 16, which may be used to cause a magnetic bit to be written by SOT into the pinning site defined by the layer of the stack 11 that is closest to the second metallic layer 16, as will be explained later in detail.

[0235] As mentioned before, it may specifically be the combined interaction between SOT and DMI that leads to the nucleation and stabilization of a magnetic domain with a given magnetic orientation, and that leads to an asymmetric domain wall motion, of which the direction depends on these two effects. SOT provides a mechanism to manipulate the magnetization dynamically in a desired direction, while DMI stabilizes the domain by influencing its behavior at the interface, in close proximity to the boundary between the SOT track 13, 16 and the magnetic material of the IMEC VZW

[0236] PA 2023 / 359 PCT1

[0237] P61984 / WO magnetic channel 12. From a local point of view, magnetic domain walls may be stabilized in a Neel configuration, i.e., in a configuration in which spins rotate within the plane of the domain wall to end up oriented perpendicular to the domain wall’s surface.

[0238] The effect can be explained as follows. In practice, the SOT current (e.g., provided as a pulse through the SOT track 13, 16) may orient the magnetization in the first few nanometers of the magnetic material of the magnetic channel 12, in-plane, i.e. pointing in the same direction as the electrical spin-polarized current. The spins further away from the interface are under the influence of the DMI. With respect to a cartesian coordinate system chosen such that the x and y axes align with the Dzyaloshinskii-Moriya vector and the current direction respectively, the energetic contribution can be written as follows: = -Dij[SiySjz- SizSjy].

[0239] With the magnetization close to the interface being oriented along the current, in other words along the y-axis of said coordinate system, the spin there may be rewritten as SL= Styey. To provide a stable configuration, looking for the energetic minimum gives that Sj = SjZezso that HDMI= —Dy SiySjZwith Dy > 0 indicating the efficiency of the interaction, and 5 > 0, SjZ> 0. To put it another way, this interaction favors a configuration where the two spins have a go0angle, leading to the spin located further away being oriented perpendicular to the interface between the SOT track 13, 16 and the vertical magnetic channel 12. This rule can therefore, from an initially in-plane magnet, lock a perpendicular depending on the direction of the SOT current. For example, an in-plane current pointing right leads to down magnetization, while one pointing left leads to up magnetization.

[0240] FIG. 2 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIG. 1 and FIG. 2 share IMEC VZW

[0241] PA 2023 / 359 PCT1

[0242] P61984 / WO the same reference signs. The magnetic memory device 10 of FIG. 2 has the same cylindrical channel 12 as the memory device 10 of FIG. 1.

[0243] As shown for the example of FIG. 2, instead of comprising the second metallic layer 16 like the magnetic memory device 10 of FIG. 1, the first metallic layer 13 may be configured as a SOT track. That is, the first metallic layer 13 may be made of a certain material, have a certain thickness, and may be connected to suitable electrodes, to allow passing the write or SOT current ISOT through the first metallic layer 13, which can cause a magnetic bit to be written by SOT into the pinning site defined by the layer of the stack 11 that is closest to the first metallic layer 13, as explained later.

[0244] At least one of the first metallic layer 13 and the second metallic layer 16, particularly at least the metallic layer 13, 16 that is configured as the SOT track, may be made of tantalum nitride, tungsten nitride, tungsten, tantalum, platinum, hafnium, molybdenum, molybdenum nitride, or alloys thereof, or of a topological insulator.

[0245] FIG. 2 shows further that the magnetic memory device 10 may comprise a second electrode 21 (also referred to as ‘bottom electrode’), which is arranged on or directly below a second end of the magnetic channel 12, or may be offset as shown later. The second electrode 21 may be placed directly on the second end of the magnetic channel 12 as shown, and / or the bottom layer of the stack 11. Alternatively, in the presence of the second metallic layer 16 as in FIG. 1, the second electrode 21 could be placed on the second metallic layer 16, for example, below the second end of the magnetic channel 12. The second electrode 21 may allow sending a push current Ipush into the magnetic channel 12 and towards the first electrode 15.

[0246] FIG. 3 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIG. 1, 2 and FIG. 3 share the same reference signs. The magnetic memory device 10 of FIG. 3 has the same cylindrical channel as the memory device 10 of FIG. 1 and 2. IMEC VZW

[0247] PA 2023 / 359 PCT1

[0248] P61984 / WO

[0249] As shown for the example of FIG. 3, and like in FIG. 1, the second metallic layer 16 is configured as SOT track. Moreover, in addition to the MTJ 14 arranged on the first metallic layer 13, the magnetic memory device 10 also comprises a further MTJ 32 located at an opposite side of the stack 11 than the MTJ 14.

[0250] Further, the magnetic memory device 10 of FIG. 3 comprises a third electrode 31 arranged on the first metallic layer 13 in a distance to respectively the first electrode 15 and the MTJ 14. The magnetic memory device 10 could also include the second electrode 21, which could be arranged on the SOT track 16, but it is not shown here. That is, the magnetic memory device 10 may comprise no second electrode 21 at the bottom. Without the second electrode 21, a more compact design of the 3DVMAG of the memory device 10 may be obtained, which may lead to a smaller footprint of the memory device 10 comprising multiple such 3DVMAGS. In the example of FIG. 3, the push current Ipush may be provided by sending current through both sides of the SOT track provided by the second metallic layer 16. In particular, the current can be pushed from both sides to limit the current density in the second metallic layer 16, and to increase its endurance and reliability. The current maybe pushed through the magnetic channel 12 and into the first and third electrodes 15, 31.

[0251] FIG. 4 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIGs. 1-3 share the same reference signs. The magnetic memory device 10 of FIG. 4 has the same cylindrical channel as the memory device 10 of FIGs. 1-3.

[0252] In the example of FIG. 4, the memory device 10 comprises the second electrode 21, which in this case is offset (horizontally) on the second metallic layer 16 from the second end of the magnetic channel 12. In this case, the push current can be pushed from the second electrode 21, through the SOT track 16, through the magnetic channel 12 and into at least the first electrode 15 (or also the third electrode 31, if present).

[0253] FIG. 5 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIGs. 1-4 share the IMEC VZW

[0254] PA 2023 / 359 PCT1

[0255] P61984 / WO same reference signs. The magnetic memory device 10 of FIG. 5 has the same cylindrical channel 12 as the memory device 10 of FIGs. 1-3.

[0256] FIG. 5 particularly shows that the 3D magnetic memory device 10 may comprise a write line 51, a push line 53, and a read line 55. In addition, the memory device 10 may comprise at least one write selector 52, at least one read selector 56, and optionally, at least one push selector 54.

[0257] The write line 51 is connected to the SOT track - here the second metallic layer 16, but it could also be the first metallic layer 13 - and the at least one write selector 52 is connected to the write line 51. The at least one write selector 52 is operable, for instance can be turned ON / OFF, in order to control the passing of a write current through the write line 51 and the SOT track 16. The write selector 52 may be a transistor, for example, a FET like a MOSFET.

[0258] The push line 53 is connected to one of the first electrode 15 or the second electrode 21, depending on from which side the push current is sent through the magnetic channel 12. The push line 53 is accordingly used to provide the push current from either one of the first electrode 15 and the second electrode 21 through the magnetic channel 12 to the other one of the first electrode 15 and the second electrode 21. The at least one push selector 54 can be connected to the push line 53, and can be operable (ON / OFF) to control the passing of the push current through the push line 53 and the magnetic channel 12.

[0259] The read line 55 is connected to the MTJ 14. The at least one read selector 56 is connected to the read line 55, and is operable (ON / OFF) to control the passing of a read current through the read line 55 and the MTJ 14.

[0260] Thus, the 3DVMAG (e.g. comprising magnetic channel 12, MTJ 14, SOT track 13, 16, electrodes 15, 21, 31) can be operated with only three lines that are used in order to write, read, or push bits in the magnetic channel 12. How the lines are disposed and how the currents flow may be dependent on the disposition of the SOT track 13, 16 and the MTJ 14. The MTJ 14 could be disposed at the top first end of the magnetic channel 122, or at the bottom second end of the magnetic channel 12. The IMEC VZW

[0261] PA 2023 / 359 PCT1

[0262] P61984 / WO

[0263] SOT track 113, 16 could be on the same side as the MTJ 14 or on opposite side. Hence, there several possible configurations. Moreover, one or both the MTJ and SOT track could be replicated on the opposite side, increasing the number of possibilities. Thus, there may even be an MTJ 14, 32 and a SOT track 13, 16 both at the top (first) and at the bottom (second) end of the magnetic channel 12. The position and number of lines is thus highly dependent on the configuration. For sake of simplicity, only a few configurations are illustrated in FIG. 5, 6 and 7.

[0264] FIG. 6 and 7 show a first and second exemplary sub-array 100 of magnetic channels 12, with different configurations. In both cases, multiple magnetic channels 12 - which can be configured the same or differently - are arranged in two or more rows and columns of the sub-array 100. In FIG. 6, the rows of magnetic channels 12 share an SOT track (could be either the first or second metallic layer 13, 16), and in FIG. 7 the columns of magnetic channels 12 share the SOT track 13, 16. The magnetic memory device 10 may comprise multiple such sub-arrays 100 to form a memory array. Each of the sub-arrays 100 maybe individually addressable using respective write lines 51, push lines 53, and read lines 55. A sub-array 100 maybe referred to as tile.

[0265] In particular, in FIG. 6, the magnetic memory device 10 comprises a plurality of SOT tracks 13, 16, a plurality of write lines 51, a plurality of push lines 53, a plurality of write selectors 52, and a plurality of push selectors 54. Each SOT track 13, 16 is associated with the magnetic channels 12 of one row of the sub-array 100, and each SOT track 13, 16 is connected to one write line 51. Each push line 53 is associated with the magnetic channels of one row of the sub-array 100. Each write line 51 is connected to a write selector 52 operable to pass a write current through the SOT track 13, 16 and connected to the write line 51. Each push line 53 is connected to multiple push selectors 54, each being operable to pass a push current through one of the magnetic channels 12 associated with the push line 53.

[0266] In FIG. 7, each SOT track 13, 16 is connected to one write line 51 and is associated with the magnetic channels 12 of one column of the sub-array 100. Each push line 53 is associated with the magnetic channels 12 of one row of the sub-array 100. Each write line 51 is connected to a write selector 52 operable to pass a write IMEC VZW

[0267] PA 2023 / 359 PCT1

[0268] P61984 / WO current through the SOT track 13, 16 connected to the write line 51. Each push line 53 is connected to a push selector 54 operable to pass a push current through the magnetic channels 12 associated with the push line 53.

[0269] In either case of FIG. 6 and FIG. 7, the sub-array 100 may further comprise a plurality of read lines 55 and read selectors 56. Each read line 55 maybe associated with the magnetic channels 12 of one column of the sub-array 100. Each read line 55 may be connected to a read selector 56 operable to pass a read current through the MTJs 14 related to the magnetic channels 12 associated with the read line 55.

[0270] Different ways of operating the selectors, in order to send relevant currents through the sub-array 100, are possible and described later.

[0271] FIG. 8 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIGs. 1-5 share the same reference signs. The magnetic memory device 10 of FIG. 8 has a cylindrical channel 12, as the memory device 10 of FIGs. 1-5, however in FIG. 8 the cylindrical channel 12 has a varying diameter.

[0272] In particular, the magnetic channel 12 has a first diameter di where it extends through a silicon-based layer 11b, and has a second diameter d2 where it extends through a dielectric layer 11a of the stack 11.

[0273] This varying diameter may be caused by partly recessing either the silicon-based layers 11b or the dielectric layers 11a of the stack 11 during the fabrication of the memory device 10, before forming the magnetic material channel 12. For example, the first diameter di may be larger than the second diameter d2 as shown in FIG. 8, but this can also be the other way around. In an example, a ratio between the first diameter di and the second diameter d2 is respectively in a range of 1.1:1 to 2:1 or in a range of 1:1.1 to 1:2.

[0274] Due to the alternation of the layers 11a, 11b of the stack 11, and further enhanced by the varying diameter of the magnetic channel 12, the plurality of pinning sites, defined by the plurality of layers 11a, 11b of the stack, are formed in the magnetic IMEC VZW

[0275] PA 2023 / 359 PCT1

[0276] P61984 / WO channel 12. It maybe beneficial for the pinning sites, that the transitions between the first diameter di and the second diameter d2 are aligned with interfaces between the alternatingly arranged layers 11a, 11b of the stack 11.

[0277] Notably, FIG. 8 shows the SOT track being the second metallic layer 16, shows one centered (not offset) MTJ 14 on the opposite side of the SOT track 16, and shows a first electrode 15. However, all the variations described in FIGs. 1-5, like the SOT track being the first metallic layer 13, two (offset) MTJs 14, 32, a third electrode 31, offset MTJ 14, and second electrode 21 or not, etc., are also applicable to the varying diameter implementation. Likewise materials can be the same.

[0278] FIG. 9 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIGs. 8 and 9 share the same reference signs. The magnetic memory device 10 of FIG. 9 has a cylindrical channel 12 with varying diameter as in FIG. 8. However, in FIG. 9, the magnetic memory device 10 has at least two such magnetic channels 12 that run in parallel through the stack 11. Accordingly, to form two 3DVMAG elements, the memory device 10 has also two MTJs 14, two first electrodes 15, and two second electrodes 21. Notably, the channels 12 do not have to be strictly parallel, and of course more than two channels and 3DVMAG can be fabricated.

[0279] Notably, like for FIG. 8, also for FIG. 9 all the variations described in FIGs. 1-5 are applicable. Moreover, the channels 12 in FIG. 9 could be cylindrical channels 12 with constant diameter or could be macaroni channels.

[0280] FIG. 10 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIG. 10 and FIGs. 1-5 share the same reference signs. The magnetic memory device 10 of FIG. 10 is related to a sidewall channel as the magnetic channel 12.

[0281] In particular, FIG. 10 shows that the magnetic memory device 10 has two sidewall channels 12. It also has the SOT track on the bottom side of the sidewall channels, i.e. implemented by the second metallic layer 16, and the MTJs 14 on the top side IMEC VZW

[0282] PA 2023 / 359 PCT1

[0283] P61984 / WO of the sidewall channels. However, like for FIG. 8 and FIG. 9, all the variations described in the FIGs. 1-5 are applicable also here to FIG. 10.

[0284] The sidewall channels 12 are formed in a trench 91 that extends through each layer 11a, 11b of the stack. In particular, a sidewall channels 12 are formed by magnetic material arranged on a first sidewall 93 of the trench 91, and by magnetic material arranged on a second sidewall 94 of the trench 91. The magnetic material maybe the same and deposited simultaneously during processing. The trench 91 maybe a rectangular trench, and the first sidewall 93 and the second sidewall 94 may accordingly be opposite sidewalls of the rectangular trench 91. The trench 91 may be filled with a dielectric material 92 (for instance an oxide-based material, such as silicon oxide) or not (e.g., can be empty, air).

[0285] That is, in this implementation of the magnetic memory device 10, the trench 91 is formed in the stack 11, and inside the trench 91 one or multiple vertical magnetic channels 12 - the sidewall channels - made of a magnetic material are formed. The channels 12 may be made of a ferromagnetic, ferrimagnetic and / or conductive material. For example, they maybe made of cobalt, iron, nickel, alloys thereof, or any of the former with the addition of boron. The dielectric layers 11a maybe silicon oxide layer or silicon layer, while the silicon-based layers 11b maybe silicon nitride layer or silicon germanium layer.

[0286] The vertical sidewall channels may be connected to electrodes, to SOT generating layers (SOT track), i.e., either the first metallic layer 13 or second metallic layer 16) and MTJs 14 of arbitrary size. In this respect, FIG. 10 shows that the second metallic layer 16 is configured as SOT track, while FIG. 11 shows the first metallic layer 13 is configured as SOT track (and the second metallic layer 16 can be omitted). The SOT track maybe equipped with one or multiple MTJs 14, allowing it to read bits in the sidewall channel(s) to which it is connected. The size of MTJs 14 can be fine-tuned to allow for the adjustment of reading performances. The SOT track 13, 16 may be made of a metallic layer which may be composed of tantalum nitride, tungsten nitride, tantalum, platinum, hafnium, molybdenum, molybdenum nitride, or alloys thereof, or is made of a topological insulator. IMEC VZW

[0287] PA 2023 / 359 PCT1

[0288] P61984 / WO

[0289] The sidewall channel(s) 12 allow(s) for the reduction of the active surface through which STT current (push current) has to run through. Thanks to that, a current reduction can be achieved compared to the cylindrical channel, without needing to scale the 3DVMAG down.

[0290] FIG. 12 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIGs. 10-12 share the same reference signs. The magnetic memory device 10 of FIG. 10 has the same sidewall channel as the memory device 10 of FIGs. 10 and 11. In particular, FIG. 12 shows that the magnetic memory device 10 with the two sidewall channels 12 can include two SOT tracks, for instance, on the top side of the magnetic channels 12, and the MTJs 14 can be arranged on the SOT tracks and offset from the first end of the magnetic channels 12.

[0291] FIG. 13 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIG. 10-13 share the same reference signs. The magnetic memory device 10 of FIG. 13 has the same sidewall channel 12 as the memory device 10 of FIGs. 10-12. In particular, FIG. 13 shows two sidewall channels with offset magnetic material, two SOT tracks on the top side of the magnetic channels 12, and the MTJs 14 on the top side of the magnetic channels on the SOT tracks.

[0292] The offset magnetic material means that the trench 91 has a first width wi where it extends through a silicon-based layer 11b of the stack 11, and has a second width w2 where it extends through a dielectric layer 11a of the stack 11. The first width wi may larger be than the second width w2 as shown, but that may also be vice versa. This is in contrast to the previous FIGs. 10-12, where the trench 91 has a constant width through the stack 11. As the trench 91 has varying width, it maybe considered recessed every other layer. In the implementation with such recesses, those recesses play a role of pinning points arranged in-between magnetic domains. Therefore, this implementation leads to a nearly point -like pinning instead of layer pinning, for example, and each individual layer in the magnetic channel 12 can be exploited. IMEC VZW

[0293] PA 2023 / 359 PCT1

[0294] P61984 / WO

[0295] FIG. 14 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIG. 10-14 share the same reference signs. The magnetic memory device 10 of FIG. 14 has the same sidewall channel 12 as the memory device 10 of FIGs. 10-12. In particular, FIG. 14 shows that the magnetic memory device 10 has two sidewall channels with offset and partly tapered magnetic material, two SOT tracks on the top side of the sidewall channels 12, and the MTJs 14 on the top side of the sidewall channels 12 on the SOT tracks 13.

[0296] In FIG. 14, the trench 91 has a constant width where it extends through a silicon- based layer 11b of the stack 11, and has a varying width where it extends through a dielectric layer 11a of the stack 11, however, this could be vice versa. In other words, the trench 91 may have a tapered recess every other layer. A distance between the sidewalls 93 and 94 of the trench 91 may be gradually reduced in a given type of layer - here the silicon-based layers 12b - downwards against the stacking direction (or increased in the stacking direction).

[0297] It is, however, also possible that the distance between the sidewalls 93 and 94 is increasing gradually in a given type of layer - here the silicon-based layer 11b - downwards against the stacking direction (or reduced in the stacking direction). This is illustrated in FIG. 15, which shows a magnetic memory device 10 with two sidewall channels 12 with offset and partly tapered magnetic material, a dielectricmat erial -filled trench 91, two SOT tracks 13 on the top side of the magnetic channels 12, and the MTJs 14 on the top side of the magnetic channels on the SOT tracks 13. Same elements of the memory devices 10 in FIG. 10-15 share the same reference signs.

[0298] To fabricate this magnetic memory device 10, the stack 11 of the plurality of silicon- and dielectric-based layers 11a, 11b is first built and planarized (e.g. with chemicalmechanical polishing (CMP). The morphology of the stack 11 may be tuned, for example, by varying the thickness of a set of layers, to improve performances of the vertical channels 12 to be fabricated such as stray field strength, pinning strength. Following that initial step, instead of a cylindrical hole in a similar fashion as for IMEC VZW

[0299] PA 2023 / 359 PCT1

[0300] P61984 / WO the cylindrical channel 12 described previously, trench features are etched onto the surface of the stack 11 and the holes thereby created extend through the layers 11a, 11b of the stack 111. In other words, holes with an extension in both one horizontal direction and the vertical direction, for example a rectangular hole, are formed. This avoids having too high aspect ratio between horizontal and vertical dimensions, and thereby leads to less process complexity.

[0301] Optional recesses (varying width of the trench 91) are then made in one or the other type of layers (which type is not crucial), for instance, by selectively etching from within the trench 91, so as to partially broaden the trench 91. The depth of the recesses - i.e. the difference between the width wi and w2 - can be tuned to adjust the domain pinning strength to achieve a good operating window or adjust retention requirements. It thus opens the path for tailored performance. The difference in etching between types of layers 11, 11b maybe clearly defined, in other words the etching may have a uniform depth in a given layer 11a or 11b, while having the depth different from adjacent layers, as described with respect to FIG. 13, for example. However, in some other cases, the etching may increase or decrease gradually by forming the tapered recesses, leading to evolving crosssections in a given type of layer, as described with respect to FIG. 14 and FIG. 15.

[0302] Then, the magnetic channels are patterned conformally onto the sidewalls 93, 94 of the trench 91, while following the shape of the recesses, with a layer thickness of the order of 1-30 nm. The thinner the layer of the sidewall channels 12, the lower the required power to operate the magnetic memory device 10. In the most extreme case, as shown in FIG. 16(b), the working principle of the magnetic memory device 10 may enter a new regime, where interfacial interactions and effects become more predominant than bulk effects. This may induce a change in the behavior and configurations of the 3DVMAGS, for example, by changing the out-of-plane magnetic orientations into in-plane orientations.

[0303] A change of regime may also be achieved by vertical scaling instead of horizontal scaling, as shown in Figure 16a. By decreasing the thickness of the silicon- and dielectric-based layers 11a, 11b, flat magnetic domains may be formed and can experience similar changes as in horizontal scaling, where interfacial effects IMEC VZW

[0304] PA 2023 / 359 PCT1

[0305] P61984 / WO become more important. This allows increasing the bit density and leads to smaller stray fields, making the magnetic memory device 10 more reliable.

[0306] Finally, the trench is optionally filled with a dielectric material, such as an oxidebased material. If any excess filling is formed on top, it can be removed with techniques such as chemical-mechanical polishing. Connections, SOT tracks, MTJ are then formed to form the device.

[0307] A possibility to achieve even longer magnetic channels 12 without encountering the limitations of high aspect ratio etching is to superpose a plurality (e.g., 2, 3, 4, 5, or even more, as long as the fabrication is not limited by technical constraints, and as long as the performance and operation do not downgrade, for example, by requiring a too high current, which could damage components or lead to too high power consumption) 3DVMAG one on top of the others and bond them together with methods including wafer-to-wafer techniques or wafer-to-die techniques. That allows for the creation of tall structures with high bit density. The bonding may be performed on a combination of 3DVMAG, and it is not excluded that they are different from one another, for instance, regarding their type of magnetic channel 12.

[0308] Several advantages can be achieved in summary with the sidewall channel 12. Forming the trench 91 instead of a high aspect ratio hole may reduce the complexity of the subsequent processing steps, and therefore allows scaling down while keeping the fabrication economically viable and sustainable. That also means that a higher density by packing more 3DVMAG closer together can be achieved. At the same time, it could also allow etching deeper and fabricate longer vertical magnetic channels 12. Further, since the cross-sectional surface is reduced, the current to run through the channel 12 is quite small, leading to less overall consumption. It also relaxes the dependence on scaling to achieve lower current which allows keeping fabrication cheap and manageable. Also, due to its shape, the stability of the magnetic sidewall channel 12 is enhanced, since the magnetic anisotropy of the individual magnetic domain is reinforced. For the implementation with recesses (varying trench diameter), the recesses do not lead IMEC VZW

[0309] PA 2023 / 359 PCT1

[0310] P61984 / WO to in-plane magnetization but only act as standard pinning points. This offers a potential two-fold increase in bit density, because bits maybe stored in each layer.

[0311] FIG. 17 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIG. 10 and FIGs. 1-5 share the same reference signs. The magnetic memory device 10 of FIG. 17 is related to a macaroni channel as the magnetic channel 12.

[0312] The magnetic macaroni channel 12 comprises a hollow cylinder 12a made of a magnetic material, and comprises a dielectric material 12b that fills the (inner core of the) hollow cylinder 12a. Accordingly, the magnetic channel 12 is referred to as a macaroni channel or a macaroni-type channel, with reference to similar channels in 3D NAND devices. The hollow cylinder 12a may have a constant wall thickness ti along its length of extension through the stack 11. The hollow cylinder 12a may have a constant outer diameter d4 along its length. A diameter of the inner core of the hollow cylinder 12a, which is filled by the dielectric material 12b, may be constant as well. The dielectric material 12b also has a cylindrical shape in this case.

[0313] The magnetic material of the hollow cylinder 12a may be or comprise a ferromagnetic or ferrimagnetic material. Alternatively or additionally, it maybe or comprise a conductive material. As an example, the magnetic material may comprise at least one of cobalt, iron, nickel, or an alloy of these. The magnetic material may also be any of the former in addition to boron. The dielectric material 12b may be an oxide, for instance, silicon oxide.

[0314] FIG. 17 shows the magnetic memory device 10 having particularly the second metallic layer 16 configured as SOT track 16, having the second electrode 21 below the second end of the magnetic channel 12 on the SOT track 16, and having the MTJ 14 above the first end of the magnetic channel 12 on the first metallic layer 13. However, all the variations described in FIGs. 1-5, like the SOT track being the first metallic layer 13, two MTJs 14, 32, a third electrode 31, offset MTJ 14, and second electrode 21 or not, etc., are also applicable to the macaroni channel implementation. Likewise materials. IMEC VZW

[0315] PA 2023 / 359 PCT1

[0316] P61984 / WO

[0317] FIG. 18 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIGs. 17 and 18 share the same reference signs. The magnetic memory device 10 of FIG. 18 has the macaroni channel 12 as well.

[0318] In the 3D magnetic memory device 10 of FIG. 18, the magnetic channel 12 has a first (outer) diameter di where it extends through a silicon-based layer 11b, and has a second (outer) diameter d2 where it extends through a dielectric layer 11a of the stack 11. That is, the macaroni channel 12 has a varying diameter. This may be achieved by partly recessing either the silicon-based layers 11b or the dielectric layers 11a of the stack 11 during the fabrication of the memory device 10, before forming the macaroni channel 12. For example, the first diameter di may be smaller than the second diameter d2, as shown in FIG. 18, but this can also be the other way around.

[0319] The hollow cylinder 12a maybe a stepped hollow cylinder 12a, as it may comprise step-like diameter changes. However, the stepped hollow cylinder 12a may have a constant wall thickness ti. That is, the hollow cylinder 12a maybe stepped both on its outer surface and on its inner surface to the inner core. Also, the dielectric material 12b, which may be an oxide in this disclosure, may have a stepped cylindrical shape. That is, the inner core may have varying diameter, in particular, varying between a smaller diameter d5 and a larger diameter d6 from layer to layer, or vice versa.

[0320] It may be beneficial for the pinning sites formed along the magnetic channel 12, if the transitions between the first diameter di and the second diameter d2 are aligned with the interfaces between the alternatingly arranged layers 11a, 11b of the stack 11. In the case of the magnetic macaroni channel 12 having varying diameter (di and d2), the recesses can also play a role of enhancing the pinning sites inbetween magnetic domains. Therefore, this configuration may provide a nearly point -like pinning instead of layer pinning, and each individual layer 11a, 11b in the stack 11 can be exploited for a pinning site. IMEC VZW

[0321] PA 2023 / 359 PCT1

[0322] P61984 / WO

[0323] Different to what is shown in FIG. 18, the MTJ 14 maybe arranged offset from the first end of the magnetic channel 12, i.e., maybe positioned not directly above said first end of the magnetic channel 12. The MTJ 14 may thus be either closer to or further away from the first electrode 15 as in the example shown in FIG. 18. Such MTJ 14 is also referred to as being arranged out-of-plane.

[0324] Further different to what is shown in FIG. 18, the magnetic memory device 10 may comprise the second electrode 21, which maybe arranged on or directly below the second end of the magnetic channel 12. The second electrode 21 maybe placed on the second metallic layer 16. However, in the absence of the second metallic layer 16, the second electrode 11 could be placed directly on the second end of the magnetic channel 12 and the first layer of the stack 11. The second electrode 21 may allow sending a push current Ipush into the magnetic channel 12 and towards the first electrode 15. Without the second electrode 21, a more compact 3DVMAG of the memory device 10 may be obtained, which may lead to a smaller footprint of the memory device 10 comprising multiple such memory cells. In this case, the push current Ipush may be provided by sending current through both sides of the SOT track provided by the second metallic layer 16. In particular, the current is pushed from both sides to limit the current density in the second metallic layer 16, and to increase its endurance and reliability.

[0325] FIG. 19 shows another example of a 3D magnetic memory device 10 according to this disclosure. Same elements of the memory devices 10 in FIG. 19 and FIGs. 1-5 or FIGs. 17 and 18 share the same reference signs. The magnetic memory device 10 of FIG. 18 is shown to have a macaroni channel without dielectric filling 12b. However, it may also have the filling 12b. Further, the concept of FIG. 19 may apply to the cylindrical channel and the sidewall channel as well, and relates to the magnetic material.

[0326] In particular, the magnetic channel 12 can comprise a plurality of different metallic material layers 12c, i2d, i2e. For example, the plurality of metallic material layers 12c, i2d, i2e can comprise a first layer 12c and second layer i2d, which are made of opposite sign spin Hall angle materials. For example, the metallic layers could further comprise a third layer I2e, which is arranged between the first layer 12c IMEC VZW

[0327] PA 2023 / 359 PCT1

[0328] P61984 / WO and the second layer i2d and is made of a spin orbit generating and / or conductive material.

[0329] In other words, the magnetic material of the magnetic channel 12 can be made of multiple layers, for instance stacked against the wall(s) of the memory hole or trench formed in the stack 12. The magnetic channel material could be composed of three layers, the first and third layer 12c, i2d being made of a heavy metal material of opposite SHA (such as those cited previously), while the intermediate layer i2e is made of a ferromagnetic or ferrimagnetic and / or conductive material (such as those cited previously for the magnetic material). This allows achieving lower required current to operate the magnetic memory device 10.

[0330] FIG. 19 shows the magnetic memory device 10 having particularly the second metallic layer 16 configured as SOT track 16, having the second electrode 21 below the second end of the magnetic channel 12 on the SOT track 16, and having the MTJ 15 above the first end of the magnetic channel 12 on the first metallic layer 13, and having the first and third electrodes 15, 31 on the first metallic layer 13. However, all the variations described in FIGs. 1-5, like the SOT track being the first metallic layer 13, two MTJs 14, 32, no third electrode 31, offset MTJ 14, no second electrode 21, etc., are also applicable to the multi-layer magnetic channel ^implementation. Likewise materials.

[0331] Notably, in all examples and implementations of this disclosure, the dielectric layers 11a may be silicon oxide layers and the silicon-based layers 11b may be silicon nitride layers. Alternatively, the dielectric layers 11a may be silicon layers and the silicon-based layers may be silicon germanium layers. Further, in all examples of this disclosure, the magnetic channel 12 may comprise a ferromagnetic or ferrimagnetic material and / or a conductive material, for example, is made of cobalt, iron, nickel, or an alloys thereof, or any of the former in addition to boron.

[0332] In all examples and implementations of this disclosure, the SOT track (either first or second metallic layer 13, 16) maybe a monolayer made of a spin-orbit generating metallic layer wherein a current may experience SOC, such as tantalum nitride, IMEC VZW

[0333] PA 2023 / 359 PCT1

[0334] P61984 / WO tungsten nitride, tantalum, platinum, hafnium, molybdenum, molybdenum nitride, or alloys thereof, or a topological insulator. In some cases, materials characterized by low electrical resistivity are preferred to prevent sneak-path issues where the current flow through alternative pathways (and through adjacent vertical wires). By reducing the resistance of the SOT track, the resistance of the desired pathway may be made negligible compared to undesired roads. Consequently, any parasitic current taking undesired pathways would have a value that would not exceed the threshold value that would have allowed magnetic domains to be moved. By doing so, this issue is also prevented from becoming a limiting factor in the scaling of the device 10, and potentially allows for higher bit density.

[0335] In all examples and implementations of this disclosure, to further improve the writing process, the SOT track 13, 16 maybe a bi-layer with layers having opposite sign for the spin Hall angle. An example of is titanium (negative SHA) and platinum (positive SHA). Another example is tungsten (negative SHA) and platinum (positive SHA). In consequence, when a current is injected in the SOT track 13, 16, both the magnetic channel corresponding to the first layer below the SOT track and the free layer of the MTJ 14 above the SOT track are switched in the same direction (e.g., down and down). As a result, there is no longer any need to wait for a pulse in the MTJ 14 to re-switch the free layer to the configuration of the magnetic cell, leading to a net gain in time and ultimately faster operation of the device. What is more, the free layer is then more stable and can henceforth assist the wire domain formation and expansion by using its aligned stray field.

[0336] In all examples and implementations of this disclosure, another way to reduce the SOT track’s resistance is to use another type of bi- / tri -layer. For example, the first layer is a spin-orbit generating layer such as mentioned before. The second layer is an orbital torque generating layer, i.e. a layer of material that can generate an orbital angular momentum through orbital Hall effect (OHE), which can exert a magnetic torque in an adjacent magnetic layer. Candidate materials are 3d transition metals such as copper (Cu), chromium (Cr), manganese (Mn),... qd transition metals such as ruthenium (Ru), molybdenum (Mo), Rhodium (Ro),... 5d transition metals such as Platinum (Pt), tungsten (W), Osmium (Os),..., alloys IMEC VZW

[0337] PA 2023 / 359 PCT1

[0338] P61984 / WO thereof, hetero-structures thereof and topological insulators. In the case where that layer is thicker, it offers the advantage of enabling lower resistance. The third layer maybe optionally added on top of the two previous layers and below the MTJ 14 to stabilize the sensor’s readings. It may be spin-orbit generating layer like the first one but does not have to be. Its primary properties are being texture-breaking, i.e. having an abrupt change of crystalline orientation at the boundary or interface, and allowing atomic diffusion, i.e. allowing atoms to migrate from one region to another over time. Candidate materials are for example tantalum (Ta), tungsten (W) and molybdenum (Mo). The second and third layers do not have to have the same dimensions and coverage as the first layer. They may be individually patterned.

[0339] In all examples and implementations of this disclosure, it is further possible to enhance the stabilization of a written magnetic state (magnetic bit) into the magnetic channel 12. The reason for this is, that although SOT and DMI offer a fundamental mechanism dictating the switching of the magnetization of the first magnetic state in the magnetic channel 12 in a desired direction, this effect can and should in some cases be improved, in order to offer an even more reliable and deterministic selection method for practical applications (e.g., reducing a fail risk to below one fail per million). That is especially beneficial when an increase of the SOT current to mitigate this issue is not desired.

[0340] To address the stabilization issue, the SOT track 13, 16 may be further engineered with certain material choices and geometries, which can help maximizing the potential of SOT / DMI at the interface between the SOT track 13, 16 and the magnetic channel 12, by further breaking the symmetry. The following implementations can be considered to further improve the performance of the magnetization switching mechanism. It should be noted that these implementations are not mutually exclusive, and can be combined with the previously discussed SOT track 13, 16 ideas hereinabove. The implementations are shown in FIG. 20.

[0341] A first implementation is shown in FIG. 20(a) and comprises a slightly curved and / or tilted SOT track 13. This implementation may specifically include an SOT IMEC VZW

[0342] PA 2023 / 359 PCT1

[0343] P61984 / WO track geometry, wherein a layer of the SOT track 13 is locally curved, caved in, tilted in the vicinity of the vertical magnetic channel. Notably, in FIG. 20 the SOT track is shown implemented by the first metallic layer 13 (i.e., SOT track 13), but likewise implementations are possible with the SOT track being implemented by the second metallic layer 16 (i.e. SOT track 16). The curve and / or tilt may be achieved by profiting from the so-called dishing effect during chemical-mechanical polishing (CMP) or other CMP engineering, or by slightly etching the magnetic material of the magnetic channel 12 before SOT track deposition. The implementation may improve the performance of the DMI, but may still be best used with a comparatively higher SOT current to ensure deterministic switching.

[0344] A second implementation is shown in FIG. 20(b) and comprises a bi-layer or trilayer. A stronger DMI can be achieved by providing a stronger chiral coupling between in-plane magnetization and perpendicular magnetization. This may be achieved by adding an in-plane magnetic material layer 131 on top of the SOT-track 13. This may also potentially contribute to additional SOT / STT / spin pumping effects (i.e., the generation of pure spin current from a precessing magnetization in a magnetic material into an adjacent heavy metal non-magnetic material), which would further improve the efficiency of the magnetic memory device 10.

[0345] This being said, it maybe possible that the in-plane magnetic layer may break into domains of various orientations, which would decrease the efficiency of its effect or even defeat its purpose. For this reason, another implementation is shown in FIG. 20(c), and improves the implementation of FIG. 20(b) further by adding on top a third layer 132 made of an antiferromagnetic (AFM) material. This third layer 132 may help to pin the magnetization of the in-plane magnetic layer 131. Exemplary materials that may be used include platinum manganese (PtMn), iridium manganese (IrMn), or similar.

[0346] It is also possible to employ AFM materials, such as PtMn, to generate SOT current. Thus, in another implementation shown in FIG. 20(d), the SOT track 13 may both provide SOT and a means to fix the in-plane magnetization of the above layer. In FIG. 20(d), the AFM layer 132 is arranged on the SOT track 13, and the in-plane magnetic layer 131 is arranged on the AFM layer 132, whereas in FIG. 20(c) the in- IMEC VZW

[0347] PA 2023 / 359 PCT1

[0348] P61984 / WO plane magnetic layer 131 is arranged on the SOT track 13, and the AFM layer 132 on the in-plane magnetic layer 131.

[0349] Moreover, for conventional SOT-MRAM, a memory cell maybe equipped with an embedded magnet generating in-plane magnetic field. For example, a (ferro)magnet, which may have a thickness of about 50 nm, may be built with strong shape anisotropy along the horizontal (current) direction to generate a maximized and homogeneous in-plane field on the free layer (FL). Similarly, in the magnetic memory device 10 of this disclosure, instead of adding the in-plane magnetic layer 131, it is possible to embed a (ferro)magnet above the MTJ 14 in the back-end-of-line (BEOL), for instance, in the SOT hardmask. This magnet may provide a more intense in-plane magnetic field that can accentuate the inversion symmetry breaking.

[0350] FIG. 21 and 22 show exemplary operations of a magnetic memory device according to this disclosure. In particular, a magnetic memory device 10 is described, which maybe operated with a SOT current, a STT current, or a combination thereof.

[0351] A modification of the magnetic memory device 10 compared to previous implementations and figures is that the first magnetic cell of the magnetic channel 12 - where the first magnetic domain is formed during a writing operation, and which is defined by the magnetic material in the layer of the stack 11 that is closest to the SOT track 13, 16 - has an adjusted geometry. That is, said magnetic material may be implemented by a magnetic layer 22 which has a larger dimension, e.g. a larger diameter, than the rest of the magnetic channel 12, e.g., up to a width of the order of the dimensions of the SOT track, which is in the depicted example the first metallic layer 13, so that the magnetic layer 22 is formed in the top layer of the stack 11. The rest of the magnetic channel 12 may have a varying diameter or a constant diameter as described before, and may be a cylindrical full channel or a macaroni channel. The magnetic layer 22 may facilitate bit switching through the SOT track 13, by enabling a predominantly in-plane magnetization to occur.

[0352] The magnetic layer 22 may further have a smaller thickness (in stacking direction) than the corresponding layer of the stack 11, for instance, a thickness in the order IMEC VZW

[0353] PA 2023 / 359 PCT1

[0354] P61984 / WO of the spin diffusion length (SDL), which may be around a few nanometers. This may make it practical and allow the magnetic domain to be pushed down by a current running through the magnetic channel 12. Further, the material composition and number of layers for the SOT track 13, 16 and for the magnetic material in the magnetic channel 12, respectively, maybe varied.

[0355] The magnetic layer 22 of the magnetic material maybe used with a combination of SOT and STT write operation. The large dimension of the magnetic layer 22 may ensure a good anisotropy in the top layer of the stack 11, and favors in-plane magnetization, which makes switching easier since it requires less energy, as it is aligned with the SOT current. The magnetic layer 22 may also be patterned like the SOT track, e.g. into a rectangular shape, in which case it has a width rather than a diameter as the larger dimension.

[0356] The magnetic layer 22 can be made of a high magnetic moment material (e.g., cobalt, iron, and alloys thereof) that leads to efficient spin transfer torque properties and allows the production of a big (high intensity or high range) stray field that can be later read by the MTJ 14.

[0357] In case the top layer of the stack 11 presents a cavity, such as in the macaroni channel configuration, the injection current originating from the SOT track 13, and entering the magnetic layer 22 should be high enough to ensure effective switching. Moreover, to be able to read the content of the magnetic layer 22 with the MTJ 14, it maybe helpful that the magnetic layer 22 is large enough to emit enough stray field to be picked up. The magnetic layer 22 could be a very thin layer of magnetic material that covers the cavity or inner core of the macaroni channel, in this case. This may lead to a larger effective width.

[0358] For a deeper understanding, the following provides an explanation of how writing may be done in the magnetic memory device 10. Notably, this is explained regarding a magnetic memory device 10 including the magnetic layer 22, however, the same method may be applied to a magnetic memory device 10 without the magnetic layer 22, i.e., with a regular magnetic channel 12 with or without varying IMEC VZW

[0359] PA 2023 / 359 PCT1

[0360] P61984 / WO diameter, as well. There are two considered mechanisms to write an orientation into the magnetic channel.

[0361] Firstly, a positive or negative write current IS0Tfrom one of the top electrodes, e.g., the first electrode 15 or third electrode 31, to the other one of these top electrodes will generate a magnetic torque due to the SOT effect, and will determine the writing of the magnetic bit as ‘up’ or ‘down’ (for the case of perpendicular magnetization) or ‘left’ or ‘right’ (for the case of in-plane magnetization). This corresponds to selecting a magnetic state of the bit to be written into the magnetic channel 12. Hence, the orientation can be adjusted based on the chirality, i.e. on the direction the write current flows between the two top electrodes. Secondly, a contribution that can affect the orientation is the amount of current running through the magnetic channel 12. Depending on the amount of STT that is generated, an inversion of the orientation can be or not nucleated in the magnetic channel 12, e.g. the first magnetic layer 22.

[0362] To write a bit into the magnetic channel 12, e.g. into the magnetic layer 22 of the magnetic channel 12, three methods maybe used: sending pure SOT current in the SOT track 13, 16; sending pure STT current in the magnetic channel 12; sending SOT combined with STT current. The chosen methodology to write the bit can depend on application and optimization considerations. But for illustrative purposes, the following is provided.

[0363] In a first step, the SOT track 13 can be used to generate spin-orbit coupling and set the magnetic state (magnetic orientation) in the top part of the magnetic channel 12, particularly in the metallic layer 22. One of the top electrodes 15 or 31 can then be set to ground voltage, while the other is set to a write voltage, so that a write current (or SOT current) ISOT flows through the SOT track 13. For example, setting the voltage of the first electrode 15 to Vwrite may lead to a magnetic bit oriented ‘down’ later in the magnetic channel 12, whereas setting the third electrode 31 to Vwrite could lead to an ‘up’ orientation instead. This first step is depicted in FIG. 21(a) or FIG. 22(a). Further, in that first step, no current flows through neither the MTJ 14 nor the magnetic channel 12. To enable this, their respective voltage(s) IMEC VZW

[0364] PA 2023 / 359 PCT1

[0365] P61984 / WO could be floating, that is the read voltage at the MTJ 14 could be Vfioat like that of the second electrode 21. Alternatively, the respective voltage(s) can be set to an adequate voltage. For example, if the first electrode 15 is at the same distance from the first end of the magnetic channel 12 and the MTJ 14 as the third electrode 31 is from the magnetic channel 12 and the MTJ 14, then the voltage could be set to (V15 +¥31 / 2, which equals V writ eh.

[0366] In a second step, the SOT mode can be combined with a STT mode. That enables to push and write the magnetic state (magnetic domain) down to the first pinning site of the magnetic channel 12. To enable that, the second electrode 21 can be set to ground voltage, as shown in FIG. 21(b) and FIG. 22(b). The MTJ 14 (read voltage) could be set to Vpush or Vfioat, as shown in FIG. 21(b) or FIG. 22(b), respectively. A push current Ipush is generated flowing into the magnetic channel 12, which may be a STT current.

[0367] In a third step, the voltage of the first electrode 15 can be set to the same voltage as the third electrode 31, while the second electrode 21 is kept at ground voltage. As shown in FIG. 21(c), the voltages of the first and third electrode 15, 31 could be floating Vfioat, while the MTJ 14 is at Vpush. As shown in FIG. 21(d), the voltages of the first and third electrode 15, 31 could be Vwrite, while the MTJ 14 is at Vpush. As shown in FIG. 22(c), the voltages of the first and third electrode 15, 31 could be Vpush, while the MTJ 14 is floating. This third step is done to push the magnetic state / domain down the magnetic channel. No current is assumed to flow through the MTJ 14. A Push current Ipush flows in the magnetic channel 12.

[0368] As said before, these procedures could be modified with steps that can be swapped, removed, added, depending on what is aimed to be achieved and the device developments. For instance, only the second step or only the third step may be used to write the magnetic bit into the pinning site closest to the SOT track 13, 16, depending on whether the next bit to write has the same magnetic orientation or not as the first.

[0369] On the one hand, if the first magnetic bit has to be switched and then pushed down, the second step may be used and both a pulse of SOT current and a pulse of STT IMEC VZW

[0370] PA 2023 / 359 PCT1

[0371] P61984 / WO current could be provided, to nucleate and push a new magnetic domain. Incidentally, the length of the SOT pulse may be smaller or equal to the length of the STT pulse, but can vary within that range and be optimized. On the other hand, in the case where no switching is required, the third step maybe used to only push down the magnetic bit. Therefore, only a pulse of STT current as maybe applied to extend the already existing magnetic domain, in order to create a sequence of bits, with the same magnetic orientation, to be pushed down. This approach may optimize and reduce write latency by reducing the overall number of steps. To provide another example, the STT current in the third step may only come from one electrode 15, 31 on one side or the other of the magnetic channel 12, instead of both electrodes 15, 31. However, using both electrodes 15, 31 maybe advantageous to reduce the push current in both branches, as only half is necessary. As a consequence, a transistor / diode / latch-up / other used to control the access to each branch can have smaller dimensions, leading to a potential increase in bit density.

[0372] FIG. 23 shows a method 22 of operating the 3D magnetic memory device 10, which summarizes generally the above-described. The method 200 is applicable to all example and implementations of the magnetic memory device 10, which are shown in the figures and / or are described. The method 200 comprises a write operation. For the write operation, the method 200 comprises a step of writing 201 a magnetic state into the magnetic channel 12 by passing a write current through the SOT track 13, 16, and a step of pushing 202 the magnetic state to the first pinning site in the magnetic channel 12, which is closest to the SOT track 13, 16, by passing a first push current through the first electrode 15 and the magnetic channel 12. The step 201 of writing the magnetic state can comprise selecting a first magnetic state of the magnetic bit by passing the write current along a first direction through the SOT track 13, 16, or selecting a second magnetic state of the magnetic bit by passing the write current along an opposite second direction through the SOT track 13, 16.

[0373] Further, as shown in FIG. 24, the method 200 may comprise at least one of the following operations: an operation 203 of pushing magnetic bits along the magnetic material channel 12, respectively from one pinning site to the next pinning site, by passing a current through the first electrode 15 and the magnetic channel 12; an operation 204 of reading a magnetic bit from the magnetic material IMEC VZW

[0374] PA 2023 / 359 PCT1

[0375] P61984 / WO channel 12 by passing a current through the MTJ 14, and thereby determining a TMR, wherein the magnetic bit stored in the pinning site in the magnetic material channel 12 that is closest to the MTJ 14 is read.

[0376] FIG. 25 shows an example of writing a magnetic bit into a magnetic memory device 10 according to this disclosure. FIG. 25 shows in particular the exemplary memory device 10 of FIG. 1 for illustrating the writing operation of the method 200. The writing of the magnetic bit into the magnetic material channel 12 starts by passing the current ISOT through the second metallic layer 16, which is configured as the SOT track, as shown in FIG. 25(a). The magnetic bit state for the first bit, to be written into the pinning site in the magnetic channel 12, which is closest to the SOT track, i.e., the pinning site corresponding to the first layer of the channel 12 in this case, is selected. A positive or negative current ISOT will determine the writing of the magnetic bit as ‘up’ or ‘down’ (for the case of perpendicular magnetization) or ‘left’ or ‘right’ (for the case of in-plane magnetization). For instance, in FIG. 25(b), the writing of the magnetic bit will result in a switching of the bit, i.e., a switching of the magnetization in the corresponding pinning site. The writing concludes with pushing the magnetic state to the first pinning site in the magnetic channel 12, by passing a first push current Ipushi through the first electrode 15 and the magnetic channel 12, as shown in FIG. 25(b).

[0377] FIG. 26 shows an example of pushing magnetic bits in a magnetic memory device 10 according to this disclosure. FIG. 26 shows in particular the example of FIG. 1 for illustrating the pushing operation, following the writing operation shown in FIG. 25. The pushing of the magnetic bits moves the magnetic bits along the magnetic material channel 12 from one pinning site to the next pinning site. As the example of FIG. 4 is used, magnetic bits are pushed upwards in the magnetic channel 12 in FIG. 26, i.e., towards the MTJ 14.

[0378] The magnetic bits are pushed by passing a second push current Ipush2 through the first electrode 15. In FIG. 26, the current is sent into the second electrode 21 towards the first electrode 15. If there would be no second electrode 41, the current Ipush2could be sent towards the first electrode 15 using the second metallic layer 16. During the pushing operation, a pulse timing may beneficially coincide with a IMEC VZW

[0379] PA 2023 / 359 PCT1

[0380] P61984 / WO domain wall movement of one period (one pinning site). The push current Ipush2will shift all magnetic bits (pinned magnetic domains) upwards by one pinning site. At the top of the magnetic channel 12 in FIG. 26, the surface of the first end of the magnetic channel 12 is advantageously flat, e.g., it may be flattened by chemical mechanic polishing (CMP). The first metallic layer 13 may function as a thin metallic spacer layer in this case (wherein it could be made of TaN), in order to provide a path for the current to go to the first electrode 15. Notably, the first push current Ipushi may be different from the second push current Ipush2, for example, it maybe smaller.

[0381] For reading a magnetic bit, the magnetic state of the uppermost magnetic bit may be sensed in the magnetic memory device 10. This can be done by using, in this case, the top-pinned MTJ 14. The free layer of the MTJ 14 may be deposited in direct contact with the first metallic layer 13. The free layer may have the above- mentioned low coercivity of 40 mT or less, such that the stray magnetic field of the top magnetic bit (e.g., ‘up’ or ‘down’, higher than the free layer coercivity) may determine the orientation of the free layer. The actual sensing can then be done by reading the resistance of the MTJ 14 and the TMR effect.

[0382] Since, in this example, the magnetic bit reaching the top of the magnetic channel 12 - which may be read using the MTJ 14 - will be annihilated at the next push operation, the read operation of the magnetic memory device 10 may be a destructive read. The magnetic bit may then either be re-written at the bottom of the magnetic material channel 12, i.e., at the SOT track, or maybe stored in a buffer memory, for instance, for a later burst write.

[0383] The magnetic memory device 10 may, for example, operate in a ‘full string’ writing and / or reading mode. This means that the smallest addressable bit -length may be equal to the number of bi-layers 11a / 11b in the stack 11. However, the operation mode of the magnetic memory device 10 may also be determined by architectural choices on the array and system level.

[0384] In the claims as well as in the description of this disclosure, the word ‘comprising’ does not exclude other elements or steps and the indefinite article ‘a’ or ‘an’ does IMEC VZW

[0385] PA 2023 / 359 PCT1

[0386] P61984 / WO not exclude a plurality. A single element may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

IMEC VZWPA 2023 / 359 PCT1P61984 / WOClaims1. A three dimensional, 3D, magnetic memory device (10), the magnetic memory device (10) comprising a stack (11) comprising a plurality of dielectric layers (11a) and silicon-based layers (11b), which are alternatingly arranged one on the other; a magnetic channel (12) comprising magnetic material and extending through each layer (11a, 11b) of the stack (11); wherein a plurality of pinning sites defined by the plurality of layers (11a, 11b) of the stack (11) is formed in the magnetic channel (12), each pinning site being configured to store one or more magnetic bits; a first metallic layer (13) arranged respectively on a first end of the magnetic channel (12) and a top layer (11a, 11b) of the stack (11); a magnetic tunnel junction, MTJ, (14) arranged on the first metallic layer (13); and a first electrode (15) arranged on the first metallic layer (13) at a distance to the MTJ (14); wherein either the first metallic layer (13) is configured as a spin orbit torque, SOT, track, or a second metallic layer (16) of the magnetic memory device (10) is configured as a SOT track and is arranged on respectively a second end of the magnetic channel (12) and a bottom layer (11a, 11b) of the stack (11).

2. The 3D magnetic memory device (10) according to claim 1, further comprising a write line (51) connected to the SOT track (13, 16); and at least one write selector (52) connected to the write line (51); wherein the at least one write selector (52) is controllable to pass a write current through the write line (51) and the SOT track (13, 16).

3. The 3D magnetic memory device (10) according to claim 1 or 2, further comprising a second electrode (21) arranged on or below the second end of the magnetic channel (12).IMEC VZWPA 2023 / 359 PCT1P61984 / WO4. The 3D magnetic memory device (10) according to claim 3, further comprising a push line (53) connected to one of the first electrode (15) and the second electrode (21); wherein the push line (53) is configured to provide a push current from one of the first and the second electrode (15, 21) through the magnetic channel (12) to the other one of the first and the second electrode (15, 21).

5. The 3D magnetic memory device (10) according to claim 4, further comprising at least one push selector (54) connected to the push line (53); wherein the at least one push selector (54) is controllable to pass the push current through the push line (53) and the magnetic channel (12).

6. The 3D magnetic memory device (10) according to claim 3 and 5, wherein for writing a bit into the magnetic channel (12), the magnetic memory device(10) is configured to control the at least one write selector (52), in order to select a magnetic state of the magnetic bit, and to control the at least one push selector (54), in order to push the magnetic bit to the pinning site closest to the SOT track (13, 16).

7. The 3D magnetic memory device (10) according to one of the claims 1 to 6, further comprising a read line (55) connected to the MTJ (14); and at least one read selector (56) connected to the read line (55); wherein the at least one read selector (56) is controllable to pass a read current through the read line (55) and the MTJ (14).

8. The 3D magnetic memory device (10) according to one of the claims 1 to 7, further comprising a third electrode (31) arranged on the first metallic layer (13) in a distance to respectively the first electrode (15) and the MTJ (14).IMEC VZWPA 2023 / 359 PCT1P61984 / WO9. The 3D magnetic memory device (10) according to one of the claims 1 to 8, wherein the magnetic channel (12) is one of a cylindrical channel (12); a macaroni channel (12); a sidewall channel (12).

10. The 3D magnetic memory device (10) according to claim 9, further comprising a trench (91) that extends through each layer (11a, 11b) of the stack (11); wherein the sidewall channel (12) is formed by magnetic material arranged on a first sidewall (93) of the trench (91).

11. The 3D magnetic memory device (10) according to claim 10, further comprising a second sidewall channel (12); wherein the second sidewall channel (12) is formed by magnetic material arranged on a second sidewall (94) of the trench (91).

12. The 3D magnetic memory device (10) according to claim 10 or 11, wherein the trench (91) is rectangular; and the first sidewall (93) and the second sidewall (94) are opposite sidewalls of the rectangular trench (91).

13. The 3D magnetic memory device (10) according to one of the claims 10 to12, wherein the trench (91) is filled with a dielectric material (92).

14. The 3D magnetic memory device (10) according to one of the claims 10 to13, wherein the trench (91) has a first width (wi) where it extends through a silicon- based layer (11b) of the stack (11), and a second width (w2) where it extends through a dielectric layer (11a) of the stack (11).IMEC VZWPA 2023 / 359 PCT1P61984 / WO15. The 3D magnetic memory device (10) according to one of the claims 10 to 13, wherein the trench (91) has a constant width where it extends through a silicon- based layer (11b) of the stack (11), and a varying width where it extends through a dielectric layer (11a) of the stack (11), or vice versa.

16. The 3D magnetic memory device (10) according to claim 9, wherein the macaroni channel (12) comprises a hollow cylinder (12a) made of magnetic material, and dielectric material (12b) that fills the hollow cylinder (12a).

17. The 3D magnetic memory device (10) according to claim 16, wherein the hollow cylinder (12a) is a stepped hollow cylinder and / or has a constant outer diameter (d4) along its length through the layers (11a, 11b) of the stack (11).

18. The 3D magnetic memory device (10) according to claim 17, wherein the stepped hollow cylinder (12a) has a constant wall thickness (ti).

19. The 3D magnetic memory device (10) according to one of the claims 16 to 18, wherein at the first end of the magnetic channel (12), an inner core of the hollow cylinder (12a) has a diameter (d3, ds) of up to 200 nm, or a diameter (d3, ds) in a range of 10-80 nm.

20. The 3D magnetic memory device (10) according to one of the claims 1 to 19, wherein the magnetic channel (12) is made of a plurality of different metallic material layers (12c, i2d, i2e).

21. The 3D magnetic memory device (10) according to claim 20, wherein the plurality of metallic material layers (12c, i2d, i2e) comprises a first layer (12c) and second layer (i2d), which are made of opposite sign spin Hall angle materials.IMEC VZWPA 2023 / 359 PCT1P61984 / WO22. The 3D magnetic memory device (10) according to claim 21, further comprising a third layer (i2e), which is arranged between the first layer (12c) and the second layer (i2d) and is made of a spin orbit generating and / or conductive material.

23. The 3D magnetic memory device (10) according to one of the claims 1 to 22, wherein a length of the magnetic channel (12) along its extension direction through the layers (11a, 11b) of the stack (12) is in a range of 5-150 nm times the number of layers (11a, 11) of the stack (11).

24. The 3D magnetic memory device (10) according to one of the claims 1 to 9 and 16 to 23, wherein the magnetic channel (12) has a first diameter (di) where it extends through a silicon-based layer (11b), and a second diameter (d2) where it extends through a dielectric layer (11a) of the stack (11).

25. The 3D magnetic memory device (10) according to claim 24, wherein the first diameter (di) is larger or smaller than the second diameter (d2) and / or wherein a ratio between the first diameter (di) and the second diameter (d2) is respectively in a range of 1.1:1 to 2:1 or in a range of 1:1.1 to 1:2.

26. The 3D magnetic memory device (10) according to claim 24 or 25, wherein transitions between the first diameter (di) and the second diameter (d2) are aligned with interfaces between the alternatingly arranged layers (11a, 11b) of the stack (11).

27. The 3D magnetic memory device (10) according to one of the claims 1 to 26, wherein the magnetic channel (12) is made of a ferromagnetic or ferrimagnetic material and / or a conductive material, for example, is made of cobalt, iron, nickel, or an alloy thereof, or any of the former in addition to boron.IMEC VZWPA 2023 / 359 PCT1P61984 / WO28. The 3D magnetic memory device (10) according to one of the claims 1 to 27, wherein a thickness of the silicon-based layers (11b) and the dielectric layers (11a) along their stacking direction in the stack (11) is respectively in range of 5-150 nm.

29. The 3D magnetic memory device (10) according to one of the claims 1 to 28, wherein the stack (11) has a length that is smaller than its width; or the stack (11) has a width that is smaller than its length.

30. The 3D magnetic memory device (10) according to one of the claims 1 to 29, wherein the layer (11a, 11b) of the stack (11), which is closest to the SOT track (13, 16), has different dimensions and / or has a different shape than the other layers (11a, 11b) of the stack (11).

31. The 3D magnetic memory device (10) according to one of the claims 1 to 30, wherein the SOT track (13, 16) is a single layer.

32. The 3D magnetic memory device (10) according to one of the claims 1 to 30, wherein the SOT track (13, 16) is a bi-layer, or is a tri-layer, or is a multi-layer.

33. The 3D magnetic memory device (10) according to claim 32, wherein the SOT track (13, 16) comprises a first layer and a second layer, which are made of opposite sign spin Hall angle materials.

34. The 3D magnetic memory device (10) according to claim 33, wherein the SOT track (13, 16) comprises a thinner first layer made of a spin orbit generating material, and a thicker second layer made of an orbital torque generating material.

35. The 3D magnetic memory device (10) according to claim 33 or 34, whereinIMEC VZWPA 2023 / 359 PCT1P61984 / WO the SOT track (13, 16) comprises a third layer arranged between the MTJ (14) and the first or second layer of the SOT track (13, 16).

36. The 3D magnetic memory device (10) according to one of the claims 1 to 35, wherein the MTJ (14) is arranged on the SOT track (13, 16).

37. The 3D magnetic memory device (10) according to one of the claims 1 to 36, further comprising a further MTJ (32) located at an opposite side of the stack than the MTJ (14).

38. The 3D magnetic memory device (10) according to one of the claims 1 to 37, wherein the MTJ (14) is arranged directly above the first end of the magnetic channel (12) on the first metallic layer (13), or is arranged offset from the first end of the magnetic channel (12) on the first metallic layer (13).

39. The 3D magnetic memory device (10) according to one of the claims 1 to 38, wherein a width or diameter of the MTJ (14) is larger or smaller than, respectively, a width or diameter of the magnetic channel (12).

40. The 3D magnetic memory device (10) according to one of the claims 1 to 39, wherein the MTJ (14) comprises a magnetic free layer having a coercivity of equal to or less than 2omT, or a coercivity in a range of 1-3 mT.

41. The 3D magnetic memory device (10) according to one of the claims 1 to 40, comprising multiple magnetic channels (12) each comprising magnetic material; wherein the multiple magnetic channels (12) are arranged in a sub-array (100) comprising rows and columns.IMEC VZWPA 2023 / 359 PCT1P61984 / WO42. The 3D magnetic memory device (10) according to claim 41, comprising a plurality of SOT tracks (13, 16), a plurality of write lines (51), a plurality of push lines (53), a plurality of write selectors (52), and a plurality of push selectors (54); wherein each SOT track (13, 16) is connected to one write line (51) and is associated with the magnetic channels (12) of one row of the sub-array (100); wherein each push line (53) is associated with the magnetic channels of one row of the sub-array (100); wherein each write line (51) is connected to a write selector (52) controllable to pass a write current through the SOT track (13, 16) connected to the write line (51); and wherein each push line (53) is connected to multiple push selectors (54), each being controllable to pass a push current through one of the magnetic channels (12) associated with the push line (53).

43. The 3D magnetic memory device (10) according to claim 41, comprising a plurality of SOT tracks (13, 16), a plurality of write lines (51), a plurality of push lines (53), and a plurality of write selectors (52) and a plurality of push selectors (54); wherein each SOT track (13, 16) is connected to one write line (51) and is associated with the magnetic channels (12) of one column of the sub-array (100); wherein each push line (53) is associated with the magnetic channels (12) of one row of the sub-array (100); wherein each write line (51) is connected to a write selector (52) controllable to pass a write current through the SOT track (13, 16) connected to the write line (51); and wherein each push line (53) is connected to a push selector (54) controllable to pass a push current through the magnetic channels (12) associated with the push line (53).

44. The 3D magnetic memory device (10) according to claim 42 or 43, further comprising a plurality of read lines (55); and a plurality of read selectors (56);IMEC VZWPA 2023 / 359 PCT1P61984 / WO wherein each read line (55) is associated with the magnetic channels (12) of one column of the sub-array (100); and wherein each read line (55) is connected to a read selector (56) controllable to pass a read current through the MTJs (14) related to the magnetic channels (12) associated with the read line (55).

45. The 3D magnetic memory device (10) according to one of the claims 41 to 44, comprising a plurality of the sub-arrays (100); wherein the magnetic channels (12) of each sub-array (100) are individually addressable using respective write lines (51), push lines (53), and read lines (55).

46. A method (200) of operating the 3D magnetic memory device (10) of any one of the claims 1 to 45, wherein the method (200) comprises writing (201) a magnetic state into the magnetic channel (12) by passing a write current through the SOT track (13, 16); and pushing (202) the magnetic state to the first pinning site in the magnetic channel (12), which is closest to the SOT track (13, 16), by passing a first push current through the first electrode (15) and the magnetic channel (12).

47. The method (200) according to claim 46, wherein writing (201) the magnetic state comprises selecting a first magnetic state of the magnetic bit by passing the write current along a first direction through the SOT track (13, 16), or selecting a second magnetic state of the magnetic bit by passing the write current along an opposite second direction through the SOT track (13, 16).

48. The method (200) according to claim 46 or 47, wherein the method (200) further comprises pushing (203) magnetic bits along the magnetic channel, respectively from one pinning site to the next pinning site, by passing a second push current through the first electrode (15) and the magnetic channel (12).IMEC VZWPA 2023 / 359 PCT1P61984 / WO49. The method (200) according to one of the claims 46 to 48, wherein the method (200) further comprises reading (204) a magnetic bit from the magnetic channel (12) by passing a current through the MTJ (14), and thereby determining a tunnelmagnetoresistance, wherein the magnetic bit stored in the pinning site in the magnetic channel (12) closest to the MTJ (14) is read.

50. The method (200) according to one of the claims 46 to 49, wherein the magnetic memory device (10) comprises the second electrode (21), and pushing (203) the magnetic bits along the magnetic channel (12) comprises sending the current from the second electrode (21) to the first electrode (15); or the magnetic memory device (15) does not comprise the second electrode (21) but comprises the second metallic layer (16), and pushing (203) the magnetic bits along the magnetic channel (12) comprises sending the current from the second metallic layer (16) to the first electrode (15); or the magnetic memory device (10) comprises the second electrode (21) and the first metallic layer (13) is configured as the SOT track, and pushing (203) the magnetic bits along the magnetic channel (12) comprises sending a bi-polar current from the second metallic layer (16) to the first electrode (15).

51. The method (200) according to one of the claims 46 to 50, wherein when pushing (203) the magnetic bits stored in the magnetic channel (12), the magnetic bit stored in the pinning site in the magnetic channel (12) that is closest to the first metallic layer (13) is destructed, and the method (200) further comprises re-writing the destructed magnetic bit into the magnetic channel (12) or storing the information corresponding to the destructed magnetic bit in a memory.

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