Optical module

Abstract

An optical module (200), comprising an optical transmitting component (400). The optical transmitting component (400) comprises a temperature regulating device (450), a first laser chip (441) and a second laser chip (442). The temperature regulating device (450) comprises a first substrate (451), a second substrate (452), and at least two third substrates (453). A seventh circuit array (453e) is formed on the upper surface of one third substrate (453) to carry the first laser chip (441), and an eighth circuit array is formed on the upper surface of another third substrate (453) to carry the second laser chip (442), thereby respectively arranging the first laser chip (441) and the second laser chip (442) on surfaces of different third substrates (453). The seventh circuit array (453e) comprises a first electrical connection part (4531) and a second electrical connection part (4532) to electrically connect the first laser chip (441) to an electrical connector (430). The seventh circuit array (453e) comprises a third electrical connection part (4533) and a fourth electrical connection part (4534) to electrically connect both a third electrode part (4571) and a fourth electrode part (4572) to the electrical connector (430). Since the first laser chip (441) and the second laser chip (442) are respectively located on different third substrates (453), the temperatures of the first laser chip (441) and the second laser chip (442) are regulated without mutual impact.

Description

Optical module

[0001] This application claims priority to the application filed on September 26, 2024 with the China National Intellectual Property Office and application number 202422361396.4; the application filed on September 26, 2024 with the China National Intellectual Property Office and application number 202411355110.X; the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of optical fiber communication, and in particular to an optical module. BACKGROUND

[0003] With the development of new business and application modes such as cloud computing, mobile Internet, video, etc., the progress of optical communication technology becomes increasingly important. In optical communication technology, the optical module, as one of the key devices in optical communication equipment, can realize optical-electric signal conversion; in the development process of optical communication technology, the data transmission rate of the optical module is required to be continuously improved.

[0004] SUMMARY

[0005] The optical module provided by the embodiments of the present disclosure comprises:

[0006] a circuit board;

[0007] an optical transmitting component electrically connected with the circuit board, comprising:

[0008] a tube shell, an end of which is formed with an opening, and an electrical connector is embedded in the opening, the electrical connector comprising a first pad surface and a second pad surface;

[0009] a first laser chip;

[0010] a second laser chip;

[0011] a temperature regulating device located in the tube shell, comprising:

[0012] a first substrate;

[0013] a second substrate located above the first substrate;

[0014] At least two third substrates are located above the second substrate, wherein an upper surface of one of the third substrates is formed with a seventh circuit array to carry the first laser chip; an upper surface of the other of the third substrates is formed with an eighth circuit array to carry the second laser chip; the third substrates are respectively embedded with a third electrode part and a fourth electrode part; the seventh circuit array includes a first electric connection part and a second electric connection part, one end of the first electric connection part is electrically connected with the positive electrode of the first laser chip, and the other end is electrically connected with the first pad surface; one end of the second electric connection part is electrically connected with the negative electrode of the first laser chip, and the other end is electrically connected with the first pad surface; the seventh circuit array includes a third electric connection part and a fourth electric connection part, one end of the third electric connection part is electrically connected with the third electric connection part, and the other end is electrically connected with the second pad surface, one end of the fourth electric connection part is electrically connected with the fourth electrode part, and the other end is electrically connected with the second pad surface;

[0015] The upper surface of the first substrate is formed with a first circuit array;

[0016] The lower surface of the second substrate is formed with a second circuit array, and the upper surface is formed with a third circuit array and a fourth circuit array which are independent of each other; the second circuit array is electrically connected with the first circuit array to realize the electrical connection between the second substrate and the first substrate;

[0017] The lower surface of one of the third substrates is formed with a fifth circuit array, and the fifth circuit array is electrically connected with the third circuit array to realize the electrical connection between the second substrate and one of the third substrates; the lower surface of the other of the third substrates is formed with a sixth circuit array, and the sixth circuit array is electrically connected with the fourth circuit array to realize the electrical connection between the second substrate and the other of the third substrates. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0019] Fig. 1 is a partial architecture diagram of an optical communication system according to some embodiments of the present disclosure;

[0020] Fig. 2 is a partial structure diagram of a host computer according to some embodiments of the present disclosure;

[0021] Fig. 3 is a structure diagram of an optical module according to some embodiments of the present disclosure;

[0022] FIG. 4 is an exploded view of an optical module according to some embodiments of the present disclosure;

[0023] FIG. 5 is a perspective view of an optical transmitting component according to some embodiments of the present disclosure;

[0024] FIG. 6A is a diagram of an electrical connector and a tube assembly structure according to some embodiments of the present disclosure;

[0025] FIG. 6B is a diagram of an electrical connector and a tube assembly structure according to some embodiments of the present disclosure;

[0026] FIG. 7 is a diagram of an internal structure of a tube according to some embodiments of the present disclosure;

[0027] FIG. 8 is an exploded view of an internal structure of a tube according to some embodiments of the present disclosure;

[0028] FIG. 9A is a diagram of a temperature control device according to some embodiments of the present disclosure;

[0029] FIG. 9B is a diagram of a temperature control device according to some embodiments of the present disclosure;

[0030] FIG. 9C is an exploded view of a temperature control device according to some embodiments of the present disclosure;

[0031] FIG. 10A is a diagram of a third substrate surface according to some embodiments of the present disclosure;

[0032] FIG. 10B is a diagram of a temperature control device according to some embodiments of the present disclosure;

[0033] FIG. 10C is a diagram of a third substrate according to some embodiments of the present disclosure;

[0034] FIG. 10D is a diagram of a temperature control device according to some embodiments of the present disclosure;

[0035] FIG. 10E is an exploded view of a temperature control device according to some embodiments of the present disclosure;

[0036] FIG. 10F is an exploded view of a temperature control device according to some embodiments of the present disclosure;

[0037] FIG. 10G is an exploded view of a temperature control device according to some embodiments of the present disclosure;

[0038] FIG. 10H is a diagram of a third substrate surface according to some embodiments of the present disclosure;

[0039] FIG. 11A is a cross-sectional view of a temperature control device according to some embodiments of the present disclosure;

[0040] FIG. 11B is a second cross-sectional view of a temperature adjustment device, according to some embodiments of the present disclosure;

[0041] FIG. 12A is a first exploded view between a first substrate and a second substrate, according to some embodiments of the present disclosure;

[0042] FIG. 12B is a second exploded view between a first substrate and a second substrate, according to some embodiments of the present disclosure;

[0043] FIG. 12C is a schematic view of current transmission between a first electrode portion and a second electrode portion, according to some embodiments of the present disclosure;

[0044] FIG. 13A is a schematic view of a temperature adjustment principle of a temperature adjustment device, according to some embodiments of the present disclosure;

[0045] FIG. 13B is a schematic view of a temperature adjustment principle of a temperature adjustment device, according to some embodiments of the present disclosure;

[0046] FIG. 14 is a third cross-sectional view of a temperature adjustment device, according to some embodiments of the present disclosure;

[0047] FIG. 15 is a second exploded view of a temperature adjustment device, according to some embodiments of the present disclosure;

[0048] FIG. 16 is a third exploded view of a temperature adjustment device, according to some embodiments of the present disclosure;

[0049] FIG. 17 is a schematic view of current transmission between a second substrate and a third substrate, according to some embodiments of the present disclosure;

[0050] FIG. 18A is a schematic view of a temperature adjustment principle of a temperature adjustment device, according to some embodiments of the present disclosure;

[0051] FIG. 18B is a schematic view of a temperature adjustment principle of a temperature adjustment device, according to some embodiments of the present disclosure;

[0052] FIG. 19 is a schematic view of an electrical connection structure of a light emitting component, according to some embodiments of the present disclosure;

[0053] FIG. 20 is a schematic view of an electrical connection structure of a light emitting component, according to some embodiments of the present disclosure;

[0054] FIG. 21 is a schematic view of an electrical connection structure of a light emitting component, according to some embodiments of the present disclosure;

[0055] FIG. 22 is a schematic view of an electrical connection structure of a light emitting component, according to some embodiments of the present disclosure;

[0056] FIG. 23 is a cross-sectional view of another light emitting component, according to some embodiments of the present disclosure;

[0057] FIG. 24 is a partial structural diagram of another light emitting component according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0059] Unless otherwise required by context, the term "comprise" and other forms of the term "comprise", such as "comprises" and "comprising", and other forms of the term "comprise", are used throughout the specification and claims in an open-ended way, i.e., to mean including, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any appropriate way in any one or more embodiments or examples.

[0060] Hereinafter, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0061] In describing some embodiments, it will be understood that the terms "coupled" and "connected," along with derivatives thereof, can be used to describe either a direct physical or electrical connection between two or more elements, or an indirect physical or electrical connection between two or more elements. In some embodiments, the terms "coupled" and "connected" can be used to indicate that two or more elements cooperate or interact with each other to also permit a flow of relative movement between the two elements. It will be understood that the embodiments disclosed herein are not necessarily limited to the arrangements described herein.

[0062] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0063] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0064] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional tasks or steps not specifically recited.

[0065] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the specific value, as determined by one of ordinary skill in the art considering the measurement being discussed and the error in measurement associated with the specific quantity being measured (i.e., the limitations of the measurement system).

[0066] In optical communication technology, in order to establish information transmission between information processing devices, information needs to be loaded onto light, and the transmission of information is achieved by the propagation of light. Here, the light loaded with information is an optical signal. The optical signal can reduce the loss of optical power when transmitted in the information transmission device, so as to achieve high-speed, long-distance, and low-cost information transmission. The signal that can be recognized and processed by the information processing device is an electrical signal. The information processing device usually includes an optical network unit (ONU), a gateway, a router, a switch, a mobile phone, a computer, a server, a tablet computer, a television, etc., and the information transmission device usually includes an optical fiber and an optical waveguide, etc.

[0067] The optical module can realize mutual conversion between optical signals and electrical signals between the information processing device and the information transmission device. For example, at least one of the optical signal input end or the optical signal output end of the optical module is connected with an optical fiber, and at least one of the electrical signal input end or the electrical signal output end of the optical module is connected with an optical network terminal; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the optical network terminal; a second electrical signal from the optical network terminal is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber. Since information transmission can be performed between multiple information processing devices through electrical signals, at least one of the multiple information processing devices needs to be directly connected with the optical module, without the need for all the information processing devices to be directly connected with the optical module. Here, the information processing device directly connected with the optical module is referred to as a host computer of the optical module. In addition, the optical signal input end or the optical signal output end of the optical module can be referred to as an optical port, and the electrical signal input end or the electrical signal output end of the optical module can be referred to as an electrical port.

[0068] FIG. 1 is a partial structure diagram of an optical communication system according to some embodiments. As shown in FIG. 1, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100, an optical module 200, an optical fiber 101, and a network cable 103.

[0069] One end of the optical fiber 101 extends towards the remote information processing device 1000, and the other end of the optical fiber 101 is connected with the optical module 200 through the optical port of the optical module 200. The optical signal can be totally reflected in the optical fiber 101, and the propagation of the optical signal in the totally reflected direction can almost maintain the original optical power. The optical signal is totally reflected multiple times in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance and low-power-loss information transmission.

[0070] The optical communication system can include one or more optical fibers 101, and the optical fiber 101 can be detachably connected with the optical module 200 or fixedly connected. The host computer 100 is configured to provide a data signal to the optical module 200, or receive a data signal from the optical module 200, or monitor or control the working state of the optical module 200.

[0071] The host computer 100 includes a housing substantially in the shape of a rectangular cuboid, and an optical module interface 102 disposed on the housing. The optical module interface 102 is configured to access the optical module 200, so as to establish a one-way or two-way electrical signal connection between the host computer 100 and the optical module 200.

[0072] The host computer 100 further comprises an external electrical interface configured to access an electrical signal network. For example, the external electrical interface comprises a Universal Serial Bus (USB) interface or a network cable interface 104 configured to access a network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103. One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100 to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103. For example, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103, and the host computer 100 generates a second electrical signal according to the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200, the optical module 200 converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber 101. The second optical signal is transmitted in the optical fiber 101 to the remote server 1000. For example, the first optical signal from the remote information processing device 1000 is transmitted through the optical fiber 101, the first optical signal from the optical fiber 101 is transmitted to the optical module 200, the optical module 200 converts the first optical signal into a first electrical signal, the optical module 200 transmits the first electrical signal to the host computer 100, the host computer 100 generates a fourth electrical signal according to the first electrical signal, and the fourth electrical signal is transmitted to the local information processing device 2000. It should be noted that the optical module is a tool for converting optical signals and electrical signals, and the information does not change in the conversion process of the optical signals and the electrical signals, and the encoding and decoding mode of the information can change.

[0073] In addition to the optical network terminal, the host computer 100 further comprises an optical line terminal (OLT), an optical network terminal (ONT), or a data center server, etc.

[0074] Figure 2 is a partial structure diagram of a host computer according to some embodiments. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 only shows the structure of the host computer 100 related to the optical module 200. As shown in Figure 2, the host computer 100 further comprises a PCB circuit board 105 arranged in the shell, a cage 106 arranged on the surface of the PCB circuit board 105, a heat sink 107 arranged on the cage 106, and an electrical connector arranged inside the cage 106. The electrical connector is configured to access the electrical port of the optical module 200; the heat sink 107 has a fin or other protruding structure that increases the heat dissipation area.

[0075] The optical module 200 is inserted into the cage 106 of the host computer 100, and the optical module 200 is fixed by the cage 106. The heat generated by the optical module 200 is conducted to the cage 106, and then diffused through the heat sink 107. After the optical module 200 is inserted into the cage 106, the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106, so that the optical module 200 and the host computer 100 establish a bidirectional electrical signal connection. In addition, the optical port of the optical module 200 is connected to the optical fiber 101, so that the optical module 200 and the optical fiber 101 establish a bidirectional optical signal connection.

[0076] FIG. 3 is a structural diagram of an optical module according to some embodiments, and FIG. 4 is an exploded view of an optical module according to some embodiments. As shown in FIGS. 3 and 4, the optical module 200 includes a shell, a circuit board 300 arranged in the shell, an optical transmitting component 400, and an optical receiving component 500. However, the present disclosure is not limited thereto, and in some embodiments, the optical module 200 includes one of the optical transmitting component 400 and the optical receiving component 500.

[0077] The shell includes an upper shell 201 and a lower shell 202. The upper shell 201 is covered on the lower shell 202 to form the above-mentioned shell having two openings 204 and 205. The outer contour of the shell generally presents a square body.

[0078] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 arranged perpendicularly to the bottom plate 2021 on both sides of the bottom plate 2021. The upper shell 201 includes a cover plate 2011, and the cover plate 2011 is covered on the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0079] In some embodiments, the lower shell 202 includes a bottom plate 2021 and two lower side plates 2022 arranged perpendicularly to the bottom plate 2021 on both sides of the bottom plate 2021. The upper shell 201 includes a cover plate 2011 and two upper side plates arranged perpendicularly to the cover plate 2011 on both sides of the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to achieve that the upper shell 201 is covered on the lower shell 202.

[0080] The direction of the line connecting the two openings 204 and 205 can be consistent with the length direction of the optical module 200, or can be inconsistent with the length direction of the optical module 200. For example, the opening 204 is located at the end of the optical module 200 (the right end of FIG. 3), and the opening 205 is also located at the end of the optical module 200 (the left end of FIG. 3). Alternatively, the opening 204 is located at the end of the optical module 200, and the opening 205 is located at the side of the optical module 200. The opening 204 is an electrical port, and the gold fingers 301 of the circuit board 300 extend from the electrical port 204 and are inserted into the electrical connector of the host computer 100. The opening 205 is an optical port configured to access the external optical fiber 101, so that the optical fiber 101 connects the optical transmitting component 400 and the optical receiving component 500 in the optical module 200.

[0081] The assembly of the upper shell 201 and the lower shell 202 facilitates the installation of the circuit board 300, the optical transmitting component 400, the optical receiving component 500, etc. in the shells, and the shells 201 and 202 can encapsulate and protect the above-mentioned devices. In addition, when assembling the circuit board 300, the optical transmitting component 400, and the optical receiving component 500, etc., the positioning components, heat dissipation components, and electromagnetic shielding components of these devices can be easily deployed, which facilitates automated production.

[0082] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0083] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside the shell thereof. The unlocking component 600 is configured to achieve fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0084] For example, the unlocking component 600 is located outside the two lower side plates 2022 of the lower shell 202 and includes a clamping component matched with the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the clamping component of the unlocking component 600 fixes the optical module 200 in the cage 106. When the unlocking component 600 is pulled, the clamping component of the unlocking component 600 moves, thereby changing the connection relationship between the clamping component and the host computer, to release the fixation between the optical module 200 and the host computer, so that the optical module 200 can be pulled out of the cage 106.

[0085] The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to circuit design through the circuit traces to realize power supply, electrical signal transmission, and grounding, etc. The electronic components may, for example, include capacitors, resistors, transistors, and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). The chips may, for example, include Microcontroller Units (MCUs), laser drive chips, Transimpedance Amplifiers (TIAs), limiting amplifiers, Clock and Data Recovery (CDR) chips, power management chips, and Digital Signal Processing (DSP) chips.

[0086] The circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize a bearing function, such as stably bearing the above-mentioned electronic components and chips. The rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.

[0087] The circuit board 300 also includes a gold finger 301 formed on the surface of the end thereof. The gold finger 301 is composed of a plurality of pins independent of each other. The circuit board 300 is inserted into the cage 106, and the gold finger 301 is in conduction with the electrical connector in the cage 106. The gold finger 301 can be provided only on the surface (e.g., the upper surface shown in FIG. 4) of one side of the circuit board 300, or can be provided on the surfaces of both upper and lower sides of the circuit board 300 to provide a larger number of pins to adapt to occasions requiring a large number of pins. The gold finger 301 is configured to establish electrical connection with the host computer to realize power supply, grounding, Inter-Integrated Circuit (I2C) signal transmission, data signal transmission, etc. Of course, flexible circuit boards are also used in some optical modules. The flexible circuit board is generally used in cooperation with the rigid circuit board to supplement the rigid circuit board.

[0088] At least one of the optical transmitting component 400 or the optical receiving component 500 is located on the side of the circuit board 300 away from the gold finger 301.

[0089] In some embodiments, the optical transmitting component 400 and the optical receiving component 500 are physically separated from the circuit board 300, and then are electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connections, respectively.

[0090] In some embodiments, at least one of the light emitting component or the light receiving component can be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component can be disposed on a surface of the circuit board 300 or a side of the circuit board 300.

[0091] FIG. 5 is a diagram of a light emitting component according to some embodiments of the present disclosure. As shown in FIG. 5, in some embodiments, the light emitting component 400 can include a tube shell 410. The tube shell 410 has a space to accommodate optical devices.

[0092] In some embodiments, the light emitting component 400 can include a cover plate 420. The cover plate 420 is connected to the tube shell 410 to achieve airtight packaging of the devices in the tube shell 410.

[0093] In some embodiments, the light emitting component 400 can include an electrical connector 430. The electrical connector 430 is located at an end of the tube shell 410, and the electrical connector 430 can achieve electrical connection between the devices in the tube shell 410 and the circuit board 300.

[0094] FIG. 6A is a diagram of an electrical connector and a tube shell assembly structure according to some embodiments of the present disclosure. As shown in FIG. 6A, in some embodiments, an end of the tube shell 410 has an opening 411, and the electrical connector 430 can be embedded in the opening 411.

[0095] In some embodiments, one end of the electrical connector 430 is located inside the tube shell 410 to be electrically connected to the optical devices inside the tube shell 410, and the other end of the electrical connector 430 is located outside the tube shell 410 to be electrically connected to the circuit board 300, so that the electrical connector 430 can achieve electrical connection between the optical devices in the tube shell 410 and the circuit board 300.

[0096] In some embodiments, the electrical connector 430 has a large wire bonding requirement, and the end of the electrical connector 430 located inside the tube shell 410 includes a first pad surface 431 and a second pad surface 432 to provide more pads to meet the wire bonding requirement. For example, the first pad surface 431 and the second pad surface 432 can be arranged in a stepped manner to fully utilize the longitudinal space.

[0097] In some embodiments, the first pad surface 431 is used for electrical connection of high-frequency signals, and the second pad surface 432 is used for electrical connection of low-frequency signals.

[0098] In some embodiments, the upper and lower surfaces of the electrical connector 430 located outside the tube shell 410 can form wire patterns respectively to form pad surfaces. As shown in FIG. 5, the upper and lower surfaces are respectively electrically connected to the first flexible circuit board 300a and the second flexible circuit board 300b. The first flexible circuit board 300a and the second flexible circuit board 300b are respectively electrically connected to the circuit board 300.

[0099] In some embodiments, the first pad surface 431 is located below the second pad surface 432, and the first pad surface 431 is electrically connected to the upper surface of the electrical connector 430 located outside the tube shell 410, thereby being electrically connected to the second flexible circuit board 300b. The second pad surface 432 is electrically connected to the lower surface of the electrical connector 430 located outside the tube shell 410, thereby being electrically connected to the first flexible circuit board 300a.

[0100] FIG. 6B is a diagram of an electrical connector and tube shell assembly structure according to some embodiments of the present disclosure. As shown in FIG. 6B, in some embodiments, the electrical connector 430 located at one end inside the tube shell 410 includes a first pad surface 431 and a second pad surface 432 to provide more pads to meet the wire bonding requirement.

[0101] In some embodiments, the electrical connector 430 located at one end outside the tube shell 410 forms a third pad surface 433 on one of the surfaces. The third pad surface 433 can be located on the upper surface or the lower surface. For example, a wire pattern is formed on the upper surface to form the third pad surface 433. The pads in the electrical connector 430 located at one end outside the tube shell 410 for the electrical connection of the first pad surface 431 and the second pad surface 432 are distributed on the third pad surface 433.

[0102] In some embodiments, the first pad surface 431 is used for the electrical connection of high-frequency signals, and the second pad surface 432 is used for the electrical connection of low-frequency signals. The third pad surface 433 is flush with the first pad surface 431 to ensure electrical connection therebetween, thereby ensuring the transmission of high-frequency signals.

[0103] In some embodiments, the second pad surface 432 is higher than the third pad surface 433. In the electrical connector 430, a via portion 434 is formed between the second pad surface 432 and the third pad surface 433. For example, the via portion 434 is electrically connected to the second pad surface 432 at the upper end and to the third pad surface 433 at the lower end, thereby achieving electrical connection between the second pad surface 432 and the third pad surface 433.

[0104] In some embodiments, the electrical connector 430 is a multi-layer structure, and the via portion 434 is arranged between the layer where the second pad surface 432 is located and the layer where the third pad surface 433 is located, and then laminated to form the electrical connector 430.

[0105] FIG. 7 is a diagram of an internal structure of a tube shell according to some embodiments of the present disclosure, and FIG. 8 is a diagram of an internal structure of a tube shell according to some embodiments of the present disclosure. As shown in FIGS. 7 and 8, in some embodiments, the end of the tube shell 410 is formed with an opening 411, and the electrical connector 430 is embedded in the opening 411.

[0106] In some embodiments, the light emitting component 400 can include a laser chip array 440. The laser chip array 440 is located inside the tube 410. Exemplarily, the laser chip array 440 includes at least a first laser chip 441 and a second laser chip 442. Different laser chips emit light signals of different wavelengths respectively.

[0107] In some embodiments, the wavelength emitted by a laser chip is affected by temperature change, and thus the wavelength emitted by a laser chip can be ensured to reach a target wavelength by adjusting the temperature of the laser chip. In some structures of optical modules, the precision requirement for the wavelength emitted by a laser chip is high, for example, when dense wavelength division multiplexing (DWDM) wavelengths are used to realize multi-channel parallel transmission, the wavelength interval between adjacent optical channels is very narrow, and thus the precision requirement for the wavelength is high.

[0108] In some embodiments, the light emitting component 400 can include a temperature adjusting device 450. The temperature adjusting device 450 can be located inside the tube 410. The laser chips in the laser chip array 440 are located on the surface of the temperature adjusting device 450. By changing the direction and size of the driving current applied to the temperature adjusting device 450, the temperature adjusting device 450 can control the laser chips carried thereby to be cooled or heated, so as to adjust the temperature of the laser chips.

[0109] In some embodiments, the temperature adjusting device 450 can adjust the laser chips in the laser chip array 440 to a common target temperature range, and then independently adjust each laser chip. When the temperature of a current laser chip is adjusted, the temperature of other laser chips will not be affected, so as to adjust each laser chip to a target temperature, thereby realizing target wavelength tuning.

[0110] In some embodiments, the light emitting component 400 can include an optical multiplexing assembly 460. The optical multiplexing assembly 460 can be located inside the tube 410. The optical multiplexing assembly 460 performs wavelength combining processing on the light signals of different wavelengths emitted by the first laser chip 441 and the second laser chip 442, combines the light signals into one beam, and outputs the beam along the tube 410.

[0111] FIG. 9A is a structural diagram of a temperature adjusting device according to some embodiments of the present disclosure, FIG. 9B is a partially exploded view of a temperature adjusting device according to some embodiments of the present disclosure, and FIG. 9C is an exploded view of a temperature adjusting device according to some embodiments of the present disclosure. As shown in FIGS. 9A-9C, in some embodiments, the temperature adjusting device 450 is used to adjust the temperature of a laser chip.

[0112] In some embodiments, the temperature adjusting device 450 can include a first substrate 451. The first substrate 451 is located at the bottom end of the temperature adjusting device 450.

[0113] In some embodiments, the temperature control device 450 can include a second substrate 452. The second substrate 452 is located above the first substrate 451, and the two are oppositely arranged.

[0114] In some embodiments, the temperature control device 450 can include a third substrate 453. The third substrate 453 is located above the second substrate 452, and the two are oppositely arranged. The third substrate 453 carries the first laser chip 441 and / or the second laser chip 442 on its surface.

[0115] In some embodiments, the third substrate 453 can carry at least one laser chip on its surface. As shown in FIG. 9A, the third substrate 453 carries one laser chip on its surface. In some embodiments, the third substrate 453 can also carry two laser chips on its surface.

[0116] In some embodiments, taking the example of four-way light emission, when the third substrate 453 carries one laser chip on its surface, four third substrates 453 are arranged above the second substrate 452 respectively to separately carry one of the laser chips. When the third substrate 453 carries two laser chips on its surface, two third substrates 453 are arranged above the second substrate 452 respectively.

[0117] In some embodiments, when the first laser chip 441 is arranged on the surface of one of the third substrates 453 and the second laser chip 442 is arranged on the surface of another third substrate 453, the first laser chip 441 and the second laser chip 442 can be first adjusted to a common target temperature interval through heat transfer between the first substrate 451 and the second substrate 452, and then the first laser chip 441 is independently temperature-adjusted through heat transfer between the second substrate 452 and the third substrate 453 on which the first laser chip 441 is arranged, so as to adjust the first laser chip 441 to a target temperature. The second laser chip 442 is independently temperature-adjusted through heat exchange between the second substrate 452 and the third substrate 453 on which the second laser chip 442 is arranged, so as to adjust the second laser chip 442 to a target temperature. The temperature change of the second laser chip 442 will not be affected when the first laser chip 441 is independently adjusted, and the temperature change of the first laser chip 441 will not be affected when the second laser chip 442 is independently adjusted.

[0118] In some embodiments, since the third substrate 453 on which the first laser chip 441 is arranged and the third substrate 453 on which the second laser chip 442 is arranged are independent circuits, the first laser chip 441 and the second laser chip 442 can be simultaneously independently temperature-adjusted, and the temperature adjustment requirements of the first laser chip 441 and the second laser chip 442 can be simultaneously met.

[0119] In some embodiments, the surface of the third substrate 453 is formed with a circuit pattern of an array of circuits for electrically connecting the surface-mounted first laser chip 441 and / or the second laser chip 442, and the first laser chip 441 and / or the second laser chip 442 can be directly disposed on the surface of the third substrate 453. For example, the surface of the third substrate 453 only carries the first laser chip 441, or the surface of the third substrate 453 only carries the second laser chip 442, or the surface of the third substrate 453 carries both the first laser chip 441 and the second laser chip 442.

[0120] In some embodiments, the temperature regulating device 450 can include N-type semiconductor portions 454 and P-type semiconductor portions 455. One N-type semiconductor portion 454 and one P-type semiconductor portion 455 are connected in series to form a thermoelectric couple. A plurality of N-type semiconductor portions 454 and P-type semiconductor portions 455 are arranged alternately to form a plurality of thermoelectric couples.

[0121] In some embodiments, the N-type semiconductor portion 454 is obtained by doping a pentavalent impurity element into an intrinsic semiconductor, and the P-type semiconductor portion 455 is obtained by doping a trivalent impurity element into the intrinsic semiconductor. The main carriers in the N-type semiconductor portion 454 are electrons, and the main carriers in the P-type semiconductor portion 455 are holes. The directions of the carrier movement in the N-type semiconductor portion 454 and the P-type semiconductor portion 455 are the same. The directions of the carrier movement in the N-type semiconductor portions 454 are the same, and the directions of the carrier movement in the P-type semiconductor portions 455 are the same.

[0122] In some embodiments, a plurality of N-type semiconductor portions 454 and P-type semiconductor portions 455 are arranged alternately between the first substrate 451 and the second substrate 452, i.e., a plurality of thermoelectric couples are arranged between the first substrate 451 and the second substrate 452, and the plurality of thermoelectric couples are connected in series.

[0123] In some embodiments, the N-type semiconductor portions 454 and the P-type semiconductor portions 455 are arranged alternately to form a plurality of thermoelectric couples. The N-type semiconductor portion 454 of each thermoelectric couple is connected to the P-type semiconductor portion 455 of the next thermoelectric couple to form a continuous electrical connection and achieve series connection.

[0124] In some embodiments, a plurality of N-type semiconductor portions 454 and P-type semiconductor portions 455 are arranged alternately between the second substrate 452 and the third substrate 453, i.e., a plurality of thermoelectric couples are arranged between the second substrate 452 and the third substrate 453, and the plurality of thermoelectric couples are connected in series.

[0125] In some embodiments, the temperature control device 450 can include a first electrode portion 4561 and a second electrode portion 4562. The first electrode portion 4561 is electrically connected to the second electrode portion 4562 through a plurality of thermocouple pairs serially connected between the first substrate 451 and the second substrate 452. The current flowing into the first electrode portion 4561 is sequentially shuttled up and down, passing through each of the serially connected thermocouple pairs to reach the second electrode portion 4562.

[0126] In some embodiments, the first electrode portion 4561 is electrically connected to the N-type semiconductor portion 454, and the second electrode portion 4562 is electrically connected to the P-type semiconductor portion 455.

[0127] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 are respectively electrically connected to a current source on the surface of the circuit board 300, so as to supply power to the thermocouple pairs between the first substrate 451 and the second substrate 452. By adjusting the direction and size of the supplied current, the direction and size of heat transfer between the first substrate 451 and the second substrate 452 can be changed, so as to control the temperature of the second substrate 452.

[0128] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 can be located on the surface of the first substrate 451. For example, the first substrate 451 is longer than the second substrate 452, so that the first electrode portion 4561 and the second electrode portion 4562 are located at the end of the first substrate 451.

[0129] In some embodiments, the temperature control device 450 can include a third electrode portion 4571 and a fourth electrode portion 4572. The third electrode portion 4571 is electrically connected to the fourth electrode portion 4572 through a plurality of thermocouple pairs serially connected between the second substrate 452 and the third substrate 453. The current flowing into the third electrode portion 4571 is sequentially shuttled up and down, passing through each of the serially connected thermocouple pairs to reach the fourth electrode portion 4572.

[0130] In some embodiments, the third electrode portion 4571 and the fourth electrode portion 4572 are respectively located in the third substrate 453. The third electrode portion 4571 and the fourth electrode portion 4572 are formed by punching holes in the third substrate 453, so as to reduce the occupied space and reasonably deploy the third electrode portion 4571 and the fourth electrode portion 4572. Of course, the third electrode portion 4571 and the fourth electrode portion 4572 can also be directly disposed on the surface of the third substrate 453.

[0131] In some embodiments, the third electrode portion 4571 is electrically connected to the N-type semiconductor portion 454, and the fourth electrode portion 4572 is electrically connected to the P-type semiconductor portion 455.

[0132] In some embodiments, the third electrode portion 4571 and the fourth electrode portion 4572 are respectively electrically connected to a current source on the surface of the circuit board 300, so as to supply power to the thermocouple pair between the second substrate 452 and the third substrate 453. By adjusting the direction and size of the supplied current, the direction of heat transfer between the second substrate 452 and the third substrate 453 can be changed, so as to control the temperature of the third substrate 453.

[0133] In some embodiments, the direction of heat transfer between the first substrate 451 and the second substrate 452 can be controlled by changing the direction of carrier movement in the N-type semiconductor portion 454 and the P-type semiconductor portion 455 between the first substrate 451 and the second substrate 452. Similarly, the direction of heat transfer between the second substrate 452 and the third substrate 453 can be controlled by changing the direction of carrier movement in the N-type semiconductor portion 454 and the P-type semiconductor portion 455 between the second substrate 452 and the third substrate 453.

[0134] In some embodiments, the third electrode portion 4571 and the fourth electrode portion 4572 can be respectively located in the third substrate 453. For example, through holes are respectively formed in the third substrate 453, and the through holes are filled with metal medium to form the third electrode portion 4571 and the fourth electrode portion 4572. Of course, the third electrode portion 4571 and the fourth electrode portion 4572 can also be directly disposed on the surface of the third substrate 453.

[0135] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 can be respectively electrically connected to the second pad surface 432 as an anode and a cathode. The second pad surface 432 is electrically connected to the third pad surface 433, and the third pad surface 433 is electrically connected to a driving chip on the circuit board 300 which is electrically connected to the temperature control device 450, so that the first electrode portion 4561 and the second electrode portion 4562 are respectively electrically connected to the driving chip. An external power supply supplies power to the circuit board 300 through the gold finger 301, and the circuit board 300 supplies power to the driving chip, so that the driving chip supplies power to the first electrode portion 4561 and the second electrode portion 4562 respectively.

[0136] In some embodiments, the third electrode portion 4571 and the fourth electrode portion 4572 can be respectively electrically connected to the second pad surface 432 as an anode and a cathode. The power supply connection mode of the third electrode portion 4571 and the fourth electrode portion 4572 can be the same as the power supply connection mode of the first electrode portion 4561 and the second electrode portion 4562 described above.

[0137] In some embodiments, by changing the direction and size of the current source electrically connected to the first electrode portion 4561 and the second electrode portion 4562, the temperature of the second substrate 452 can be controlled, so that the temperature of the second substrate 452 is refrigerated or heated by the laser chip, thereby adjusting the reference temperature of the laser chip on the surface of the third substrate 453.

[0138] In some embodiments, the second substrate 452 is provided with a second temperature-sensitive part 458 to monitor the temperature of the second substrate 452. The second temperature-sensitive part 458 is sensitive to temperature, and changes in ambient temperature will cause its resistance to change. The MCU collects the resistance of the second temperature-sensitive part 458, and converts the temperature characteristics of the resistance changing with temperature into an electrical signal. The MCU controls the driving chip electrically connected to the temperature control device 450 according to the electrical signal, thereby controlling the direction and size of the current provided by the driving chip to the first electrode part 4561 and the second electrode part 4562, and further controlling the temperature of the second substrate 452, so that the second substrate 452 performs reference temperature adjustment on the first laser chip 441 to adjust the temperature of the first laser chip 441 to the target temperature range.

[0139] In some embodiments, the second temperature-sensitive part 458 can be a thermistor.

[0140] FIG. 10A is a schematic diagram of a third substrate surface according to some embodiments of the present disclosure. As shown in FIG. 10A, in some embodiments, the temperature control device 450 includes a third substrate 453a. The surface of the third substrate 453a is formed with a circuit pattern to carry laser chips.

[0141] In some embodiments, the array of laser chips includes a first laser chip 441 and a second laser chip 442. The first laser chip 441 is located on the surface of one of the third substrates 453a, and the second laser chip 442 is located on the surface of another third substrate 453a.

[0142] In some embodiments, the upper surface of one of the third substrates 453a is formed with a seventh circuit array 453e to carry the first laser chip 441. The upper surface of another third substrate 453a is formed with an eighth circuit array to carry the second laser chip 442. Exemplarily, the structures of the seventh circuit array 453e and the eighth circuit array can be the same or different. Hereinafter, an example is exemplarily described with the structures of the seventh circuit array 453e and the eighth circuit array being the same.

[0143] In some embodiments, the first laser chip 441 is located on the surface of the seventh circuit array 453e, and the second laser chip 442 is located on the surface of the eighth circuit array.

[0144] In some embodiments, the seventh circuit array 453e includes a first electrical connection part 4531 and a second electrical connection part 4532. The first electrical connection part 4531 and the second electrical connection part 4532 are respectively wire-bonded to the electrical connector 430.

[0145] In some embodiments, the first electrical connection part 4531 is for signal connection of the first laser chip 441, and the second electrical connection part 4532 is for ground connection of the first laser chip 441.

[0146] In some embodiments, one end of the first electrical connection part 4531 is electrically connected to the positive electrode of the first laser chip 441, and the other end is electrically connected to the first pad surface 431; one end of the second electrical connection part 4532 is electrically connected to the negative electrode of the first laser chip 441, and the other end is electrically connected to the first pad surface 431.

[0147] In some embodiments, the third substrate 453a is embedded with a third electrode part 4571 and a fourth electrode part 4572, respectively. The third electrode part 4571 is electrically connected to the N-type semiconductor part 454 downward, and the fourth electrode part 4572 is electrically connected to the P-type semiconductor part 455 downward.

[0148] In some embodiments, the seventh circuit array 453e includes a third electrical connection part 4533 and a fourth electrical connection part 4534. The third electrical connection part 4533 and the fourth electrical connection part 4534 are respectively wire-connected to the electrical connector 430. The third electrical connection part 4533 is for wire-connection between the third electrode part 4571 and the electrical connector 430, and the fourth electrical connection part 4534 is for wire-connection between the fourth electrode part 4572 and the electrical connector 430.

[0149] In some embodiments, one end of the third electrical connection part 4533 is electrically connected to the third electrode part 4571, and the other end is electrically connected to the second pad surface 432; one end of the fourth electrical connection part 4534 is electrically connected to the fourth electrode part 4572, and the other end is electrically connected to the second pad surface 432.

[0150] In some embodiments, the surface of the third substrate 453a is formed with a third thermosensitive part 4535 for monitoring the temperature of the first laser chip 441. Exemplarily, the third thermosensitive part 4535 is a thermistor wire.

[0151] In some embodiments, the third thermosensitive part 4535 is sensitive to temperature, and changes in the ambient temperature will cause changes in its resistance. The MCU collects the resistance of the third thermosensitive part 4535 and converts the temperature characteristics of the resistance with temperature into an electrical signal. The MCU controls the driving chip electrically connected to the temperature control device 450 according to the electrical signal, so as to control the direction and size of the current provided by the driving chip to the third electrode part 4571 and the fourth electrode part 4572, and further control the temperature of the third substrate 453a, so as to further adjust the temperature of the laser chip on the surface of the third substrate 453a, and ensure the wavelength accuracy of the laser chip output.

[0152] In some embodiments, the third thermosensitive part 4535 can be a thermistor.

[0153] In some embodiments, the seventh circuit array 453e includes a fifth electrical connection part 4536 and a sixth electrical connection part 4537.

[0154] In some embodiments, one end of the fifth electrical connection 4536 is electrically connected to the third temperature-sensitive portion 4535, and the other end is electrically connected to the electrical connector 430. One end of the sixth electrical connection 4537 is electrically connected to the third temperature-sensitive portion 4535, and the other end is electrically connected to the electrical connector 430.

[0155] In some embodiments, the fifth electrical connection 4536 is used to electrically connect the positive electrode of the third temperature-sensitive portion 4535 to the electrical connector 430, and the sixth electrical connection 4537 is used to electrically connect the negative electrode of the third temperature-sensitive portion 4535 to the electrical connector 430.

[0156] FIG. 10B is a partial enlarged view of a temperature adjustment device according to some embodiments of the present disclosure, and FIG. 10C is a partial enlarged view of a third substrate according to some embodiments of the present disclosure. As shown in FIG. 10B and FIG. 10C, in some embodiments, the third substrate 453a is embedded with a third electrode portion 4571 and a fourth electrode portion 4572, respectively.

[0157] In some embodiments, the third electrode portion 4571 is electrically connected to the N-type semiconductor portion 454, and the fourth electrode portion 4572 is electrically connected to the P-type semiconductor portion 455.

[0158] In some embodiments, the N-type semiconductor portion 454 electrically connected to the third electrode portion 4571 and the P-type semiconductor portion 455 electrically connected to the fourth electrode portion 4572 are located on different pads of the second substrate 452 and on different pads of the third substrate 453a, respectively.

[0159] In some embodiments, one end of the third electrode portion 4571 located on the top surface of the third substrate 453a is electrically connected to the electrical connector 430 through the third electrical connection 4533, and the other end of the third electrode portion 4571 located on the bottom surface of the third substrate 453a is electrically connected to the N-type semiconductor portion 454.

[0160] In some embodiments, one end of the fourth electrode portion 4572 located on the top surface of the third substrate 453a is electrically connected to the electrical connector 430 through the fourth electrical connection 4534, and the other end of the fourth electrode portion 4572 located on the bottom surface of the third substrate 453a is electrically connected to the P-type semiconductor portion 455.

[0161] In some embodiments, the current source of the surface of the circuit board 300 is electrically connected with the third electrode part 4571 and the fourth electrode part 4572 through the electrical connector 430 respectively. Exemplarily, the third electrode part 4571 is the positive electrode, and the fourth electrode part 4572 is the negative electrode. When the current source is a positive current source, the current is transmitted to the third electrode part 4571 through the electrical connector 430, and then transmitted to the N-type semiconductor part 454 electrically connected with the third electrode part 4571, and thus transmitted along the P-type semiconductor part 455 and the N-type semiconductor part 454 connected in series in turn, until reaching the P-type semiconductor part 455 electrically connected with the fourth electrode part 4572, and then transmitted to the fourth electrode part 4572.

[0162] The third substrate 453a has a first via part 4538 and a second via part 4539. The first via part 4538 and the second via part 4539 respectively penetrate the third substrate 453a. Exemplarily, the hole depth of the first via part 4538 and the second via part 4539 is the thickness of the third substrate 453a respectively.

[0163] In some embodiments, the first via part 4538 and the second via part 4539 are respectively filled with metal medium to form the third electrode part 4571 and the fourth electrode part 4572 respectively.

[0164] In some embodiments, the first laser chip 441 and the second laser chip 442 are respectively adjusted to the common target temperature interval by heat transfer between the first substrate 451 and the second substrate 452, and can also be adjusted to different temperature intervals, and then the first laser chip 441 is independently temperature-adjusted by heat transfer between the second substrate 452 and the third substrate 453 where the first laser chip 441 is located, taking the target temperature interval as the reference temperature, so as to adjust the first laser chip 441 to the target temperature. The second laser chip 442 is independently temperature-adjusted by heat exchange between the second substrate 452 and the third substrate 453 where the second laser chip 442 is located, so as to adjust the second laser chip 442 to the target temperature.

[0165] In some embodiments, the number of N-type semiconductor portions 454 distributed between the first substrate 451 and the second substrate 452 is greater than the number of N-type semiconductor portions 454 distributed between the second substrate 452 and one of the third substrates 453a, the number of P-type semiconductor portions 455 distributed between the first substrate 451 and the second substrate 452 is greater than the number of P-type semiconductor portions 455 distributed between the second substrate 452 and one of the third substrates 453a, and the thermoelectric effect between the first substrate 451 and the second substrate 452 is stronger than the thermoelectric effect between the second substrate 452 and one of the third substrates 453a. Therefore, the heat transfer between the first substrate 451 and the second substrate 452 can quickly adjust the first laser chip 441 and the second laser chip 442 to the common target temperature range, thereby improving the speed.

[0166] In some embodiments, the size of the N-type semiconductor portions 454 distributed between the first substrate 451 and the second substrate 452 is greater than the size of the N-type semiconductor portions 454 distributed between the second substrate 452 and one of the third substrates 453a, the size of the P-type semiconductor portions 455 distributed between the first substrate 451 and the second substrate 452 is greater than the size of the P-type semiconductor portions 455 distributed between the second substrate 452 and one of the third substrates 453a, and the thermoelectric effect between the first substrate 451 and the second substrate 452 is stronger than the thermoelectric effect between the second substrate 452 and one of the third substrates 453a. Therefore, the heat transfer between the first substrate 451 and the second substrate 452 can quickly adjust the first laser chip 441 and the second laser chip 442 to the common target temperature range, thereby improving the speed.

[0167] FIG. 10D is a schematic diagram of another temperature adjustment device structure according to some embodiments of the present disclosure, and FIG. 10E is a schematic diagram of another temperature adjustment device exploded view I according to some embodiments of the present disclosure. As shown in FIGS. 10D and 10E, in some embodiments, the temperature adjustment device 450 includes a third substrate 453b.

[0168] In some embodiments, the surface of the third substrate 453b is formed with a circuit pattern to carry laser chips.

[0169] In some embodiments, the surface of the third substrate 453b can carry two laser chips. Taking a four-way emission as an example, the laser chip array 440 includes a first laser chip 441, a second laser chip 442, a third laser chip 443, and a fourth laser chip 444. Among them, the first laser chip 441 and the second laser chip 442 are located on the surface of one of the third substrates 453b, and the third laser chip 443 and the fourth laser chip 444 are located on the surface of another third substrate 453b.

[0170] In some embodiments, the temperature adjustment device 450 includes the third substrate 453b, the first substrate 451 and the second substrate 452 are electrically connected in the same way as when the temperature adjustment device 450 includes the third substrate 453a. The second substrate 452 and the third substrate 453a are electrically connected in the same way as the second substrate 452 and the third substrate 453b.

[0171] In some embodiments, because the length of the third substrate 453b is greater than the length of the third substrate 453a, the number of N-type semiconductor portions 454 and P-type semiconductor portions 455 distributed between the second substrate 452 and the third substrate 453b is greater than the number of N-type semiconductor portions 454 and P-type semiconductor portions 455 distributed between the second substrate 452 and the third substrate 453a.

[0172] In some embodiments, in order to control the refrigeration or heating of the third substrate 453b, one side of the third substrate 453b is penetrated by a third electrode portion 4571b and a fourth electrode portion 4572b. The third electrode portion 4571b is electrically connected to the fourth electrode portion 4572b through the N-type semiconductor portions 454 and P-type semiconductor portions 455 alternately arranged between the third substrate 453b and the second substrate 452. By changing the direction and size of the current transmitted to the N-type semiconductor portions 454 and P-type semiconductor portions 455 alternately arranged between the second substrate 452 and the third substrate 453b, the refrigeration or heating effect of the third substrate 453b can be controlled.

[0173] In some embodiments, the third electrode portion 4571b and the fourth electrode portion 4572b in the third substrate 453b can be arranged and electrically connected in the same way as the third electrode portion 4571 and the fourth electrode portion 4572 in the third substrate 453a.

[0174] FIG. 10F is a second exploded schematic view of another temperature adjustment device according to some embodiments of the present disclosure, FIG. 10G is a third exploded schematic view of another temperature adjustment device according to some embodiments of the present disclosure, and FIG. 10H is a schematic view of a surface structure of another third substrate according to some embodiments of the present disclosure. As shown in FIGS. 10F-10H, in some embodiments, the third substrate 453b carries a first laser chip 441 and a second laser chip 442 on its surface.

[0175] In some embodiments, the upper surface of the second substrate 452 is formed with a ninth circuit array 452d. In some embodiments, the lower surface of the third substrate 453b is formed with a tenth circuit array 453f. The ninth circuit array 452d and the tenth circuit array 453f are distributed with N-type semiconductor portions 454 and P-type semiconductor portions 455 alternately arranged to support the third substrate 453b.

[0176] In some embodiments, the ninth circuit array 452d and the tenth circuit array 453f are staggered with each pad portion of the ninth circuit array 452d and the tenth circuit array 453f being electrically connected to each other, thereby achieving series connection of the alternating N-type semiconductor portion 454 and P-type semiconductor portion 455.

[0177] In some embodiments, an upper surface of the third substrate 453b is formed with an eleventh circuit array 453g.

[0178] In some embodiments, the first laser chip 441 and the second laser chip 442 are respectively arranged on a surface of the eleventh circuit array 453g.

[0179] In some embodiments, the eleventh circuit array 453g can include a first temperature control portion 4531b. The first temperature control portion 4531b is located on one side of the first laser chip 441 to separately heat or cool the first laser chip 441.

[0180] In some embodiments, the eleventh circuit array 453g can include a second temperature control portion 4532b. The second temperature control portion 4532b is located on one side of the second laser chip 442 to separately heat or cool the second laser chip 442.

[0181] In some embodiments, the eleventh circuit array 453g can include a first temperature sensing portion 4533b. The first temperature sensing portion 4533b is configured to monitor the temperature of the first laser chip 441 and the second laser chip 442.

[0182] In some embodiments, in order to monitor the temperature of the first laser chip 441 and the second laser chip 442, the first temperature sensing portion 4533b is located between the first laser chip 441 and the second laser chip 442. For example, the first temperature sensing portion 4533b is located between the first temperature control portion 4531b and the second temperature control portion 4532b.

[0183] In some embodiments, the first temperature sensing portion 4533b is located in the middle of the third substrate 453b, with the first laser chip 441 on one side of the first temperature sensing portion 4533b and the second temperature control portion 4532b on the other side of the first temperature sensing portion 4533b.

[0184] In some embodiments, when temperature adjustment is performed, the first laser chip 441 and the second laser chip 442 are respectively adjusted to be within a first target temperature range by the second substrate 452 through controlling heating or cooling of the first substrate 451 and the second substrate 452; then the first laser chip 441 and the second laser chip 442 are respectively adjusted to be within a second target temperature range by controlling heating or cooling of the third substrate 453 with the first target temperature range as a reference temperature. Then the first laser chip 441 is independently temperature-adjusted by the first temperature control part 4531b to adjust the first laser chip 441 to a target temperature, or the second laser chip 442 is independently temperature-adjusted by the second temperature control part 4532b to adjust the second laser chip 442 to a target temperature, with the second target temperature range as a reference temperature. Since the second laser chip 442 is far away from the first temperature control part 4531b, the temperature of the second laser chip 442 will not be affected when the first laser chip 441 is independently temperature-adjusted by the first temperature control part 4531b. Similarly, the temperature of the first laser chip 441 will not be affected when the second laser chip 442 is temperature-adjusted. Therefore, when the wavelength is tuned, the first laser chip 441 or the second laser chip 442 can be independently temperature-adjusted, so as to avoid affecting the temperature of the other laser chip.

[0185] In some embodiments, since the first temperature control part 4531b and the second temperature control part 4532b are independent circuits, the first laser chip 441 and the second laser chip 442 can be independently temperature-adjusted at the same time.

[0186] In some embodiments, the first temperature control part 4531b can be a resistance wire, and two ends of the first temperature control part 4531b respectively form two pad parts to realize positive and negative electrode connection of the first temperature control part 4531b. For example, one end is electrically connected to the surface of the first pad face 431, and the other end is electrically connected to the surface of the second pad face 432.

[0187] In some embodiments, the second temperature control part 4532b can be a resistance wire, and two ends of the second temperature control part 4532b respectively form two pad parts to realize positive and negative electrode connection of the second temperature control part 4532b. For example, one end is electrically connected to the surface of the first pad face 431, and the other end is electrically connected to the surface of the second pad face 432.

[0188] In some embodiments, two ends of the first temperature-sensitive part 4533b respectively form two pad parts to realize positive and negative electrode connection of the first temperature-sensitive part 4533b. For example, one end is electrically connected to the surface of the first pad face 431, and the other end is electrically connected to the surface of the second pad face 432.

[0189] In some embodiments, the eleventh circuit array 453g can include a chip anode pad portion 4534b and a chip cathode pad portion 4535b. The chip anode pad portion 4534b and the chip cathode pad portion 4535b are electrically connected to the electrical connector 430, respectively.

[0190] In some embodiments, the chip anode pad portion 4534b is used for an anode connection of the first laser chip 441, and the chip cathode pad portion 4535b is used for a cathode connection of the first laser chip 441. Exemplarily, the chip anode pad portion 4534b and the chip cathode pad portion 4535b are electrically connected to the first pad surface 431, respectively.

[0191] In some embodiments, the eleventh circuit array 453g can include a first via pad portion 4536b and a second via pad portion 4537b. One end of the first via pad portion 4536b is electrically connected to the third electrode portion 4571, and the other end is electrically connected to the electrical connector 430. One end of the second via pad portion 4537b is electrically connected to the fourth electrode portion 4572, and the other end is electrically connected to the electrical connector 430.

[0192] In some embodiments, the first via pad portion 4536b is used for electrically connecting the third electrode portion 4571, and the second via pad portion 4537b is used for electrically connecting the fourth electrode portion 4572. Exemplarily, one of the first via pad portion 4536b and the second via pad portion 4537b is electrically connected to the first pad surface 431, and the other is electrically connected to the second pad surface 432.

[0193] In some embodiments, the first via pad portion 4536b is formed into a first via portion by penetrating downward from the surface, and the first via portion is filled with a metal medium to form the third electrode portion 4571. The second via pad portion 4537b is formed into a second via portion by penetrating downward from the surface, and the second via portion is filled with a metal medium to form the fourth electrode portion 4572.

[0194] FIG. 11A is a cross-sectional structure diagram of a temperature control device one, and FIG. 11B is a cross-sectional structure diagram of a temperature control device two, according to some embodiments of the present disclosure. As shown in FIG. 11A and FIG. 11B, in some embodiments, the temperature control device 450 includes a first electrode portion 4561 and a second electrode portion 4562.

[0195] In some embodiments, the first electrode portion 4561 and the second electrode portion 4562 can be located on the surface of the first substrate 451, respectively.

[0196] In some embodiments, the first electrode portion 4561 is electrically connected to the second electrode portion 4562 by each thermoelectric couple distributed between the first substrate 451 and the second substrate 452. For example, a positive current source is transmitted into the temperature regulating device 450, starting from the first electrode portion 4561, passing through each series-connected thermoelectric couple to the second electrode portion 4562. In this case, one N-type semiconductor portion 454 and one P-type semiconductor portion 455 are connected in series to form a thermoelectric couple.

[0197] In some embodiments, the first electrode portion 4561 is electrically connected to the N-type semiconductor portion 454. The first electrode portion 4561 and the N-type semiconductor portion 454 are located on the same pad portion on the surface of the first substrate 451.

[0198] In some embodiments, the second electrode portion 4562 is electrically connected to the P-type semiconductor portion 455. The second electrode portion 4562 and the P-type semiconductor portion 455 are located on the same pad portion on the surface of the first substrate 451.

[0199] In some embodiments, when the current source is a positive current source, the current flows out of the first electrode portion 4561, and is transmitted to the N-type semiconductor portion 454 located on the same pad as the first electrode portion 4561, and then continues to be transmitted to the P-type semiconductor portion 455 located on the same pad as the N-type semiconductor portion 454, and so on through each thermoelectric couple, and finally flows into the second electrode portion 4562 through the P-type semiconductor portion 455 located on the same pad as the second electrode portion 4562. When the current source is a negative current source, the current is transmitted along the opposite path.

[0200] FIG. 12A is an exploded view I between the first substrate and the second substrate according to some embodiments of the present disclosure, FIG. 12B is an exploded view II between the first substrate and the second substrate according to some embodiments of the present disclosure, and FIG. 12C is a schematic diagram of current transmission between the first electrode portion and the second electrode portion according to some embodiments of the present disclosure. As shown in FIGS. 12A-12C, in some embodiments, a plurality of thermoelectric couples are distributed between the first substrate 451 and the second substrate 452, and the plurality of thermoelectric couples are connected in series. One N-type semiconductor portion 454 and one P-type semiconductor portion 455 are connected in series to form a thermoelectric couple.

[0201] In some embodiments, each series-connected thermoelectric couple is located between the first electrode portion 4561 and the second electrode portion 4562. When the current source is a positive current source, the current starts from the first electrode portion 4561, and the current shuttles up and down on the N-type semiconductor portion 454 and the P-type semiconductor portion 455 to pass through each thermoelectric couple until reaching the second electrode portion 4562.

[0202] In some embodiments, by adjusting the current direction and size, the carrier motion direction in the N-type semiconductor part 454 and the P-type semiconductor part 455 is adjusted, and then the heat transfer direction between the first substrate 451 and the second substrate 452 is adjusted, so as to control the temperature of the second substrate 452, so that the second substrate 452 has a refrigeration or heating function, so as to adjust the temperature of the laser chip carried on the surface of the third substrate 453a to a target temperature interval, and the target temperature interval is taken as the reference temperature.

[0203] In some embodiments, the upper surface of the first substrate 451 is formed with a first circuit array 451a, and the lower surface of the second substrate 452 is formed with a second circuit array 452a. The first circuit array 451a and the second circuit array 452a are arranged in a top-down manner and are electrically connected. For example, the first circuit array 451a includes a plurality of pad parts, and the second circuit array 452a includes a plurality of pad parts.

[0204] In some embodiments, a plurality of thermocouple pairs are distributed between the first circuit array 451a and the second circuit array 452a. The pad parts between the first circuit array 451a and the second circuit array 452a are staggered, and by the cooperation between the pad parts on the surfaces of the first substrate 451 and the second substrate 452, each thermocouple pair can be connected in series to realize the electrical connection of the first substrate 451 and the second substrate 452.

[0205] In some embodiments, the top ends of the N-type semiconductor part 454 and the P-type semiconductor part 455 in the first thermocouple pair are located on the same pad on the surface of the second substrate 452, the bottom end of the P-type semiconductor part 455 in the first thermocouple pair and the N-type semiconductor part 454 in the second thermocouple pair are located on the same pad on the surface of the first substrate 451, the top end of the N-type semiconductor part in the second thermocouple pair and the P-type semiconductor part 455 in the second thermocouple pair are located on the same pad on the surface of the second substrate 452, the bottom end of the P-type semiconductor part 455 in the second thermocouple pair and the N-type semiconductor part 454 in the third thermocouple pair are located on the same pad on the surface of the first substrate 451, and the top end of the N-type semiconductor part 454 in the third thermocouple pair and the P-type semiconductor part 455 in the third thermocouple pair are located on the same pad on the surface of the second substrate 452. In this way, the pad parts staggered on the surfaces of the first substrate 451 and the second substrate 452 are connected in series to form a line of N-type semiconductor parts 454 and P-type semiconductor parts 455.

[0206] In some embodiments, to illustrate the manner of electrical connection between the first electrode part 4561, each thermocouple pair, and the second electrode part 4562, exemplary, the first circuit array 451a includes a first pad part 4511, a second pad part 4512, a third pad part 4513, a fourth pad part 4514, and the like. Exemplary, one end of the second pad part 4512 faces the first pad part 4511, and the other end faces the third pad part 4513. A plurality of pad parts are provided between the third pad part 4513 and the fourth pad part 4514.

[0207] In some embodiments, the first electrode part 4561 is located on the surface of the first pad part 4511, and the second electrode part 4562 is located on the surface of the fourth pad part 4514. The first pad part 4511 and the fourth pad part 4514 are located at the same end of the first substrate 451.

[0208] In some embodiments, to illustrate the manner of electrical connection between the first electrode part 4561, each thermocouple pair, and the second electrode part 4562, exemplary, the second circuit array 452a includes a fifth pad part 4521, a sixth pad part 4522, a seventh pad part 4523, a ninth pad part 4524, and the like. The fifth pad part 4521 and the first pad part 4511 are staggered, the sixth pad part 4522 and the second pad part 4512 are staggered, and the seventh pad part 4523 and the third pad part 4513 are staggered.

[0209] In some embodiments, to illustrate the manner of electrical connection between the first electrode part 4561, each thermocouple pair, and the second electrode part 4562. Exemplary, the first substrate 451 and the second substrate 452 are distributed with a first N-type semiconductor part 454a, a second N-type semiconductor part 454b, a third N-type semiconductor part 454c, and the like. There are a plurality of N-type semiconductor parts between the second N-type semiconductor part 454b and the third N-type semiconductor part 454c, respectively. In some embodiments, to illustrate the manner of electrical connection between the first electrode part 4561, each thermocouple pair, and the second electrode part 4562. Exemplary, the first substrate 451 and the second substrate 452 are distributed with a first P-type semiconductor part 455a and a second P-type semiconductor part 455b. A plurality of P-type semiconductor parts are distributed between the first P-type semiconductor part 455a and the second P-type semiconductor part 455b.

[0210] In some embodiments, the first N-type semiconductor part 454a and the first P-type semiconductor part 455a constitute a first thermocouple pair, the first P-type semiconductor part 455a and the second N-type semiconductor part 454b constitute a second thermocouple pair, the second N-type semiconductor part 454b and the second P-type semiconductor part 455b constitute a third thermocouple pair, and the second P-type semiconductor part 455b and the third N-type semiconductor part 454c constitute a fourth thermocouple pair, and so on.

[0211] In some embodiments, the first electrode part 4561 and the first N-type semiconductor part 454a are respectively located on the surface of the first pad part 4511 on the first substrate 451. The first N-type semiconductor part 454a and the first P-type semiconductor part 455a are located on the surface of the fifth pad part 4521 on the second substrate 452. The first P-type semiconductor part 455a and the second N-type semiconductor part 454b are located on the surface of the second pad part 4512 on the first substrate 451. In this way, the second N-type semiconductor part 454b and the next P-type semiconductor part are located on the surface of one pad part on the second substrate 452. The next P-type semiconductor part and the next N-type semiconductor part are located on the surface of one pad part on the first substrate 451. In this way, each thermocouple pair is connected in series.

[0212] In some embodiments, the first electrode part 4561 and the first N-type semiconductor part 454a are respectively located on the surface of the first pad part 4511 on the first substrate 451. The second electrode part 4562 and the P-type semiconductor part 455 near the second electrode part 4562 are electrically connected, and are respectively located on the surface of the fourth pad part 4514 on the first substrate 451. The first pad part 4511 is configured to have a surface size larger than that of the first N-type semiconductor part 454a. The fourth pad part 4514 is configured to have a surface size larger than that of the corresponding P-type semiconductor part 455.

[0213] In some embodiments, when the current source is a forward current source, the current flows out from the first electrode part 4561, flows upward to the first N-type semiconductor part 454a on the same pad part as the first electrode part 4561, then flows downward to the first P-type semiconductor part 455a on the same fifth pad part 4521 as the first N-type semiconductor part 454a, then flows upward to the second N-type semiconductor part 454b on the same pad part as the first P-type semiconductor part 455a. In this way, the current is transmitted up and down. Until the current flows upward to the second N-type semiconductor part 454c, then flows downward to the second P-type semiconductor part 455b on the same ninth pad part 4524 as the second N-type semiconductor part 454c, and then flows upward to the second electrode part 4562 on the same pad part as the second P-type semiconductor part 455b, realizing the closed-loop transmission of the current. When the current source is a negative current source, the transmission is in the opposite direction.

[0214] As shown in FIG. 12C, the N-type semiconductor part 454 and the P-type semiconductor part 455 are arranged on the surface of the pad part. The pad part in the dashed line is the pad part on the lower surface of the second substrate 452, and the pad part in the solid line is the pad part on the upper surface of the first substrate 451. The N-type semiconductor part 454 and the P-type semiconductor part 455 are arranged in an alternating manner to form a plurality of thermocouple pairs. The N-type semiconductor part 454 of each thermocouple pair is connected to the P-type semiconductor part 455 of the next thermocouple pair to form a continuous electrical connection.

[0215] In some embodiments, the top ends of the N-type semiconductor part 454 and the P-type semiconductor part 455 in the same thermocouple pair are located on the same pad part on the lower surface of the second substrate 452. The bottom ends of the P-type semiconductor part 455 in each thermocouple pair and the N-type semiconductor part 454 in the next thermocouple pair are located on the same pad part on the surface of the first substrate 451, and the connection is alternated to achieve the series connection of the thermocouple pairs.

[0216] In some embodiments, when the current source is a forward current source, the current is unidirectionally transmitted, and the current is output from the first electrode part 4561, sequentially passes through the N-type semiconductor part 454 and the P-type semiconductor part 455 arranged in an alternating manner, and flows into the second electrode part 4562. When the current source is a reverse current source, the current is transmitted in the opposite direction.

[0217] FIG. 13A is a schematic diagram of the temperature adjustment principle of a temperature adjustment device according to some embodiments of the present disclosure. As shown in FIG. 13A, in some embodiments, when the current source electrically connected to the first electrode part 4561 and the second electrode part 4562 is a forward current source, the current flows out from the first electrode part 4561, passes through the N-type semiconductor part 454 and the P-type semiconductor part 455 arranged in an alternating manner, and directly enters the second electrode part 4562.

[0218] In some embodiments, when the electrically connected current source is a forward current source, the second substrate 452 can be controlled to be a cold end, and the first substrate 451 can be controlled to be a hot end, so as to cool the laser chip on the surface of the third substrate 453a to a target temperature range. When the electrically connected current source is a negative current source, the second substrate 452 can be controlled to be a hot end, and the third substrate 453a can be controlled to be a cold end.

[0219] In some embodiments, the actual temperature of the second substrate 452 can be monitored according to the resistance change of the second temperature-sensitive part 458, so as to monitor the temperature of the laser chip on the surface of the third substrate 453a. By comparing the actual temperature of the second substrate 452 with the target temperature, the MCU can control the driving chip electrically connected to the temperature adjustment device 450 to control the driving chip to output a current with a corresponding size.

[0220] In some embodiments, when the electrically connected current source is a forward current source, the current output by the first electrode portion 4561 flows upward into the N-type semiconductor portion 454 electrically connected thereto, and then flows downward into the P-type semiconductor portion 455 electrically connected to the N-type semiconductor portion 454, and so on.

[0221] In some embodiments, when the electrically connected current source is a forward current source, the current output by the first electrode portion 4561 flows upward into the N-type semiconductor portion 454 electrically connected thereto, and then flows downward into the P-type semiconductor portion 455 electrically connected to the N-type semiconductor portion 454, and so on.

[0222] In some embodiments, when the electrically connected current source is a forward current source, the current output by the first electrode portion 4561 flows upward into the N-type semiconductor portion 454 electrically connected thereto, and then flows downward into the P-type semiconductor portion 455 electrically connected to the N-type semiconductor portion 454, and so on.

[0223] In some embodiments, when the electrically connected current source is a forward current source, the current output by the first electrode portion 4561 flows upward into the N-type semiconductor portion 454 electrically connected thereto, and then flows downward into the P-type semiconductor portion 455 electrically connected to the N-type semiconductor portion 454, and so on.

[0224] In some embodiments, when the electrically connected current source is a forward current source, the current output by the first electrode portion 4561 flows upward into the N-type semiconductor portion 454 electrically connected thereto, and then flows downward into the P-type semiconductor portion 455 electrically connected to the N-type semiconductor portion 454, and so on.

[0225] In some embodiments, when the electrically connected current source is a forward current source, the current output by the first electrode portion 4561 flows upward into the N-type semiconductor portion 454 electrically connected thereto, and then flows downward into the P-type semiconductor portion 455 electrically connected to the N-type semiconductor portion 454, and so on.

[0226] In some embodiments, when the electrically connected current source is a forward current source, the current output by the first electrode portion 4561 flows upward into the N-type semiconductor portion 454 electrically connected thereto, and then flows downward into the P-type semiconductor portion 455 electrically connected to the N-type semiconductor portion 454, and so on.

[0227] In some embodiments, the main carrier in the N-type semiconductor part 454 is electron, the direction of electron movement in the N-type semiconductor part 454 is opposite to the direction of current transmission in the N-type semiconductor part 454, and the current source is a negative current source. In this case, the electrons in the N-type semiconductor part 454 move upward from the first substrate 451 to the second substrate 452.

[0228] In some embodiments, the main carrier in the P-type semiconductor part 455 is hole, the direction of hole movement in the P-type semiconductor part 455 is the same as the direction of current transmission in the P-type semiconductor part 455, and the current source is a negative current source. In this case, the holes in the P-type semiconductor part 455 also move upward from the first substrate 451 to the second substrate 452.

[0229] In some embodiments, when the current source is a negative current source, both the electrons and the holes move upward from the first substrate 451 to the second substrate 452. The movement of the carriers carries energy, and the energy is transferred from the first substrate 451 to the second substrate 452. The second substrate 452 forms a hot end to generate heat, and the first substrate 451 forms a cold end to generate cold.

[0230] FIG. 14 is a cross-sectional structure diagram III of a temperature regulating device according to some embodiments of the present disclosure. As shown in FIG. 14, in some embodiments, a third substrate 453a is provided with a laser chip on its surface. Taking four-way light emission as an example, the laser chip array 440 includes a first laser chip 441, a second laser chip 442, a third laser chip 443, and a fourth laser chip 444. The first laser chip 441, the second laser chip 442, the third laser chip 443, and the fourth laser chip 444 are respectively located on the surface of a separate third substrate 453a. At this time, the temperature of each third substrate 453a can be controlled to independently cool or heat the laser chip on its surface.

[0231] In some embodiments, the temperature of the laser chip on the surface of the third substrate 453a can be adjusted to a target temperature range by adjusting the temperature of the second substrate 452. Then, by independently controlling each third substrate 453a, the temperature of the laser chip on its surface can be independently adjusted to the target temperature of the corresponding laser chip.

[0232] In some embodiments, a plurality of N-type semiconductor parts 454 and P-type semiconductor parts 455 are alternately arranged between the first substrate 451 and the second substrate 452. The current shuttles between the plurality of N-type semiconductor parts 454 and P-type semiconductor parts 455, and the movement of the carriers realizes the energy transfer between the first substrate 451 and the second substrate 452, thereby controlling the cooling or heating of the second substrate 452.

[0233] In some embodiments, a plurality of N-type semiconductor portions 454 and P-type semiconductor portions 455 are alternately arranged between the second substrate 452 and the third substrate 453a, and the current is shuttled between the plurality of N-type semiconductor portions 454 and P-type semiconductor portions 455, so that the movement of the carriers can realize energy transfer between the second substrate 452 and the third substrate 453a, thereby controlling the refrigeration or heating of the third substrate 453a.

[0234] FIG. 15 is a second temperature regulating device exploded view according to some embodiments of the present disclosure, FIG. 16 is a third temperature regulating device exploded view according to some embodiments of the present disclosure, and FIG. 17 is a schematic diagram of current transmission between the second substrate and the third substrate according to some embodiments of the present disclosure. As shown in FIGS. 15-17, in some embodiments, a plurality of N-type semiconductor portions 454 and P-type semiconductor portions 455 are alternately arranged between the second substrate 452 and the third substrate 453a.

[0235] In some embodiments, the first laser chip 441 is located on the surface of one of the third substrates 453a, and the second laser chip 442 is located on the surface of another third substrate 453a.

[0236] In some embodiments, the upper surface of the second substrate 452 is formed with a third circuit array 452b and a fourth circuit array 452c which are independent of each other. The N-type semiconductor portions 454 and P-type semiconductor portions 455 are alternately arranged on the surface of the third circuit array 452b, and the third substrate 453a is located above the N-type semiconductor portions 454 and P-type semiconductor portions 455. The N-type semiconductor portions 454 and P-type semiconductor portions 455 are also alternately arranged on the surface of the fourth circuit array 452c, and another third substrate 453a is located above the N-type semiconductor portions 454 and P-type semiconductor portions 455.

[0237] For example, the third circuit array 452b and the fourth circuit array 452c which are independent of each other can have the same structure or different structures.

[0238] In some embodiments, the third circuit array 452b and a third substrate 453a are distributed with alternately arranged N-type semiconductor portions 454 and P-type semiconductor portions 455. The fourth circuit array 452c and another third substrate 453a are distributed with alternately arranged N-type semiconductor portions 454 and P-type semiconductor portions 455.

[0239] In some embodiments, the lower surface of one of the third substrates 453a is formed with a fifth circuit array 453c, and the fifth circuit array 453c is electrically connected to the third circuit array 452b, so that the third substrate 453a is located above the N-type semiconductor portions 454 and P-type semiconductor portions 455 carried on the surface of the third circuit array 452b.

[0240] In some embodiments, the lower surface of the other third substrate 453a is formed with a sixth circuit array 453d, and the sixth circuit array 453d is electrically connected with the fourth circuit array 452c, so that the third substrate 453 is located above the N-type semiconductor part 454 and the P-type semiconductor part 455 carried on the surface of the fourth circuit array 452c.

[0241] In some embodiments, the third circuit array 452b and the fifth circuit array 453c are distributed with the N-type semiconductor part 454 and the P-type semiconductor part 455 arranged alternately, and the third circuit array 452b and the fifth circuit array 453c are electrically connected to realize the electrical connection between the second substrate 452 and the third substrate 453a.

[0242] In some embodiments, the fourth circuit array 452c and the sixth circuit array 453d are distributed with the N-type semiconductor part 454 and the P-type semiconductor part 455 arranged alternately, and the fourth circuit array 452c and the sixth circuit array 453d are electrically connected to realize the electrical connection between the second substrate 452 and the other third substrate 453a.

[0243] In some embodiments, in order to illustrate the electrical connection mode between the third electrode part 4571, each thermocouple pair, and the fourth electrode part 4572, exemplarily, the third circuit array 452b includes a ninth pad part 4525, a tenth pad part 4526, and an eleventh pad part 4527. A plurality of pad parts are arranged between the tenth pad part 4526 and the eleventh pad part 4527.

[0244] In some embodiments, in order to illustrate the electrical connection mode between the third electrode part 4571, each thermocouple pair, and the fourth three electrode part 4572, exemplarily, the lower surface of the third substrate 453a is formed with a fifth circuit array 453c, and the fifth circuit array 453c includes a twelfth pad part 4531c, a thirteenth pad part 4532c, a fourteenth pad part 4533c, and a fifteenth pad part 4534c.

[0245] In some embodiments, in order to illustrate the electrical connection mode between the third electrode part 4571, each thermocouple pair, and the fourth electrode part 4572, exemplarily, the third substrate 453a and the second substrate 452 are provided with an N-type semiconductor part 454d, an N-type semiconductor part 454e, a P-type semiconductor part 455c, and a P-type semiconductor part 455d.

[0246] In some embodiments, the third electrode portion 4571 is electrically connected with the N-type semiconductor portion 454d, and the fourth electrode portion 4572 is electrically connected with the P-type semiconductor portion 455d. Exemplarily, the bottom surface of the third electrode portion 4571 is connected with the N-type semiconductor portion 454d, and the bottom surface of the fourth electrode portion 4572 is connected with the P-type semiconductor portion 455d. The N-type semiconductor portion 454d is electrically connected with the twelfth pad portion 4531c on the bottom surface of the third substrate 453a, and the P-type semiconductor portion 455d is electrically connected with the fifteenth pad portion 4534c on the bottom surface of the third substrate 453a.

[0247] In some embodiments, the N-type semiconductor portion 454d and the P-type semiconductor portion 455c are electrically connected to form a pair of thermocouple. The P-type semiconductor portion 455c is electrically connected with the N-type semiconductor portion in the next thermocouple pair.

[0248] In some embodiments, the bottom ends of the N-type semiconductor portion 454 and the P-type semiconductor portion 455 in the same thermocouple pair are located on the same pad portion on the top surface of the second substrate 452. The bottom ends of the P-type semiconductor portion 455 in each thermocouple pair and the N-type semiconductor portion 454 in the next thermocouple pair are located on the same pad portion on the bottom surface of the third substrate 453a, and the connection is alternated to realize the series connection of each thermocouple pair.

[0249] In some embodiments, the N-type semiconductor portion 454d and the P-type semiconductor portion 455c are located on the surface of the ninth pad portion 4525 on the top surface of the second substrate 452. The P-type semiconductor portion 455c and the N-type semiconductor portion 454e are located on the surface of the thirteenth pad portion 4532c on the bottom surface of the third substrate 453a. The N-type semiconductor portion 454e and the P-type semiconductor portion in the thermocouple pair are located on the tenth pad portion 4526 on the top surface of the second substrate 452, and the connection is alternated to realize the series connection of each thermocouple pair.

[0250] As shown in FIG. 17, when the current source is a forward current source, the current is transmitted in one direction, and the current is output from the third electrode portion 4571, sequentially passes through the N-type semiconductor portion 454 and the P-type semiconductor portion 455 arranged in an alternating manner, and flows into the fourth electrode portion 4572. When the current source is a reverse current source, the current is transmitted in the opposite direction.

[0251] FIG. 18A is a schematic diagram of the temperature adjustment principle of a temperature adjustment device according to some embodiments of the present disclosure. As shown in FIG. 18A, in some embodiments, when the current source electrically connected with the third electrode portion 4571 and the fourth electrode portion 4572 is a forward current source, the current flows out from the third electrode portion 4571, passes through each N-type semiconductor portion 454 and P-type semiconductor portion 455 arranged in an alternating manner, and directly enters the fourth electrode portion 4572.

[0252] In some embodiments, when the electrically connected current source is a positive current source, the second substrate 452 can be controlled to be a cold end and the third substrate 453a can be controlled to be a hot end, so as to adjust the temperature of the laser chip on the surface of the third substrate 453a to the target temperature range. When the electrically connected current source is a negative current source, the second substrate 452 can be controlled to be a hot end and the third substrate 453a can be controlled to be a cold end.

[0253] In some embodiments, the actual temperature of the third substrate 453a can be monitored according to the resistance change of the third thermosensitive part 4535, and by comparing the actual temperature of the third substrate 453a with the target temperature, the MCU can control the driving chip electrically connected to the temperature control device 450 to control the driving chip to output a current of a corresponding size.

[0254] In some embodiments, the third thermosensitive part 4535 is a thermistor.

[0255] In some embodiments, when the electrically connected current source is a positive current source, the current output by the third electrode part 4571 flows downward into the N-type semiconductor part 454d electrically connected thereto, and then flows upward into the P-type semiconductor part 455c electrically connected to the N-type semiconductor part 454d, and so on.

[0256] In some embodiments, the main carriers in the N-type semiconductor part 454 are electrons, and the motion direction of the electrons in the N-type semiconductor part 454 is opposite to the current transmission direction in the N-type semiconductor part 454. Therefore, when the current source is a positive current source, the electrons in the N-type semiconductor part 454 move upward from the second substrate 452 to the third substrate 453a.

[0257] In some embodiments, the main carriers in the P-type semiconductor part 455 are holes, and the motion direction of the holes in the P-type semiconductor part 455 is the same as the current transmission direction in the P-type semiconductor part 455. Therefore, when the current source is a positive current source, the holes in the P-type semiconductor part 455 also move upward from the second substrate 452 to the third substrate 453a.

[0258] In some embodiments, when the current source is a positive current source, both the electrons and the holes move upward from the second substrate 452 to the third substrate 453a. The motion of the carriers carries energy, so the energy moves upward from the second substrate 452 to the third substrate 453a. The second substrate 452 forms a cold end to cool, and the third substrate 453a forms a hot end to heat.

[0259] FIG. 18B is a schematic diagram of a temperature adjustment principle of a temperature adjustment device according to some embodiments of the present disclosure. As shown in FIG. 18B, in some embodiments, when the electrically connected current source is a negative current source, the current flows out of the fourth electrode portion 4572, passes through each of the alternately arranged N-type semiconductor portion 454 and P-type semiconductor portion 455, and directly enters the third electrode portion 4571.

[0260] In some embodiments, when the electrically connected current source is a negative current source, the second substrate 453 can be controlled as a hot end and the third substrate 451 can be controlled as a cold end, so as to cool the laser chip on the surface of the third substrate 453a to a target temperature range.

[0261] In some embodiments, when the electrically connected current source is a negative current source, the current output by the fourth electrode portion 4572 flows downward into the P-type semiconductor portion 455 electrically connected thereto, and then flows upward into the N-type semiconductor portion 454 electrically connected to the P-type semiconductor portion 455, and so on.

[0262] In some embodiments, the main carrier in the N-type semiconductor portion 454 is an electron, and the motion direction of the electron in the N-type semiconductor portion 454 is opposite to the current transmission direction in the N-type semiconductor portion 454. Therefore, when the current source is a negative current source, the electron in the N-type semiconductor portion 454 moves downward from the third substrate 453a to the second substrate 452.

[0263] In some embodiments, the main carrier in the P-type semiconductor portion 455 is a hole, and the motion direction of the hole in the P-type semiconductor portion 455 is the same as the current transmission direction in the P-type semiconductor portion 455. Therefore, when the current source is a negative current source, the hole in the P-type semiconductor portion 455 also moves downward from the third substrate 453a to the second substrate 452.

[0264] In some embodiments, when the current source is a negative current source, both the electron and the hole move downward from the third substrate 453a to the second substrate 452. The motion of the carriers carries energy, and the energy is transferred from the third substrate 453a to the second substrate 452. The second substrate 452 forms a hot end to generate heat, and the third substrate 453a forms a cold end to generate cold.

[0265] FIG. 19 is a schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure, and FIG. 20 is a schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure. As shown in FIGS. 19-20, in some embodiments, in order to meet the requirement of a larger wire bonding, the end of the electrical connector 430 inside the tube shell 410 includes a first pad surface 431 and a second pad surface 432 to provide more pad portions. The first pad surface 431 and the second pad surface 432 can be arranged in a stepped manner.

[0266] In some embodiments, the first pad surface 431 is used for electrical connection of high frequency signals, and the second pad surface 432 is used for electrical connection of low frequency signals.

[0267] In some embodiments, the positive electrode of the second thermal sensitive part 458 is electrically connected to the second pad surface 432, and the negative electrode is electrically connected to the first pad surface 431 to achieve grounding.

[0268] In some embodiments, the surface of the third substrate 453a is formed with a first electrical connection part 4531 and a second electrical connection part 4532. The first electrical connection part 4531 is used for signal connection of the first laser chip 441, and the second electrical connection part 4532 is used for grounding connection of the first laser chip 441. Exemplarily, the first electrical connection part 4531 and the second electrical connection part 4532 are respectively electrically connected to the first pad surface 431.

[0269] In some embodiments, the surface of the third substrate 453a is formed with a third electrical connection part 4533 and a fourth electrical connection part 4534. The third electrical connection part 4533 is used for wire bonding connection of the third electrode part 4571 and the electrical connector 430, and the fourth electrical connection part 4534 is used for wire bonding connection of the fourth electrode part 4572 and the electrical connector 430. Exemplarily, the third electrical connection part 4533 is electrically connected to the first pad surface 431 or the second pad surface 432, and the fourth electrical connection part 4534 is electrically connected to the second pad surface 432 or the first pad surface 431.

[0270] In some embodiments, the surface of the third substrate 453a is formed with a fifth electrical connection part 4536 and a sixth electrical connection part 4537. The fifth electrical connection part 4536 is used for electrical connection of the positive electrode of the third thermal sensitive part 4535 to the electrical connector 430, and the sixth electrical connection part 4537 is used for electrical connection of the negative electrode of the third thermal sensitive part 4535 to the electrical connector 430. Exemplarily, the fifth electrical connection part 4536 can be electrically connected to the second pad surface 432, and the sixth electrical connection part 4537 can be electrically connected to the pad part electrically connected by the second electrical connection part 4532 in the first pad surface 431.

[0271] In some embodiments, the first electrode part 4561 and the second electrode part 4562 can be respectively electrically connected to the second pad surface 432.

[0272] FIG. 21 is a schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure; and FIG. 22 is a schematic diagram of an electrical connection structure of a light emitting component according to some embodiments of the present disclosure. As shown in FIGS. 21 and 22, in some embodiments, the surface of the third substrate 453b carries the first laser chip 441 and the second laser chip 442.

[0273] In some embodiments, the third substrate 453b is provided with a first temperature control part 4531b, a second temperature control part 4532b, and a first temperature sensitive part 4533b on the surface thereof. The first temperature control part 4531b is located on the side of the first laser chip 441 to control the temperature of the first laser chip 441; and the second temperature control part 4532b is located on the side of the second laser chip 442 to control the temperature of the second laser chip 442.

[0274] In some embodiments, when the temperature of the first laser chip 441 is adjusted, the current transmission direction of the N-type semiconductor part and the P-type semiconductor part between the first substrate 451 and the second substrate 452 is controlled to control the heating or cooling of the second substrate 452, so as to adjust the temperature of the first laser chip 441 to a target temperature range; and then the current transmission direction of the N-type semiconductor part and the P-type semiconductor part between the second substrate 452 and the third substrate on which the first laser chip 441 is located is controlled to control the heating or cooling of the third substrate, so as to further heat or cool the first laser chip 441. The first temperature control part 4531b is controlled to independently adjust the temperature of the first laser chip 441, so as to ensure the wavelength accuracy of the first laser chip 441. By arranging the first laser chip 441 and the second laser chip 442 on the same third substrate 453b, and arranging the first temperature control part 4531b on the side of the first laser chip 441 and the second temperature control part 4532b on the side of the second laser chip 442, the first laser chip 441 and the second laser chip 442 can be independently adjusted in temperature at the same time, while meeting the wavelength accuracy requirements of the first laser chip 441 and the second laser chip 442. By arranging the first laser chip 441 and the second laser chip 442 on the same third substrate 453b, the number of third substrates 453b can be reduced.

[0275] In some embodiments, the third substrate 453b is provided with a second temperature sensitive part 458 on the surface thereof. The positive electrode of the second temperature sensitive part 458 is electrically connected to the second pad surface 432, and the negative electrode thereof is electrically connected to the first pad surface 431.

[0276] In some embodiments, the positive electrodes of the first temperature control part 4531b, the second temperature control part 4532b, and the first temperature sensitive part 4533b are electrically connected to the second pad surface 432, and the negative electrodes thereof are electrically connected to the first pad surface 431.

[0277] In some embodiments, the positive electrode and the negative electrode of the first laser chip 441 are both electrically connected to the first pad surface 431, and the positive electrode and the negative electrode of the second laser chip 442 are both electrically connected to the first pad surface 431.

[0278] FIG. 23 is a cross-sectional view of another light emitting component according to some embodiments of the present disclosure, and FIG. 24 is a partial view of another light emitting component according to some embodiments of the present disclosure. As shown in FIG. 23 and FIG. 24, in some embodiments, the end of the tube 410 is provided with an electrical connector 430. In order to meet the wire bonding requirement, the end of the tube 410 inside the electrical connector 430 includes a first pad surface 431 and a second pad surface 432 to provide more pad portions. Exemplarily, the first pad surface 431 is lower than the second pad surface 432.

[0279] In some embodiments, the light emitting component 400 can include a TEC 470. The TEC 470 is located inside the tube 410. The TEC 470 is located on one side of the electrical connector 430.

[0280] In some embodiments, the light emitting component 400 can include a substrate 480. The substrate 480 is located on the surface of the TEC 470. The surface of the substrate 480 is formed with a circuit pattern.

[0281] In some embodiments, the substrate 480 is used to carry laser chips. The surface of the substrate 480 can carry at least one laser chip. Taking the example of the surface of the substrate 480 carrying one laser chip, taking the example of four-way emission, the laser chip array 440 includes a first laser chip 441, a second laser chip 442, a third laser chip 443, and a fourth laser chip 444. Then the first laser chip 441, the second laser chip 442, the third laser chip 443, and the fourth laser chip 444 are respectively arranged on the surface of the corresponding substrate 480.

[0282] In some embodiments, the surface of the substrate 480 is formed with a heating monitoring portion 481. Exemplarily, through the heating monitoring portion 481, the corresponding laser chip arranged on the surface of the substrate 480 can be heated or cooled, and the real-time temperature of the laser chip arranged on the surface of the substrate 480 can be monitored.

[0283] In some embodiments, the heating monitoring portion 481 can be a heating wire that is sensitive to temperature. Exemplarily, the heating monitoring portion 481 is a Pt heating wire.

[0284] In some embodiments, the surface of the TEC 470 can be provided with a thermal sensitive portion 473 to monitor the surface temperature of the TEC 470. In some embodiments, the positive electrode of the thermal sensitive portion 473 is electrically connected to the second pad surface 432, and the negative electrode is electrically connected to the first pad surface 431. Exemplarily, the thermal sensitive portion 473 can be a thermistor.

[0285] In some embodiments, the surface of the substrate 480 is respectively formed with a circuit pattern for electrically connecting the laser chip on its surface and the heating monitoring portion 481 thereof. Exemplarily, the laser chip and the heating monitoring portion 481 arranged on the surface of the substrate 480 are respectively electrically connected to the first pad surface 431.

[0286] In some embodiments, the TEC 470 is respectively provided with a first electrode column 471 and a second electrode column 472. The first electrode column 471 and the second electrode column 472 can be respectively electrically connected to the second pad surface 432.

[0287] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit them; although the foregoing embodiments of the present disclosure have been described in detail, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An optical module comprising: a circuit board; an optical emitting component electrically connected with the circuit board, comprising: a tube shell, an electrical connector is embedded in the shell of the tube shell, the electrical connector comprises a first pad surface and a second pad surface; a first laser chip; a second laser chip; a temperature control device located in the tube shell, comprising: a first substrate; a second substrate located above the first substrate; at least two third substrates, one of the third substrates is located above the second substrate, wherein the upper surface of one of the third substrates is formed with a seventh circuit array to carry the first laser chip; the upper surface of another of the third substrates is formed with an eighth circuit array to carry the second laser chip; the third substrate is respectively embedded with a third electrode part and a fourth electrode part; the seventh circuit array comprises a first electrical connection part and a second electrical connection part, one end of the first electrical connection part is electrically connected with the positive electrode of the first laser chip, and the other end is electrically connected with the first pad surface; one end of the second electrical connection part is electrically connected with the negative electrode of the first laser chip, and the other end is electrically connected with the first pad surface; the seventh circuit array comprises a third electrical connection part and a fourth electrical connection part, one end of the third electrical connection part is electrically connected with the third electrical connection part, and the other end is electrically connected with the second pad surface, one end of the fourth electrical connection part is electrically connected with the fourth electrode part, and the other end is electrically connected with the second pad surface; wherein the upper surface of the first substrate is formed with a first circuit array; the lower surface of the second substrate is formed with a second circuit array, and the upper surface is formed with a third circuit array and a fourth circuit array which are independent of each other; wherein the second circuit array is electrically connected with the first circuit array to realize the electrical connection between the second substrate and the first substrate; the lower surface of one of the third substrates is formed with a fifth circuit array, and the fifth circuit array is electrically connected with the third circuit array to realize the electrical connection between the second substrate and one of the third substrates; the lower surface of another of the third substrates is formed with a sixth circuit array, and the sixth circuit array is electrically connected with the fourth circuit array to realize the electrical connection between the second substrate and another of the third substrates.

2. The optical module according to claim 1, wherein the third circuit array surface carries N-type semiconductor parts and P-type semiconductor parts arranged alternately, and the fourth circuit array surface carries N-type semiconductor parts and P-type semiconductor parts arranged alternately, one of the third substrates is located above the N-type semiconductor parts and the P-type semiconductor parts carried by the third circuit array surface; another of the third substrates is located above the N-type semiconductor parts and the P-type semiconductor parts carried by the fourth circuit array surface; the third electrode part penetrates the third substrate and is electrically connected with one of the N-type semiconductor parts; the fourth electrode part penetrates the third substrate and is electrically connected with one of the P-type semiconductor parts; the fourth electrode part is electrically connected to the third electrode part through the N-type semiconductor parts and the P-type semiconductor parts distributed between the third substrate and the second substrate.

3. The optical module of claim 1, wherein, A third heat-sensitive part is formed on the third substrate surface carrying the first laser chip, and the third heat-sensitive part is located on one side of the first laser chip; The seventh circuit array includes a fifth electric connection part and a sixth electric connection part; One end of the fifth electric connection part is electrically connected with the third heat-sensitive part, and the other end is electrically connected with the electric connector; one end of the sixth electric connection part is electrically connected with the third heat-sensitive part, and the other end is electrically connected with the electric connector.

4. The optical module according to claim 2, wherein N-type semiconductor parts and P-type semiconductor parts are alternately arranged between the first substrate and the second substrate; N-type semiconductor parts and P-type semiconductor parts are alternately arranged between the second substrate and one of the third substrates; The number of N-type semiconductor parts arranged between the first substrate and the second substrate is greater than the number of N-type semiconductor parts arranged between the second substrate and one of the third substrates; The number of P-type semiconductor parts arranged between the first substrate and the second substrate is greater than the number of P-type semiconductor parts arranged between the second substrate and one of the third substrates.

5. The optical module according to claim 2, wherein The first substrate surface is provided with a first electrode part and a second electrode part, the first electrode part is electrically connected with N-type semiconductor parts, and the second electrode part is electrically connected with P-type semiconductor parts; The first circuit array includes a first pad part, the first pad part supports the N-type semiconductor parts electrically connected with the first electrode part and the first electrode part; The first circuit array includes a fourth pad part, the fourth pad part supports the P-type semiconductor parts electrically connected with the second electrode part and the second electrode part; The N-type semiconductor parts electrically connected with the third electrode part and the P-type semiconductor parts electrically connected with the fourth electrode part are respectively located on different pad parts on the upper surface of the second substrate and respectively located on different pad parts on the lower surface of the third substrate.

6. An optical module, wherein, It includes: A circuit board; An optical emission component electrically connected with the circuit board, including: A tube shell, the end of which is formed with an opening, and an electric connector is embedded in the opening; A first laser chip; A second laser chip; A temperature control device located in the tube shell, including: A first substrate; A second substrate located above the first substrate; A third substrate is located above the second substrate; the third substrate surface is penetrated by a third electrode part and a fourth electrode part; the third substrate surface is formed with an eleventh circuit array to carry the first laser chip and the second laser chip; the eleventh circuit array includes a first temperature control part and a second temperature control part, the first temperature control part and the second temperature control part are electrically connected to the electric connector respectively, the first temperature control part is located on one side of the first laser chip, and the second temperature control part is located on one side of the second laser chip; the eleventh circuit array includes a chip positive electrode pad part and a chip negative electrode pad part, the chip positive electrode pad part and the chip negative electrode pad part are electrically connected to the electric connector respectively; the eleventh circuit array includes a first via pad part and a second via pad part, one end of the first via pad part is electrically connected to the third electrode part, and the other end is electrically connected to the electric connector, one end of the second via pad part is electrically connected to the fourth electrode part, and the other end is electrically connected to the electric connector; The upper surface of the first substrate is formed with a first circuit array; The lower surface of the second substrate is formed with a second circuit array, and the upper surface is formed with a ninth circuit array; wherein the second circuit array is electrically connected with the first circuit array to realize the electrical connection between the second substrate and the first substrate; The lower surface of the third substrate is formed with a tenth circuit array, and the tenth circuit array is electrically connected with the ninth circuit array to realize the electrical connection between the third substrate and the second substrate.

7. The optical module according to claim 6, wherein The ninth circuit array surface carries N-type semiconductor parts and P-type semiconductor parts arranged alternately; The third substrate is located above the N-type semiconductor parts and P-type semiconductor parts carried on the surface of the ninth circuit array; The third electrode part penetrates the third substrate and is connected to one of the N-type semiconductor parts; The fourth electrode part penetrates the third substrate and is electrically connected to one of the P-type semiconductor parts; the fourth electrode part is electrically connected to the third electrode part through the N-type semiconductor parts and P-type semiconductor parts distributed between the third substrate and the second substrate.

8. The optical module according to claim 6, wherein A first thermal sensitive part is formed between the first laser chip and the second temperature control part; Two pad parts are formed at both ends of the first thermal sensitive part, and the two pad parts are electrically connected to the electric connector respectively.

9. The optical module of claim 7, wherein, N-type semiconductor parts and P-type semiconductor parts are distributed alternately between the first substrate and the second substrate; N-type semiconductor parts and P-type semiconductor parts are distributed alternately between the second substrate and one of the third substrates; The number of N-type semiconductor parts distributed between the first substrate and the second substrate is more than that of N-type semiconductor parts distributed between the second substrate and the third substrate; The number of P-type semiconductor parts distributed between the first substrate and the second substrate is more than that of P-type semiconductor parts distributed between the second substrate and the third substrate.

10. The optical module of claim 7, wherein, The first substrate surface is provided with a first electrode part and a second electrode part; The first electrode part is electrically connected to the N-type semiconductor part, and the second electrode part is electrically connected to the P-type semiconductor part; The first circuit array includes a first pad portion supporting an N-type semiconductor portion connected to the first electrode portion and the first electrode portion; The first circuit array includes a fourth pad portion supporting a P-type semiconductor portion connected to the second electrode portion and the second electrode portion; The N-type semiconductor portion connected to the third electrode portion and the P-type semiconductor portion connected to the fourth electrode portion are respectively located on different pad portions of the upper surface of the second substrate and respectively located on different pad portions of the lower surface of the third substrate.

11. The optical module of claim 7, wherein, The third substrate is provided with a first via portion and a second via portion, the first via portion is filled with a metal medium to form the third electrode portion, and the second via portion is filled with a metal medium to form the fourth electrode portion; The bottom end of the third electrode portion is electrically connected to the N-type semiconductor portion, and the bottom end of the fourth electrode portion is electrically connected to the P-type semiconductor portion.

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