Display drive circuit, display drive chip, display module and electronic device

Abstract

A display drive circuit, a display drive chip (100), a display module (1000) and an electronic device. The display drive circuit comprises: a first digital-analog converter DAC (51), a second DAC (52), a drive enhancement circuit (54) and a buffer (53). The first DAC (51) is used for receiving a first digital signal and performing digital-to-analog conversion on the first digital signal; the second DAC (52) has an input end connected to an output end of the first DAC (51), and is used for receiving a second digital signal and performing digital-to-analog conversion on the second digital signal; the buffer (53) is used for outputting a voltage signal, an input end of the buffer (53) being connected to an output end of the second DAC (52); and the drive enhancement circuit (54) has an output end connected to the output end of the second DAC (52), and is used for charging the output end of the second DAC (52). The display drive circuit can reduce brightness inversion of pixel points on display panels.

Description

Display driving circuit, display driving chip, display module and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411394971.9, filed on September 30, 2024, and entitled "Display driving circuit, display driving chip, display module and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display driving, in particular to a display driving circuit, a display driving chip, a display module and an electronic device. BACKGROUND

[0003] The source driving circuit is a circuit module integrated in the display driving chip, which can receive a digital signal and convert it into an analog signal, and charge the corresponding gray scale voltage of the analog signal to the pixel capacitance of the display panel, so that the pixel capacitance emits the brightness corresponding to the analog signal. In order to make the picture displayed by the display panel more delicate and accurate, the gray scale voltage can usually be divided into multiple levels.

[0004] The source driving circuit usually includes a digital-analog converter (DAC), which can convert a digital signal into a corresponding analog signal output. The more levels of gray scale voltage, the more complex the structure of the DAC, and the larger the volume. Therefore, in order to save the area of the display driving chip, interpolation technology is usually used to realize the conversion of digital signal to analog signal. That is, the voltage of multiple levels, wherein a part of the voltage of the levels is non-interpolation step voltage, and the voltage of another part of the levels is interpolation step voltage, and a plurality of interpolation step voltages are uniformly inserted between each adjacent two non-interpolation step voltages.

[0005] However, in the related art, the non-interpolation step voltage is often less than the previous interpolation step voltage, which leads to the brightness inversion of the pixel points on the display panel, thereby causing dark stripes on the display panel, and further failing to achieve accurate display of the picture. SUMMARY

[0006] In order to solve the above technical problems, the present application provides a display driving circuit, a display driving chip, a display module and an electronic device, which can reduce the brightness inversion of the pixel points on the display panel.

[0007] In a first aspect, the present application provides a display driving circuit, comprising: a first digital-analog converter (DAC), a second DAC, a driving enhancement circuit and a buffer. The output end of the first DAC is connected with the input end of the second DAC, the output end of the second DAC is connected with the input end of the buffer, and the output end of the driving enhancement circuit is connected with the output end of the second DAC.

[0008] The display driving circuit of the present application can be applied to a display driving chip, which further comprises a timing control circuit capable of sending a timing signal to the display driving circuit. The first DAC is used to receive a first digital signal, which can be the high several bits of the timing signal. The first DAC performs analog-to-digital conversion on the first digital signal to obtain a first voltage signal. The second DAC is used to receive a second digital signal and the first voltage signal, and the second digital signal can be the low several bits of the timing signal. The second DAC can perform analog-to-digital conversion on the second digital signal, and according to the analog-to-digital conversion result, divide the first voltage signal into multiple second voltage signals and output them. The driving enhancement circuit is used to charge the output end of the second DAC, i.e., to perform voltage enhancement on the multiple second voltage signals output by the second DAC. The buffer is used to receive the multiple second voltage signals and output one voltage signal (for the sake of distinction, hereinafter referred to as a third voltage signal). In the specific charging process of the driving enhancement circuit, when the voltage corresponding to the timing signal is the first type of voltage (for the sake of description, hereinafter referred to as non-interpolation step voltage), the driving enhancement circuit can charge the output end of the second DAC; when the voltage corresponding to the timing signal is the second type of voltage (for the sake of description, hereinafter referred to as interpolation step voltage), the driving enhancement circuit can not charge the output end of the second DAC. In this way, the voltage of the output end of the second DAC can be increased when the voltage of the third voltage signal is the non-interpolation step voltage, thereby ensuring that the current output non-interpolation voltage is always greater than the interpolation voltage of the previous step, reducing the brightness reversal of the pixel points on the display panel, and reducing the occurrence of dark stripes on the display panel, thereby realizing accurate display of the picture.

[0009] In some embodiments of the present application, the driving enhancement circuit comprises a first capacitor, a first end of the first capacitor is connected to the first power supply, and a second end of the first capacitor is connected to the output end of the second DAC. The first power supply can charge the first capacitor, that is, the potential of the first end of the first capacitor is the same as the potential of the output end of the first power supply. Moreover, after the first power supply charges the first capacitor for a period of time, the potential of the second end of the first capacitor is the same as the potential of the first end of the first capacitor. Since the second end of the first capacitor is connected to the output end of the second DAC, the potential of the output end of the second DAC is the same as the potential of the second end of the first capacitor, thereby realizing that the first capacitor charges the output end of the second DAC. The driving enhancement circuit is realized by the first capacitor, which can make the structure of the scheme simple and easy to realize. In addition, when the potential of the output end of the second DAC is the same as the potential of the second end of the first capacitor, and the first power supply no longer charges the first capacitor, under the action of the first capacitor, the potential of the output end of the second DAC slowly decreases, and the voltage of the pixel capacitor also slowly decreases to be slightly higher than the previous interpolation step voltage. Before the charging of the pixel capacitor is completed, the current non-interpolation step voltage is always higher than the previous interpolation step voltage, thereby better avoiding the brightness inversion of the pixel points on the display panel.

[0010] Therefore, the driving enhancement circuit further comprises a second capacitor and a third capacitor, a first end of the second capacitor is connected to the second power supply, and a second end of the second capacitor is connected to the output end of the second DAC. A first end of the third capacitor is connected to the third power supply, and a second end of the third capacitor is connected to the output end of the second DAC. Since the voltage of the third voltage signal output by the buffer can be one of the plurality of non-interpolation step voltages, and different non-interpolation step voltages have different sizes. When the driving enhancement circuit further comprises the second capacitor and the third capacitor, the first end of the first capacitor is connected to the first power supply, the first end of the second capacitor is connected to the second power supply, and the first end of the third capacitor is connected to the third power supply, that is, the first ends of the first capacitor, the second capacitor and the third capacitor are respectively connected to different power supplies. Thus, the number of capacitors charging the output end of the second DAC can be controlled by each power supply, thereby controlling the degree of charging the output end of the second DAC, and further realizing different degrees of charging for different non-interpolation step voltages, so that the voltage of the third voltage signal output after charging and from the buffer is closer to the theoretical value of the corresponding non-interpolation step voltage, thereby improving the accuracy of brightness control of the pixel points of the display panel.

[0011] In some embodiments of the present application, the driving enhancement circuit further comprises a first capacitor state control circuit, an input terminal of the first capacitor state control circuit is connected to the second terminal of the first capacitor, and an output terminal of the first capacitor state control circuit is connected to the output terminal of the second DAC. The first capacitor state control circuit is configured to control whether the first capacitor charges the output terminal of the second DAC. In a specific implementation, when the voltage corresponding to the timing signal is a non-interpolation step voltage, the first capacitor state control circuit controls the first capacitor to charge the output terminal of the second DAC; when the voltage corresponding to the timing signal is an interpolation step voltage, the first capacitor state control circuit controls the first capacitor not to charge the output terminal of the second DAC, thereby making the charging of the output terminal of the second DAC more accurate. In addition, when the voltage corresponding to the timing signal is an interpolation step voltage, the first power supply charges the first capacitor, and the first capacitor does not need to charge the output terminal of the second DAC; when the voltage corresponding to the timing signal is an interpolation step voltage, the first power supply has completed charging the first capacitor, and the first capacitor can charge the output terminal of the second DAC, thereby avoiding occupying an additional clock cycle, and thus the charging speed of the pixel capacitor can be improved.

[0012] In a specific implementation, the first capacitor state control circuit can receive low-bit digital signals in the timing signal, and determine whether the corresponding voltage is an interpolation step voltage or a non-interpolation step voltage according to the low-bit digital signals, so as to control the first capacitor to charge the output terminal of the second DAC when the voltage corresponding to the timing signal is a non-interpolation step voltage.

[0013] Further, the driving enhancement circuit further comprises a second capacitor and a third capacitor, a first terminal of the second capacitor is configured to be connected to the first power supply, and a first terminal of the third capacitor is configured to be connected to the first power supply. The driving enhancement circuit further comprises a second capacitor state control circuit and a third capacitor state control circuit. An input terminal of the second capacitor state control circuit is connected to a second terminal of the second capacitor, and an output terminal of the second capacitor state control circuit is connected to the output terminal of the second DAC. In this way, the second capacitor state control circuit can control whether the second capacitor charges the output terminal of the second DAC. An input terminal of the third capacitor state control circuit is connected to a second terminal of the third capacitor, and an output terminal of the third capacitor state control circuit is connected to the output terminal of the second DAC. In this way, the third capacitor state control circuit can control whether the third capacitor charges the output terminal of the second DAC. Therefore, in the present application, when a plurality of capacitors are included in the driving enhancement circuit, each capacitor state control circuit can control whether the corresponding capacitor charges the output terminal of the second DAC.

[0014] In some embodiments of the present application, the first capacitor state control circuit includes a first switch tube, a first pole of the first switch tube is connected with the second end of the first capacitor, and a second pole of the first switch tube is connected with the output end of the second DAC. The control pole of the first switch tube can be used to receive a low-bit digital signal in the timing signal. In one example, when the low-bit digital signal is 0, the first switch tube is open; when the low-bit digital signal is 1, the first switch tube is closed. In another example, when the low-bit digital signal is 1, the first switch tube is open; when the low-bit digital signal is 0, the first switch tube is closed. When the first switch tube is closed, the first switch tube can connect the second end of the first capacitor with the output end of the second DAC and charge the output end of the second DAC. This scheme is simple in structure, easy to implement, and relatively reliable.

[0015] In some cases, the second DAC can receive a multi-bit digital signal in the timing signal, and each switch tube can receive a bit of the digital signal. Therefore, in order to implement the reception of each bit of the multi-bit digital signal, in one embodiment, the capacitor state control circuit can further include a second switch tube and a third switch tube, a first pole of the second switch tube is connected with the second pole of the first switch tube, a first pole of the third switch tube is connected with the second pole of the second switch tube, and a second pole of the third switch tube is connected with the output end of the second DAC. That is, the first switch tube, the second switch tube and the third switch tube are connected in series. The control pole of the first switch tube, the control pole of the second switch tube and the control pole of the third switch tube can respectively receive one bit of the multi-bit digital signal. When each bit of the digital signal is 1, the first switch tube, the second switch tube and the third switch tube are all closed, so that the first capacitor can charge the output end of the second DAC.

[0016] In another embodiment, the second DAC can receive a two-bit digital signal in the timing signal, and the first capacitor state control circuit can include two switch tubes, i.e. a first switch tube and a second switch tube, and a first pole of the second switch tube is connected with the second pole of the first switch tube, and a second pole of the second switch tube is connected with the output end of the second DAC. Therefore, when the control poles of the first switch tube and the second switch tube receive digital signals of 1, the first switch tube, the second switch tube and the third switch tube are all closed, so that the first capacitor can charge the output end of the second DAC.

[0017] It can be understood that in other embodiments, the second DAC can receive a four-bit digital signal in the timing signal, and the first capacitor state control circuit can include four switch tubes; the second DAC can receive a five-bit digital signal in the timing signal, and the first capacitor state control circuit can include five switch tubes; and so on.

[0018] In some embodiments of the present application, the driving enhancement circuit further comprises a second capacitor and a third capacitor, a first end of the second capacitor is configured to be connected to the first power supply, and a second end of the third capacitor is configured to be connected to the first power supply. In this case, the driving enhancement circuit further comprises a charging gear control circuit, the second ends of the first capacitor, the second capacitor and the third capacitor are all connected to an input end of the charging gear control circuit, an output end of the charging gear control circuit is connected to an output end of the second DAC, and the charging gear control circuit is configured to control the number of capacitors that charge the output end of the second DAC. That is, the charging gear control circuit can control whether the first capacitor charges the output end of the second DAC, control whether the second capacitor charges the output end of the second DAC, and control whether the third capacitor charges the output end of the second DAC. The first capacitor, the second capacitor and the third capacitor can form a capacitor array, the more capacitors that charge the output end of the second DAC, the larger the capacitance value of the capacitor array, the faster the voltage build-up speed of the output end of the second DAC and the higher the voltage. Thus, it is convenient to select different numbers of capacitors to charge the output end of the second DAC according to the size of the voltage corresponding to the timing signal, so as to control the degree of charging for the output end of the second DAC, and then realize different degrees of charging for different non-interpolation step voltages, so that the voltage of the third voltage signal after charging and output from the buffer is closer to the theoretical value of the corresponding non-interpolation step voltage, thereby improving the accuracy of the brightness control of the pixel points of the display panel.

[0019] In a specific implementation, the received signal of the driving enhancement circuit can be the same as the received signal of the first DAC, for example, both are high-bit digital signals of the timing signal, and the driving enhancement circuit can determine the number of capacitors that charge the output end of the second DAC according to the size relationship between the high-bit digital signals.

[0020] Specifically, the charging gear control circuit includes a fourth switch tube, a fifth switch tube and a sixth switch tube, the first electrode of the fourth switch tube is connected with the second end of the first capacitor, and the second electrode of the fourth switch tube is connected with the output end of the second DAC; the first electrode of the fifth switch tube is connected with the second end of the second capacitor, and the second electrode of the fifth switch tube is connected with the output end of the second DAC; the first electrode of the sixth switch tube is connected with the second end of the third capacitor, and the second electrode of the sixth switch tube is connected with the output end of the second DAC. That is, the fourth switch tube controls whether the first capacitor charges the output end of the second DAC, the fifth switch tube controls whether the second capacitor charges the output end of the second DAC, and the sixth switch tube controls whether the third capacitor charges the output end of the second DAC. For example, when the fourth switch tube, the fifth switch tube and the sixth switch tube are all closed, the first capacitor, the second capacitor and the third capacitor can all charge the output end of the second DAC, that is, the number of capacitors charging the output end of the second DAC is three; when 2 of the fourth switch tube, the fifth switch tube and the sixth switch tube are closed, the number of capacitors charging the output end of the second DAC is two; when 1 of the fourth switch tube, the fifth switch tube and the sixth switch tube is closed, the number of capacitors charging the output end of the second DAC is one.

[0021] In a specific implementation, the control electrodes of the fourth switch tube, the fifth switch tube and the sixth switch tube can respectively receive three bits of high-bit digital signals, when the fourth switch tube receives a digital signal of 1, it is closed; when the received digital signal is 0, it is opened, so that the first capacitor can charge the output end of the second DAC. Similarly, when the fifth switch tube is closed, the second capacitor can charge the output end of the second DAC. When the sixth switch tube is closed, the third capacitor can charge the output end of the second DAC.

[0022] It can be understood that the number of capacitors in the driving enhancement circuit can be the same as the number of bits of high-bit digital signals in the timing signal received by the first DAC. For example, when the first DAC receives a high-6-bit digital signal, the driving enhancement circuit can include 6 capacitors. Correspondingly, the number of switch tubes in the charging gear control circuit can also be the same as the number of bits of high-bit digital signals in the timing signal received by the first DAC, that is, also 6. In this way, the charging degree of the driving enhancement circuit to the output end of the second DAC can be more accurately controlled.

[0023] The second aspect of the present application also provides a display driving chip, which includes a timing control circuit and a display driving circuit of any of the above embodiments, and the timing control circuit is electrically connected with the display driving circuit. The display driving chip can realize all the effects of the display driving circuit.

[0024] The third aspect of the present application further provides a display module comprising the display panel and the display driving chip. The display module can realize all effects of the display driving chip.

[0025] The fourth aspect of the present application further provides an electronic device comprising the controller and the display module. The electronic device can realize all effects of the display module. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] FIG. 1 is a structural schematic diagram of a display module in the embodiments of the present application;

[0028] FIG. 2 is a specific structural schematic diagram of a power supply, a display driving chip and a display panel in the embodiments of the present application;

[0029] FIG. 3 is a voltage change curve in the process of charging a pixel capacitor by a non-interpolation step voltage 127 and an interpolation step voltage 126;

[0030] FIG. 4 is a structural schematic diagram of a display driving circuit in the embodiments of the present application;

[0031] FIG. 5 is a specific structural schematic diagram of the display driving circuit shown in FIG. 4;

[0032] FIG. 6a is a specific structure of a driving enhancement circuit in the display driving circuit shown in FIG. 5 and a connection structure between the driving enhancement circuit and a second DAC and a first power supply;

[0033] FIG. 6b is another specific structure of the driving enhancement circuit in the display driving circuit shown in FIG. 5 and a connection structure between the driving enhancement circuit and a second DAC, a first power supply, a second power supply and a third power supply;

[0034] FIG. 7 is a voltage change curve in the process of charging a pixel capacitor C by a non-interpolation step voltage 127 and an interpolation step voltage 126 and a voltage change curve in the process of charging the pixel capacitor C by the non-interpolation step voltage 127 when the display driving circuit 50 does not comprise the driving enhancement circuit 54;

[0035] FIG. 8a is a third specific structure of the driving enhancement circuit in the display driving circuit shown in FIG. 5 and a connection structure between the driving enhancement circuit and a second DAC and a first power supply;

[0036] Fig. 8b is a fourth specific structure of the driving enhancement circuit in the display driving circuit shown in Fig. 5 and a connection structure between the first power supply, the second power supply and the third power supply of the second DAC;

[0037] Fig. 9 is a fifth specific structure of the driving enhancement circuit in the display driving circuit shown in Fig. 5 and a connection structure between the first power supply, the second power supply and the third power supply of the second DAC;

[0038] Fig. 10 is a sixth specific structure of the driving enhancement circuit in the display driving circuit shown in Fig. 5 and a connection structure between the first power supply, the second power supply and the third power supply of the second DAC;

[0039] Fig. 11 is a seventh specific structure of the driving enhancement circuit in the display driving circuit shown in Fig. 5 and a connection structure between the first power supply, the second power supply and the third power supply of the second DAC;

[0040] Fig. 12 is an eighth specific structure of the driving enhancement circuit in the display driving circuit shown in Fig. 5 and a connection structure between the first power supply, the second power supply and the third power supply of the second DAC.

[0041] Fig. 12 is an eighth specific structure of the driving enhancement circuit in the display driving circuit shown in Fig. 5 and a connection structure between the first power supply, the second power supply and the third power supply of the second DAC. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0043] The term "and / or", merely used to describe associated objects, means that there can be three relationships, for example, A and / or B, can mean: A alone, A and B exist at the same time, B alone, the three cases, where A, B can be singular or plural. The character " / " generally represents the "or" relationship between the associated objects before and after. "At least one" means one or more, and "multiple" means two or more. "At least one" or the like means any combination of these items, including single or multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0044] The terms "first" and "second" and the like in the description and claims of the present application are used to distinguish different objects, not to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, not to describe the specific order of the target objects.

[0045] The terms "connection", "connected", and the like are used to express the intercommunication or interaction between different components, which can include direct connection or indirect connection through other components. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, including a series of steps or units. The method, system, product or device does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", and the like are only used to describe the orientation of the components in the drawings, and these directional terms are relative concepts, which are used for relative description and clarification, which can change accordingly according to the change of the orientation of the components in the drawings.

[0046] In the embodiments of the present application, the words "exemplary" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" and the like is intended to present the relevant concept in a specific manner.

[0047] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. For example, multiple processing units mean two or more processing units; multiple systems mean two or more systems.

[0048] The electronic device usually comprises a display module and a controller, the display module is electrically connected with the controller, and the controller can send a control signal to the display module to control the display module to display images, characters and the like.

[0049] Here, the electronic device may, for example, be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like, and the embodiments of the present application do not limit this. Illustratively, the above-mentioned consumer electronic product may, for example, be a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (for example, a smart watch, a smart bracelet, and the like), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, and the like. The home electronic product may, for example, be a smart door lock, a television, a smart sound box, a sweeping robot, and the like. The vehicle-mounted electronic product may, for example, be a vehicle-mounted navigator, a vehicle-mounted display, and the like. The financial terminal product may, for example, be an automated teller machine (ATM), an electronic device for self-service operation, and the like.

[0050] As shown in FIG. 1, the display module 1000 can comprise a display panel 400, a power supply 200, a display driving chip 1000, and a flexible flat cable 300, the display panel 400 is connected with the display driving chip 1000 through the flexible flat cable 300, and the power supply 200 is connected with the display driving chip 1000.

[0051] As shown in FIG. 2, the display panel 400 can comprise a plurality of pixel capacitances C arranged in a rectangular array, each pixel capacitance C corresponds to each pixel point on the display panel 400 respectively, and after charging the pixel capacitance C, the corresponding pixel point will be lit.

[0052] As shown in FIG. 2, the display driving chip 1000 can include a power conversion circuit 10, a reference voltage generation circuit 20, a timing control circuit 30, a gate driving circuit 40 and a source driving circuit 50. The input end of the power conversion circuit 10 can be connected with an external power supply 200, the output end of the power conversion circuit 10 can be connected with the input end of the reference voltage generation circuit 20, and the output end of the power conversion circuit 10 can also be connected with the power supply end of the gate driving circuit 40, the power supply end of the timing control circuit 30 and the power supply end of the source driving circuit 50 respectively. The external power supply 200 can provide an original voltage to the power conversion circuit 10, and the power conversion circuit 10 can convert the received original voltage into different specifications of voltage and provide them to the reference voltage generation circuit 20, the timing control circuit 30, the gate driving circuit 40 and the source driving circuit 50 respectively.

[0053] As shown in FIG. 2, the output end of the timing control circuit 30 is also connected with the input end of the gate driving circuit 40. The timing control circuit 30 is used to receive a display data signal and generate a first timing signal according to the display data signal, and send the first timing signal to the gate driving circuit 40. After receiving the first timing signal, the gate driving circuit 40 can generate a gate driving signal and send the gate driving signal to the display panel 400, so as to select a certain pixel capacitor C in the plurality of pixel capacitors C of the display panel 400 as a pixel capacitor C which needs to be charged currently.

[0054] As shown in FIG. 2, the output end of the timing control circuit 30 is also connected with the input end of the source driving circuit 50. The timing control circuit 30 is used to receive a display data signal and generate a second timing signal according to the display data signal, and send the second timing signal to the source driving circuit 50. The second timing signal can be a digital signal. After receiving the second timing signal, the source driving circuit 50 can convert the second timing signal into a voltage signal and send the voltage signal to the display panel 400. The voltage signal can be charged to the pixel capacitor C selected by the gate driving signal, so as to charge the pixel capacitor C, and the pixel point corresponding to the pixel capacitor C is lit up.

[0055] When the area of the display panel 400 is larger, the length of the wire of the source driving circuit 50 is also longer, and the parasitic capacitance generated is also larger. In the application of high resolution (more pixel points) and high refresh rate (higher frequency of switching the brightness of each pixel point), the charging time of the pixel point is continuously compressed, that is, the display driving chip 1000 is required to charge the pixel capacitor C in the display panel 400 faster.

[0056] The voltage of any pixel capacitor C shown in FIG. 2 determines the brightness of the corresponding pixel. To make the brightness control of the pixel more accurate and the display more delicate and accurate, more voltage levels are required. Here, taking an 8-bit binary digital signal as an example, the voltage is divided into 256 levels accordingly. In the display driving chip 1000, if a 8-bit digital-to-analog conversion is directly implemented, the design difficulty is great and the number of switches is large, which consumes more chip area resources. Therefore, in the related art, an interpolation technology is usually used. For example, 64 non-interpolation step voltages are generated by using a 6-bit DAC, and 3 interpolation step voltages are uniformly inserted between two adjacent non-interpolation step voltages by using a 2-bit interpolation DAC, so that the conversion of 8-bit data is realized by using the 6-bit DAC and the 2-bit DAC. Moreover, among the multiple voltage levels, part of the voltage levels are non-interpolation step voltages, and part of the voltage levels are interpolation step voltages, and multiple interpolation step voltages are uniformly inserted between every two adjacent non-interpolation step voltages. The structures of the 6-bit DAC and the 2-bit DAC are relatively simple, and fewer components are required, so that the chip area can be saved.

[0057] Taking the voltages of 127 and 126 of the pixel capacitor C as examples, the charging effect of the pixel capacitor C is analyzed. The voltage 127 is a non-interpolation step voltage, and the voltage 126 is an interpolation step voltage. In theory, the voltage 127 should be higher than the voltage 126. FIG. 3 shows the voltage change curve (curve a) of the non-interpolation step voltage 127 in the charging process of the pixel capacitor C shown in FIG. 2, and the voltage change curve (curve b) of the interpolation step voltage 126 in the charging process of the pixel capacitor C shown in FIG. 2. As can be seen from FIG. 3, the rising edge starts charging, and if the charging result is pushed out to the pixel capacitor C shown in FIG. 2 soon after the falling edge, the pixel capacitor C corresponding to the voltage 127 has not been charged completely at this time, and the voltage is lower than 126, which will cause brightness inversion and dark stripes will appear on the display panel 400.

[0058] Based on this, the embodiment of the present application provides a display driving circuit, which can be the source driving circuit 50 shown in FIG. 2. As shown in FIG. 4, the display driving circuit can include a first DAC 51, a second DAC 52, a buffer 53 and a driving enhancement circuit 54. The output end of the first DAC 51 is connected with the input end of the second DAC 52, the output end of the second DAC 52 is connected with the input end of the buffer 53, and the output end of the driving enhancement circuit 54 is also connected with the output end of the second DAC 52.

[0059] In the embodiment, the first DAC 51 can be connected with the timing control circuit 30 shown in FIG. 2 to receive a first digital signal. The first digital signal can be the high several bits of the timing signal sent by the timing control circuit 30 shown in FIG. 2, i.e., the number of bits of the first digital signal is less than the number of bits of the timing signal. For example, when the number of bits of the timing signal is 8 bits, the number of bits of the first digital signal can be 4 bits, 5 bits, 6 bits, 7 bits, etc. Hereinafter, the number of bits of the first digital signal is 6 bits. Then, the first digital signal can be the high 6 bits of the timing signal. For example, when the timing signal is 1111100 (corresponding to the voltage 124), the timing signal is 1111101 (corresponding to the voltage 125), the timing signal is 1111110 (corresponding to the voltage 126), and the timing signal is 1111111 (corresponding to the voltage 127), the first digital signal is 111111.

[0060] The first DAC 51 performs digital-to-analog conversion on the first digital signal to obtain and output a first voltage signal. The first voltage signal can include two sub-voltage signals. For convenience of description, they are named as a first sub-voltage signal and a second sub-voltage signal. The voltage of the first sub-voltage signal is obtained by reducing the first digital signal by 1 and taking the high 6 bits as a number and taking the low 2 bits as 11. The voltage of the second sub-voltage signal can be obtained by taking the first digital signal as the high 6 bits and taking the low 2 bits as 11. For example, when the voltage corresponding to the timing signal is 124, 125, 126, and 127, the voltage of the first sub-voltage signal output by the first DAC 51 is 123, and the voltage of the second sub-voltage signal is 127. The voltage of the first sub-voltage signal and the voltage of the second sub-voltage signal differ by 4.

[0061] In a specific implementation, as shown in FIG. 5, the first DAC 51 can include a plurality of resistors R and a plurality of selectors Mux connected in series. The first resistor R of the plurality of resistors R can be connected to the power conversion circuit 10 shown in FIG. 2, and the last resistor R of the plurality of resistors R can be grounded. The plurality of selectors Mux have a plurality of input ends connected to each two resistors R. The selectors Mux connected to different positions can receive different voltages. The plurality of selectors Mux can be used to receive the first digital signal, select the corresponding first sub-voltage signal and second sub-voltage signal according to the first digital signal, and output from the output end of the plurality of selectors Mux.

[0062] As shown in FIG. 5, the second DAC 52 can be configured to receive a second digital signal, which can be the low several bits of the timing signal sent by the timing control circuit 30 shown in FIG. 2, and the number of bits of the second digital signal and the number of bits of the first digital signal can be added to be the number of bits of the timing signal. For example, when the number of bits of the timing signal is 8 bits and the number of bits of the first digital signal is 5 bits, the number of bits of the second digital signal can be 3 bits; when the number of bits of the first digital signal is 6 bits, the number of bits of the second digital signal can be 2 bits; and when the number of bits of the first digital signal is 7 bits, the number of bits of the second digital signal can be 1 bit. Hereinafter, the number of bits of the second digital signal is taken as an example of 2 bits. Then, the second digital signal is the low 2 bits of the timing signal output by the timing control circuit 30. For example, when the timing signal is 1111100, the second digital signal is 00.

[0063] When the timing signal is 1111100 (corresponding to the voltage 124), the voltage 124 can be calculated by 0.75*123+0.25*127, where 0.75 and 0.25 are weight coefficients. When the timing signal is 1111101 (corresponding to the voltage 125), the voltage 125 can be calculated by 0.5*123+0.5*127, where 0.5 and 0.5 are weight coefficients. When the timing signal is 1111110 (corresponding to the voltage 126), the voltage 126 can be calculated by 0.75*123+0.25*127, where 0.75 and 0.25 are weight coefficients. When the timing signal is 1111111 (corresponding to the voltage 127), the voltage 127 can be calculated by 0*123+1*127, where 0 and 1 are weight coefficients. It can be seen that when the low 2 bits of the timing signal, i.e., the second digital signal, are different, the corresponding weight coefficients are different. Therefore, a corresponding relationship between the second digital signal and the weight coefficients can be established in advance, and the second DAC 52 can determine the weight coefficients according to the second digital signal after receiving the second digital signal. When the second digital signal is 00, the weight coefficients are determined to be 0.75 and 0.25. When the second digital signal is 01, the weight coefficients are determined to be 0.5 and 0.5. When the second digital signal is 10, the weight coefficients are determined to be 0.25 and 0.75. When the second digital signal is 11, the weight coefficients are determined to be 0 and 1.

[0064] The second DAC 52 can also receive the two first voltage signals sent by the first DAC 51, and divide the two first voltage signals into four second voltage signals according to the weight coefficients. For example, when the timing signal outputted by the timing control circuit 30 shown in FIG. 1 is 1111100 (corresponding to a voltage of 124), and the weight coefficients are 0.75 and 0.25, then in the four second voltage signals outputted, three of the second voltage signals have a voltage of the first sub-voltage, and the other second voltage signal has a voltage of the second sub-voltage. When the weight coefficients are 0.5 and 0.5, then in the four second voltage signals outputted, two of the second voltage signals have a voltage of the first sub-voltage, and the other two second voltage signals have a voltage of the second sub-voltage; when the weight coefficients are 0.25 and 0.75, then in the four second voltage signals outputted, one of the second voltage signals has a voltage of the first sub-voltage, and the other three second voltage signals have a voltage of the second sub-voltage; when the weight coefficients are 0 and 1, then in the four second voltage signals outputted, all have a voltage of the first sub-voltage.

[0065] As shown in FIG. 4, the output end of the drive enhancement circuit 54 is connected to the output end of the second DAC 52, and the drive enhancement circuit 54 can be used to charge the output end of the second DAC 52. Since the output end of the second DAC 52 outputs multiple second voltage signals, the drive enhancement circuit 54 can perform voltage enhancement on each second voltage signal.

[0066] As shown in FIG. 5, the buffer 53 can include a differential circuit 531 and a power amplifier 532, the differential circuit 531 can include a plurality of differential pairs 5311, the number of the differential pairs 5311 is the same as the number of the second voltage signals output by the second DAC 52, therefore, in the embodiment, the buffer 53 can include four differential pairs 5311 as shown in FIG. 4. Each of the differential pairs 5311 corresponds to one of the second voltage signals. When the voltage corresponding to the timing signal is 124, the weight coefficients are 0.75 and 0.25, among the four second voltage signals, three of the second voltage signals correspond to the first sub-voltage, and the other one of the second voltage signals corresponds to the second sub-voltage, then three of the differential pairs 5311 are driven by the first sub-voltage, and one of the differential pairs 5311 is driven by the second sub-voltage, that is, the four differential pairs 5311 are driven by the first sub-voltage and the second sub-voltage. Similarly, when the voltage corresponding to the timing signal is 125, the weight coefficients are 0.5 and 0.5, and when the voltage corresponding to the timing signal is 126, the weight coefficients are 0.75 and 0.25, the four differential pairs 5311 are driven by the first sub-voltage and the second sub-voltage. When the voltage corresponding to the timing signal is 127, the weight coefficients are 1 and 0, the voltage corresponding to the four second voltage signals output is the first sub-voltage, and the four differential pairs 5311 are driven by the first sub-voltage. The four differential pairs 5311 can output one voltage signal to the power amplifier 532 for amplification and output the third voltage signal to the display panel 400 shown in FIG. 1.

[0067] The voltage of the third voltage signal corresponds to the timing signal, which can be the same as the first sub-voltage output by the first DAC 51, or can be obtained by using the first sub-voltage and the second sub-voltage and the respective weight coefficients. Since the voltage corresponding to the timing signal is divided into 256 levels, the voltage of 64 levels is the same as the first sub-voltage or the second sub-voltage output by the first DAC 51, and is not obtained by interpolation, these voltages can be referred to as non-interpolation step voltages; the remaining voltages are obtained by interpolation, and therefore can also be referred to as interpolation step voltages. For example, among the four voltages 124, 125, 126 and 127, 124, 125 and 126 are interpolation step voltages, and 127 is a non-interpolation step voltage.

[0068] For non-interpolation voltage, four differential pairs 5311 need to be driven simultaneously, and for interpolation voltage, it can be driven by two voltages, so the charging speed of interpolation voltage is faster than that of non-interpolation voltage. For example, for the charging process diagram shown in FIG. 3, the charging speed of voltage 126 is faster than that of voltage 127, and then voltage 126 is higher than voltage 127, which causes the brightness inversion of the pixel capacitance C shown in FIG. 2. Based on this, in the embodiment, the driving enhancement circuit 54 can charge the output end of the second DAC 52 when the timing signal corresponds to the non-interpolation voltage, thereby improving the charging speed of the non-interpolation voltage, reducing the brightness inversion of the pixel capacitance, reducing the occurrence of dark stripes on the display panel 400 shown in FIG. 2, and realizing accurate display of the picture.

[0069] In the embodiment, as shown in FIG. 6a, the driving enhancement circuit 54 includes a first capacitor C1, a first end of the first capacitor C1 is connected to the first power supply 11, and a second end of the first capacitor C1 is connected to the output end of the second DAC 52. The first power supply 11 can charge the first capacitor C1 under the control of the display module 1000 shown in FIG. 1, that is, the potential of the first end of the first capacitor C1 is the same as the potential of the output end of the first power supply 11. Moreover, after the first power supply 11 charges the first capacitor C1 for a period of time, the potential of the second end of the first capacitor C1 is the same as the potential of the first end of the first capacitor C1. Since the second end of the first capacitor C1 is connected to the output end of the second DAC 52, the potential of the output end of the second DAC 52 is the same as the potential of the second end of the first capacitor C1, thereby realizing the charging of the output end of the second DAC 52 by the first capacitor C1. The driving enhancement circuit 54 is realized by the first capacitor C1, which can make the structure of the scheme simple and easy to realize.

[0070] In addition, in the embodiment, the first capacitor C1 can be a general capacitor or a metal-oxide-semiconductor field-effect transistor (MOS) capacitor. When the first capacitor C1 is a MOS capacitor, the area of the display driving chip 1000 shown in FIG. 1 can be saved.

[0071] In addition, when the potential of the output terminal of the second DAC 52 is the same as the potential of the second terminal of the first capacitor C1, and the first power supply 11 no longer charges the first capacitor C1, the potential of the output terminal of the second DAC 52 slowly decreases under the action of the first capacitor C1, and the voltage of the pixel capacitor C also slowly decreases. The specific change process is shown in FIG. 7. In FIG. 7, curve a1 represents the voltage change curve of the pixel capacitor C during charging by the non-interpolation step voltage 127 in the embodiment, curve a2 represents the voltage change curve of the pixel capacitor C during charging by the non-interpolation step voltage 127 when the display driving circuit 50 does not include the driving enhancement circuit 54, and curve b represents the voltage change curve of the pixel capacitor C during charging by the interpolation step voltage 126 in the embodiment. As can be seen from FIG. 7, the voltage of the pixel capacitor C also slowly decreases, and in the embodiment, the voltage of the pixel capacitor corresponding to the non-interpolation step voltage 127 is always higher than the voltage of the pixel capacitor corresponding to the interpolation step voltage 126. That is, during charging of the pixel capacitor, the current non-interpolation step voltage is always higher than the previous interpolation step voltage, so that the brightness inversion of the pixel points on the display panel 400 shown in FIG. 2 can be better avoided.

[0072] In other embodiments of the present application, as shown in FIG. 6b, the difference between the embodiment shown in FIG. 6a is that the number of capacitors is different. Specifically, the driving enhancement circuit 54 further includes a second capacitor C2 and a third capacitor C3, the first terminal of the second capacitor C2 is connected to the second power supply 12, and the second terminal of the second capacitor C2 is connected to the output terminal of the second DAC 52. The first terminal of the third capacitor C3 is connected to the third power supply 13, and the second terminal of the third capacitor C3 is connected to the output terminal of the second DAC 52. Since the voltage of the third voltage signal output by the buffer 53 shown in FIG. 4 can be one of a plurality of non-interpolation step voltages, and different non-interpolation step voltages have different sizes. In the embodiment, the driving enhancement circuit 54 further includes the second capacitor C2 and the third capacitor C3, and the first terminal of the first capacitor C1 is connected to the first power supply 11, the first terminal of the second capacitor C2 is connected to the second power supply 12, and the first terminal of the third capacitor C3 is connected to the third power supply 13, that is, the first terminals of the first capacitor C1, the second capacitor C2 and the third capacitor C3 are respectively connected to different power supplies. Thus, the number of capacitors charging the output terminal of the second DAC 52 can be controlled by each power supply, so as to control the degree of charging of the output terminal of the second DAC 52, and further to realize different degrees of charging for different non-interpolation step voltages, so that the voltage of the third voltage signal output after charging and from the buffer 53 is closer to the corresponding non-interpolation step voltage, thereby improving the accuracy of brightness control of the pixel points of the display panel 400 shown in FIG. 2.

[0073] In a specific implementation, the controller in the display module 1000 shown in FIG. 1 can be used to achieve the above-mentioned example. For example, when one or more capacitors need to be charged to the output terminal of the second DAC 52, the controller controls the corresponding power supply to provide voltage to the corresponding capacitor. For example, when two capacitors need to be charged to the output terminal of the second DAC 52, the controller can send a control signal to the first power supply 11 and the second power supply 12. The first power supply 11 can receive the control signal and start providing voltage to the first capacitor C1, so that the first capacitor C1 is charged to the output terminal of the second DAC 52. Similarly, the second power supply 12 can also receive the control signal and start providing voltage to the second capacitor C2, so that the second capacitor C2 is charged to the output terminal of the second DAC 52.

[0074] In other embodiments of the present application, as shown in FIG. 8a, the difference from FIG. 6a is that the first capacitor state control circuit 541 is added based on the embodiment shown in FIG. 6a. Specifically, the driving enhancement circuit 54 further includes the first capacitor state control circuit 541, the input terminal of the first capacitor state control circuit 541 is connected with the second terminal of the first capacitor C1, the output terminal of the first capacitor state control circuit 541 is connected with the output terminal of the second DAC 52, and the first capacitor state control circuit 541 can be used to control whether the first capacitor C1 is charged to the output terminal of the second DAC 52.

[0075] In a specific implementation, when the voltage corresponding to the timing signal is a non-interpolation step voltage, the first capacitor state control circuit 541 controls the first capacitor C1 to be charged to the output terminal of the second DAC 52; when the voltage corresponding to the timing signal is an interpolation step voltage, the first capacitor state control circuit 541 controls the first capacitor C1 not to be charged to the output terminal of the second DAC 52, so that the charging of the output terminal of the second DAC 52 is more accurate. Moreover, when the voltage corresponding to the timing signal is an interpolation step voltage, the first power supply 11 can charge the first capacitor C1, and the first capacitor C1 does not need to be charged to the output terminal of the second DAC 52; when the voltage corresponding to the timing signal is a non-interpolation step voltage, the first power supply 11 has completed charging the first capacitor C1, and the first capacitor C1 can be charged to the output terminal of the second DAC 52, so that the clock cycle is not additionally occupied, and the charging speed of the pixel capacitor C shown in FIG. 2 can be improved.

[0076] Further, the first capacitor state control circuit 541 can receive low-bit digital signals in the timing signal, and determine whether the corresponding voltage is an interpolation step voltage or a non-interpolation step voltage according to the low-bit digital signals, so that when the voltage corresponding to the timing signal is a non-interpolation step voltage, the first capacitor C1 is controlled to be charged to the output terminal of the second DAC 52; when the voltage corresponding to the timing signal is an interpolation step voltage, the first capacitor C1 is controlled not to be charged to the output terminal of the second DAC 52, and at this time the first power supply 11 can charge the first capacitor C1.

[0077] In other embodiments of the present application, as shown in FIG. 8b, the difference between the embodiment shown in FIG. 8b and the embodiment shown in FIG. 8a is that the driving enhancement circuit 54 adds a second capacitor C2, a third capacitor C3, a second capacitor state control circuit 542 and a third capacitor state control circuit 543 based on the embodiment shown in FIG. 8a.

[0078] Specifically, as shown in FIG. 8b, the first end of the second capacitor C2 is connected to the first power supply 11, the second end of the second capacitor C2 is connected to the input end of the second capacitor state control circuit 542, and the output end of the second capacitor state control circuit 542 is connected to the output end of the second DAC 52. In this way, the second capacitor state control circuit 542 can control whether the second capacitor C2 charges the output end of the second DAC 52.

[0079] As shown in FIG. 8b, the first end of the third capacitor C3 is connected to the first power supply 11, the second end of the third capacitor C3 is connected to the input end of the third capacitor state control circuit 543, and the output end of the third capacitor state control circuit 543 is connected to the output end of the second DAC 52. In this way, the third capacitor state control circuit 543 can control whether the third capacitor C3 charges the output end of the second DAC 52. Therefore, in the present embodiment, when multiple capacitors are included in the driving enhancement circuit 54, each capacitor state control circuit can control whether the corresponding capacitor charges the output end of the second DAC 52.

[0080] Based on this, as shown in FIG. 9, the first capacitor state control circuit 541 includes a first switch tube M1, the first pole S1 of the first switch tube M1 is connected to the second end of the first capacitor C1, and the second pole D1 of the first switch tube M1 is connected to the output end of the second DAC 52. The control pole G1 of the first switch tube M1 can be used to receive a low-bit digital signal in a timing signal. In one example, when the low-bit digital signal is 0, the first switch tube M1 is open; when the low-bit digital signal is 1, the first switch tube M1 is closed. In another example, when the low-bit digital signal is 1, the first switch tube M1 is open; when the low-bit digital signal is 0, the first switch tube M1 is closed. When the first switch tube M1 is closed, the first switch tube M1 can connect the second end of the first capacitor C1 to the output end of the second DAC 52 and charge the output end of the second DAC 52. This scheme is simple, easy to implement, and relatively reliable.

[0081] In some cases, the second DAC 52 can receive a multi-bit digital signal in the timing signal, each switch tube can receive a one-bit digital signal, therefore, in order to achieve the ability to receive each bit of the multi-bit digital signal, in an embodiment, as shown in FIG. 9, the first capacitor state control circuit 541 can further include a second switch tube M2 and a third switch tube M3, the first pole S2 of the second switch tube M2 is connected with the second pole D1 of the first switch tube M1, the first pole S3 of the third switch tube M3 is connected with the second pole D2 of the second switch tube M2, and the second pole D3 of the third switch tube M3 is connected with the output end of the second DAC 52. That is, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are connected in series. The control pole G1 of the first switch tube M1, the control pole G2 of the second switch tube M2 and the control pole G3 of the third switch tube M3 can respectively receive one bit of the multi-bit digital signal, when each bit of the digital signal is 1, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are all closed, thereby the first capacitor C1 can charge the output end of the second DAC 52.

[0082] In another embodiment, the second DAC 52 can receive a two-bit digital signal in the timing signal, then the first capacitor state control circuit 541 can include two switch tubes, which are the first switch tube M1 and the second switch tube M2, and the first pole S2 of the second switch tube M2 is connected with the second pole D1 of the first switch tube M1, and the second pole D2 of the second switch tube M2 is connected with the output end of the second DAC 52. Thereby, when the control pole G1 of the first switch tube M1 and the control pole G2 of the second switch tube M2 receive the digital signal of 1, the first switch tube M1, the second switch tube M2 and the third switch tube M3 are all closed, thereby the first capacitor C1 can charge the output end of the second DAC 52.

[0083] It can be understood that in other embodiments, the second DAC 52 can receive a four-bit digital signal in the timing signal, then the first capacitor state control circuit 541 can include four switch tubes; the second DAC 52 can receive a five-bit digital signal in the timing signal, then the first capacitor state control circuit 541 can include five switch tubes; and so on.

[0084] In other embodiments of the present application, as shown in FIG. 10, the difference between the embodiment shown in FIG. 10 and the embodiment shown in FIG. 6b is that the driving enhancement circuit 54 adds a charging gear control circuit 544 on the basis of the embodiment shown in FIG. 6b. The second end of the first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected with the input end of the charging gear control circuit 544, and the output end of the charging gear control circuit 544 is connected with the output end of the second DAC 52. The charging gear control circuit 544 is used to control the number of capacitors charging the output end of the second DAC 52. That is, the charging gear control circuit 544 can control whether the first capacitor C1 charges the output end of the second DAC 52, control whether the second capacitor C2 charges the output end of the second DAC 52, and control whether the third capacitor C3 charges the output end of the second DAC 52. The first capacitor C1, the second capacitor C2 and the third capacitor C3 can form a capacitor array. The more capacitors charging the output end of the second DAC 52, the larger the capacitance value of the capacitor array, the faster the voltage establishment speed of the output end of the second DAC 52 and the higher the voltage. Therefore, it is convenient to select different number of capacitors charging the output end of the second DAC 52 according to the size of the voltage corresponding to the timing signal, so as to control the degree of charging the output end of the second DAC 52, and then realize different degrees of charging for different non-interpolation step voltages, so that the voltage of the third voltage signal after charging and output from the buffer 53 is closer to the theoretical value of the corresponding non-interpolation step voltage, thereby improving the accuracy of the brightness control of the pixel points of the display panel 400.

[0085] In specific implementation, the received signal of the driving enhancement circuit 54 can be the same as the received signal of the first DAC 51, for example, both are high-bit digital signals of the timing signal. The driving enhancement circuit 54 can determine the number of capacitors charging the output end of the second DAC 52 according to the size relationship between the high-bit digital signals.

[0086] As shown in FIG. 11, the charging gear control circuit 544 includes a fourth switch tube M4, a fifth switch tube M5 and a sixth switch tube M6. The first pole S4 of the fourth switch tube M4 is connected with the second end of the first capacitor C1, and the second pole D4 of the fourth switch tube M4 is connected with the output end of the second DAC 52. The first pole S5 of the fifth switch tube M5 is connected with the second end of the second capacitor C2, and the second pole D5 of the fifth switch tube M5 is connected with the output end of the second DAC 52. The first pole S6 of the sixth switch tube M6 is connected with the second end of the third capacitor C3, and the second pole D6 of the sixth switch tube M6 is connected with the output end of the second DAC 52. That is, the fourth switch tube M4 controls whether the first capacitor C1 charges the output end of the second DAC 52, the fifth switch tube M5 controls whether the second capacitor C2 charges the output end of the second DAC 52, and the sixth switch tube M6 controls whether the third capacitor C3 charges the output end of the second DAC 52. For example, when the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 are all closed, then the first capacitor C1, the second capacitor C2 and the third capacitor C3 can all charge the output end of the second DAC 52, that is, the number of capacitors charging the output end of the second DAC 52 is three. When two of the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 are closed, the number of capacitors charging the output end of the second DAC 52 is two. When one of the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 is closed, the number of capacitors charging the output end of the second DAC 52 is one.

[0087] In a specific implementation, the control poles of the fourth switch tube M4, the fifth switch tube M5 and the sixth switch tube M6 can respectively receive three bits of high-bit digital signals. When the fourth switch tube M4 receives a digital signal of 1, it is closed; when the received digital signal is 0, it is opened, so that the first capacitor C1 can charge the output end of the second DAC 52. Similarly, when the fifth switch tube M5 is closed, the second capacitor C2 can charge the output end of the second DAC 52. When the sixth switch tube M6 is closed, the third capacitor C3 can charge the output end of the second DAC 52.

[0088] It can be understood that the number of capacitors in the driving enhancement circuit 54 can be the same as the number of bits of high-bit digital signals in the timing signal received by the first DAC 51. For example, when the first DAC 51 receives a high-6-bit digital signal, the driving enhancement circuit 54 can include six capacitors. Correspondingly, the number of switch tubes in the charging gear control circuit 544 can also be the same as the number of bits of high-bit digital signals in the timing signal received by the first DAC 51, that is, also six. Thus, the charging degree of the driving enhancement circuit 54 to the output end of the second DAC 52 can be more accurately controlled.

[0089] It can be understood that, in the embodiments of the present application, the first pole of each switch tube can be a source pole, and the second pole of each switch tube can be a drain pole. In other embodiments, the first pole of each switch tube can be a drain pole, and the second pole of each switch tube can be a source pole.

[0090] In the embodiments shown in FIGS. 8b and 9, the driving enhancement circuit 54 includes the first capacitor state control circuit 541, the second capacitor state control circuit 542, and the third capacitor state control circuit 543, and does not include the charging gear control circuit 544; in the embodiments shown in FIGS. 10 and 11, the driving enhancement circuit 54 includes the charging gear control circuit 544, and does not include the first capacitor state control circuit 541, the second capacitor state control circuit 542, and the third capacitor state control circuit 543. In other embodiments of the present application, as shown in FIG. 12, the driving enhancement circuit 54 can include the first capacitor state control circuit 541, the second capacitor state control circuit 542, the third capacitor state control circuit 543, and the charging gear control circuit 544. The first pole S4 of the fourth switch tube M4 in the charging gear control circuit 544 is connected with the second end of the first capacitor C1, the second pole D4 of the fourth switch tube M4 is connected with the first pole S1 of the first switch tube M1 in the first capacitor state control circuit 541, and the second pole D3 of the switch tube M3 is connected with the output end of the second DAC 52. The first pole S5 of the fifth switch tube M5 in the charging gear control circuit 544 is connected with the second end of the second capacitor C2, the second pole D5 of the fifth switch tube M5 is connected with the first pole S1 of the first switch tube M1 in the second capacitor state control circuit 542, and the second pole D3 of the switch tube M3 in the second capacitor state control circuit 542 is connected with the output end of the second DAC 52. The first pole S6 of the sixth switch tube M6 in the charging gear control circuit 544 is connected with the second end of the first capacitor C1, the second pole D6 of the sixth switch tube M6 is connected with the first pole S1 of the first switch tube M1 in the third capacitor state control circuit 543, and the second pole D3 of the switch tube M3 in the third capacitor state control circuit 543 is connected with the output end of the second DAC 52.

[0091] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-described specific embodiments, which are only illustrative but not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A display drive circuit, characterized by comprising: include: First digital-to-analog converter (DAC), second DAC, drive enhancement circuitry, and buffer; The first DAC is used to receive the first digital signal and perform digital-to-analog conversion on the first digital signal; The second DAC has its input terminal connected to the output terminal of the first DAC, and is used to receive the second digital signal and perform analog-to-digital conversion on the second digital signal; The buffer is used to output a voltage signal, and the input terminal of the buffer is connected to the output terminal of the second DAC. The drive enhancement circuit has its output terminal connected to the output terminal of the second DAC, and is used to charge the output terminal of the second DAC.

2. The display driving circuit according to claim 1, wherein The drive enhancement circuit includes a first capacitor, a first end of which is connected to a first power supply, and a second end of which is connected to the output of the second DAC.

3. The display driving circuit according to claim 2, wherein The drive enhancement circuit further includes a second capacitor and a third capacitor. The first end of the second capacitor is used to connect to the second power supply, and the second end of the second capacitor is connected to the output terminal of the second DAC. The first end of the third capacitor is used to connect to the third power supply, and the second end of the third capacitor is connected to the output of the second DAC.

4. The display driving circuit according to claim 2, wherein The drive enhancement circuit further includes a first capacitor state control circuit. The input terminal of the first capacitor state control circuit is connected to the second terminal of the first capacitor, and the output terminal of the first capacitor state control circuit is connected to the output terminal of the second DAC. The first capacitor state control circuit is used to control whether the first capacitor charges the output terminal of the second DAC.

5. The display driving circuit according to claim 4, wherein The drive enhancement circuit further includes a second capacitor and a third capacitor, wherein a first terminal of the second capacitor is used to connect to a first power supply, and a first terminal of the third capacitor is used to connect to the first power supply. The drive enhancement circuit further includes a second capacitor state control circuit and a third capacitor state control circuit. The input terminal of the second capacitor state control circuit is connected to the second terminal of the second capacitor, and the output terminal of the second capacitor state control circuit is connected to the output terminal of the second DAC. The input terminal of the third capacitor state control circuit is connected to the second terminal of the third capacitor, and the output terminal of the third capacitor state control circuit is connected to the output terminal of the second DAC.

6. The display driving circuit according to claim 4 or 5, characterized in that, The capacitor state control circuit includes a first switching transistor, the first terminal of which is connected to the second terminal of the capacitor, and the second terminal of which is connected to the output terminal of the second DAC.

7. The display driving circuit according to claim 6, wherein The capacitor state control circuit includes a second switch and a third switch. The first terminal of the second switch is connected to the second terminal of the first switch, the first terminal of the third switch is connected to the second terminal of the second switch, and the second terminal of the third switch is connected to the output terminal of the second DAC.

8. The display driving circuit according to any one of claims 2 or 4-7, wherein, The drive enhancement circuit further includes a second capacitor and a third capacitor, wherein a first terminal of the second capacitor is used to connect to a first power supply, and a second terminal of the third capacitor is used to connect to the first power supply. The driving enhancement circuit further comprises a charging gear control circuit, second ends of the first capacitor, the second capacitor and the third capacitor are connected with an input end of the charging gear control circuit, an output end of the charging gear control circuit is connected with an output end of the second DAC, and the charging gear control circuit is used for controlling a number of the capacitors charging the output end of the second DAC.

9. The display driving circuit according to claim 8, wherein, The charging gear control circuit comprises a fourth switch tube, a fifth switch tube and a sixth switch tube, a first electrode of the fourth switch tube is connected with the second end of the first capacitor, and a second electrode of the fourth switch tube is connected with the output end of the second DAC; a first electrode of the fifth switch tube is connected with the second end of the second capacitor, and a second electrode of the fifth switch tube is connected with the output end of the second DAC; a first electrode of the sixth switch tube is connected with the second end of the third capacitor, and a second electrode of the sixth switch tube is connected with the output end of the second DAC.

10. A display driving chip, characterized in that, The display driving circuit comprises a timing control circuit and any one of the display driving circuits in claims 1-9, and the timing control circuit is electrically connected with the display driving circuit.

11. A display module, characterized by The display driving chip comprises a display panel and the display driving chip in claim 10, and the display panel is electrically connected with the display driving chip.

12. An electronic device, comprising: The display module comprises a controller and the display module in claim 11, and the controller is electrically connected with the display module.

Images