Passive device and integrated passive device

Abstract

Provided are a passive device and an integrated passive device. The passive device comprises a base substrate and an inductor located on one side of the base substrate. The inductor comprises: a first conductive layer and a second conductive layer, the first conductive layer being arranged on one side of the base substrate, the second conductive layer being arranged on the side of the first conductive layer away from the base substrate, and the first conductive layer and the second conductive layer having different thicknesses; a first insulation layer, which is arranged between the first conductive layer and the second conductive layer; and at least one first connecting portion, which runs through the first insulation layer and is electrically connected to the first conductive layer and the second conductive layer.

Description

Passive device and integrated passive device

[0001] This application claims priority to Chinese Patent Application No. 2024113578704, filed on September 26, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the field of semiconductor technology, and in particular, to a passive device and an integrated passive device. BACKGROUND

[0003] With the development of communication technology, the integration and performance requirements of integrated passive devices prepared by semiconductor processes are increasingly high. Integrated passive devices include capacitors, inductors, resistors, etc. During operation, excessive loss will affect the operation effect of the integrated passive devices. Therefore, improving the performance of the devices is a current problem to be solved. SUMMARY

[0004] The present disclosure provides a passive device, comprising:

[0005] a substrate and an inductor located on one side of the substrate, the inductor comprising:

[0006] a first conductive layer disposed on one side of the substrate;

[0007] a second conductive layer disposed on the side of the first conductive layer away from the substrate, the thickness of the first conductive layer and the second conductive layer being different;

[0008] a first insulating layer disposed between the first conductive layer and the second conductive layer;

[0009] at least one first connecting portion penetrating the first insulating layer and electrically connected to the first conductive layer and the second conductive layer.

[0010] According to an embodiment of the present disclosure, the first insulating layer is provided with at least one first via hole corresponding to the at least one first connecting portion one by one, at least a part of the first connecting portion is disposed in the first via hole;

[0011] In the direction away from the substrate, the aperture of the first via hole gradually increases.

[0012] According to an embodiment of the present disclosure, the first conductive layer is provided with at least one first blind hole corresponding to the at least one first connecting portion on the side away from the substrate, the first blind hole is in the orthographic projection of the first via hole on the substrate, a part of the first connecting portion is disposed in the first via hole, and another part of the first connecting portion is disposed in the first blind hole.

[0013] According to an embodiment of the present disclosure, an aperture variation rate of the first via is less than an aperture variation rate of the first blind via in a direction away from the substrate.

[0014] According to an embodiment of the present disclosure, the first conductive layer and the second conductive layer are arranged in a strip structure, and an aperture of the first via is positively correlated with a thickness or a strip width of the second conductive layer.

[0015] According to an embodiment of the present disclosure, the passive device further comprises a second transition layer,

[0016] The second transition layer is arranged on a sidewall of the first via, a bottom and a sidewall of the first blind via, and a side of the first insulating layer away from the substrate.

[0017] The second conductive layer covers the second transition layer.

[0018] According to an embodiment of the present disclosure, the first conductive layer and the second conductive layer are arranged in a strip structure, and a thickness of the second transition layer is positively correlated with a thickness or a strip width of the second conductive layer.

[0019] According to an embodiment of the present disclosure, the second transition layer comprises a second adhesion layer and a second seed layer, and the second seed layer is arranged on a side of the second adhesion layer away from the substrate.

[0020] According to an embodiment of the present disclosure, a projection of the first conductive layer on the substrate is a first annular pattern with a first opening, and a projection of the second conductive layer on the substrate is a second annular pattern with a second opening.

[0021] According to an embodiment of the present disclosure, a proportion of the first opening in the first annular pattern and a proportion of the second opening in the second annular pattern are both greater than one half.

[0022] According to an embodiment of the present disclosure, the first opening and the second opening are directed to different directions.

[0023] According to an embodiment of the present disclosure, the first annular pattern and the second annular pattern are symmetrical patterns.

[0024] According to an embodiment of the present disclosure, the symmetrical pattern is a circle or a polygon.

[0025] According to an embodiment of the present disclosure, an internal angle of the polygon is greater than 90°.

[0026] According to an embodiment of the present disclosure, the first annular pattern and the second annular pattern are the same in pattern and different in size.

[0027] According to an embodiment of the present disclosure, a width of the second annular pattern is greater than a width of the first annular pattern, the width being a distance between an inner ring and an outer ring of an annular pattern.

[0028] According to an embodiment of the present disclosure, at least one of the first conductive layer and the second conductive layer has a protrusion in a direction parallel to the substrate in the same layer, the protrusion connecting the first connecting portion.

[0029] According to an embodiment of the present disclosure, the passive device further comprises:

[0030] a third conductive layer disposed on a side of the second conductive layer away from the substrate;

[0031] a second insulating layer disposed between the second conductive layer and the third conductive layer;

[0032] at least one second connecting portion penetrating the second insulating layer and electrically connecting the second conductive layer and the third conductive layer;

[0033] a thickness of one of the first conductive layer, the second conductive layer and the third conductive layer is different from thicknesses of the other two.

[0034] According to an embodiment of the present disclosure, a normal projection of the third conductive layer on the substrate is a third annular pattern with a third opening, a width of the third annular pattern being greater than a width of the second annular pattern.

[0035] According to an embodiment of the present disclosure, a thickness of the second conductive layer is greater than thicknesses of the first conductive layer and the third conductive layer; or

[0036] a thickness of the first conductive layer is greater than a thickness of the second conductive layer, and the thickness of the second conductive layer is greater than a thickness of the third conductive layer.

[0037] According to an embodiment of the present disclosure, the second insulating layer is provided with at least one second via hole corresponding to the second connecting portion one by one, at least part of the second connecting portion being disposed in the second via hole;

[0038] the first connecting portion and the second connecting portion have no overlap in a normal projection on the substrate.

[0039] The present disclosure further provides an integrated passive device, comprising:

[0040] the above-mentioned passive device, and

[0041] a capacitor, the capacitor being electrically connected to the first conductive layer of the inductor.

[0042] According to an embodiment of the present disclosure, the capacitor comprises a first electrode disposed on one side of a substrate, a second electrode disposed on a side of the first electrode away from the substrate, and a first dielectric layer disposed between the first electrode and the second electrode;

[0043] The first electrode, the first dielectric layer and the second electrode at least partially overlap in the orthographic projection of the substrate;

[0044] The inductor and the capacitor are disposed on the same side of the substrate, and the first conductive layer of the inductor and the first electrode of the capacitor are disposed in the same layer and electrically connected.

[0045] According to an embodiment of the present disclosure, the thickness of the first electrode is the same as the thickness of the first conductive layer, and the thickness of the first electrode is greater than the thickness of the second electrode.

[0046] The beneficial effects of the present disclosure are to reduce the parasitic resistance of the inductor, improve the quality factor of the inductor, and at the same time avoid the phenomenon that the outermost conductive layer is prone to peeling as much as possible. BRIEF DESCRIPTION OF DRAWINGS

[0047] The accompanying drawings are used to further illustrate various embodiments and explain all various principles and advantages according to the present disclosure, in which like reference numerals refer to like elements or functionally similar elements throughout the various views, and each figure is not necessarily drawn to scale, the accompanying drawings together with the following detailed description are incorporated into the present specification and form part of the present specification.

[0048] Figure 1 shows a schematic diagram of a partial structure of an integrated passive integrated circuit.

[0049] Figure 2 shows a cross-sectional view of a passive device according to an embodiment of the present disclosure.

[0050] Figure 3 shows a cross-sectional view of a passive device according to another embodiment of the present disclosure.

[0051] Figure 4 shows a cross-sectional view of a passive device according to another embodiment of the present disclosure.

[0052] Figure 5 shows a perspective view of a passive device according to an embodiment of the present disclosure.

[0053] Figure 6 shows a perspective view of a passive device according to another embodiment of the present disclosure.

[0054] Figure 7 shows a cross-sectional view of a passive device according to an embodiment of the present disclosure.

[0055] Figure 8 shows a partial cross-sectional view of a passive device according to an embodiment of the present disclosure.

[0056] Figure 9 shows a partial cross-sectional view of a passive device according to another embodiment of the present disclosure.

[0057] Figure 10 illustrates a partial cross-sectional view of a passive device according to another embodiment of the disclosure.

[0058] Figure 11 illustrates a cross-sectional view of a passive device according to another embodiment of the disclosure.

[0059] Figure 12 illustrates a cross-sectional view of a passive device according to another embodiment of the disclosure.

[0060] Figure 13 illustrates a perspective view of a passive device according to another embodiment of the disclosure.

[0061] Figure 14 illustrates a perspective view of a passive device according to another embodiment of the disclosure.

[0062] Figure 15 illustrates a perspective view of a passive device according to another embodiment of the disclosure.

[0063] Figure 16 illustrates a perspective view of a passive device according to another embodiment of the disclosure.

[0064] Figure 17 illustrates a perspective view of a passive device according to another embodiment of the disclosure.

[0065] Figure 18 illustrates a perspective view of a passive device according to another embodiment of the disclosure.

[0066] Figure 19 illustrates a perspective view of a passive device according to another embodiment of the disclosure.

[0067] Figure 20 illustrates a cross-sectional view of an integrated passive device according to an embodiment of the disclosure.

[0068] Figure 21 illustrates a cross-sectional view of an integrated passive device according to another embodiment of the disclosure.

[0069] Figure 22 illustrates a cross-sectional view of an integrated passive device according to another embodiment of the disclosure.

[0070] Figure 23 illustrates a cross-sectional view of an integrated passive device according to another embodiment of the disclosure.

[0071] The reference signs of the components in the drawings are as follows: 1 substrate; 2 capacitor; 21 first electrode; 22 first dielectric; 23 second electrode; 3 inductor; 31 first conductive layer; 32 second conductive layer; 33 third conductive layer; 34 fourth conductive layer; first trace 302; second trace 303; 4 insulating layer; 5 connecting part; 51 first connecting part; 52 second connecting part; 53 third connecting part; 54 fourth connecting part; 511 first via hole; 521 second via hole; 501 first aperture; 502 second aperture; 512 first blind hole; 522 second blind hole; 540 first transition layer; 550 second transition layer; 560 second transition layer; 541 first adhesion layer; 542 first seed layer; 551 second adhesion layer; 552 second seed layer; 561 third adhesion layer; 562 third seed layer; 530 protruding part; 531 first protruding part; 532 second protruding part; 6 bump; 7 solder ball; 100 integrated passive circuit DETAILED DESCRIPTION

[0072] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the drawings, and descriptions of the same or similar elements can be omitted. In addition, the drawings are to be considered in the illustrative mode, and not necessarily to scale.

[0073] Although relative terms such as "upper", "lower", etc. are used herein to describe one component's relationship to another component in the drawings, these terms are used herein for convenience only and are not necessarily limiting. It is to be understood that if a device were turned over such that its "upper" portion is then an "lower" portion, then such terms as "upper" and "lower" would, of course, apply accordingly. When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure or that the structure is "directly" on the other structure, or that the structure is "indirectly" on the other structure via another structure.

[0074] The terms "one", "a", "an", "the", and "at least one" are used to mean that "zero", "one", or "more than one" of the element is present; the term "includes" and the term "comprising", and variations thereof, mean "open ended" and do not exclude additional elements; the term "first", "second", and "third", and the like, are used merely as labels, and are not meant to impose numerical requirements on their objects.

[0075] Throughout the description, the terms "vertical", "vertically" and "first direction" refer to a direction perpendicular to a plane parallel to a general plane or surface of the substrate, i.e. the Z direction or the first direction.

[0076] Throughout the description, "the outermost layer" refers to a layer farthest away from the substrate in the first direction, where the Z direction refers to the first direction. The "outermost conductive layer" refers to the conductive layer farthest away from the substrate among the plurality of conductive layers.

[0077] An integrated passive device (IPD) is a technology that integrates passive components (such as resistors, capacitors, inductors, etc.) in a circuit on a small chip. Compared with traditional discrete components, an integrated passive device has many advantages such as small size, high performance consistency, good stability, low cost, and high efficiency. Since integrated passive devices can provide excellent high-frequency characteristics and wide bandwidth, they are widely used in mobile communications, wireless networks, satellite communications, radar systems, and other fields, and are often used for filtering, matching networks, power distribution, and signal coupling in these applications.

[0078] An integrated passive device typically includes various passive components such as resistors, capacitors, and inductors, and is usually implemented using a semiconductor process to achieve high-density and high-performance passive component integration on a substrate 10. Figure 1 shows a partial structure diagram of an integrated passive integrated circuit. The passive integrated circuit includes a capacitor structure 20 and an inductor 30 on one side of the substrate 10, which are connected by conductive material filled in the via structure of the multi-layer insulating layer 40.

[0079] During operation of the integrated passive device, the conductive layer in the inductor 30 generates a parasitic resistance, which affects the quality factor (Q value) and efficiency of the inductor 30, resulting in operating losses. The higher the Q value, the smaller the loss; conversely, the lower the Q value, the greater the loss, and the greater the impact on the operating performance of the inductor 30 and the entire integrated passive device. Currently, as the integration level of integrated passive devices increases, the area of the inductor 30 becomes smaller and smaller. How to reduce the loss caused by parasitic resistance and improve the Q value of the inductor in the case of high integration is a major problem faced by the development of integrated passive devices.

[0080] The embodiments of the present disclosure provide an integrated passive device and an integrated passive circuit that can improve the quality factor of the inductor.

[0081] As shown in FIG. 2, the passive device includes a substrate 1 and an inductor 3 located on one side of the substrate 1. The inductor 3 includes a first conductive layer 31, a second conductive layer 32, a first insulating layer P1, and at least one first connecting part 51. The first conductive layer 31 is disposed on one side of the substrate 1, and the second conductive layer 32 is disposed on the side of the first conductive layer 31 away from the substrate 1. The thicknesses of the first conductive layer 31 and the second conductive layer 32 are different. The first insulating layer P1 is disposed between the first conductive layer 31 and the second conductive layer 32. The at least one first connecting part 51 penetrates the first insulating layer P1 and is electrically connected to the first conductive layer 31 and the second conductive layer 32.

[0082] In some embodiments, the first insulating layer P1 is provided with at least one first via hole 511 corresponding to the at least one first connecting part 51. At least a portion of the first connecting part 51 is disposed in the first via hole 511. In the direction away from the substrate 1, the aperture of the first via hole 511 gradually increases.

[0083] The above is described by way of example of two conductive layers. The inductor 3 includes the first conductive layer 31 and the second conductive layer 32 disposed on one side of the substrate 1, the first insulating layer P1 disposed between the first conductive layer 31 and the second conductive layer 32, the first insulating layer P1 provided with at least one first via hole 511, and the first connecting part 51 disposed in the first via hole 510 to electrically connect the first conductive layer 31 and the second conductive layer 32. However, embodiments of the present disclosure are not limited thereto. In some embodiments, the inductor 3 can also include three or more conductive layers.

[0084] As shown in FIG. 2, the inductor can also include a third conductive layer 33, a second insulating layer P2, and at least one second connecting part 52. The third conductive layer 33 is disposed on the side of the second conductive layer 32 away from the substrate 1. The second insulating layer P2 is disposed between the second conductive layer 32 and the third conductive layer 33. The at least one second connecting part 52 penetrates the second insulating layer P2 and is electrically connected to the second conductive layer 32 and the third conductive layer 33.

[0085] The thickness of one of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 can be different from the thicknesses of the other two. In some embodiments, the thickness of the third conductive layer 33 is smaller than the thicknesses of the first conductive layer 31 and the second conductive layer 32. In the process of preparing multiple film layers in sequence, the thicker the conductive layer in the subsequent process, the more likely it is to induce film layer peeling or separation. By designing the thickness of the third conductive layer 33 to be smaller than the thicknesses of the first conductive layer 31 and the second conductive layer 32, the conductive layer farthest from the substrate 1 is thinnest, preventing film layer peeling in the process of preparing multiple film layers, and improving the reliability of the inductor and the integrated passive device.

[0086] The thickness of the second conductive layer 32 and the first conductive layer 31 can be the same or different.

[0087] For example, the thickness of the second conductive layer 32 can be greater than the thickness of the first conductive layer 31 and the third conductive layer 33, as shown in FIG. 2. In this way, a multi-layer conductive structure with a thick middle and thin sides is achieved, which can reduce the parasitic resistance during operation of the inductor 3, increase the inductance Q value without changing the area of the inductor 3, and improve the operation performance of the inductor and the integrated passive device. In addition, the thickness of the outermost conductive layer is thin, which prevents the outermost conductive layer from peeling off during the preparation of the integrated passive device, thereby improving the manufacturing yield of the integrated passive device. In some embodiments, the thickness of the second conductive layer 32 is 1.5-2 times the thickness of the third conductive layer 33, as shown in FIG. 2. When the thickness of the second conductive layer 32 is less than 1.5 times the thickness of the third conductive layer 33, the effect of improving the parasitic resistance of the inductor middle layer is not obvious; when the thickness of the second conductive layer 32 is greater than 2 times the thickness of the third conductive layer 33, due to the large difference between the film layers, the multi-film inductor is prone to film peeling during preparation, which reduces the reliability between the film layers of the inductor.

[0088] For another example, the thickness of the first conductive layer 31 can be greater than the thickness of the second conductive layer 32, and the thickness of the second conductive layer 32 can be greater than the thickness of the third conductive layer 33, as shown in FIG. 3. In this way, a multi-layer conductive structure is achieved, which gradually thins from bottom to top, and the first conductive layer 31 at the bottom layer has the largest thickness, thereby reducing the parasitic resistance of the inductor 3 and the risk of film peeling, and improving the performance of the inductor 3. In some embodiments, the thickness of the first conductive layer 31 is 1.5-2 times the thickness of the second conductive layer 32. This can further improve the quality factor of the inductor while ensuring that the film layers do not peel off.

[0089] For example, as shown in FIG. 4, a four-layer inductor 3 is taken as an example, the inductor 3 is an alternating stack structure including four conductive layers and insulating layers, and the first conductive layer 31, the second conductive layer 32, the third conductive layer 33, and the fourth conductive layer 34 are sequentially and spaced apart on one side of the substrate 1. Each conductive layer is covered by an insulating layer P1, P2, P3, and P4. During the preparation of the inductor 3, the preparation sequence of the conductive layers is the first conductive layer 31, the second conductive layer 32, the third conductive layer 33, and the fourth conductive layer 34.

[0090] In some embodiments, the thickness of the fourth conductive layer 34 is less than the thickness of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33. By increasing the thickness of the conductive layer in the inductor 3, the Q value of the inductor 3 is improved while ensuring that the inductance value is increased. In addition, the outermost conductive layer of the inductor is made thin to avoid the phenomenon of outer film peeling caused by the multi-film structure.

[0091] In some embodiments, the thickness of the fourth conductive layer 34 is less than the thickness of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33, and the thickness of the third conductive layer 33 is less than the thickness of the first conductive layer 31 and the second conductive layer 32.

[0092] In some embodiments, the thickness of the first conductive layer 31, the second conductive layer 32, the third conductive layer 33 and the fourth conductive layer 34 decreases in order. That is, the thickness of the fourth conductive layer 34 is less than the thickness of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33, the thickness of the third conductive layer 33 is less than the thickness of the first conductive layer 31 and the second conductive layer 32, and the thickness of the second conductive layer 32 is less than the thickness of the first conductive layer 31. In the case of achieving a high inductance value of the multi-layer inductor 3, the inductance Q value is improved by adjusting the thickness of the conductive layer.

[0093] In actual applications, the inductance value of the inductor 3 is different, and in order to obtain a larger inductance value, the number of inductor coil layers can be increased. How to ensure the inductance Q value in the case of ensuring multiple conductive layers and high inductance value is one of the main problems that need to be faced in the process of preparing passive devices. The present application increases the thickness of the conductive layer in the inductor 3 to obtain an inductor 3 with a higher Q value.

[0094] In the embodiments of the present disclosure, the conductive layer in the inductor 3 is in a strip structure, and the strip width of the conductive layer can be different.

[0095] For example, a two-layer inductor includes a first conductive layer 31 disposed on one side of a substrate 1, a second conductive layer 32 disposed on the side of the first conductive layer 31 away from the substrate 1, the thickness of the first conductive layer 31 and the second conductive layer 32 being different, a first insulating layer P1 disposed between the first conductive layer 31 and the second conductive layer 32, and at least one first connecting part 51 penetrating the first insulating layer P1 and electrically connected with the first conductive layer 31 and the second conductive layer 32. The width of the second conductive layer 32 is greater than the width of the first conductive layer 31. By increasing the cross section of the second conductive layer 32, the parasitic resistance is reduced, and the quality factor of the inductor is further improved.

[0096] FIG. 5 shows a perspective view of a passive device according to an embodiment of the present disclosure. In order to make the drawing clear, only the conductive structure of the passive device, i.e. the conductive layer and the connecting part, is shown in the drawing.

[0097] As shown in FIG. 5, the inductor includes a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33, and a first connecting portion 51 and a second connecting portion 52 between the conductive layers. The first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 are all provided in a strip structure, and the width of the strip is the width of the conductive layer in the plane perpendicular to the extension direction of the strip. As shown in FIG. 5, the width of the third conductive layer 33 is greater than the width of the first conductive layer 31 and the second conductive layer 32. Through this arrangement, the cross-sectional area of the conductive layer can be increased without increasing the thickness of the inductor film layer as much as possible, the parasitic resistance is reduced, and the inductor quality is improved; in addition, the contact area between the outermost conductive layer (the third conductive layer 33 in this embodiment) and the lower insulating layer can be increased, and the film layer peeling in the multi-layer inductor structure can be prevented.

[0098] In some embodiments, the width of the third conductive layer 33 is 1.5-2 times the width of the second conductive layer 32. When the width of the third conductive layer 33 is less than 1.5 times the width of the second conductive layer 32, the performance of the inductor is not significantly improved; when the width of the third conductive layer 33 is greater than 2 times the width of the second conductive layer 32, the projected area of the conductive layer on the insulating layer 4 is increased, affecting the uniformity of the conductive layer and further affecting the performance of the inductor. The embodiments of the present disclosure can achieve a good balance between the above two aspects by setting the width of the third conductive layer 33 to be 1.5-2 times the width of the second conductive layer 32, so that the performance of the inductor is improved.

[0099] In other embodiments, as shown in FIG. 6, the width of the third conductive layer 33 can be greater than the width of the first conductive layer 31 and the second conductive layer 32, and the width of the second conductive layer 32 can be greater than the width of the first conductive layer 31. By increasing the cross-sectional area of the second conductive layer 32, the Q value of the inductor structure can be improved. For example, the width of the third conductive layer 33 and the width of the second conductive layer 32 are 1.5-2 times the width of the first conductive layer 31. When the width of the third conductive layer 33 and the width of the second conductive layer 32 are less than 1.5 times the width of the first conductive layer 31, the performance of the inductor is not significantly improved; when the width of the third conductive layer 33 and the width of the second conductive layer 32 are greater than 2 times the width of the first conductive layer 31, the projected area of the conductive layer on the insulating layer 4 is increased, affecting the uniformity of the conductive layer and further affecting the performance of the inductor. The embodiments of the present disclosure can achieve a good balance between the above two aspects by setting the width of the third conductive layer 33 and the width of the second conductive layer 32 to be 1.5-2 times the width of the first conductive layer 31, so that the performance of the inductor is improved.

[0100] According to embodiments of the present disclosure, the thickness of the insulating layer can be set as needed. In some embodiments, the thickness of the first insulating layer P1 is 1-2.5 times the thickness of the first conductive layer 31, preventing the distance between the first conductive layer 31 and the second conductive layer 32 from being too small, resulting in parasitic resistance and reducing the inductance quality. In other embodiments, the thickness of the second insulating layer P2 is 1-2.5 times the thickness of the second conductive layer 32, preventing the distance between the second conductive layer 32 and the third conductive layer 33 from being too small, resulting in parasitic resistance and reducing the inductance quality.

[0101] FIG. 7 shows a cross-sectional view of a passive device according to embodiments of the present disclosure.

[0102] As shown in FIG. 7, the inductor is arranged in a three-layer conductive structure, including the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33, and the first to third insulating layers P1, P2, P3 and the first to third connecting portions 51, 52, 53 therebetween.

[0103] The first conductive layer 31 is provided with at least one first blind hole 512 corresponding to at least one first connecting portion 51 on the side away from the substrate 11, the first blind hole 512 is in the orthographic projection of the substrate 1 within the orthographic projection of the first via 511, a part of the first connecting portion 51 is arranged in the first via 511, and another part of the first connecting portion 51 is arranged in the first blind hole 512. In this way, the part of the first connecting portion 51 in the first blind hole 512 is surrounded by the material of the first conductive layer 31, which can make the first connecting portion 51 better contact with the first conductive layer 31, improve the electrical connection reliability of the inductor structure, and further improve the quality factor of the inductor.

[0104] The first connecting portion 51 can be further prepared by photolithography technology after the first blind hole 512 is prepared, so as to remove the material of the surface residual insulating layer 4 of the lower conductive layer connected with the first connecting portion 51 or the formed metal oxide, improve the electrical connection performance of the first connecting portion 51 and the lower connected conductive layer, reduce the contact resistance of the via structure 5 between the conductive layers, and improve the performance of the inductor.

[0105] In some embodiments, the depth of the first blind hole 512 is less than 15% of the thickness of the first conductive layer 31. This can avoid reducing the thickness of the first conductive layer 31 at the blind hole due to the first blind hole being too deep, thereby reducing the inductance quality factor.

[0106] For example, the depth of the first blind hole 512 can be greater than 50 nm, and the oxide thickness generated on the surface of the first conductive layer 31 is relatively thin. This can effectively improve the electrical connection between the first conductive layer 31 and the second conductive layer 32, and improve the inductance quality.

[0107] For example, the first blind hole 512 can be less than 400 nm in depth. This can effectively improve the electrical connection between the first conductive layer 31 and the second conductive layer 32, improve the inductance quality, and save process time.

[0108] For example, the first blind hole 512 can be less than 100 nm in depth. In the process of the inductance structure, the oxide thickness generated on the surface of the first conductive layer 31 is thin, and the depth of the first blind hole 512 is less than 100 nm, which can improve the electrical connection performance of the conductive layer and the first connecting part 51.

[0109] For example, the first blind hole 512 can be 100-200 nm in depth. In the process of the inductance structure, it is ensured that the oxide generated on the surface of the first conductive layer 31 is removed as much as possible, and the inductance quality is improved by improving the electrical connection.

[0110] For example, the first blind hole 512 can be 200-400 nm in depth. In the process of the inductance structure, it is ensured that the oxide thickness generated on the surface of the first conductive layer 31 is completely removed, and the inductance quality is improved by improving the electrical connection.

[0111] In the embodiment of the present disclosure, as shown in FIG. 7, the inductance 3 further includes a first transition layer 540, which is arranged on the side of the first conductive layer 31 close to the substrate substrate 1, and the first conductive layer 31 covers the first transition layer 540. The first transition layer 540 includes a first adhesion layer 541 and a first seed layer 542, and the first seed layer 542 is arranged on the side of the first adhesion layer 541 away from the substrate substrate 1.

[0112] In the embodiment of the present disclosure, as shown in FIG. 7, the inductance 3 further includes a second transition layer 550, which is arranged on the sidewall of the first via hole 511, the bottom and sidewall of the first blind hole 512, and the side of the first insulating layer P1 away from the substrate substrate 1; and the second conductive layer 32 covers the second transition layer 550. The second transition layer 550 connects the second conductive layer 32 and the first connecting part 51 away from the substrate substrate 1, improves the stability of the second conductive layer 32, prevents the second conductive layer 32 from peeling off, and ensures the compactness of the prepared second conductive layer 32.

[0113] The second transition layer 550 can include a second adhesion layer 551 and a second seed layer 552, and the second seed layer 552 is arranged on the side of the second adhesion layer 551 away from the substrate substrate 1. The second adhesion layer 551 prevents the first connecting part 51 and the second conductive layer 32 from peeling off during preparation, and the second seed layer 552 is arranged on the side of the second adhesion layer 551 away from the substrate substrate 1. The prepared second conductive layer 32 is more compact, and the first connecting part 51 fills the first via hole 511 and the first blind hole 512.

[0114] In the embodiments of the present disclosure, as shown in FIG. 7, the aperture variation rate of the first via hole 511 is less than that of the first blind hole 512 in the direction away from the substrate base plate 1. For example, the aperture of the first via hole 511 and the first blind hole 512 can gradually increase in the direction away from the substrate base plate 1. This is because the uneven energy in the direction of laser beam extension in the photolithography process, such as laser etching, causes it. By making the aperture variation rate of the first via hole 511 less than that of the first blind hole 512, the electrical connection between the first connecting part 51 and the first conductive layer 31 is further improved, and the quality factor of the inductor is improved.

[0115] As shown in FIG. 7, at least one second via hole 521 corresponding to the second connecting part 52 is arranged in the second insulating layer P2, and at least a part of the second connecting part 52 is arranged in the second via hole 521; the first connecting part 51 and the second connecting part 52 do not overlap in the orthographic projection of the substrate. A part of the second connecting part 52 is arranged in the second via hole 521, and another part of the second connecting part 52 is arranged in the second blind hole 522. The arrangement of the second blind hole 522 can make the second connecting part 52 better contact with the second conductive layer 32, further improve the electrical connection reliability of the inductor structure, and further improve the quality factor of the inductor.

[0116] In the embodiments of the present disclosure, as shown in FIG. 7, the inductor further comprises a third transition layer 560, which is arranged on the side wall of the second via hole 521, the bottom and side wall of the second blind hole 522, and the side of the second insulating layer P2 away from the substrate base plate; and the third conductive layer 33 covers the third transition layer 560. The third transition layer 560 comprises a third adhesion layer 561 and a third seed layer 562, and the third seed layer 562 is arranged on the side of the third adhesion layer 561 away from the substrate base plate 1. The third transition layer 560 connects the third conductive layer 33 and the second connecting part 52 away from the substrate base plate 1, improves the stability of the third conductive layer 33, prevents the third conductive layer 33 from peeling off, and ensures the compactness of the prepared third conductive layer 33.

[0117] In some embodiments, the orthographic projection of the first connecting part 51 between the first conductive layer 31 and the second conductive layer 32 on the substrate base plate 1 and the orthographic projection of the second connecting part 52 between the second conductive layer 32 and the third conductive layer 33 on the substrate base plate 1 do not overlap. The orthographic projection of the first connecting part 51 and the second connecting part 52 on the substrate base plate 1 keeps a certain distance, which can prevent the problem of poor uniformity of the conductive layer caused by the via hole structure, and further improve the quality and performance of the inductor structure.

[0118] For example, the distance between the first connection portion 51 and the second connection portion 52 is greater than 15-50 μm. Here, the distance between the connection portions can be the distance between the geometric centers of the two. For example, the first connection portion 51 and the second connection portion 52 can be provided in a columnar structure, and the distance between the first connection portion 51 and the second connection portion 52 can be defined as the distance between the central axes of the columnar structures. In some embodiments, as shown in FIGS. 2-7, the central axes of the first connection portion 51 located between the first conductive layer 31 and the second conductive layer 32 and the second connection portion 52 located between the second conductive layer 32 and the third conductive layer 33 are parallel but do not intersect, and the distance between the first connection portion 51 and the second connection portion 52 is greater than 15-50 μm.

[0119] As shown in FIG. 8, the first via hole 511 has a slope angle a, and the first blind hole 512 has a slope angle β. Here, the slope angle refers to the angle between the sidewall of the hole and the direction parallel to the substrate (the horizontal direction in the figure). The slope angle a of the first via hole 511 can be greater than the slope angle β of the first blind hole 512. For example, the slope angle (a) of the first via hole 511 ranges from 20° to 90°. The slope angle β of the first blind hole 512 can range from 30° to 60°. This can remove as much as possible the surface insulating layer 4 material or metal oxide of the first conductive layer 31 connected to the first connection portion 51.

[0120] In some embodiments, the slope angle a of the first via hole 511 ranges from 70°±5°. The first via hole 511 can be formed by a photolithography process, such as laser drilling. When the slope angle of the first via hole 511 is less than 20°, film peeling is likely to occur. By setting the slope angle a of the first via hole 511 to range from 70°±5°, the sidewall of the via hole is as vertical as possible within the process limitations, thereby reducing the risk of film peeling as much as possible.

[0121] In FIG. 8, the surface (the upper surface in the figure) of the second transition layer 550 on the side away from the substrate 1 in the first blind hole 512 is recessed relative to the surface (the upper surface in the figure) of the first conductive layer 31 on the side away from the substrate 1. However, embodiments of the present disclosure are not limited thereto, and the former can be flush with or protrude relative to the latter.

[0122] As shown in FIG. 9, the distance between the upper surface of the second transition layer 550 and the first surface S1 of the substrate 1 is equal to the thickness of the first conductive layer 31. This removes as much as possible the oxide on the surface of the first conductive layer 31, thereby improving the electrical connection between the first conductive layer 31 and the first connection portion 51.

[0123] As shown in FIG. 10, the distance between the upper surface of the second transition layer 550 and the first surface S1 of the substrate 1 is higher than the thickness of the first conductive layer 31, which improves the uniformity of the thickness of the first conductive layer 21 as a whole while removing the oxide on the surface of the first conductive layer 31, thereby ensuring the quality of the inductor.

[0124] In the embodiments of the present disclosure, the aperture of the first via 511 is positively correlated with the thickness of the second conductive layer 32. When the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31, the size of the first via 511 increases accordingly, and the size of the first connecting portion 51 also increases, thereby preventing the second conductive layer 32 from being easily peeled off. In some embodiments, the aperture of the first via 511 can be correlated with the size of the second conductive layer 32 in other dimensions, such as length, width, etc. In some embodiments, the first conductive layer 31 and the second conductive layer 32 are provided in a strip structure, such as the strip structure shown in FIGS. 5 and 6. In this case, the aperture of the first via 511 can be positively correlated with the strip width of the second conductive layer 32. Here, the strip width refers to the width in the direction perpendicular to the extension direction of the strip.

[0125] In some embodiments, the size of the first aperture 501 of the first via 511 is 3 to 6 times the thickness of the second conductive layer 32. When the size of the first aperture 501 of the first via 511 is greater than or equal to 3 times the thickness of the second conductive layer 32, the mechanical reliability of the second conductive layer 32 is significantly improved; when the size of the first aperture 501 of the first via 511 is less than or equal to 6 times the thickness of the second conductive layer 32, the thickness uniformity of the second conductive layer 32 is ensured, and the quality factor of the inductor is reduced.

[0126] For example, as shown in FIG. 11, in the case of a three-layer inductor, when the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31 and the third conductive layer 33, the size of the first via 511 is greater than the size of the second via 521, and the difference between the size of the first aperture 501 of the first via 511 and the size of the second aperture 532 of the second via 521 is 15 to 30 μm. When the difference between the size of the first aperture 501 and the size of the second aperture 532 of the second via 521 is greater than 15 μm, the effect of preventing the second conductive layer 32 from being peeled off is significant; when the difference between the size of the first aperture 501 and the size of the second aperture 532 of the second via 521 is less than 30 μm, there is enough space to set the conductive layer, the thickness uniformity of the second conductive layer 32 is ensured, and the quality factor of the inductor 3 is improved.

[0127] For example, when the width of the second conductive layer 32 is the same as that of the first conductive layer 31, the size of the first via 511 increases as the width of the second conductive layer 32 is greater than that of the first conductive layer 31, and the size of the corresponding first connection portion 51 increases to prevent the second conductive layer 32 from easily peeling off.

[0128] For example, the size of the first aperture 501 of the first via 511 is 3 to 6 times the width of the second conductive layer 32. When the size of the first aperture 501 of the first via 511 is greater than or equal to 3 times the width of the second conductive layer 32, the mechanical reliability of the second conductive layer 32 is significantly improved. When the size of the first aperture 501 of the first via 511 is less than or equal to 6 times the width of the second conductive layer 32, the width uniformity of the second conductive layer 32 is ensured and the inductance quality factor is improved.

[0129] For example, taking a three-layer inductor, when the width of the second conductive layer 32 is greater than the widths of the first conductive layer 31 and the third conductive layer 33, the size of the first via 511 is greater than the size of the second via 521, and the difference between the first aperture 501 of the first via 511 and the second aperture 532 of the second via 521 is 15-30 μm. When the difference between the first aperture 501 and the second aperture 532 of the second via 521 is greater than or equal to 15 μm, the effect of preventing the second conductive layer 32 from peeling off is significant; when the difference between the first aperture 501 and the second aperture 532 of the second via 521 is less than or equal to 30 μm, the uniformity of the width of the second conductive layer 32 is ensured, and the quality factor of the inductor 3 is improved.

[0130] For example, as shown in FIG12, when the width of the third conductive layer 33 is greater than the width of the second conductive layer 32 and the first conductive layer 31, the size of the second via 521 is greater than the size of the first via 511 to prevent the film layer of the third conductive layer 33 from peeling off.

[0131] In other embodiments, the first conductive layer 31 and the second conductive layer 32 are configured as strip structures, and the thickness of the first transition layer 540 is positively correlated with the width of the second conductive layer 32. When the width of the second conductive layer 32 is greater than the width of the first conductive layer 31, the thickness of the second transition layer 550 is greater than the thickness of the first transition layer 540. This prevents film peeling due to the increased width of the second conductive layer 32. When the third conductive layer 33 is greater than the thickness of the second conductive layer 32 and / or the first conductive layer 31, the thickness of the third transition layer 560 is greater than the thickness of the first transition layer 540 and / or the second transition layer 550. This prevents film peeling of the third conductive layer 33 during preparation and use.

[0132] As an example, as shown in FIG. 12, the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 are arranged in a strip structure, and the thickness of the first transition layer 540 is positively correlated with the thickness of the second conductive layer 32. When the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31 and / or the third conductive layer 33, the thickness of the second transition layer 550 is greater than the thickness of the first transition layer 540 and / or the third transition layer 560, thereby preventing the problem that the second conductive layer 32 is prone to film layer peeling as the thickness of the second conductive layer 32 increases.

[0133] For example, the thickness of the second transition layer 550 is 1.25-2x10 -2 times the thickness of the second conductive layer 32, or the thickness of the third transition layer 560 is 1.25-2x10 -2 When the conductivity of the transition layer is less than the conductivity of the conductive layer, the conductive layer is controlled to be within a suitable range, ensuring stable electrical connection between the conductive layers and improving inductance performance.

[0134] The following describes a plurality of examples of inductance in a passive device of an embodiment of the present disclosure with reference to FIGS. 13-19.

[0135] As shown in FIGS. 13-19, in an embodiment of the present disclosure, the first conductive layer 31 is a first annular pattern having a first opening in the orthographic projection of the substrate 1, and the second conductive layer 32 is a second annular pattern having a second opening in the orthographic projection of the substrate 1. The proportion of the first opening in the first annular pattern and the proportion of the second opening in the second annular pattern are both greater than one-half.

[0136] In an embodiment of the present disclosure, the annular pattern described above is a symmetric pattern, and the conductive layer of the inductance is a strip structure, and the projection of the substrate is a part of the symmetric pattern. This is advantageous for the inductance to be more evenly distributed during operation, further improving inductance quality.

[0137] As an example, the center-symmetric pattern can be a circle or a polygon. When the symmetric pattern is a polygon, the internal angle of the polygon is greater than or equal to 90°. When the angle of the included angle is less than 90°, the outer edge of the conductive layer at the included angle is farther from the position of the central axis of the conductive layer, which is prone to cause the problem of poor consistency of the conductive layer, thereby affecting the performance of the inductance. By setting the internal angle of the polygon to be greater than 90°, the embodiment of the present disclosure can avoid this problem.

[0138] In FIG. 13, the orthographic projection pattern of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 on the substrate 1 is a symmetric quadrilateral with an opening, such as a rectangle or a square, and the opening occupies two adjacent sides of the quadrilateral. The wiring angle of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 is 90°; in some embodiments, the quadrilateral can be set as a round-cornered quadrilateral. The first conductive layer 31 and the second conductive layer 32 are connected by the first connecting part 51, and the second conductive layer 32 and the third conductive layer 33 are connected by the second connecting part 52; the first conductive layer 31 and the second conductive layer 32 overlap in the orthographic projection part of the substrate 1, the second conductive layer 32 and the third conductive layer 33 overlap in the orthographic projection part of the plane perpendicular to the thickness direction of the conductive layer; the first connecting part 51 and the second connecting part 52 do not overlap in the orthographic projection of the substrate 1.

[0139] Exemplarily, as shown in FIG. 14, taking three-layer inductance structure as an example, the orthographic projection pattern of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 on the substrate 1 is a symmetric quadrilateral with an opening, such as a rectangle or a square, and the opening occupies one side of the quadrilateral. The wiring angle of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 is 90°; in some embodiments, the quadrilateral can be set as a round-cornered quadrilateral. The first conductive layer 31 and the second conductive layer 32 are connected by the first connecting part 51, and the second conductive layer 32 and the third conductive layer 33 are connected by the second connecting part 52; the first conductive layer 31 and the second conductive layer 32 overlap in the orthographic projection part of the substrate 1, the second conductive layer 32 and the third conductive layer 33 overlap in the orthographic projection part of the substrate 1; the first connecting part 51 and the second connecting part 52 do not overlap in the orthographic projection of the substrate 1.

[0140] Exemplarily, as shown in FIG. 15, taking three-layer inductance structure as an example, the orthographic projection pattern of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 on the substrate 1 is a symmetric octagonal structure of seven-eighth, the wiring angle of the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 is 135°; the first conductive layer 31 and the second conductive layer 32 are connected by the first connecting part 51, and the second conductive layer 32 and the third conductive layer 33 are connected by the second connecting part 52; the first conductive layer 31 and the second conductive layer 32 overlap in the orthographic projection part of the substrate 1, the second conductive layer 32 and the third conductive layer 33 overlap in the orthographic projection part of the substrate 1; the first connecting part 51 and the second connecting part 52 do not overlap in the orthographic projection of the substrate 1.

[0141] In the embodiments of the present disclosure, the first conductive layer 31 is a ring pattern with a first opening in the orthographic projection of the substrate 1, the second conductive layer 32 is a ring pattern with a second opening in the orthographic projection of the substrate 1, and the first opening and the second opening are in different directions. Reducing the overlapping area of the orthographic projection of the first conductive layer 31 and the second conductive layer 32 on the substrate 1 reduces the parasitic resistance of the first conductive layer 31 and the second conductive layer 32 during operation, and improves the inductance quality.

[0142] For example, in a three-layer inductor 3, the first conductive layer 31 is a first ring pattern with a first opening in the orthographic projection of the substrate 1, the second conductive layer 32 is a second ring pattern with a second opening in the orthographic projection of the substrate 1, and the third conductive layer 33 is a third ring pattern with a third opening in the orthographic projection of the substrate 1. The first opening, the second opening, and the third opening are in different directions. Further reducing the overlapping area of the orthographic projection of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 on the substrate 1 reduces the parasitic resistance of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 during operation, and improves the inductance quality.

[0143] In the embodiments of the present disclosure, the first ring pattern and the second ring pattern have the same pattern and different sizes. The parasitic resistance generated between adjacent conductive layers during operation can cause the inductance value and the Q value of the inductor to decrease, thereby affecting the operation reliability of the entire integrated passive device. For example, during the operation of the filter, the parasitic resistance generated between adjacent conductive layers can cause the filter frequency band to change, and the filter cannot achieve good filtering effect. By adjusting the orthographic projection relationship of the conductive layers of the inductor 3 on the substrate 1, the parasitic resistance between the conductive layers can be reduced, and the inductance quality can be improved.

[0144] For example, the width of the second ring pattern is greater than the width of the first ring pattern, and the width is the distance between the inner ring and the outer ring of the ring pattern. As described above, by increasing the width of the second conductive layer 32 of the strip structure, the parasitic resistance during operation can be reduced, and the inductance quality can be improved.

[0145] For example, the width of the first ring pattern is greater than the width of the second ring pattern, which can also reduce the parasitic resistance of the inductor.

[0146] Further, for example, in a three-layer inductor, the width of the third ring pattern is greater than the width of the second ring pattern, which can improve the quality factor of the multi-layer inductor.

[0147] For example, the first, second and third ring patterns are the same in shape and different in size, as shown in Fig. 6. This can minimize the overlapping area of the first, second and third conductive layers 31, 32 and 33 in the orthographic projection on the substrate 1, further improving the quality factor of the three-layer inductor 3.

[0148] For example, as shown in Fig. 17, taking the three-layer inductor 3 as an example, the orthographic projection of at least one of the first and second conductive layers 31 and 32 on the substrate 1 is a part of a circle, the orthographic projection of the first conductive layer 31 on the substrate 1 has a first ring pattern, the orthographic projection of the second and third conductive layers 32 and 33 on the substrate 1 has a second ring pattern, and the orthographic projection of the third conductive layer 33 on the substrate 1 has a third ring pattern. The size of the second ring pattern is smaller than the size of the first and third ring patterns, where the size refers to the diameter of the ring. However, embodiments of the present disclosure are not limited thereto, and the size can also be the width (distance between the inner diameter and the outer diameter) of the ring or the area of the ring, etc. In this way, the problem of inductance quality degradation caused by parasitic resistance between adjacent conductive layers can be avoided.

[0149] For example, as shown in Fig. 18, taking the three-layer inductor 3 as an example, the orthographic projection of at least one of the first and second conductive layers 31 and 32 on the substrate 1 is a part of a circle, the orthographic projection of the first conductive layer 31 on the substrate 1 has a first ring pattern, the orthographic projection of the second and third conductive layers 32 and 33 on the substrate 1 has a second ring pattern, and the orthographic projection of the third conductive layer 33 on the substrate 1 has a third ring pattern. The size of the second ring pattern is larger than the size of the first and third ring patterns, which can also avoid the problem of inductance quality degradation caused by parasitic resistance between adjacent conductive layers.

[0150] For example, as shown in Fig. 19, taking the three-layer inductor 3 as an example, the orthographic projection of at least one of the first and second conductive layers 31 and 32 on the substrate 1 is a part of a circle, the orthographic projection of the first conductive layer 31 on the substrate 1 has a first ring pattern, the orthographic projection of the second and third conductive layers 32 and 33 on the substrate 1 has a second ring pattern, and the orthographic projection of the third conductive layer 33 on the substrate 1 has a third ring pattern. The size of the second ring pattern is larger than the size of the first ring pattern, and the size of the third ring pattern is larger than the size of the second ring pattern, which can also avoid the problem of inductance quality degradation caused by parasitic resistance between adjacent conductive layers.

[0151] Further, the geometric centers (e.g. the centers of the circles) of the first, second and third ring patterns can overlap or not overlap, adjusted according to actual conditions.

[0152] In the embodiments of the present disclosure, at least one of the first conductive layer 31 and the second conductive layer 32 in the same layer has a protruding portion 530 in a direction parallel to the substrate substrate 1, and the protruding portion 530 connects the first connecting portion 51. The protruding portion 53 is prepared in the same layer as the conductive layer, reducing the process, and realizing the connection of conductive layers of different sizes.

[0153] As shown in FIGS. 17-19, taking a three-layer inductor as an example, one or more of the first to third conductive layers can have a protruding portion. Taking the second conductive layer 32 as an example, it has a protruding portion in a direction parallel to the substrate substrate 1, and the protruding portion includes a first protruding portion 501 and a second protruding portion 502, the first protruding portion 501 connects the first connecting portion 51, and the second protruding portion 502 connects the second connecting portion 52. According to actual conditions, the position of the protruding portion relative to the conductive layer in the same layer is adjusted. For example, in FIGS. 17 and 19, the protruding portion of the second conductive layer 32 is outside the circular ring of the second conductive layer 32 in the substrate substrate 1; in FIG. 18, the protruding portion of the second conductive layer 32 is inside the circular ring of the second conductive layer 32 in the substrate substrate 1.

[0154] The embodiments of the present disclosure provide an integrated passive device. As shown in FIGS. 20-23, the integrated passive device includes the above-mentioned passive device and a capacitor 2, which is electrically connected to the first conductive layer 31 of the inductor 3. The connection of the capacitor 2 and the inductor 3 realizes their series connection, and constitutes a circuit of the integrated passive device, which can be used in filters, duplexers and other integrated passive devices.

[0155] The capacitor 2 can include a first electrode 21 disposed on one side of the substrate substrate 1, a second electrode 23 disposed on the side of the first electrode 21 away from the substrate substrate 1, and a first dielectric layer 22 disposed between the first electrode 21 and the second electrode 23. The first electrode 21, the first dielectric layer 22 and the second electrode 23 at least partially overlap in the projection of the substrate substrate 1. The overlapping projection area of the first electrode 21, the first dielectric layer 22 and the second electrode 23 on the substrate substrate 1 determines the capacitance of the capacitor 2.

[0156] As shown in FIG. 20, the capacitor 2 is provided with a first trace 302 and a second trace 303 on the side away from the substrate 1, the first trace 302 is in the same layer as the second conductive layer 32, and the second trace 303 is in the same layer as the third conductive layer 33. The third connecting portion 53 penetrates the insulating layer P2 to connect the second electrode 23 and the first trace 302, and the fourth connecting portion 54 penetrates the insulating layer P3 to connect the first trace 302 and the second trace 303, and the third connecting portion 53 and the fourth connecting portion 54 do not overlap in the orthographic projection of the substrate 1.

[0157] As shown in FIG. 20, the integrated passive device 100 further comprises a fifth connecting portion 55 and a sixth connecting portion 56, the fifth connecting portion 55 and the sixth connecting portion 56 penetrate the third insulating layer P3 to connect different bumps 6, the bumps 6 are connected to different solder balls 7, and the solder balls 7 are used to connect external circuits.

[0158] The first trace 302 and the second trace 303 can be used for signal connection, and can also be used to form an inductor 3 connected to the second electrode 23 of the capacitor 2.

[0159] As shown in FIG. 20, the inductor 3 and the capacitor 2 are arranged on the same side of the substrate 1, the first conductive layer 31 of the inductor 3 and the first electrode 21 of the capacitor 2 are arranged in the same layer and are electrically connected. The preparation process of this structure is simpler and saves process; the first conductive layer 31 and the first electrode 21 are prepared in the same layer on the surface of the substrate 1, the first conductive layer 31 and the first electrode 21 are more flat, the electrical connection performance is more stable, and it is beneficial to improve the reliability of the integrated passive device circuit; at the same time, the thickness of the integrated passive device 100 is reduced, and the problem of film peeling easily caused by the multi-film layer integrated passive device 100 is prevented.

[0160] In some embodiments, the thickness of the first electrode 21 is the same as the thickness of the first conductive layer 31, and the thickness of the first electrode 21 is greater than the thickness of the second electrode 22. As the thickness of the first conductive layer 31 increases, the high-temperature structural stability of the first electrode 21 is higher, which can prevent the problem of reduced consistency of the capacitor 2 caused by deformation of the first electrode 21 in high-temperature processes.

[0161] As shown in FIG. 21, the inductor 3 and the capacitor 2 are arranged on the same side of the substrate 1, the first electrode 21 and the first conductive layer 31 are arranged in the same layer, the thickness of the first electrode 21 is the same as the thickness of the first conductive layer 31, and the thickness of the first electrode 21 is greater than the thickness of the second electrode 22. The capacitor 2 is provided with a first trace 302 and a second trace 303 on the side away from the substrate 1, the first trace 302 is in the same layer as the second conductive layer 32, and the second trace 303 is in the same layer as the third conductive layer 33 and is electrically connected. The connection between the capacitor 2 and the inductor 3 can be realized through the third conductive layer 33. The bumps 6 and the solder balls 7 used for signal connection are arranged according to actual conditions.

[0162] For example, as shown in FIG. 22, the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31 and the second conductive layer 32. By increasing the thickness of the second conductive layer 32, the quality factor of the inductor is improved.

[0163] For example, as shown in FIG. 23, the thickness of the first conductive layer 31 is greater than the thickness of the second conductive layer 32, and the thickness of the second conductive layer 32 is greater than the thickness of the third conductive layer 33, further improving the quality factor of the inductor.

[0164] For example, taking the two-layer inductor 3 as an example, the inductor 3 includes the first conductive layer 31 and the second conductive layer 32. The first conductive layer 31 and the first electrode 21 are prepared in the same layer, and the thickness of the first electrode 21 is greater than the thickness of the second electrode 23. Among them, the first electrode 21 and the first conductive layer 31 can be electrically connected to realize the series connection of the capacitor 2 and the inductor 3; or the second conductive layer 32 and the first trace 302 are arranged in the same layer and electrically connected to realize the series connection of the capacitor 2 and the inductor 3.

[0165] Further, the fifth connecting part 55 and the sixth connecting part 56 penetrate through the second insulating layer P2 and connect different bumps 6 on the side of the second insulating layer P2 away from the substrate substrate. The bumps 6 are connected to the solder balls 7 for connecting external circuits. According to actual conditions, the number and position of the bumps 6 and the solder balls 7 are designed.

[0166] The disclosure embodiment provides a preparation method of an integrated passive device. The method is suitable for preparing the integrated passive device of any of the above embodiments. The steps of the preparation method are described below with reference to the above FIGS. 20-23.

[0167] Step 1601, forming the first electrode 21 and the first conductive layer 31 on one side of the substrate substrate 1.

[0168] For example, the first electrode 21 and the first conductive layer 31 pattern are formed by additive method: coating the whole photoresist on the first surface S1 side of the substrate substrate 1, then using Mask, photoresist exposure and development are performed to form a photoresist pattern corresponding to the area and thickness of the first electrode 21 and the first conductive layer 31, and then electroplating process is performed to form the first conductive layer 31 pattern on the side of the insulating layer 4 away from the substrate substrate 1.

[0169] Exemplarily, the first electrode 21 and the first conductive layer 31 pattern are formed by subtractive method: the first conductive layer 31 is formed on the substrate 1 by physical vapor deposition (PVD), a layer of photoresist is coated on the surface of the first conductive layer 31 away from the substrate 1, and the thickness of the photoresist can ensure complete coverage of the surface of the first conductive pattern material. Then, using a mask, the photoresist is exposed to light, and developed, and the photoresist above the pattern of the first electrode 21 and the first conductive layer 31 is retained, and the other areas are completely removed. The structure outside the pattern of the first electrode 21 and the first conductive layer 31 is etched, and then the photoresist above the pattern of the first electrode 21 and the first conductive layer 31 is removed, to form the pattern of the first electrode 21 and the first conductive layer 31. Compared with the previous semi-additive method process, the subtractive method process has lower precision, and the metal surface is rougher, and the roughness is also affected by the skin effect to some extent, which increases the resistance and thus the loss, so the semi-additive method process is usually used.

[0170] Further, the first adhesive layer 541 and the first seed layer 542 pattern are formed on one side of the substrate 1. The first adhesive layer 541 and the first seed layer 542 are formed on one side of the substrate 1 by electroplating, chemical plating or sputtering, and the pattern of the first adhesive layer 541 and the first seed layer 542 is formed by using a photoetching process.

[0171] Step 1602, forming the first dielectric 22 on the side of the first electrode 21 away from the substrate 1, and forming the second electrode 23 on the side of the first dielectric 22 away from the substrate 1.

[0172] Exemplarily, the first dielectric 22 is formed on the side of the first electrode 21 away from the substrate 1. The first dielectric 22 layer is deposited on the side of the first electrode 21 away from the substrate 1 by physical vapor deposition (PVD), and the pattern of the first dielectric 22 is formed by coating photoresist, exposing, developing and etching processes.

[0173] Exemplarily, the second electrode 23 is formed on the first dielectric 22. The second electrode layer 23 is formed on the side of the first dielectric 22 away from the substrate 1 by physical vapor deposition (PVD), and a layer of photoresist is coated on the surface of the second electrode layer 23 away from the substrate 1, and the thickness of the photoresist can ensure complete coverage of the surface of the first conductive pattern material. Then, using a mask, the photoresist is exposed to light, and developed, and the photoresist above the pattern of the second electrode 23 is retained, and the other areas are completely removed. The second electrode layer 23 outside the pattern of the second electrode 23 is etched, and the photoresist above the pattern of the second electrode 23 is removed, to form the pattern of the second electrode 23

[0174] Step 1603, a first insulating layer P1 is formed on the side of the second electrode 23 and the first conductive layer 31 away from the substrate 1; the first insulating layer P1 is formed on the side of the second conductive layer 32 and the first trace 302 away from the substrate 1, the first connecting part 51 connecting the second conductive layer 32 and the first conductive layer 31, and the third connecting part 53 connecting the first trace 302 and the second electrode 23.

[0175] For example, the second electrode 23 and the first conductive layer 31 are formed on the side of the first insulating layer P1 away from the substrate 1. After the whole insulating layer P0 is covered by spin coating, the pattern of the insulating layer P0 is formed by using photoresist coating, exposure, development and etching processes. The second conductive layer 32, the first trace 302, the first connecting part 51 connecting the second conductive layer 32 and the first conductive layer 31, and the third connecting part 53 connecting the first trace 302 and the second electrode 23 can be prepared by additive or subtractive method.

[0176] Further, before the second conductive layer 32, the first trace 302, the first connecting part 51 connecting the second conductive layer 32 and the first conductive layer 31, and the third connecting part 53 connecting the first trace 302 and the second electrode 23 are prepared, the second adhesive layer 551 and the second seed layer 552 can be formed on the side of the first insulating layer P1 away from the substrate 1 by electroplating, chemical plating or sputtering, and the pattern of the second adhesive layer 551 and the second seed layer 552 is formed by using photoetching process.

[0177] Step 1604, a second insulating layer P2 is formed on the side of the second conductive layer 32 and the first trace 302; the third conductive layer 33 and the second trace 303 are formed on the side of the second insulating layer P2 away from the substrate 1, the second connecting part 52 connecting the third conductive layer 33 and the second conductive layer 32, and the fourth connecting part 54 connecting the second trace 303 and the first trace 302.

[0178] For example, the second insulating layer P2 can be prepared by semiconductor photoetching process, and the preparation method of the second insulating layer P1; the third conductive layer 33, the second trace 303, the second connecting part 52 connecting the third conductive layer 33 and the second conductive layer 32, and the fourth connecting part 54 connecting the second trace 303 and the first trace 302 can be prepared by additive or subtractive method.

[0179] Further, before the third conductive layer 33, the second trace 303, the second connecting part 52 connecting the third conductive layer 33 and the second conductive layer 32, and the fourth connecting part 54 connecting the second trace 303 and the first trace 302 are prepared, the third adhesive layer 561 and the third seed layer 562 are formed on the side of the first insulating layer P1 away from the substrate 1, and the pattern of the third adhesive layer 561 and the third seed layer 562 is formed by using photoetching process.

[0180] Step 1604, a third insulating layer P3 pattern is formed on the third conductive layer 33 and the second trace 303 away from the substrate 1; the third insulating layer P3 away from the substrate 1 forms a bump 6 and a tin ball 7.

[0181] Exemplary, the third insulating layer P3 can be made by semiconductor lithography process, the same as the second insulating layer P2; the fifth connecting part 55 and the sixth connecting part 56 and the bump 6 connected by the two can be made by half method or additive method.

[0182] The integrated passive device disclosed in the application can be used in filters, baluns, duplexers, etc., and is suitable for mobile communication radio frequency front-end modules, Bluetooth and mobile hot spot fields.

[0183] The first electrode 21 and the second electrode 23 can select one or more metal materials (Au, Al, Ag, Cu, w, etc.) or other materials with good conductivity, and the thickness is generally between 0.2-2um.

[0184] The first dielectric 22 can select an insulating material such as silicon nitride (SiNx), and the thickness can be designed according to the demand of the capacitance 2 value, and the thickness can be set to be between 80-200nm.

[0185] It should be noted that the substrate 1 can be glass, ceramic, silicon or other polymer materials, and the thickness of the substrate 1 can be about 200um, which is determined according to the design requirements.

[0186] It should be noted that the thickness of the insulating layer 4 is 5-8um. The material of the insulating layer 4 can select a photosensitive insulating material, such as polyimide (PI) material; a common photosensitive photoresist can be selected, and a positive photoresist or a negative photoresist can be selected, and the thickness is determined according to the design requirements. If the thickness of the light insulating layer 4 is too small, the conductive layers on the upper and lower sides of the insulating layer 4 are easy to produce parasitic resistance in the process of device operation, which affects the operation effect of the device; if the thickness of the insulating layer 4 is too large, the film layer glass phenomenon is easy to occur in the process of preparing the integrated passive device with multiple film layers, which reduces the preparation yield of the device.

[0187] It should be noted that the thickness of the conductive layer is 3-9um. If the thickness of the conductive layer is too small, the parasitic resistance is easy to occur due to the small area of the conductive cross section, which affects the performance of the device; if the thickness of the conductive layer is too thick, the conductive layer is easy to peel off in the preparation process, which affects the reliability of the device.

[0188] It should be noted that the conductive layer and the conductive material filled in the first connecting part 51 can be Au, Al, Ag, Cu, W or other conductive materials, which are not limited here. The electrical connection of different conductive layers is realized.

[0189] It should be noted that the first adhesive layer 541, the second adhesive layer 551 and the third adhesive layer 561 in the present application can be Ti, Ti, Ta, TiN or TaN, etc., the thickness of the adhesive layer 541 ranges from 100 to 200 nm, which is not limited herein. If the thickness of the adhesive layer is too small, the adhesion of the grown conductive layer to the lower film layer is weak, and film layer peeling may occur; the thickness of the adhesive layer should not be too thick, otherwise the conductivity of the adhesive layer will be weak, which will affect the electrical connection between the conductive layers.

[0190] It should be particularly noted that the first seed layer 542, the second seed layer 552 and the third seed layer 562 in the via structure include the above-mentioned first, which can be Ti or Cu and the like, and the thickness of the seed layer ranges from 5 to 300 nm, which is not limited herein. The seed layer is used for the growth of the conductive material filled in the electroplating process.

[0191] It should be particularly noted that the drawings of the present disclosure are schematic diagrams, and in the passive device and the passive integrated device, the position of the passive device can be set according to the actual situation.

[0192] In the structure of the actual product, since the thickness of the adhesive layer and the seed layer is relatively thin, it is difficult to accurately distinguish the boundary position of the two in the microscopic characterization, such as the scanning electron microscope image and the transmission electron microscope image.

[0193] The above only describes the embodiments of the present disclosure, and does not limit the patent scope of the present disclosure, and any equivalent structure or equivalent flow transformation made by using the content of the present disclosure specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present disclosure.

Claims

1. A passive device, comprising a substrate and an inductor on one side of the substrate, the inductor comprising: a first conductive layer on one side of the substrate; a second conductive layer on a side of the first conductive layer away from the substrate, the first conductive layer and the second conductive layer having different thicknesses; a first insulating layer between the first conductive layer and the second conductive layer; and at least one first connecting portion penetrating the first insulating layer and electrically connecting the first conductive layer and the second conductive layer. 2.The passive device of claim 1, wherein: the first insulating layer has at least one first via hole corresponding to the at least one first connecting portion, at least a portion of the first connecting portion being arranged in the first via hole; and the first via hole has a gradually increasing aperture in a direction away from the substrate. 3.The passive device of claim 2, wherein: the first conductive layer has at least one first blind hole corresponding to the at least one first connecting portion on a side of the first conductive layer away from the substrate, the first blind hole being in a projection of the first via hole on the substrate, a portion of the first connecting portion being arranged in the first via hole and another portion of the first connecting portion being arranged in the first blind hole; the first via hole has a smaller aperture variation rate than the first blind hole in a direction away from the substrate; the first conductive layer and the second conductive layer are arranged in a strip structure, the aperture of the first via hole being positively correlated with the thickness or strip width of the second conductive layer; a second transition layer is further included, the second transition layer being arranged on a sidewall of the first via hole, a bottom and a sidewall of the first blind hole, and a side of the first insulating layer away from the substrate; the second conductive layer covers the second transition layer; the second transition layer has a thickness positively correlated with the thickness or strip width of the second conductive layer; the second transition layer comprises a second adhesion layer and a second seed layer, the second seed layer being arranged on a side of the second adhesion layer away from the substrate; the first conductive layer has a first annular pattern with a first opening in a projection of the substrate, and the second conductive layer has a second annular pattern with a second opening in a projection of the substrate; the first opening and the second opening each have a proportion greater than one half in the first annular pattern and the second annular pattern, respectively; the first opening and the second opening are directed in different directions; the first annular pattern and the second annular pattern are symmetrical patterns; the symmetrical pattern is a circle or a polygon; the polygon has an internal angle greater than 90°; the first annular pattern and the second annular pattern have the same pattern and different sizes; and the second annular pattern has a width greater than that of the first annular pattern, the width being a distance between an inner ring and an outer ring of the annular pattern. ​ ​ ​ ​ ​ ​ ​ 4. The passive device of claim 2, wherein, ​ 5. The passive device of claim 2, wherein, ​ 6. The passive device of claim 2, wherein, ​ ​ 7. The passive device of claim 6, wherein, ​ 8. The passive device of claim 6, wherein, ​ 9. The passive device of claim 1, wherein, ​ 10. The passive device of claim 9, wherein, ​ 11. The passive device of claim 9, wherein, ​ 12. The passive device of claim 9, wherein, ​ 13. The passive device of claim 12, wherein, ​ 14. The passive device of claim 13, wherein, ​ 15. The passive device of claim 9, wherein, ​ 16. The passive device of claim 15, wherein, ​ 17. The passive device of claim 1, wherein, At least one of the first conductive layer and the second conductive layer has a protrusion in a direction parallel to the substrate, the protrusion connecting the first connection portion.

18. The passive device of any of claims 1-17, wherein, Further comprising: a third conductive layer disposed on a side of the second conductive layer distal to the substrate; a second insulating layer disposed between the second conductive layer and the third conductive layer; at least one second connection portion electrically connecting the second conductive layer and the third conductive layer through the second insulating layer; a thickness of one of the first conductive layer, the second conductive layer, and the third conductive layer is different from thicknesses of the other two.

19. The passive device of claim 18, wherein, A third conductive layer has a third ring-like pattern with a third opening in a plan view of the substrate, a width of the third ring-like pattern being greater than a width of the second ring-like pattern.

20. The passive device of claim 18, wherein, A thickness of the second conductive layer is greater than thicknesses of the first conductive layer and the third conductive layer; or A thickness of the first conductive layer is greater than a thickness of the second conductive layer, and a thickness of the second conductive layer is greater than a thickness of the third conductive layer.

21. The passive device of claim 18, wherein, The second insulating layer has at least one second via hole corresponding to the second connection portion, at least a portion of the second connection portion being disposed in the second via hole; The first connection portion and the second connection portion do not overlap in a plan view of the substrate.

22. An integrated passive device, comprising: at least one passive device according to any one of claims 1-21; and a capacitor electrically connected to the first conductive layer of the inductor.

23. The integrated passive device of claim 22, wherein, The capacitor includes a first electrode disposed on a side of a substrate, a second electrode disposed on a side of the first electrode distal to the substrate, and a first dielectric layer disposed between the first electrode and the second electrode; The first electrode, the first dielectric layer, and the second electrode at least partially overlap in a plan view of the substrate; The inductor and the capacitor are disposed on the same side of the substrate, the first conductive layer of the inductor and the first electrode of the capacitor being disposed in the same layer and electrically connected.

24. The integrated passive device of claim 23, wherein, A thickness of the first electrode is the same as a thickness of the first conductive layer, and the thickness of the first electrode is greater than a thickness of the second electrode.

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