Optoelectronic co-packaging structure and optical module

Abstract

An optoelectronic co-packaging structure (100) and an optical module (200). The optoelectronic co-packaging structure (100) comprises a multi-layer circuit board (110), a photonic integrated circuit chip (120) and an anti-warpage member (130). The photonic integrated circuit chip (120) is provided with an optical waveguide and an optical coupling port (121) connected to the optical waveguide, the optical coupling port (121) being used for optical coupling with an external optical element of the photonic integrated circuit chip (120); the photonic integrated circuit chip (120) is flip-chip bonded onto the multi-layer circuit board (110) and is electrically connected to the multi-layer circuit board (110); and the anti-warpage member (130) is arranged in the multi-layer circuit board (110). The projection of the photonic integrated circuit chip (120) on the surface of the multi-layer circuit board (110) at least partially overlaps that of the anti-warpage member (130) on the surface of the multi-layer circuit board (110). Since the multi-layer circuit board (110) is provided with the anti-warpage member (130), packaging stress can be reduced, thereby reducing warpage deformation of the multi-layer circuit board (110) and the photonic integrated circuit chip (120), improving packaging quality and reliability.

Description

Optoelectronic co-packaging structure and optical module

[0001] The present application claims priority to the Chinese patent application No. 202422364178.6, filed on September 27, 2024, and entitled "Optoelectronic co-packaging structure and optical module", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of optical communication technology, in particular to an optoelectronic co-packaging structure and an optical module. BACKGROUND

[0003] In the existing silicon optical module, the silicon optical chip is attached to a heat sink or a printed circuit board (PCB) through glue, and then is electrically connected to the circuit board through a bonding wire. The silicon optical chip has a glue buffer between the silicon optical chip and the heat sink or the circuit board, and there is no special requirement for the thermal expansion coefficient of the heat sink or the circuit board.

[0004] With the continuous increase of the speed of the optical module, the electrical connection through the bonding wire is difficult to meet the requirement of high-frequency performance for single-channel high-speed signal transmission. Therefore, the silicon optical chip is directly flip-chip soldered on the circuit board to simplify the high-speed link and improve the high-frequency performance, so as to realize single-channel high-speed transmission of 100Gbps or even 200Gbps and above. Due to the large difference between the thermal expansion coefficient of the silicon optical chip and the thermal expansion coefficient of the circuit board, a large stress is generated during the flip-chip process due to the high reflow soldering temperature, which causes the circuit board and the silicon optical chip to warp and deform after reflow. During the production and use of the optical module, the warping amount also dynamically changes with the change of temperature. The warping and deformation of the silicon optical chip causes the optical coupling ports in the silicon optical chip to deviate from each other, and the deviation dynamically changes, which increases the difficulty of subsequent alignment and coupling with optical elements such as fiber arrays, reduces the optical coupling efficiency, and affects the stability of the optical path of the optical module. In addition, the warping and deformation of the circuit board will pull the solder joints between the circuit board and the silicon optical chip, which is easy to cause the solder joints to crack (ball cracking), and then causes the electrical connection between the silicon optical chip and the circuit board to be poor or fail, thereby reducing the packaging reliability. Practical new type content

[0005] The purpose of the present application is to provide an optoelectronic co-packaging structure and an optical module, which can effectively reduce the warping and deformation of the multilayer circuit board and the photonic integrated circuit chip, solve the problem of deviation of the optical coupling port of the photonic integrated circuit chip, improve the stability of the coupled optical path, reduce the risk of cracking of the flip-chip solder joints, and improve the packaging reliability.

[0006] Embodiments of the present application are implemented as follows:

[0007] In a first aspect, the present application provides an optoelectronic co-packaging structure, comprising:

[0008] a multilayer circuit board;

[0009] a photonic integrated circuit chip, the photonic integrated circuit chip being provided with an optical waveguide and an optical coupling port connected to the optical waveguide; the optical coupling port being configured to optically couple with an optical element outside the photonic integrated circuit chip; the photonic integrated circuit chip being flip-chip bonded to the multilayer circuit board and electrically connected to the multilayer circuit board;

[0010] a warpage-preventing member, the warpage-preventing member being embedded in the multilayer circuit board; a projection of the photonic integrated circuit chip on a surface of the multilayer circuit board and a projection of the warpage-preventing member on the surface of the multilayer circuit board at least partially overlapping.

[0011] In an optional embodiment, the projection of the warpage-preventing member on the surface of the multilayer circuit board covers the projection of the area where the photonic integrated circuit chip is flip-chip bonded on the surface of the multilayer circuit board.

[0012] In an optional embodiment, the multilayer circuit board comprises a first outer layer structure, an inner layer structure and a second outer layer structure stacked together, the first outer layer structure comprising a first surface of the multilayer circuit board, the second outer layer structure comprising a second surface of the multilayer circuit board, the first surface being opposite to the second surface; the warpage-preventing member being embedded in the inner layer structure.

[0013] In an optional embodiment, a side of the warpage-preventing member close to the first surface is spaced apart from the first surface by a first distance, a side of the warpage-preventing member close to the second surface is spaced apart from the second surface by a second distance, the first distance being equal to the second distance.

[0014] In an optional embodiment, the thickness of the warpage-preventing member is 20% to 80% of the thickness of the multilayer circuit board.

[0015] In an optional embodiment, a side of the multilayer circuit board opposite to the photonic integrated circuit chip is provided with a recess, and the warpage-preventing member is embedded in the recess.

[0016] In an optional embodiment, the warpage-preventing member and a side surface of the multilayer circuit board opposite to the photonic integrated circuit chip are flush.

[0017] In an optional embodiment, the thickness of the warpage-preventing member is 30% to 50% of the thickness of the multilayer circuit board.

[0018] In an optional embodiment, the optical coupling port is located at an edge of the photonic integrated circuit chip, and the edge where the optical coupling port is arranged extends out of the multilayer circuit board; or the optical coupling port is located at a surface of the photonic integrated circuit chip facing away from the multilayer circuit board.

[0019] In an optional embodiment, the photonic integrated circuit chip has a plurality of the optical coupling ports arranged side by side, and the plurality of the optical coupling ports are used to optically couple with an array of optical elements outside the photonic integrated circuit chip.

[0020] In an optional embodiment, the coefficient of thermal expansion of the anti-warping member matches the coefficient of thermal expansion of the photonic integrated circuit chip.

[0021] In an optional embodiment, the anti-warping member is one of an aluminum nitride ceramic sheet, a glass sheet, a silicon sheet, and a tungsten copper block.

[0022] In an optional embodiment, a surface of the anti-warping member combined with the multilayer circuit board is provided with a copper plating layer.

[0023] The thickness of the copper plating layer is less than or equal to 40 microns.

[0024] In a second aspect, the present application provides an optical module comprising the optoelectronic co-packaging structure described above.

[0025] The optical module further comprises an optical fiber array, one end of the optical fiber array optically coupling the optical coupling port of the photonic integrated circuit chip, and the other end having an optical fiber connector used to connect an external optical fiber.

[0026] The present application has the following beneficial effects:

[0027] The optoelectronic co-packaging structure provided by the present application has an anti-warping member in the multilayer circuit board soldered with the photonic integrated circuit chip, and the anti-warping member is located inside the multilayer circuit board corresponding to the soldering area, which can effectively reduce the warping deformation of the multilayer circuit board and the photonic integrated circuit chip caused by thermal stress, thereby solving the problem of deviation of the optical coupling port of the photonic integrated circuit chip, improving the stability of the coupled optical path, reducing the risk of cracking of the flip-chip soldering point, and improving the packaging reliability.

[0028] The present application also provides an optical module comprising the optoelectronic co-packaging structure described above, which can solve the problem of deviation of the optical coupling port of the photonic integrated circuit chip and the problem of cracking of the flip-chip soldering point, improve the stability of the coupled optical path, and improve the packaging reliability. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0030] FIG. 1 is a structural schematic diagram of a warped state of a conventional optoelectronic co-packaging structure;

[0031] FIG. 2 is a structural schematic diagram of an optical module provided by an embodiment of the present application;

[0032] FIG. 3 is a first structural schematic diagram of an optoelectronic co-packaging structure provided by an embodiment of the present application;

[0033] FIG. 4 is a second structural schematic diagram of an optoelectronic co-packaging structure provided by an embodiment of the present application;

[0034] FIG. 5 is a third structural schematic diagram of an optoelectronic co-packaging structure provided by an embodiment of the present application;

[0035] FIG. 6 is a structural schematic diagram of a multi-layer circuit board in the optoelectronic co-packaging structure of FIG. 5.

[0036] FIG. 1 is a structural schematic diagram of a warped state of a conventional optoelectronic co-packaging structure; DETAILED DESCRIPTION

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0038] Therefore, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application claimed, but merely represents selected embodiments of the application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the application without creative labor are within the scope of protection of the application.

[0039] It should be noted that similar reference numbers and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0040] In the description of the application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the utility model product is usually placed, and are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0041] In addition, the terms "horizontal", "vertical", etc. do not mean that the components must be absolutely horizontal or vertical, but can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0042] In the description of the application, it should also be noted that unless otherwise explicitly specified and limited, the terms "arrangement", "installation", "connection", "connection" should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements inside. For those of ordinary skill in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0043] With the light module speed increasing to single-channel 100Gbps / 200Gbps and above, the high-speed link requires more and more simple. Direct flip-chip of high-speed chips to the circuit board 10 has become an effective solution to improve bandwidth. In the existing scheme of mounting the silicon optical chip 20 to the circuit board 10, the expansion coefficient of the silicon optical chip 20 is generally below 4ppm, the expansion coefficient of the circuit board 10 is about 9ppm below the Tg (glass transition temperature point), and the expansion coefficient will rise sharply above the Tg point, and the Tg point is lower than the furnace temperature of lead-free reflow soldering. This makes the expansion of the silicon optical chip 20 lower and the expansion of the circuit board 10 larger in the reflow soldering process because the soldering temperature is higher than the Tg point. When the temperature cools down to the solder solidification temperature, this trend still remains, that is, the expansion of the silicon optical chip 20 is lower and the expansion of the circuit board 10 is larger. Finally, after cooling down to room temperature, the side of the circuit board 10 on which the silicon optical chip 20 is soldered has a small overall shrinkage due to the constraint of the silicon optical chip 20; while the free side of the circuit board 10 (i.e. the side of the circuit board 10 facing away from the silicon optical chip 20) has a large shrinkage, resulting in a warped state of the circuit board 10 as a whole, as shown in FIG. 1. The warping deformation of the circuit board 10 will pull the solder joint between the circuit board 10 and the silicon optical chip 20, which is easy to cause the solder joint to crack, and then cause the problem of poor or failed electrical connection between the silicon optical chip 20 and the circuit board 10, reducing the packaging reliability.

[0044] And when filling the bottom filling glue 30 later, the expansion coefficient of the glue is relatively large compared to the expansion coefficient of the silicon optical chip 20, and the warping deformation of the circuit board 10 is further aggravated after high-temperature solidification.

[0045] In addition, the silicon optical chip 20 has an optical coupling port array that is optically aligned with the outside, and has very strict optical alignment requirements. Due to the overall structure of the circuit board 10, the silicon optical chip 20 and the bottom filling glue 30 changing with temperature, the warping amount is also dynamically changing, causing the optical coupling ports 40 distributed on the silicon optical chip 20 to have inconsistent heights in the Z-axis, that is, not on the same horizontal plane, and dynamically changing. This will increase the difficulty of optical coupling, and directly affect the optical coupling efficiency and the stability of the optical path.

[0046] In order to overcome at least one technical defect in the prior art, the present embodiment proposes an optoelectronic co-packaging structure which can reduce the warping deformation of the multilayer circuit board, thereby reducing the risk of solder joint cracking and improving the packaging reliability. At the same time, it is beneficial to ensure that each optical coupling port is on the same height plane, reduce the coupling difficulty, and improve the optical coupling efficiency and the stability of the optical path.

[0047] In combination with FIG. 2, the embodiment of the present application provides an optical module 200, which comprises a multilayer circuit board 110, a photonic integrated circuit chip 120, a light source 230 and a fiber array 210. The photonic integrated circuit chip 120 is flip-chip bonded on the multilayer circuit board 110 and electrically connected with the multilayer circuit board 110. The light source 230 can be a laser. The photonic integrated circuit chip 120 has an array of optical coupling ports coupled with the fiber array 210 and the light source 230. One end of the fiber array 210 is optically coupled with the optical coupling ports of the photonic integrated circuit chip 120, and the other end has a fiber connector 220 for connecting an external optical fiber. It can be understood that, in some embodiments, the light source 230 can also be optically coupled with the photonic integrated circuit chip 120 through the fiber array 210.

[0048] The optical module 200 shown in FIG. 2 adopts a pluggable packaging form, and one end of the multilayer circuit board 110 has a gold finger, which can be electrically connected with an external device such as a switch or a server through the gold finger. In some embodiments, the optical module 200 can also adopt a near packaged optics (NPO) form, and can also adopt a co-packaged optics (CPO) form, and the present application does not limit the packaging form of the optical module 200. The multilayer circuit board 110 further has an electrical chip (not shown in the figure) flip-chip bonded thereon, and the electrical chip is electrically connected with the photonic integrated circuit chip 120 through the multilayer circuit board 110. The optical module 200 adopts an optoelectronic co-packaging structure of flip-chip bonding the photonic integrated circuit chip 120 and the electrical chip on the multilayer circuit board 110, which improves the high-frequency performance of the high-speed link and can achieve a higher transmission rate. The optoelectronic co-packaging structure of the optical module 200 will be described in detail below in combination with the accompanying drawings.

[0049] Please combine FIG. 3, the embodiment provides an optoelectronic co-packaging structure 100, which comprises a multilayer circuit board 110, a photonic integrated circuit chip 120 and a warpage prevention member 130. The photonic integrated circuit chip 120 is internally provided with an optical waveguide and an optical coupling port 121 connected with the optical waveguide. The optical coupling port 121 is used for optical coupling with an optical element outside the photonic integrated circuit chip 120. The photonic integrated circuit chip 120 is flip-chip bonded on the multilayer circuit board 110 and electrically connected with the multilayer circuit board 110.

[0050] The photonic integrated circuit chip 120 in the embodiment is a PIC chip (Photonic Integrated Circuit, PIC for short). The PIC chip includes but is not limited to a silicon optical chip. The photonic integrated circuit chip 120 and the multilayer circuit board 110 are respectively provided with corresponding fine bump arrays, and the bump arrays of the two are aligned and welded through a flip-chip process to form welding points 122 between the photonic integrated circuit chip 120 and the multilayer circuit board 110, thereby realizing electrical connection between the photonic integrated circuit chip 120 and the multilayer circuit board 110.

[0051] The anti-warping member 130 is arranged in the multilayer circuit board 110. The projection of the photonic integrated circuit chip 120 on the surface of the multilayer circuit board 110 and the projection of the anti-warping member 130 on the surface of the multilayer circuit board 110 at least partially overlap, which can be full overlap or partial overlap. Since the region corresponding to the photonic integrated circuit chip 120 in the multilayer circuit board 110 is provided with the anti-warping member 130, the warping deformation of the multilayer circuit board 110 and the photonic integrated circuit chip 120 caused by thermal stress can be reduced, and problems such as cracking of the welding points 122 caused by warping deformation of the multilayer circuit board 110 can be avoided, thereby improving the packaging quality and reliability. At the same time, the problem of mutual deviation of the optical coupling ports 121 of the photonic integrated circuit chip 120 is solved, the coupling difficulty is reduced, the strict optical alignment requirement of the optical coupling ports 121 can be met, and the optical coupling efficiency and the stability of the optical path are improved.

[0052] In the embodiment, the thermal expansion coefficient of the anti-warping member 130 matches the thermal expansion coefficient of the photonic integrated circuit chip 120, which can be understood as the same or similar. The thermal expansion coefficient of the anti-warping member 130 is lower than the thermal expansion coefficient of the multilayer circuit board 110, and the thermal expansion coefficient of the anti-warping member 130 is closer to the thermal expansion coefficient of the photonic integrated circuit chip 120. In this way, the problem of uneven shrinkage caused by the large difference between the thermal expansion coefficients of the multilayer circuit board 110 and the photonic integrated circuit chip 120 can be solved, and the warping deformation of the multilayer circuit board 110 and the photonic integrated circuit chip 120 can be reduced. Optionally, the anti-warping member 130 can be any one of an aluminum nitride ceramic sheet, a glass sheet, a silicon sheet, and a tungsten copper block. In the embodiment, the anti-warping member 130 is an aluminum nitride ceramic sheet, and the thermal expansion coefficient of the aluminum nitride ceramic sheet is about 4ppm, which is relatively small compared with the thermal expansion coefficient of the photonic integrated circuit chip 120. Moreover, the cost of the aluminum nitride ceramic sheet is extremely low, which is more conducive to mass production.

[0053] In this embodiment, the projection of the warpage-preventing member 130 on the surface of the multilayer circuit board 110 covers the projection on the surface of the multilayer circuit board 110 of the area where the flip-chip bonding of the photonic integrated circuit chip 120 and the multilayer circuit board 110 is performed, in other words, the position of the warpage-preventing member 130 in the multilayer circuit board 110 corresponds to the position of the flip-chip bonding area of the photonic integrated circuit chip 120 on the multilayer circuit board 110, and the warpage-preventing member 130 is larger than the flip-chip bonding area. In this way, the warpage-preventing member 130 can fully play its role, the local coefficient of thermal expansion of the position where the photonic integrated circuit chip 120 is mounted on the multilayer circuit board 110 is reduced, the matching degree of the coefficients of thermal expansion of the flip-chip bonding area of the multilayer circuit board 110 and the photonic integrated circuit chip 120 is improved, the warpage deformation amount of the multilayer circuit board 110 and the photonic integrated circuit chip 120 is reduced, the problem of the optical coupling port 121 of the photonic integrated circuit chip 120 deviating is better solved, and the risk of cracking of the flip-chip bonding point is reduced, so as to improve the stability of the coupling optical path and the packaging reliability.

[0054] The warpage-preventing member 130 is in the form of a plate or a strip. In this embodiment, the warpage-preventing member 130 adopts a flat sheet or block structure, and the multilayer circuit board 110 adopts an organic multilayer circuit board 110. The warpage-preventing member 130 with a low coefficient of thermal expansion is added to the multilayer circuit board 110 to reduce the warpage deformation of the multilayer circuit board 110 in reflow soldering. Compared with the use of a pure inorganic multilayer ceramic board, this mode has lower cost and can save cost.

[0055] In this embodiment, the warpage-preventing member 130 is embedded in the multilayer circuit board 110. For example, the warpage-preventing member 130 is completely embedded in the multilayer circuit board 110 by lamination.

[0056] Specifically, the multilayer circuit board 110 is a multilayer printed circuit board, which comprises a first outer layer structure 101, an inner layer structure 102 and a second outer layer structure 103 stacked along a thickness direction, the first outer layer structure 101 comprises a first surface 104 of the multilayer circuit board 110, the second outer layer structure 103 comprises a second surface 105 of the multilayer circuit board 110, and the first surface 104 is opposite to the second surface 105. The anti-warping member 130 is embedded in the inner layer structure 102. In the preparation process of the multilayer printed circuit board, the inner layer structure 102 can be slotted after the inner layer structure 102 is laminated with the first outer layer structure 101 or the second outer layer structure 103, the flat anti-warping member 130 is added, and the remaining outer layer structure of the multilayer circuit board 110 is laminated to embed the anti-warping member 130 in the multilayer circuit board 110 by lamination. Of course, the anti-warping member 130 can also be embedded in the multilayer circuit board 110 by other means. Optionally, the anti-warping member 130 can be fixed in the inner layer structure 102 by adhesion. In this embodiment, the surface of the anti-warping member 130 combined with the multilayer circuit board 110 is provided with a copper plating layer, and specifically, thin copper can be plated on both surfaces of the anti-warping member 130 opposite in the thickness direction of the multilayer circuit board 110, so that the anti-warping member 130 is better combined with the multilayer circuit board 110. The thickness of the copper plating layer is less than or equal to 40 microns, so as to reduce the influence on the overall thermal expansion coefficient of the anti-warping member 130.

[0057] In this embodiment, in the thickness direction of the multilayer circuit board 110, the side of the anti-warping member 130 close to the first surface 104 is spaced apart from the first surface 104 by a first distance, and the side of the anti-warping member 130 close to the second surface 105 is spaced apart from the second surface 105 by a second distance, and the first distance and the second distance are equal. In this way, the stress on both sides of the multilayer circuit board 110 is more uniform, and the overall deformation of the multilayer circuit board 110 can be further reduced. Moreover, in the preparation process of the multilayer circuit board 110, the anti-warping member 130 is arranged in the middle of the multilayer circuit board 110, which is conducive to adjusting the amount of glue used for bonding the anti-warping member 130, the process is more convenient, and is conducive to improving the bonding force between the anti-warping member 130 and the multilayer circuit board 110. Moreover, arranging the anti-warping member 130 in the middle of the multilayer circuit board 110 has less influence on the precision of the wiring layer 112 in the multilayer circuit board 110, and the position layout of the wiring layer 112 is more convenient.

[0058] Optionally, the thickness of the anti-warping member 130 is 20% to 80% of the thickness of the multi-layer circuit board 110. In this way, the overall deformation of the multi-layer circuit board 110 can be ensured to be small, and the multi-layer circuit board 110 is provided with sufficient bending resistance, and the anti-warping effect is better. At the same time, it can also ensure that the anti-warping member 130 does not occupy too much internal space of the multi-layer circuit board 110, and the influence on the wiring layer 112 in the multi-layer circuit board 110 is minimized. In this embodiment, the thickness of the anti-warping member 130 is consistent with the thickness of the internal layer structure 102, which facilitates the manufacturing of the multi-layer circuit board 110.

[0059] In combination with FIG. 4, in some embodiments, the multi-layer circuit board 110 can also serve as an interposer, and the wiring layer 112 in the multi-layer circuit board 110 can be used to realize the fan-out of the bumps on the multi-layer circuit board 110. For example, the side of the multi-layer circuit board 110 away from the photonic integrated circuit chip 120 is provided with solder balls 111, which are used to solder and electrically connect the multi-layer circuit board 110 and other substrates.

[0060] In combination with FIG. 5 and FIG. 6, in other some embodiments, the anti-warping member 130 and the multi-layer circuit board 110 can also be combined in the following way: the anti-warping member 130 is embedded in the side of the multi-layer circuit board 110 away from the photonic integrated circuit chip 120.

[0061] Specifically, the side of the multi-layer circuit board 110 away from the photonic integrated circuit chip 120 is provided with a recess 113, and the anti-warping member 130 is arranged in the recess 113. Optionally, the anti-warping member 130 is bonded to the multi-layer circuit board 110 by a glue layer 114. After the bottom wall and the side wall of the recess 113 are coated with glue, the anti-warping member 130 is bonded in the recess 113. The anti-warping member 130 can be combined and fixed with the multi-layer circuit board 110 during the manufacturing of the multi-layer circuit board 110, and can be manufactured together with the multi-layer circuit board 110 and then shipped. Alternatively, as shown in FIG. 6, the recess 113 can be reserved during the manufacturing of the multi-layer circuit board 110, and the anti-warping member 130 can be embedded in the recess 113 in the module packaging process, so that the manufacturing is more flexible. In this embodiment, the anti-warping member 130 is flush with the surface of the side of the multi-layer circuit board 110 away from the photonic integrated circuit chip 120. That is, the depth of the recess 113 is determined according to the thickness of the anti-warping member 130. In this way, the surface of the multi-layer circuit board 110 can be ensured to be flat without recesses or protrusions. In this embodiment, the surface of the anti-warping member 130 combined with the multi-layer circuit board 110 can also be provided with a copper plating layer. Specifically, a thin copper layer can be plated on the surface of the anti-warping member 130 opposite to the bottom surface of the recess 113, so that the anti-warping member 130 is better combined with the multi-layer circuit board 110. The thickness of the copper plating layer is less than or equal to 40 microns, so as to reduce the influence on the overall thermal expansion coefficient of the anti-warping member 130.

[0062] In this embodiment, the thickness of the warpage prevention member 130 is 30% to 50% of the thickness of the multilayer circuit board 110. In this way, the overall deformation of the multilayer circuit board 110 can be ensured to be small, and the warpage prevention effect is good. At the same time, it can also ensure that the warpage prevention member 130 does not occupy too much internal space of the multilayer circuit board 110, and can minimize the impact on the wiring layer 112 inside the multilayer circuit board 110.

[0063] Optionally, a bottom filling glue 140 is also arranged in the gap between the solder joints 122 between the photonic integrated circuit chip 120 and the multilayer circuit board 110. The bottom filling glue 140 plays a protective role for the electrical connection structure of the photonic integrated circuit chip 120 and the multilayer circuit board 110. At the same time, the bottom filling glue 140 plays an insulating isolation role for the plurality of solder joints 122 between the photonic integrated circuit chip 120 and the multilayer circuit board 110, preventing short circuit connection between the solder joints 122.

[0064] In the embodiments shown in FIGS. 2 and 3, the optical coupling port 121 of the photonic integrated circuit chip 120 is located at the edge of the photonic integrated circuit chip 120, and the edge provided with the optical coupling port 121 extends to the outside of the multilayer circuit board 110. That is, part of the photonic integrated circuit chip 120 extends outside the multilayer circuit board 110 and is arranged in a suspended manner. In this way, the edge with the optical coupling port 121 is not blocked by the multilayer circuit board 110, so as to facilitate alignment and coupling and fixing with the fiber array 210. In this embodiment, the projection of the photonic integrated circuit chip 120 on the surface of the multilayer circuit board 110, except for the edge end part extending outside the multilayer circuit board 110, falls within the projection of the warpage prevention member 130 on the surface of the multilayer circuit board 110.

[0065] In some other embodiments, the optical coupling port 121 can also be located on the surface of the photonic integrated circuit chip 120 away from the multilayer circuit board 110, such as a grating coupling port or a vertical coupling port. In this way, the photonic integrated circuit chip 120 does not need to be partially suspended outside the multilayer circuit board 110, and the packaging reliability is better. In this embodiment, the projection of the photonic integrated circuit chip 120 on the surface of the multilayer circuit board 110 can fall within the projection of the warpage prevention member 130 on the surface of the multilayer circuit board 110.

[0066] In the embodiments provided in the present application, the photonic integrated circuit chip 120 has a plurality of optical coupling ports 121 arranged side by side, and the plurality of optical coupling ports 121 are used for optical coupling with an optical element array outside the photonic integrated circuit chip 120. The optical element includes but is not limited to the fiber array 210, such as the fiber array 210 in the optical module 200 described above, or a light source array.

[0067] In summary, the optoelectronic co-packaging structure 100 and the optical module 200 provided in the embodiments of the present application have the following beneficial effects, including:

[0068] The photoelectric co-encapsulation structure 100 provided by the embodiment of the present application is provided with the warpage prevention member 130 matched with the photonic integrated circuit chip 120 in the multilayer circuit board 110 welded with the photonic integrated circuit chip 120, and the warpage prevention member 130 is located in the inside of the multilayer circuit board 110 corresponding to the welding area, so as to provide sufficient bending resistance for the multilayer circuit board 110, effectively reduce the warpage deformation of the multilayer circuit board 110 and the photonic integrated circuit chip 120 caused by thermal stress, thereby solving the problem of the deviation of the optical coupling port 121 of the photonic integrated circuit chip 120, reducing the coupling difficulty, improving the optical coupling efficiency and the stability of the coupled optical path. Moreover, the risk of cracking of the flip welding point is reduced, and the packaging reliability is improved. In addition, the multilayer circuit board 110 adopts the combination of the organic multilayer circuit board and the warpage prevention member 130, and the cost is lower than that of the multilayer ceramic plate, which is conducive to cost saving.

[0069] The optical module 200 provided by the embodiment of the present application includes the light array 210 and the photoelectric co-encapsulation structure 100, which can effectively solve the problem of the deviation of the optical coupling port 121 of the photonic integrated circuit chip 120, reduce the coupling difficulty, and be conducive to improving the optical coupling efficiency and the stability of the optical path. Moreover, the problem of the cracking of the welding point 122 between the multilayer circuit board 110 and the photonic integrated circuit chip 120 caused by the warpage deformation of the multilayer circuit board 110 can be solved, and the packaging quality and reliability are improved.

[0070] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An opto-electronic co-packaged structure, characterized in that, The application relates to an optoelectronic co-packaging structure. The optoelectronic co-packaging structure comprises: a multilayer circuit board; a photonic integrated circuit chip, which is internally provided with an optical waveguide and an optical coupling port connected to the optical waveguide; the optical coupling port is used for optical coupling with an optical element outside the photonic integrated circuit chip; the photonic integrated circuit chip is flip-chip bonded on the multilayer circuit board and electrically connected with the multilayer circuit board; 2. The optoelectronic co-packaged structure of claim 1, wherein, a warpage-preventing member, which is arranged in the multilayer circuit board; a projection of the photonic integrated circuit chip on the surface of the multilayer circuit board and a projection of the warpage-preventing member on the surface of the multilayer circuit board at least partially overlap.

3. The optoelectronic co-packaged structure of claim 1, wherein, The projection of the warpage-preventing member on the surface of the multilayer circuit board covers the projection of the area, where the photonic integrated circuit chip is flip-chip bonded with the multilayer circuit board, on the surface of the multilayer circuit board.

4. The optoelectronic co-packaged structure of claim 3, wherein, The multilayer circuit board comprises a first outer layer structure, an internal layer structure and a second outer layer structure which are stacked; the first outer layer structure comprises a first surface of the multilayer circuit board; the second outer layer structure comprises a second surface of the multilayer circuit board; the first surface is opposite to the second surface; the warpage-preventing member is embedded in the internal layer structure.

5. The optoelectronic co-packaged structure of claim 1, wherein, The side of the warpage-preventing member close to the first surface is spaced apart from the first surface by a first distance; the side of the warpage-preventing member close to the second surface is spaced apart from the second surface by a second distance; the first distance is equal to the second distance.

6. The optoelectronic co-packaged structure of claim 1, wherein, The thickness of the warpage-preventing member is 20% to 80% of the thickness of the multilayer circuit board.

7. The optoelectronic co-packaged structure of claim 6, wherein, The side of the multilayer circuit board away from the photonic integrated circuit chip is provided with a groove; the warpage-preventing member is arranged in the groove.

8. The optoelectronic co-packaged structure of claim 7, wherein, The surface of the side of the warpage-preventing member and the surface of the side of the multilayer circuit board away from the photonic integrated circuit chip are flush. The thickness of the warpage-preventing member is 30% to 50% of the thickness of the multilayer circuit board.

9. The optoelectronic co-packaging structure according to claim 1, wherein: the optical coupling port is located at the edge of the photonic integrated circuit chip; the edge where the optical coupling port is arranged extends to outside the multilayer circuit board; 10. The optoelectronic co-packaged structure of claim 1, wherein, or, the optical coupling port is located at the surface of the photonic integrated circuit chip away from the multilayer circuit board.

11. The optoelectronic co-packaged structure of any of claims 1-10, wherein, The photonic integrated circuit chip has a plurality of the optical coupling ports arranged side by side; the plurality of the optical coupling ports are used for optical coupling with an array of optical elements outside the photonic integrated circuit chip.

12. The optoelectronic co-packaged structure of claim 11, wherein, The warpage-preventing member has a thermal expansion coefficient matched with the thermal expansion coefficient of the photonic integrated circuit chip.

13. The optoelectronic co-packaged structure of claim 11, wherein, The warpage-preventing member is one of an aluminum nitride ceramic sheet, a glass sheet, a silicon sheet and a tungsten copper block. The surface of the warpage-preventing member combined with the multilayer circuit board is provided with a copper plating layer; 14. An optical module characterized by comprising: The thickness of the copper plating layer is less than or equal to 40 microns.

15. The optical module of claim 14, wherein, The optoelectronic co-packaging structure according to any one of claims 1 to 13. The optical module further comprises an optical fiber array; one end of the optical fiber array is optically coupled with the optical coupling port of the photonic integrated circuit chip; the other end of the optical fiber array is provided with an optical fiber connector; the optical fiber connector is used for connecting an external optical fiber.

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