Circuit and apparatus for distribution matching

Abstract

This disclosure relates to a distribution matching circuit for data transmission. The circuit comprises a first stage distribution matcher (DM) bank and a second stage DM bank, connected via a crossbar interconnect. The first stage DM bank includes a plurality of first stage distribution matchers, which perform an initial stage of distribution matching, generating output bits that are then transmitted to the second stage DM bank via the crossbar interconnect. The second stage DM bank receives these output bits and performs a second stage of distribution matching. The circuit allows for adjustable input lengths in both stages, achieving flexible rates. The second stage DM outputs sequences of different costs. This disclosure is particularly suited for optical communication systems requiring fine-grained rate flexibility and improved performance.

Description

[0001] CIRCUIT AND APPARATUS FOR DISTRIBUTION MATCHING

[0002] TECHNICAL FIELD

[0003] The present disclosure generally relates to the field of digital communications. For instance, the present disclosure provides a distribution matching circuit and apparatus, which pertains to an architecture for flexible and efficient distribution matching in high-speed data transmission systems.

[0004] BACKGROUND

[0005] In modem digital communication systems, particularly in optical transceivers, there is a constant drive to improve data transmission efficiency and reliability. One of the key techniques employed is Probabilistic Amplitude Shaping (PAS), which is often combined with channel coding and bit mapping to higher order constellations such as Quadrature Amplitude Modulation (QAM).

[0006] In PAS, a distribution matcher (DM) is typically used to control the probabilities by which different constellation points are selected (e.g., QAM symbols).

[0007] SUMMARY

[0008] In recent years, there has been growing interest in a rate-flexible distribution matcher capable of adjusting the constellation point probability with fine granularity. Such flexibility is particularly valuable in adapting to varying channel conditions or changing system requirements.

[0009] For practical applications in optical transceivers, distribution matchers with certain characteristics are highly desirable. Specifically, distribution matchers that combine low penalty (in terms of performance loss compared to theoretical limits), low complexity (for efficient hardware implementation), and flexible rate (for adaptability) are of significant interest to the industry.

[0010] The need for such distribution matchers has become particularly acute in the context of interoperable PAS for 1600G ZR+ optical transceivers, as discussed in the OIF (Optical Internetworking Forum). There is a strong interest in agreeing on a DM architecture that may be specified in a straightforward manner and that has low implementation complexity.

[0011] One approach to achieve low complexity is to use a short distribution matcher, i.e., a distribution matcher with a relatively short input length of k bits and a relatively short output length of n bits (in which k and n are positive integers). If k is small enough, such a short DM may be implemented by a look-up table (LUT) with 2krows, with a binary sequence of length n in each row. Alternatively, the distribution matcher may be specified by such a LUT and implemented by a simple algorithm that realizes the mapping specified by the LUT.

[0012] However, this approach faces challenges in achieving the required fine rate resolution. As the input length k can only be changed in steps of ±1 bit, correspondingly, the DM rate is changed by ±l / n. If the output length n is small, then the rate resolution achieved by the short distribution matcher is too coarse for many applications. Furthermore, the short distribution matcher inherently has a cost penalty dictated by n, and smaller n results in a larger penalty. These conflicting requirements - the need for short distribution matchers for low complexity, and the need for longer distribution matchers for fine rate resolution and lower penalty - present a significant challenge in distribution matcher design. Existing solutions often involve trade-offs between flexibility, complexity, and performance.

[0013] In view of the above, an objective of this disclosure is to improve distribution matching to balance the competing requirements, particularly for high-speed optical communication systems where efficiency, adaptability, and interoperability are paramount. Further objectives may include providing improved flexibility and efficiency in distribution matching of probabilistic amplitude shaping for digital communication systems.

[0014] This and other objectives are achieved by the solutions of the present disclosure, as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0015] According to the present disclosure two stages of distribution matching are concatenated, e.g., using two stages of DM banks. The overall rate may be adjusted via rates of component distribution matchers in both stages, providing a finer resolution than what a single distribution matcher alone could achieve.

[0016] According to a first aspect, the present invention provides a distribution matching circuit comprising a first stage DM bank comprising a plurality of first stage distribution matchers; and a second stage DM bank comprising a plurality of second stage distribution matchers.

[0017] The first stage DM bank and the second stage DM bank are connected via a crossbar interconnect, such that outputs of the first stage distribution matchers are connected to inputs of the second stage distribution matchers.

[0018] The crossbar interconnect may be based on any suitable crossbar structure. For instance, the crossbar may be implemented using a crossbar switch (also referred to as a cross-point switch or a matrix switch), which allows any-to-any connections between first and second stage distribution matchers. Alternatively, the crossbar interconnect may be implemented using programmable / reconfigurable interconnect array (e.g., FPGA). This is not limited in the present disclosure. In general, the second stage distribution matchers are configured to output sequences of different cost.

[0019] Each second stage distribution matcher may be configured to: combine outputs of multiple first stage distribution matchers as its input, and output a sequence based on a desired / preset symbol distribution.

[0020] The crossbar interconnect allows for a flexible and efficient connection between the two stages of DM banks, enabling each second stage distribution matcher to potentially receive inputs from all first stage distribution matchers. The two-stage structure with a crossbar interconnect allows for a finer granularity in rate adjustment compared to a single distribution matcher. The overall rate may be adjusted by changing the rates of the component distribution matchers in both stages.

[0021] In an implementation form of the first aspect, each second stage distribution matcher may be configured to receive outputs of the first-stage distribution matchers via the crossbar interconnect as inputs. Each second stage distribution matcher may be configured to receive outputs of all first-stage distribution matchers via the crossbar interconnect as inputs.

[0022] Alternatively, a subset of the first-stage distribution matchers are configured to provide valid outputs. In this case, each second stage distribution matcher may be configured to receive outputs of all of the subset of first-stage distribution matchers (that provide valid outputs) via the crossbar interconnect as inputs. For instance, if there is a first stage distribution matcher with a rate of zero (providing no output, or output of 0), then it may be seen as that the second stage distribution matcher does not receive output from this first stage distribution matcher.

[0023] The number of first stage distribution matchers providing valid outputs to the second stage distribution matchers are not limited, as long as each second stage distribution matcher is configured to receive outputs of multiple first stage distribution matchers.

[0024] In a further implementation form of the first aspect, at least two of the plurality of first stage distribution matchers have a rate between 0 and 1. A rate between 0 and 1 (exclusive) may be referred to as a non-trivial rate. A rate being 0 or 1 may be referred to as a trivial rate. By having a minimum of two first stage distribution matchers with non-trivial rates, it allows for fine-grained control over the overall shaping effect, as these non-trivial rates contribute to the nuanced probability distribution.

[0025] In a further implementation form of the first aspect, there are more than two distribution matchers in the first stage DM bank, and only two of the plurality of first stage distribution matchers have a rate between 0 and 1. This configuration balances complexity and flexibility, allowing for nuanced shaping while keeping most distribution matchers with trivial rates of 0 or 1.

[0026] In a further implementation form of the first aspect, the second stage distribution matchers are configured to output sequences of different cost. The cost are usually related to energy, complexity, or other factors associated with transmitting or processing symbols (or constellation points). For instance, the cost may be an energy cost (power consumption). For example, a signal point with real value + / - 1.0 has a power proportional to 1.0A2=l and a signal point with real value + / - 3.0 has a power proportional to 3.0A2=9.0. The desired probabilities may be chosen based on the energy cost, e.g., using higher energy cost points least likely than lower energy cost points. This allows for more sophisticated shaping of the output distribution, as different cost sequences may be used to achieve desired probabilistic properties.

[0027] In a further implementation form of the first aspect, the second stage distribution matchers are configured to order the output sequences by cost. Second stage distribution matchers may be configured to order the output sequences with the same cost lexicographically .

[0028] In a further implementation form of the first aspect, the plurality of second stage distribution matchers share a same rate. This simplifies implementation and control, as all second stage distribution matchers may be identical.

[0029] In a further implementation form of the first aspect, the first stage distribution matchers and / or the second stage distribution matchers have adjustable input lengths to achieve a flexible rate of the distribution matching circuit.

[0030] In a further implementation form of the first aspect, the first stage distribution matchers and / or the second stage distribution matchers are binary distribution matchers. Binary distribution matchers are often simpler to implement and can be more efficient in terms of hardware resources.

[0031] In a further implementation form of the first aspect, the first stage distribution matchers and / or the second stage distribution matchers are binary multi-composition distribution matchers (MCDM). MCDMs can achieve better penalty at same output length than constant composition distribution matchers (CCDMs).

[0032] In a further implementation form of the first aspect, the first stage distribution matchers and / or the second stage distribution matchers are binary distribution matchers specified by lookup tables. LUT-based implementation can be relatively fast and efficient, especially for shorter input / output lengths. In a further implementation form of the first aspect, the first stage distribution matchers and / or the second stage distribution matchers are non-binary distribution matchers. Non-binary distribution matchers can directly shape larger symbol alphabets, potentially improving efficiency for certain modulation schemes.

[0033] In a further implementation form of the first aspect, the first stage distribution matchers are ordered accordingly from rates of zero, over rates between zero to one, to rates of one from a most significant bit to a least significant bit of the second stage DM bank. This ordering can simplify control and potentially improve shaping performance by applying more sophisticated shaping to more significant bits.

[0034] According to a second aspect, the present invention provides an apparatus for data transmission, comprising: a distribution matching circuit according to the first aspect; a demultiplexer configured to receive an input bitstream and distribute the input bitstream to the first stage distribution matchers of the distribution matching circuit; and a multiplexer configured to receive outputs from the second stage distribution matchers of the distribution matching circuit and combine the outputs into an output bitstream.

[0035] According to a third aspect, the present invention provides a method for distribution matching applied to a distribution matching circuit. The distribution matching circuit comprises: a first stage DM bank comprising a plurality of first stage distribution matchers; and a second stage DM bank comprising a plurality of second stage distribution matchers, wherein the first stage DM bank and the second stage DM bank are connected via a crossbar interconnect.

[0036] The method comprises: performing, by the first stage distribution matchers, a first stage of distribution matching to generate first stage output bits; transmitting the first stage output bits to the second stage distribution matchers via the crossbar interconnect; and performing, by the second stage distribution matchers, a second stage of distribution matching of the first stage output bits to generate second stage output bits.

[0037] The implementation forms, optional features, and effects described for the first aspect may be applied, mutatis mutandis, to the second and third aspects of this disclosure.

[0038] A fourth aspect of the present disclosure provides a computer program product comprising a program code for performing the method according to the third aspect or any implementation form thereof, when executed on a computer.

[0039] A fifth aspect of the present disclosure provides a computer-readable medium comprising instructions which, when executed by a computer, cause the computer to carry out the method according to the third aspect or any implementation form thereof.

[0040] A sixth aspect of the present disclosure provides a chipset comprising instructions which, when executed by the chipset, cause the chipset to carry out the method according to the third aspect or any implementation form thereof.

[0041] It has to be noted that all apparatus, devices, elements, units, and means described in the present application could be implemented in software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity, which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities may be implemented in respective software or hardware elements, or any kind of combination thereof.

[0042] BRIEF DESCRIPTION OF DRAWINGS

[0043] The above-described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which:

[0044] FIG. 1 shows a schematic diagram of a distribution matching circuit;

[0045] FIG. 2 shows an example of an operation performed by a distribution matcher;

[0046] FIG. 3 shows examples of different ordering schemes for output sequences in a distribution matcher;

[0047] FIG. 4 shows a schematic diagram of a data transmission apparatus;

[0048] FIG. 5 shows a diagram of a method of this disclosure;

[0049] FIG. 6 shows an example of a distribution matching circuit;

[0050] FIG. 7 shows a further example of a distribution matching circuit;

[0051] FIG. 8 shows an example of a rate 58 / 64 distribution matching circuit;

[0052] FIG. 9 shows an example of a rate 53 / 64 distribution matching circuit;

[0053] FIG. 10 shows an example of a rate 36 / 64 distribution matching circuit;

[0054] FIG. 11 shows an alternative schematic diagram of a distribution matching circuit; and

[0055] FIG. 12 shows an application scenario of this disclosure.

[0056] DETAILED DESCRIPTION OF EMBODIMENTS

[0057] FIG. 1 shows a schematic diagram of a distribution matching circuit 10. The distribution matching circuit comprises a first stage DM bank 11 and a second stage DM bank 12. The first stage DM bank 11 comprises a plurality of first stage distribution matchers 111, 112, 113. The second stage DM bank comprising a plurality of second stage distribution matchers 121, 122, 123. The first stage DM bank 11 and the second stage DM bank 12 are connected via a crossbar interconnect 13. In this way, outputs of the first stage distribution matchers 111, 112, 113 are connected to inputs of the second stage distribution matchers 121, 122, 123. Each distribution matcher 111 , 112, 113, 121, 122, 123 may be configured to have a rate of 0, a rate between 0 and 1 (exclusive), or a rate of 1. A rate of 0 or 1 may be referred to as a trivial rate. A rate between 0 and 1 (exclusive) may be referred to as a non-trivial rate.

[0058] Each second stage distribution matcher (121, 122, 123) is configured to receive outputs of the first stage distribution matchers via the crossbar interconnect (13) as inputs.

[0059] For instance, if all the first stage distribution matchers are configured to provide valid outputs (i.e., there is no first stage distribution matcher with a rate of zero), then each second stage distribution matcher is configured to receive outputs of all the first stage distribution matchers via the crossbar interconnect (13) as inputs.

[0060] Alternatively, a subset of the first stage distribution matchers may be configured to provide valid outputs; the remaining one or more first stage distribution matchers have a rate of zero (i.e., providing no (valid) output). In this case, each second stage distribution matcher is configured to receive outputs of all of the subset of first stage distribution matchers.

[0061] The first stage DM bank 11 may be designed such that at least two of the first stage distribution matchers have a non-trivial rate. This allows for fine-grained control over the overall shaping effect. For instance, there may be more than two distribution matchers in the first stage DM bank 11, but only two of them have a non-trivial rate, with the remaining first stage distribution matcher(s) operating at rates of either 0 or 1.

[0062] The plurality of second stage distribution matchers may share the same rate, simplifying implementation and control. That is, each and every second stage distribution matcher may have the same rate.

[0063] The first stage distribution matchers 111, 112, 113 and / or the second stage distribution matchers 121, 122, 123 can have adjustable input lengths to achieve a flexible rate of the distribution matching circuit 10. For instance, the input length of each first stage distribution matcher 111, 112, 113 and / or each second stage distribution matchers 121, 122, 123 may be programmable, e.g., for different application scenarios where different rates are desired.

[0064] Each distribution matcher, whether in the first stage or second stage, may be implemented based on various designs. For example, they may be constructed using look-up tables (LUTs), where each LUT indexes all possible sequences of a certain length. The possible sequences may be ordered by their cost. The cost could be determined by factors such as the number of '1's in the sequence or other application-specific criteria.

[0065] One or more first stages 111, 112, 113 may be a binary distribution matcher, optionally as a binary multi-composition distribution matcher (MCDM). Optionally, one or more second stages 121, 122, 123 may be a binary distribution matcher, optionally as a binary MCDM.

[0066] An MCDM refers to a type of distribution matcher that generates output sequences with different symbol compositions from a given alphabet. In this context, composition specifically refers to the number of occurrences of each symbol in a sequence. For example, in a binary alphabet {0,1 }, the composition (#0=2, #1=3) indicates that the sequence contains exactly two zeros and three ones. The MCDM is adapted to output sequences with various compositions, allowing for more flexibility in generating sequences.

[0067] For example, in a binary alphabet {0,1 }, a simple MCDM may output sequences of both compositions (#0=3, #1=0) and (#0=2, #1=1), meaning that it can generate sequences such as 000, 100, 010, and 001, thereby covering multiple compositions. By using multiple compositions, the MCDM ensures more granular control over output symbol distributions, allowing for rate flexibility and reduced complexity compared to a simpler distribution matcher, such as a CCDM, which produce sequences with only a single, fixed composition.

[0068] One or more first stages distribution matchers 111, 112, 113 may be a non-binary distribution matcher. One or more second stages distribution matchers 121, 122, 123 may be a non-binary distribution matcher.

[0069] It is possible that the binary distribution matchers and the non-binary distribution matchers are mixedly used in the circuit 10. For instance, in a single circuit, the first stage distribution matchers 111, 112, 113 may be non-binary distribution matchers, and the second stage distribution matcher 121, 122, 123 may be binary distribution matchers.

[0070] The first stage distribution matchers and / or the second stage distribution matchers may be configured to select less costly sequences more frequently, which can improve the performance of the circuit (compared to using a single distribution matcher).

[0071] This two-stage architecture with crossbar interconnect disclosed in this disclosure allows for finer granularity in rate adjustment compared to a single distribution matcher. Each distribution matcher may be implemented with a relatively short input length, since each of them take a portion of an input bitstream. This lowers implementation complexity due to the use of short distribution matchers.

[0072] The overall rate may be changed by fine granularity of l / (noxni), where no, m are the output lengths of the distribution matcher in the first and second stage respectively. For instance, the overall rate can be increased or decreased by l / ( noxm) via increasing or decreasing the input length of one distribution matcher in the first stage by 1 bit.

[0073] FIG. 2 shows an example of an operation performed by a distribution matcher.

[0074] This figure demonstrates the concept of mapping input bit sequences to output sequences based on a cost metric.

[0075] In this example, a binary distribution matcher that outputs Os and 1 s is considered. The left side shows input bit sequences <b2 bl b0>, where b2 is the most significant bit (MSB) and bO is the least significant bit (LSB). The right side shows an ordered list of output sequences, arranged according to their cost.

[0076] The cost in this example could represent, for example, the number of 1 s (which may correspond to the energy required to transmit a particular sequence). Therefore, the sequences are ordered from those with the most Os (lowest cost) to those with the most Is (highest cost).

[0077] Each distribution matcher in the first stage DM bank 11 and the second stage DM bank 12 of our invention may be configured to perform distribution matching as illustrated in FIG. 2. The length of inputs, the length of outputs, the specific mapping and cost ordering may vary according to the requirements of each stage and an overall system requirement (e.g., the end-to-end rate, k / n).

[0078] For instance, a distribution matcher in the first stage DM bank 11 may use only a subset of this mapping. It could, for example, fix the MSB (b2) to 0 and encode only <bl b0> into the lower half of the list. This would correspond to a distribution matcher with an input length k = 2, an output length n = 3, and a rate R = 2 / 3. Similarly, a distribution matcher in the second stage DM bank 12 may use this type of mapping to further shape the probability distribution of its output sequences. The crossbar interconnect 13 allows the outputs of the first stage distribution matchers to be flexibly routed to the inputs of the second stage distribution matchers, enabling sophisticated shaping of the overall output distribution.

[0079] The flexibility of this disclosure allows for fine-grained control over the output probabilities. For example, using the lower half of the list (with b2 fixed to 0) results in output probabilities of Pr(0) = 3 / 4 and Pr(l) = 1 / 4. If instead using only the lowest quarter of the list (fixing <b2 bl> to 00), output probabilities are obtained as Pr(0) = 5 / 6 and Pr(l) = 1 / 6.

[0080] FIG. 3 illustrates examples of different ordering schemes for output sequences in a distribution matcher, which may be applied to distribution matchers in both the first and second stages of this disclosure.

[0081] The left side of FIG. 3 shows a lexicographic ordering of 4-bit sequences, while the right side shows a balanced running sum ordering of the same sequences. Both orderings are arranged from top to bottom with increasing cost, where the cost is determined by the number of 1 s in each sequence.

[0082] In the lexicographic ordering, sequences with the same cost (same number of Is) are ordered alphabetically. The balanced running sum ordering uses a different criterion. This alternative ordering aims to ensure that the statistics of the different output bits are as similar as possible, which can lead to improved shaping performance in certain applications.

[0083] A comparison of the two ordering schemes reveals their different characteristics. For instance, if the first 8 rows are selected, the occurrences of 1 in the 4 bit positions are 1333 for lexicographic ordering and 2332 for balanced ordering. This demonstrates how the balanced ordering achieves a more uniform distribution of 1 s across the bit positions.

[0084] The choice between these ordering schemes, or potentially other criteria, allows for flexibility in the distribution matcher design. Depending on the specific requirements of the application scenarios, one ordering scheme may be preferable over the other. This flexibility in sequence ordering, combined with the two-stage architecture and crossbar interconnect of this disclosure, enables sophisticated and finely tuned probability shaping for various communication scenarios. For instance, lexicographic ordering results in a simpler distribution, but for certain high-performance applications, the balanced running sum ordering may provide a more uniform distribution of ‘ 1 s’ across bit positions, improving overall system efficiency.

[0085] FIG. 4 shows a schematic diagram of a data transmission apparatus 40 of this disclosure.

[0086] The apparatus 40 comprises a distribution matching circuit 10 disclosed according to this disclosure, which may be built based on FIG. 1-3.

[0087] At the input side of the distribution matching circuit, the apparatus includes a demultiplexer (DEMUX) 41. This DEMUX 41 is configured to receive an input bitstream (e.g., with a length of k). The DEMUX 41 is configured to distribute input bits of the input bitstream among the multiple first stage distribution matchers in the first stage DM bank 11. The distribution of bits by the DEMUX 41 may be determined based on the specific rates and configurations of the individual first stage distribution matchers. In this way, a first stage distribution matcher is configured to receive a portion of the input bits. The input bitstream can remain relatively long while the input length of each first stage distribution matcher can be relatively short. In this way, the complexity can be reduced while the fine-grained control can be achieved. After the input bits are processed through the two-stage distribution matching circuit, the shaped output bits from the second stage DM bank 12 are fed into a multiplexer (MUX) 42 comprised in the apparatus 40. The MUX 42 is positioned at the output side of the distribution matching circuit. Its function is to combine the outputs from all the second stage distribution matchers 121, 122, ..., 123 into a single output bitstream (with a length of n).

[0088] In operation, the apparatus receives an input bitstream at the DEMUX 41. The DEMUX distributes these bits to the first stage distribution matchers, which perform initial distribution matching. The outputs of the first stage distribution matchers are then routed through the crossbar interconnect 13 to the second stage distribution matchers, where further distribution matching is performed. Finally, the MUX 42 is configured to combine the outputs of the second stage distribution matchers into a single output bitstream.

[0089] This configuration allows the distribution matching circuit to be efficiently integrated into a larger data transmission system. The DEMUX 41 enables the circuit to accept a single input stream and appropriately distribute it across the first stage distribution matchers, while the MUX 42 consolidates the shaped output from the second stage distribution matchers into a single output stream suitable for further processing or transmission.

[0090] FIG. 5 illustrates a diagram of a method 500 of this disclosure. The method is applied to a distribution matching circuit 10 built based on FIG. 1-3, and comprises the following steps.

[0091] Step 501: performing, by the first stage distribution matchers 111, 112, 113, a first stage of distribution matching to generate first stage output bits.

[0092] Step 502: transmitting, by the first stage distribution matchers 111, 112, 113, the first stage output bits to the second stage distribution matchers 121, 122, 123 via the crossbar interconnect 13.

[0093] Step 503: performing 503, by the second stage distribution matchers 121, 122, 123, a second stage of distribution matching of the first stage output bits to generate second stage output bits.

[0094] The steps of the method 500 may share the same optional features of the circuit 10 introduced above in FIG. 1-3. The method 500 may also be applied to the apparatus 40 accordingly, when the circuit 10 is incorporated in the apparatus 40.

[0095] FIG. 6 shows an example of a distribution matching circuit.

[0096] In this example, binary multi-composition distribution matchers (MCDMs) are used in the second stage. The first stage may use arbitrary distribution matchers.

[0097] In the first stage DM bank, the distribution matchers are arranged in a specific order from the most significant bit (MSB) to the least significant bit (LSB) of the input to the second stage DM bank. The first stage distribution matchers are ordered as follows from MSB to LSB: distribution matchers with rate 0, followed by distribution matchers with non-trivial rates between 0 and 1 (7?fc<_!, / ?„), and finally distribution matchers with rate 1.

[0098] It is noted that in practical implementations, distribution matchers with rate 0 may be omitted from the circuit, as they produce a constant zero output. Distribution matchers with rate 1 in the first stage may be replaced by direct circuit lines, as they pass their input directly to their output without modification. The first stage DM bank and / or second stage DM bank in this figure can incorporate multi-composition distribution matchers (MCDMs). MCDMs are configured to output sequences of different cost.

[0099] The use of MCDMs enables the circuit to achieve finer control over the output probability distribution. This can lead to improved shaping performance compared to simpler binary distribution matchers, while still maintaining reasonable implementation complexity.

[0100] The crossbar interconnect between the first and second stages ensures that each MCDM in the second stage has access to the outputs of all first stage distribution matchers. This flexible routing allows the circuit to adapt to various shaping requirements and achieve a wide range of output distributions.

[0101] FIG. 7 shows a further example of a distribution matching circuit.

[0102] In FIG. 7, the first stage distribution matchers are non-binary distribution matchers, for instance, quaternary distribution matchers. The second stage distribution matchers are binary distribution matchers. Note that the example in FIG. 6 where the second stage distribution matchers being MCDMs can also be applied to this example.

[0103] In general, non-binary distribution matchers (with non-binary output) may be used in the first stage and / or in the second stage. The following Table 1 shows a binary representation of an output symbol and its cost by a non-binary distribution matcher (e.g., quaternary distribution matcher).

[0104] Table 1

[0105] It is noted that while the symbols could have a binary representation, their costs cannot be represented by a simple binary cost structure. For instance, cost(b) = 2 is different from cost(c) = 3, whereas in a binary cost structure, it would typically have cost(01) = cost(0) + cost(l) = cost(10). This discrepancy highlights the need for non-binary distribution matchers in such scenarios.

[0106] FIG. 7 depicts two quaternary distribution matchers (labelled as "Quaternary DM #0" and "Quaternary DM #1 ") in the first stage. The outputs of these quaternary distribution matchers are converted to binary representations as follows:

[0107] Quaternary DM #0 outputs are converted to bits b()’0. bg±, b°0, b^' '.

[0108] Quaternary DM #1 outputs are converted to bits b'!0, bg±, bjo. bj .

[0109] This conversion allows the non-binary distribution matchers outputs to interface with the crossbar interconnect, which then feeds the binary outputs into the second stage distribution matchers.

[0110] The use of non-binary distribution matchers allows the circuit to handle more complex cost structures and symbol alphabets, providing improved flexibility and potentially improved shaping performance in scenarios where simple binary cost structures are insufficient. FIG. 8-10 shows various examples of a distribution matching circuit for different rates. In FIG. 8-10, a scheme of rate k / n (end- to-end) is used for the distribution matching circuit, in which k denotes the length of input bits, and n denotes the length of output bits.

[0111] FIG. 8 shows an example of a distribution matching circuit with rate 58 / 64. In this example, there is:

[0112] • no DM of rate 0 in the first stage;

[0113] • 1 DM of rate 3 / 8 in the first stage;

[0114] • 1 DM of rate 7 / 8 in the first stage;

[0115] • 6 DMs of rate 8 / 8=1 in the first stage.

[0116] In this example, the input bitstream with length 58 is distributed by a demultiplexer (DEMUX) as short DM inputs with a length of 3, 7, 6, 8, 8, 8, 8, 8, 8 respectively among the first stage distribution matchers. The crossbar interconnect has a 8x8 structure. Each second stage distribution matcher receives 8 bits from the first stage DM bank via the crossbar interconnect as input and produces 8 bits as output. The outputs of the second stage distribution matchers are then combined by a multiplexer (MUX) to produce a 64-bit output stream.

[0117] A rate-1 distribution matcher in the first stage may be configured to pass its input directly to its output without modification. Therefore, a first stage distribution matcher with rate 1 may be replaced by a direct line in the circuit as shown in FIG. 8. However, a distribution matcher in the second stage is configured to combine outputs from multiple first stage distribution matchers and output a sequence based on a desired symbol distribution. Thus, the second stage distribution matcher, even with a rate of 8 / 8, cannot be replaced by a direct line.

[0118] FIG. 9 shows an example of a distribution matching circuit with rate 53 / 64. In this example, there is:

[0119] • 1 DM of rate 0 in the first stage;

[0120] • 1 DM of rate 6 / 8 in the first stage;

[0121] • 1 DM of rate 7 / 8 in the first stage;

[0122] • 5 DMs of rate 8 / 8=1 in the first stage.

[0123] Since a rate-0 distribution matcher provides no output (or provides a constant output of 0), it may be omitted in the circuit.

[0124] The DEMUX in this case distributes 53 input bits among the first stage distribution matchers. The crossbar interconnect now has a 7x8 structure, reflecting the fact that one first stage distribution matcher has a rate of 0 and thus produces no output. Each second stage distribution matcher receives 7 bits as input.

[0125] FIG. 10 shows an example of a distribution matching circuit with rate 36 / 64. In this example, there is:

[0126] • 3 DMs of rate 0 in the first stage (not shown);

[0127] • 1 DM of rate 6 / 8 in the first stage;

[0128] • 1 DM of rate 6 / 8 in the first stage;

[0129] • 3 DMs of rate 8 / 8=1 in the first stage.

[0130] The DEMUX in this case distributes 36 input bits, and the crossbar interconnect has a 5x8 structure. Each second stage distribution matcher receives 5 bits as input.

[0131] In all the three examples, the second stage comprises eight distribution matchers, each producing 8 output bits. The MUX combines these to form the 64-bit output. It is further noted that the number of distribution matchers in each stage, the input lengths, and output lengths of each distribution matcher shown in FIG. 8-10 are for illustration purposes only.

[0132] FIG. 8-10 show the flexibility of this disclosure in achieving different overall rates (or end-to-end rates) by adjusting the rates and number of active distribution matchers in the first stage. The crossbar interconnect adapts accordingly, which ensures that all outputs from the first stage DMs are provided to all second stage distribution matchers. By adjusting the rates of individual first stage distribution matchers and the number of active distribution matchers, a wide range of overall rates can be achieved.

[0133] FIG. 11 shows an alternative schematic diagram of a distribution matching circuit. This example presents a serialized implementation of a two-stage distribution matching process, which is alternative to FIG. 1.

[0134] FIG. 11 shows a distribution matching circuit comprising three buffers and two distribution matchers, operating in a sequential manner. In this example, only one distribution matcher at each stage is used.

[0135] The process begins with a 1st Buffer, which receives kdm input bits. This buffer has nl states and is designed to dispense between 0 and no bits, depending on its current state.

[0136] In the next stage, the bits dispensed by the 1 st buffer are encoded either with rate 0, or by a rate adaptive distribution matcher supporting input lengths 1 ...,no-l, or copied to the output with rate 1, depending on the state.

[0137] A second buffer is filled with no bits at each step column by column. Note that encoding with rate 0 corresponds to writing an all zero column to the 2nd buffer. After kdm input bits are processed and the second buffer is filled, the second DM stage reads the buffer in no steps row by row. After no steps, the second buffer is empty. The second buffer implements the crossbar structure, or achieves the function of a crossbar structure.

[0138] The output of the second distribution matcher is then written to a third buffer.

[0139] This serialized approach can reduced hardware complexity. Since by reusing one distribution matcher for both stages, this implementation can potentially reduce the hardware resources and the overall chip area.

[0140] However, this sequential implementation may have lower throughput compared to a fully parallel implementation as in FIG. 1, as the sequential implementation processes data sequentially rather than simultaneously. The choice between this sequential implementation and the parallel implementation in FIG. 1 may depend on the specific requirements of the application, balancing factors such as hardware resources, power consumption, and required data rates.

[0141] FIG. 12 shows an application scenario of this disclosure.

[0142] FIG. 12 shows a high-level block diagram of an optical communications system. The distribution matching circuit 10 disclosed above may be applied in this system as illustrated in FIG. 12. The distribution matching circuit 10 is positioned in the transmission chain. This circuit implements the two-stage distribution matching process with crossbar interconnect as described in previous figures.

[0143] Following the distribution matching circuit, there is a Forward Error Correction (FEC) encoder. The shaped output from the distribution matcher circuit 10 is fed into this FEC encoder to add error correction capabilities to the transmitted data. After FEC encoding, the data passes through a bit mapper. This component maps the encoded and shaped bits onto constellation points of a higher-order modulation scheme, such as Quadrature Amplitude Modulation (QAM).

[0144] The mapped symbols are then sent to a Digital-to-Analog Converter (DAC), which converts the digital symbols into analog signals suitable for transmission.

[0145] Finally, the analog signals are fed into an optical modulator, which modulates the optical carrier with the shaped, encoded, and mapped data for transmission over an optical fiber.

[0146] The fine granularity of rate adjustment achieved by the two-stage architecture enables precise control over the spectral efficiency of the transmission, which is crucial for optimizing performance in varying channel conditions.

[0147] The low-complexity implementation of using relatively short distribution matchers, especially when using look-up table (LUT) based distribution matchers, allows for efficient hardware realization, which is important for high-speed optical transceivers.

[0148] By using the disclosed distribution matching circuit, the optical transceiver can achieve the probabilistic amplitude shaping required for advanced modulation schemes while maintaining the flexibility and efficiency needed for next-generation optical communication standards like OIF 1600 ZR+.

[0149] In general, this disclosure provides a distribution matching circuit for data transmission. The circuit comprises a first stage DM bank and a second stage DM bank, connected via a crossbar interconnect. The first stage DM bank includes a plurality of first stage distribution matchers, which perform an initial stage of distribution matching, generating output bits that are then transmitted to the second stage DM bank via the crossbar interconnect. The second stage DM bank receives these output bits and performs a second stage of distribution matching. The circuit allows for adjustable input lengths in both stages, achieving flexible rates.

[0150] It is noted that the distribution matching circuit of this disclosure may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors.

[0151] This disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed subject matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. For example, the user-defined code indicated by the data request may comprise a series of executable binaries and / or commands. A single element or another unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

CLAIMS1. A distribution matching circuit (10) comprising: a first stage distribution matcher, DM, bank (11) comprising a plurality of first stage distribution matchers (111, 112, 113); and a second stage DM bank comprising a plurality of second stage distribution matchers (121, 122, 123); wherein the first stage DM bank (11) and the second stage DM bank (12) are connected via a crossbar interconnect (13), such that outputs of the first stage distribution matchers (111, 112, 113) are connected to inputs of the second stage distribution matchers (121, 122, 123).

2. The distribution matching circuit (10) according to claim 1, wherein each second stage distribution matcher (121, 122, 123) is configured to receive outputs of the first stage distribution matchers (111, 112, 113) via the crossbar interconnect (13) as inputs.

3. The distribution matching circuit (10) according to claim 1 or 2, wherein at least two of the plurality of first stage distribution matchers (111, 112, 113) have a rate between 0 and 1.

4. The distribution matching circuit (10) according to any one of claims 1 to 3, wherein there are more than two distribution matchers in the first stage DM bank (11), and only two of the plurality of first stage distribution matchers (111, 112, 113) have a rate between 0 and 1.

5. The distribution matching circuit (10) according to any one of claims 1 to 4, wherein the second stage distribution matchers (121, 122, 123) are configured to output sequences of different cost.

6. The distribution matching circuit (10) according to claim 5, wherein the second stage distribution matchers (121, 122, 123) are configured to order the output sequences by cost.

7. The distribution matching circuit (10) according to any one of claims 1 to 6, wherein plurality of second stage distribution matchers (121, 122, 123) share a same rate.

8. The distribution matching circuit (10) according to any one of claims 1 to 7, wherein the first stage distribution matchers (111, 112, 113) and / or the second stage distribution matchers (121, 122, 123) have adjustable input lengths to achieve a flexible rate of the distribution matching circuit (10).

9. The distribution matching circuit (10) according to any one of claims 1 to 8, wherein the first stage distribution matchers (111, 112, 113) and / or the second stage distribution matchers (121, 122, 123) are binary distribution matchers.

10. The distribution matching circuit (10) according to any one of claims 1 to 9, wherein the first stage distribution matchers (111, 112, 113) and / or the second stage distribution matchers (121, 122, 123) are binary multi-composition distribution matchers.

11. The distribution matching circuit (10) according to any one of claims 1 to 10, wherein the first stage distribution matchers (111, 112, 113) and / or the second stage distribution matchers (121, 122, 123) are binary distribution matchers specified by lookup tables.

12. The distribution matching circuit (10) according to any one of claims 1 to 11, wherein the first stage distribution matchers (111, 112, 113) and / or the second stage distribution matchers (121, 122, 123) are non-binary distribution matchers.

13. The distribution matching circuit (10) according to any one of claims 1 to 12, wherein the first stage distribution matchers (111, 112, 113) are ordered accordingly from rates of zero, overrates between zero to one, to rates of one from a most significant bit to a least significant bit of the second stage DM bank (12).

14. An apparatus (40) for data transmission, comprising: a distribution matching circuit (10) according to any one of claims 1 to 13; a demultiplexer (41) configured to receive an input bitstream and distribute the input bitstream to the first stage distribution matchers (111, 112, 113) of the distribution matching circuit (10); and a multiplexer (42) configured to receive outputs from the second stage distribution matchers (121, 122, 123) of the distribution matching circuit (10) and combine the outputs into an output bitstream.

15. A method (500) for distribution matching applied to a distribution matching circuit (10), wherein the distribution matching circuit (10) comprises: a first stage distribution matcher, DM, bank (11) comprising a plurality of first stage distribution matchers (111, 112, 113); and a second stage DM bank (12) comprising a plurality of second stage distribution matchers (121, 122, 123), wherein the first stage DM bank (11) and the second stage DM bank (12) are connected via a crossbar interconnect (13), wherein the method comprises: performing (501), by the first stage distribution matchers (111, 112, 113), a first stage of distribution matching to generate first stage output bits; transmitting (502) the first stage output bits to the second stage distribution matchers (121, 122, 123) via the crossbar interconnect (13); and performing (503), by the second stage distribution matchers (121, 122, 123), a second stage of distribution matching of the first stage output bits to generate second stage output bits.

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