Integrated circuit comprising communication interface for communication between plurality of semiconductor dies and electronic device comprising same

Abstract

A processing chip according to the present embodiment may comprise: a first die; a second die; and a communication interface including a main band interface for data communication between the first die and the second die, and a sideband interface for controlling the main band interface. The communication interface may be configured to perform data communication between the first die and the second die through the main band interface while the main band interface is in an active mode for data communication. The communication interface may be configured to transmit data through the sideband interface on the basis of identifying the data to be transmitted from the first die to the second die while the main band interface is in a sleep mode different from the active mode.

Description

An integrated circuit including a communication interface for communication between a plurality of semiconductor dies and an electronic device including the same

[0001] The present disclosure relates to an integrated circuit comprising a communication interface for communication between a plurality of semiconductor dies and an electronic device comprising said integrated circuit.

[0002] A System on a Chip (SOC) is an electronic component in which circuits performing different functions are integrated. As the number of functions supported by the electronic device containing the SOC increases, the complexity of the circuits integrated within the SOC may increase.

[0003] The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. None of the foregoing shall be claimed as prior art related to the present disclosure, nor shall it be used to determine prior art.

[0004] According to one embodiment, a processing chip component may include a communication interface comprising a first die, a second die, a mainband interface for data communication between the first die and the second die, and a sideband interface for controlling the mainband interface. The communication interface may be configured to perform the data communication between the first die and the second die through the mainband interface while the mainband interface is in an active mode for data communication. The communication interface may be configured to transmit the data through the sideband interface based on identifying the data to be transmitted from the first die to the second die while the mainband interface is in a sleep mode different from the active mode.

[0005] According to one embodiment, a processing chip component may include a communication interface comprising a first die, a second die, a mainband interface for data communication between the second die and the second die, and a sideband interface for controlling the mainband interface. The communication interface may be configured to identify a request to transmit data from a first circuit of the first die to a second circuit of the second die through the communication interface. The communication interface may be configured to transmit the data from the first circuit of the first die to the second circuit of the second die through the mainband interface based on identifying the request while the mainband interface is in an active mode. The communication interface may be configured to identify the size of the data based on identifying the request while the mainband interface is in a sleep mode different from the active mode. The communication interface may be configured to transmit the data from the first circuit of the first die to the second circuit of the second die through the sideband interface, based on identifying the size of the data that is less than or equal to the threshold size. The communication interface may be configured to switch the mainband interface from the sleep mode to the active mode in order to transmit the data through the mainband interface, based on identifying the size of the data that exceeds the threshold size.

[0006] In one embodiment, a method of a processing chip component may be provided. The processing chip component may include a communication interface comprising a first die, a second die, a main band interface for data communication between the first die and the second die, and a side band interface for controlling the main band interface. The method may include an operation of performing the data communication between the first die and the second die through the main band interface while the main band interface is in an active mode for data communication. The method may include an operation of transmitting data to be transmitted from the first die to the second die through the side band interface in order to maintain the sleep mode of the main band interface while the main band interface is in a sleep mode different from the active mode.

[0007] FIG. 1 illustrates an exemplary hardware configuration of an electronic device including a processing chip component (e.g., a processor) according to one embodiment.

[0008] FIGS. 2a and 2b illustrate exemplary structures of a plurality of semiconductor dies included in a processing chip component according to one embodiment.

[0009] FIGS. 3A, 3B, 3C, and 3D illustrate exemplary structures of a processing chip component comprising a communication interface based on the UCIe (universal chiplet interconnect express) protocol and a plurality of semiconductor dies interconnected through said communication interface.

[0010] FIG. 4 illustrates a diagram of the layers and functions of the UCIe protocol for communication between semiconductor dies included in a processing chip component according to one embodiment.

[0011] FIGS. 5A, FIGS. 5B, and FIGS. 5C illustrate diagrams for explaining instances of the UCIe protocol.

[0012] FIG. 6 is an exemplary block diagram schematically illustrating a communication interface connecting multiple semiconductor dies included in a processing chip component (e.g., a standard package module).

[0013] FIG. 7 is an exemplary state diagram for explaining the state of a communication interface connecting multiple semiconductor dies within a processing chip component.

[0014] FIG. 8 is an exemplary flowchart for explaining the operation of a communication interface connecting multiple semiconductor dies within a processing chip component.

[0015] FIG. 9 is an exemplary signal flow diagram for explaining data communication between multiple semiconductor dies through a communication interface.

[0016] FIG. 10 is a block diagram of an electronic device in a network environment according to various embodiments.

[0017] Hereinafter, various embodiments of this document will be described with reference to the attached drawings.

[0018] Within this document, when expressions regarding the positional relationship between one element and another (e.g., “on,” “at the top,” “below,” “at the bottom,” “next to”) are mentioned, it should be understood that, unless expressions such as “rightly” or “directly” are used, there may be one or more intervening elements between the two elements, and it should be noted that this does not limit the arrangement relationship between the two elements.

[0019] For example, when one element is referred to as being “above” another element, it may mean that one or more intermediate elements may exist between the two elements, in addition to the one element being attached to the other element, integrally combined, or integrally formed. For example, in the present disclosure, “B placed above A” may indicate “B placed over A”. For example, within this document, “B placed above A” may indicate “B facing A and spaced apart from A”. For example, “a first planar portion placed above the first housing part” may indicate “a first planar portion in contact with the first housing part”. For example, “a first planar portion placed above the first housing part” may indicate “a first planar portion facing the first housing part and spaced apart from the first housing part”.

[0020] For example, within this document, “B on A” may refer to “B disposed at least partially on one surface of A.” For example, within this document, “B on (or above) A” may refer to “B formed on A.” For example, within this document, “B on A” may refer to “B, a portion of which is formed on one surface of A, and the remainder of which is formed on another surface opposite to the said one surface of A.” For example, “B on A” may refer to “B, a portion of which is bonded to the outer surface of A, and the remainder of which is bonded to the interior of A.”

[0021] FIG. 1 illustrates an exemplary hardware configuration of an electronic device (101) including a processing chip component (e.g., processor (110)) according to one embodiment.

[0022] Referring to FIG. 1, the electronic device (101) may be one of various types of electronic devices, such as a laptop PC (personal computer) (190), smartphones (191) having various form factors (e.g., a bar-type smartphone (191-1), a foldable-type smartphone (191-2), or a sliderable (or rollable)-type smartphone (191-3)), a tablet PC (192), a head-mounted display (HMD) device (193), a watch (194), a cellular phone (not shown), and other similar computing devices (not shown). The electronic device (101) may be referred to as a mobile device, user equipment (UE) (or user terminal), a multifunction device, a portable device, or a server. The form factor of the electronic device (101) is not limited to the exemplary form factors shown in FIG. 1. For example, the electronic device (101) may be included as an electronic control unit (ECU) within a vehicle (e.g., an electric vehicle, EV). For example, the electronic device (101) may have a wearable form factor, such as an earbud (or wireless earphone) and / or a ring, or may have an implantable form factor on a part of the user's body.

[0023] The components, their relationships, and their functions illustrated in FIG. 1 are merely exemplary and do not limit the implementations described or claimed herein. Referring to FIG. 1, an electronic device (101) according to one embodiment may include components such as a processor (e.g., application processor (AP), communication processor (CP)) (110), memory (e.g., volatile memory (121) and / or non-volatile memory (122)), a display (123), a communication circuit (124), an image sensor (125), and / or a sensor (126).

[0024] Referring to FIG. 1, an embodiment is illustrated in which a processor (110), volatile memory (121), non-volatile memory (122), and / or a communication circuit (124) are placed over or on a printed circuit board (PCB) (105), but the embodiment is not limited thereto. On the PCB (105), the processor (110) may be electrically connected to or operably coupled with the volatile memory (121), non-volatile memory (122), and / or the communication circuit (124). Hereinafter, operably coupled components may mean that a direct connection or an indirect connection between the components is established via wired or wireless means so that a second component is controlled by a first component among the components.

[0025] The components included in the electronic device (101) are not limited to the embodiment of FIG. 1, and the electronic device (101) may include other components (e.g., a power management integrated circuit (PMIC), an audio processing circuit, an antenna, a rechargeable battery, or an input / output interface). For example, some components may be omitted from the electronic device (101). For example, some components may be integrated into a single component.

[0026] Referring to FIG. 1, volatile memory (121) and / or non-volatile memory (122) may be configured to store data and / or instructions based on an address space managed by the processor (110). A display (123) may display images and / or videos provided by the processor (110) on one side (e.g., flat and / or curved) of the housing of the electronic device (101). A communication circuit (124) may be configured to support wired and / or wireless communication between the electronic device (101) including the processor (110) and an external electronic device. An image sensor (125) may be configured to provide an electrical signal representing external light to the processor (110) and / or memory (e.g., volatile memory (121) and / or non-volatile memory (122)). The sensor (126) may be configured to provide an electrical signal based at least on an external environment to the processor (110) and / or memory (e.g., volatile memory (121) and / or non-volatile memory (122)). Each of the volatile memory (121), non-volatile memory (122), display (123), communication circuit (124), image sensor (125), and sensor (126) of FIG. 1 may correspond to the volatile memory (1032), non-volatile memory (1034), display module (1060), communication module (1090), camera module (1080), and sensor module (1076) shown in FIG. 10.

[0027] According to one embodiment, an electronic device (101) may include a processor (110) for processing data. The processor (110) may include a circuit element including a passive component, a transistor, a diode, or any combination thereof. Within the processor (110), logic circuits for processing data may be interconnected. The processor (110) may be referred to as an integrated circuit (IC) and / or a system on chip (SoC). Circuits included in the processor (110) may be classified into units, modules, intellectual property (IP), and / or electronic components according to their function. For example, the processor (110) may include electronic components such as a CPU (central processing unit), GPU (graphics processing unit), NPU (neural processing unit), ISP (image signal processor), display controller, memory controller, storage controller, CP (communication processor), and / or sensor interface (or sensor hub). Hereinafter, a unit, module, and / or electronic component may refer to a set of circuits included in the processor (110) and at least a part of the processor (110) designed to perform a specific function. The processor (110) of FIG. 1 may correspond to the processor (120) of FIG. 7. In this disclosure, the term “processor” may be replaced with the term “processing chip component” and / or the term “AP”.

[0028] As a plurality of circuit elements are integrated on a wafer (e.g., silicon (Si) wafer, silicon carbide (SiC) wafer, gallium nitride (GaN) wafer, and / or gallium arsenide (GaAs) wafer), a semiconductor die to be included in (or packaged in) a processor (110) can be produced. In this disclosure, the term “semiconductor die” may be used interchangeably with the term “die” and / or the term “chiplet”. Referring to FIG. 1, a substrate (140) included in the processor (110) and a plurality of semiconductor dies (e.g., a first die (131) and / or a second die (132)) disposed on the substrate (140) are shown. In the present disclosure, “layer” may be used as a term to distinguish dies and / or substrates stacked along a reference direction (in one embodiment of FIG. 1, the z-axis direction) within the processor (110). Referring to FIG. 1, the processor (110) may include a first layer comprising a substrate (140), and a second layer located on the first layer and comprising a first die (131) and a second die (132).

[0029] The yield of a die (e.g., the failure rate of the die) may decrease as the area of ​​the die decreases (e.g., random fail or RDF (random defect failure)). A processor (110) designed to include multiple dies may be produced with an increased yield compared to a case designed to include a single die, because it includes dies with a smaller area than the case designed to include a single die. A method for densely integrating circuit elements on the die may be required. A process for producing circuit elements on the die may have a name based on the minimum line width (or line pitch) that can be made on the die. For example, a 3 nm process may be described as a process capable of producing a die containing circuit elements having a minimum line width of 3 nm. When the minimum line width is reduced, the number of circuit elements that can be made on a die of the same area may increase.

[0030] The performance of a circuit included in a die (e.g., performance measured by parameters such as IPC (instructions per cycle) and / or FLOPS (floating point operations per second)), power consumption, and / or yield may be related to the process used to produce the die (or the minimum linewidth supported by the process). As the size of the circuit elements included in the die decreases, the power consumption of the circuit containing said circuit elements may decrease, heat dissipation may be improved, and speed (e.g., driving frequency and / or clock frequency) may increase. In other words, as the process is improved, the minimum linewidth supported by the process may decrease.

[0031] Dies produced by a newer process (e.g., a process capable of creating circuit elements with a relatively small minimum linewidth on a die) may have relatively higher production costs than dies produced by an older process (e.g., a process capable of creating circuit elements with a relatively large minimum linewidth on a die). Newer processes may have higher instability than older processes. That is, newer processes may have a lower yield (empirically) than older processes. To compensate for the yield reduction caused by the instability of newer processes, dies produced by newer processes may be designed to have a smaller size than other dies produced by older processes (e.g., die size shrink). For example, electronic components (or circuits) requiring high performance may be implemented on a first die based on the newer process, while other electronic components (or other circuits) requiring lower performance may be implemented on a second die based on the older process.

[0032] Referring to FIG. 1, a plurality of dies (131, 132) positioned or disposed above one surface of a substrate (140) are shown. The plurality of dies may be produced by different processes and / or the same process. Referring to FIG. 1, an embodiment in which the plurality of dies are positioned on the same plane (or layer) within a processor (110) is shown. For example, a first die (131) may be positioned on a first portion of the substrate (140), and a second die (132) may be positioned on a second portion of the substrate (140) different from the first portion. On the substrate (140), the first die (131) and the second die (132) may be spaced apart from each other. An embodiment in which the first die (131) and the second die (132) are positioned on one (a) layer above the substrate (140) is shown, but the embodiment is not limited thereto. For example, the processor (110) may have a three-dimensional integrated circuit (3D-IC) structure in which a plurality of dies (131, 132) are stacked. The 3D-IC may be referred to as 3D packaging, 3D SIC (stacked ICs), or monolithic 3D IC.

[0033] As an electronic device (101) including a processor (110) is developed, a method for supporting communication between a circuitry located on a first die (131) and another circuitry located on a second die (132) may be required. Referring to FIG. 1, a communication interface (150) for supporting communication (e.g., data communication) between a circuitry within the first die (131) and a circuitry within the second die (132) may be formed on a substrate (140) on which a plurality of dies (131, 132) are located. In terms of interconnecting the plurality of dies (131, 132), the substrate (140) may be referred to as an interposer layer (or interposer) and / or an interconnect layer. In terms of interconnecting multiple dies (131, 132), the communication interface (150) may be referred to as an interconnect structure (or architecture). The substrate (140) may be formed based on a material such as silicon, glass, and / or an organic compound. An exemplary structure of the communication interface (150) for communication between the first die (131) and the second die (132) based on the substrate (140) is described with reference to FIG. 2a, FIG. 2b, and / or FIG. 6.

[0034] In one embodiment, the processor (110) may include the first die (131), the second die (132), the substrate (140), and / or the communication interface (150) illustrated exemplarily in FIG. 1, as well as other components not illustrated in FIG. 1. For example, the substrate (140) of the processor (110) may be associated with or / or include a redistribution layer (RDL). The processor (110) may include at least one solder ball (or bump) located between the first die (131) and the substrate (140), and / or between the second die (132) and the substrate (140). A stacked structure of dies (e.g., first die (131) and / or second die (132)), a substrate (140), and solder balls is described with reference to FIG. 2b, FIG. 3a, FIG. 3b, FIG. 3c, and / or FIG. 3d.

[0035] The processor (110) may include a packaging structure that encloses the components described above (e.g., a first die (131), a second die (132), and a substrate (140)). In terms of including the packaging structure, the processor (110) may be referred to as a chip package, a package module, and / or a package. To support various functions, the processor (110) may include a plurality of dies, such as the first die (131) and the second die (132), each having a circuit configured to perform different functions implemented therein. Referring to FIG. 1, the processor (110) may be configured to control other electronic components of the electronic device (101) (e.g., volatile memory (121), non-volatile memory (122), a display (123), a communication circuit (124), an image sensor (125), and a sensor (126)).

[0036] In one embodiment in which the processor (110) comprises a plurality of dies (e.g., a first die (131) and / or a second die (132)), a circuit for communication of each of the plurality of dies, such as a communication interface (150), may be included. In the present disclosure, “interface” may include or refer to a circuit (formed on said two or more dies and on a substrate (140) on which said two or more dies are located) for communication between circuits located on each of said two or more dies. In the present disclosure, “protocol” may include a method of operating the interface (or a circuit referred to as the interface) defined for data exchange between said two or more dies through the interface, a program for executing said method (e.g., a set of instructions, and / or firmware), and / or a non-transient computer-readable storage medium containing (or storing) said program. For example, the interface may include circuit elements (e.g., a logic circuit, and / or a buffer) for executing said protocol.

[0037] A protocol defined for a communication interface (150) may include the universal chiplet interconnect express (UCIe) protocol. The UCIe protocol may be defined to provide high-bandwidth, low-wattage, power-efficient, and / or cost-effective on-package connections (or off-package connections) between dies (or chiplets). In other words, the UCIe protocol may be described as an open on-package interconnect standard for connecting dies within the same package. In terms of supporting die-to-die communication based on the UCIe protocol, the communication interface (150) may be referred to as a UCIe interface. Layers included in the UCIe protocol are described with reference to FIG. 4, FIG. 5a, FIG. 5b, and / or FIG. 5c.

[0038] The present disclosure may include a method (or protocol) for reducing (or optimizing) power consumption for die-to-die communication by utilizing the structure and / or state of a communication interface (150) for supporting a UCIe protocol, and a communication interface (150) for performing die-to-die communication according to said method. The present disclosure may include a method (or protocol) for transmitting a signal (e.g., a control signal such as an interrupt signal, and / or a data signal containing data of a relatively small size) (of a specific purpose or specific object) more quickly from one die (e.g., a first die (131)) to another die (e.g., a second die (132)), and a communication interface (150) configured to perform said method.

[0039] Below, exemplary structures of a communication interface (150) for supporting the UCIe protocol are described with reference to FIG. 2a and / or FIG. 2b.

[0040] FIGS. 2A and 2B illustrate exemplary structures of a plurality of semiconductor dies (e.g., a first die (131) and / or a second die (132)) included in a processing chip component (e.g., the processor (110) of FIG. 1) according to one embodiment. Referring to FIGS. 2A and / or 2B, a substrate (140), dies (the first die (131) and / or the second die (132)) located on the substrate (140), and a communication interface (150) for communication between the dies are schematically illustrated, which are included in the processor (110) (e.g., the processor (110) of FIG. 1). The first die (131), second die (132), substrate (140), and / or communication interface (150) of FIG. 1 may include the first die (131), second die (132), substrate (140), and / or communication interface (150) of FIG. 2a and / or FIG. 2b.

[0041] Referring to FIG. 2a, the schematic structure of the first die (131), the second die (132), and the substrate (140) is shown when viewed in the direction of the z-axis shown in FIG. 1. Referring to FIG. 2a, for convenience of explanation, the circuit implemented on the die is shown in the form of blocks. For example, as an example of a circuit included in the second die (132), a CPU (central processing unit) (210), a GPU (graphic processing unit) (220), an NPU (neural processing unit) (230), and / or an ISP (image signal processor) (240) is shown. The circuits included in the second die (132) (or processor (110)) are not limited thereto, for example, the second die (132) may include a serial communication interface (SCI) / last level cache (LLC), a Signal I / F (interface), a high speed synchronous serial interface (HSI), a memory management (M / M), a low power dynamic random access memory (LP-DDR) physical interface (PHY), a network on chip (NOC), or any combination thereof. For example, the first die (131) may include a communication processor (CP) for communication between an electronic device (e.g., electronic device (101) of FIG. 1) containing the processor (110) and another electronic device.

[0042] For example, the CPU (210) may include a circuit (e.g., core circuit and / or core) configured to process data based on at least one instruction input to the CPU (210). For example, the GPU (220) may include a circuit configured to execute parallel operations for graphics (e.g., rendering). For example, the NPU (230) (or neural engine) may include a circuit configured to execute operations for an artificial intelligence model (e.g., convolution computation, weighted sum computation, and / or normalize computation on numeric values ​​expressed as integer type and / or floating point type). For example, the ISP (240) may include a circuit for controlling a camera (e.g., one or more cameras that are at least partially visible through the front or rear of the electronic device (101) of FIG. 1) electrically connected to the processor (110), and / or receiving data (e.g., an image, video, frame data, and / or image frame acquired by the camera) from the camera. For example, the CP (e.g., a CP included in the first die (131)) may include a circuit configured to control a communication circuit (e.g., a communication circuit (124) of FIG. 1) connected to the processor (110).

[0043] For example, the first die (131) and the second die (132) may be produced based on different processes. For example, the minimum size (or minimum line width) of the circuit elements included in the second die (132) may be smaller than the minimum size (or minimum line width) of the circuit elements included in the first die (131). For example, the second die (132) may be produced by a first process (e.g., a 3 nm process and / or a 2 nm process) capable of implementing circuit elements (e.g., a transistor having a gate-all-around (GAA) structure) based on a minimum line width (line width or line pitch) of 3 nm. For example, the first die (131) may be produced by a second process that supports the production of circuit elements (e.g., a fin field-effect transistor (FinFET)) with a minimum line width greater than 3 nm. The processes used for the production of each of the first die (131) and the second die (132) are not limited to the second process and the first process described above.

[0044] Referring to FIG. 2a, the processor (110) may include a communication interface (150) for communication between a first die (131) on which a CP is located and a second die (132) on which a set of circuits including a CPU (210) is located. The communication interface (150) may be configured to support high-bandwidth communication between the CP located on the first die (131) and the CPU (210) located on the second die (132). Embodiments are not limited thereto, but in one embodiment where the first die (131) includes a circuit (or IP) different from the CP, the communication interface (150) may be configured to support communication between any circuit included in the second die (132) (e.g., IP such as a CPU (210), GPU (220), NPU (230), and / or ISP (240)) and said circuit included in the first die (131). Through the communication interface (150), a communication link can be established between the circuit in the first die (131) and the circuit in the second die (132).

[0045] According to one embodiment, the communication interface (150) may include circuit elements based on the UCIe protocol. Referring to FIG. 2a, the communication interface (150) may include a first PHY (physical or physical layer) logic circuitry (151) placed on a first die (131) and corresponding to the physical layer of the UCIe protocol. The first PHY logic circuitry (151) may be referred to as a module and / or PHY logic placed on the first die (131) in the UCIe protocol. Referring to FIG. 2a, the communication interface (150) may include a second PHY logic circuitry (152) placed on a second die (132) and corresponding to the physical layer of the UCIe protocol. The second PHY logic circuit (152) may be referred to as a module and / or PHY logic placed on the second die (132) in the UCIe protocol. Referring to FIG. 2a, the communication interface (150) may include a plurality of lanes (153) formed on the substrate (140) and electrically connecting the first PHY logic circuit (151) and the second PHY logic circuit (152).

[0046] Referring to FIG. 2b, a schematic structure of a first die (131), a second die (132), and a substrate (140) is shown when viewed in a direction perpendicular to the z-axis of FIG. 1 and FIG. 2a. A plurality of layers defined within the processor (110) along the direction of the z-axis may include a first layer comprising a substrate (140), and a second layer located on the first layer comprising a first die (131) and a second die (132). The plurality of layers are not limited to the first layer and the second layer. For example, the plurality of layers may further include a third layer located on the second layer comprising a dynamic RAM (250). The DRAM (250) may be configured to store (at least temporarily) data to be input to a component included in the processor (110), such as a CPU, and / or data output from said component.

[0047] Referring to FIG. 2b, the first die (131) and / or the second die (132) may include connecting members (260) for electrical connection to other parts (e.g., other dies) within the processor (110). The connecting members (260) may include through silicon vias (TSVs), referred to as through chip vias and / or through holes. The connecting members (260) may include wires, traces, solder balls, solder bumps, metal bumps, and / or other conductive adhesives.

[0048] Referring to FIG. 2b, the processor (110) may include an RDL for the arrangement and / or redistribution of wiring within the processor (110) (e.g., signal path between the first die (131) and the second die (132)). The RDL may include a substrate (140) and connecting members (260). The RDL may include wiring that interconnects the connecting members (260) and / or a structure of said wiring. Referring to FIG. 2b, a first set of connecting members (260) may be (electrically) connected to a first PHY logic circuit (151) of the first die (131), and a second set of connecting members (260) may be (electrically) connected to a second PHY logic circuit (152) of the second die (132). A plurality of lanes (153) connecting the first PHY logic circuit (151) and the second PHY logic circuit (152) may include components (e.g., pins, bonding wires, and / or traces) formed on the substrate (140) for the electrical connection of the first set, the second set, and the first set and the second set.

[0049] According to one embodiment, the communication interface (150) may include a mainband interface and a sideband interface. The mainband and the sideband may be related to the terms “mainband” and “sideband” within the UCIe protocol and / or UCIe specification. For example, the mainband interface of the communication interface (150) may correspond to a portion of the communication interface (150) for data communication between the first die (131) and the second die (132).

[0050] In the present disclosure, data communication between the first die (131) and the second die (132) may refer to data communication from any circuit (or IP) of the first die (131) (e.g., CP within the first die (131)) interposed with a communication interface (150) to another circuit (or IP) of the second die (132) (e.g., CPU (210) within the second die (132)). That is, data communication may include an operation in which data is sequentially transmitted from the circuit of the first die (131) to the first PHY logic circuit (151), a plurality of lanes (153), the second PHY logic circuit (152), and the circuit of the second die (132). The embodiments are not limited thereto, and data communication may include an operation in which data is sequentially transmitted from the circuit of the second die (132) to the second PHY logic circuit (152), a plurality of lanes (153), the first PHY logic circuit (151), and the circuit of the first die (131). According to the UCIe protocol, it may be configured to support data communication based on a bandwidth of up to 16 Gbps (or exceeding this). One or more channels having said bandwidth may be established (or linked) between the dies (or chiplets) via RDL, or disconnect, unlink, or disassociate.

[0051] For example, a sideband interface of the communication interface (150) may correspond to another part of the communication interface (150) for controlling the mainband interface. The sideband interface may be included in the UCIe protocol for communication between physical layers including a first PHY logic circuit (151) and a second PHY logic circuit (152). In other words, according to the UCIe protocol, signals, data, and / or information exchanged between the first die (131) (or the first PHY logic circuit (151) within the first die (131)) and the second die (142) (or the second PHY logic circuit (152) within the second die (132)) through the sideband interface are not transmitted to other circuits different from the communication interface (150) (e.g., a CP within the first die (131), and / or a CPU (210), GPU (220), NPU (230), and / or ISP (240) within the second die (132)). A portion of the communication interface (150) for the main band interface (or a portion of the plurality of lanes (153)) and another portion of the communication interface (150) for the side band interface (or another portion of the plurality of lanes (153)) are described with reference to FIG. 6.

[0052] According to one embodiment, a communication interface (150) within a processing chip component (e.g., processor (110)) can perform communication based on a sideband interface (e.g., communication at a layer higher than the physical layer, and / or data communication). According to the UCIe protocol, the mode of the mainband interface for data communication between dies (e.g., first die (131) and second die (132)) can be switched between an active mode in which a communication link for data communication is established, and a sleep mode different from said active mode. In the present disclosure, the active mode may be referred to as an active state, an enabled mode, and / or an enabled state. In the present disclosure, the sleep mode may be referred to as a sleep state, a disabled mode, and / or a disabled state. The active mode and the sleep mode are described with reference to FIG. 7.

[0053] For example, the communication interface (150) may be configured to perform data communication between the first die (131) and the second die (132) through the main band interface while the main band interface is in an active mode for data communication. For example, the communication interface (150) may be configured to transmit data to be transmitted from the first die (131) to the second die (132) through the side band interface in order to maintain the sleep mode of the main band interface while the main band interface is in a sleep mode different from the active mode. The operation of the communication interface (150) transmitting the data through the side band while the main band interface is in a sleep mode is described with reference to FIG. 8 and / or FIG. 9.

[0054] Hereinafter, with reference to FIGS. 3a to 3d, exemplary structures for connecting a plurality of dies, such as a first die (131) and a second die (132), are described.

[0055] FIGS. 3a, 3b, 3c, and 3d illustrate exemplary structures of a processing chip component comprising a communication interface based on the UCIe protocol and a plurality of semiconductor dies interconnected through said communication interface. Referring to FIGS. 3a through 3d, different structures of a processing chip component are illustrated, comprising a substrate (314) and three dies (e.g., die-0 (311), die-1 (312), and die-2 (313)) located on the substrate (314). A processing chip component (or SOC) comprising a plurality of dies as in FIGS. 3a through 3d may be referred to as a 2.5D package. The substrate (140) of FIGS. 1, 2a, and / or FIGS. 2b may include the substrate (314) of FIGS. 3a through 3d. A communication interface for supporting communication between multiple dies may include an electrical path formed in at least a portion of a substrate (314) located below all of the multiple dies.

[0056] Referring to the exemplary processor (110-1) of FIG. 3a, an exemplary structure of a communication interface based on one or more traces (e.g., a first trace (153-1), a second trace (153-2)) included in a substrate (314) is illustrated. For example, a communication interface for communication between die-0 (311) and die-1 (312) may include a first trace (153-1) of the substrate (314). For example, a communication interface for communication between die-0 (311) and die-2 (313) may include a second trace (153-2) of the substrate (314). The traces (e.g., the first trace (153-1) and / or the second trace (153-2)) may be used for communication between dies separated by a long distance (e.g., 10 mm to 25 mm) within the processor (110-1). The first trace (153-1) and / or the second trace (153-2) may include lanes for communication between the dies.

[0057] Referring to FIG. 3a, a plurality of solder balls (315) may be positioned between the substrate (314) and the dies. Signal paths between the dies may be established or formed by the plurality of solder balls (315) and traces (e.g., a first trace (153-1) and / or a second trace (153-2)).

[0058] Referring to the exemplary processor (110-2) of FIG. 3b, the substrate (314) may include a silicon bridge (e.g., an Embedded Multi-die Interconnect Bridge (EMIB)). Lanes of a communication interface for communication between Die-0 (311) and Die-1 (312) may be included in a first silicon bridge (321) extending from a portion of the substrate (314) where Die-0 (311) is located to another portion of the substrate (314) where Die-1 (312) is located. Similarly, a second silicon bridge (322) extending from a portion of the substrate (314) where Die-0 (311) is located to another portion of the substrate (314) where Die-2 (313) is located may include lanes of a communication interface for communication between Die-0 (311) and Die-2 (313).

[0059] Referring to the exemplary processor (110-3) of FIG. 3c, an interposer (331) may be positioned on a substrate (314). A plurality of dies (e.g., die-0 (311), die-1 (312), and die-2 (313)) may be positioned on the interposer (331). A plurality of solder balls (332) may be positioned between the substrate (314) and the interposer (331). A plurality of solder balls (315) may be positioned between the interposer (331) and the plurality of dies. A communication interface connecting the plurality of dies may include links formed within the interposer (331). The interposer (331) may include a CoWoS (Chip on Wafer on Substrate) as a substrate on which the dies may be positioned. The substrate (314) may be referred to as a package substrate.

[0060] Referring to the exemplary processor (110-4) of FIG. 3d, an interposer (331) that is a FoCoS (Fan-Out Chip on Substrate) may be interposed between a first layer (345) comprising a substrate (314) and a second layer (346) comprising a plurality of dies (e.g., die-0 (311), die-1 (312), and die-2 (313)). Links for connecting the plurality of dies (e.g., UCIe links based on the UCIe protocol) may be established on silicon bridges (341, 342) included in the interposer (331). For example, the first silicon bridge (341) may be located in the region between die-0 (311) and die-1 (312) within the interposer (331) and may include lanes of a communication interface between die-0 (311) and die-1 (312). For example, lanes of communication interfaces between die-0 (311) and die-2 (313) may be located within a second silicon bridge (342) that extends from a part of the interposer (331) where die-0 (311) is located to another part of the interposer (331) where die-2 (313) is located.

[0061] Below, with reference to FIG. 4, a UCIe protocol for communication between multiple dies is described.

[0062] FIG. 4 illustrates a diagram of the layers and functions of a UCIe protocol for communication between semiconductor dies included in a processing chip component according to one embodiment. Referring to FIG. 4, the layers of the UCIe protocol may include a physical layer (410), a die-to-die adapter (420), and a protocol layer (430). The UCIe protocol may include a fly-aware D2D interface (FDI) (425) for communication between the die-to-die adapter (420) and the protocol layer (430). Referring to FIG. 4, the FDI (425) may be located within the UCIe protocol between the protocol layer (430) and the D2D adapter (420). For example, a signal between the die-to-die adapter (420) and the protocol layer (430) may be defined by the FDI (425). The UCIe protocol may include a raw D2D interface (RDI) (415) for communication between the physical layer (410) and the die-to-die adapter (420). Referring to FIG. 4, the RDI (415) may be located between the D2D adapter (420) and the physical layer (410) within the UCIe protocol. For example, signals between the physical layer (410) and the die-to-die adapter (420) may be defined by the RDI (415). For example, through the RDI (415), a circuit of the physical layer (410) (e.g., a PHY logic circuit) may be connected to the die-to-die adapter (420), which is separated from the circuit within the die. In the RDI (415), a one-to-one relationship between the physical layer (410) and the D2D adapter (420) is illustrated, but the embodiment is not limited thereto. Various relationships between the physical layer (410) and the D2D adapter (420) in the RDI (415) are described with reference to FIGS. 5a through 5c.

[0063] Referring to FIG. 4, the functions of the die-to-die adapter (420) and the functions of the physical layer (410) are illustrated. The die-to-die adapter (420) may be configured to perform arbitration (ARB) and / or multiplexing (MUX) of a signal transmitted through a communication interface. The die-to-die adapter (420) may be configured to perform error detection based on cyclic redundancy checking (CRC) and fleet retries based on detecting errors. The die-to-die adapter (420) may be configured to perform link state management (LSM) and / or power state management for the link. Here, the link may include a communication link established between the dies through a communication interface.

[0064] Referring to FIG. 4, the physical layer (410) may be configured to perform link training of the mainband interface and / or sideband interface. The physical layer (410) may be configured to perform lane recovery and / or lane inversion. The physical layer (410) may be configured to perform scrambling on a signal to be transmitted through the mainband interface and / or sideband interface. The physical layer (410) may be configured to perform descramble on a signal received through the mainband interface and / or sideband interface. The physical layer (410) may be configured to generate a clock, such as a phase-locked-loop (PLL), and / or transmit the generated clock.

[0065] Referring to FIG. 4, the physical layer (410) may include logic for communication at the sideband interface (e.g., logic circuit) and logic for communication at the mainband interface (e.g., logic circuit) (e.g., AFE (analog front-end)). Within a communication interface for communication between two dies (e.g., communication interface (150) of FIG. 2a), the physical layer (410) may correspond to a PHY logic circuit (e.g., second PHY logic circuit (151) and / or second PHY logic circuit (152) of FIG. 2a). The sideband interface may be used for initialization of the RDI (415) defined by the UCIe protocol. The sideband interface may be used for synchronization at the physical layer (410) for debugging / protocol compliance.

[0066] Referring to FIG. 4, M lanes (411) included in the sideband interface are illustrated. Through the lanes (411), signals associated with the sideband interface (e.g., parameter exchange, register access of PHY logic circuits, and / or signals for link training) may be transmitted. According to the UCIe protocol, the driving frequency of the sideband interface may be set to a specified frequency (e.g., 800 MHz) or fixed. Within the communication interface, circuit elements for the sideband interface may be managed by a power management profile referred to as the always-ON domain. For example, circuit elements for the sideband interface remain in an active state while the processor is turned on and do not switch to an inactive state.

[0067] Referring to FIG. 4, the mainband interface may include a forward clock lane (412), lanes for data communication (413), and a verification lane (414) (or a verification track lane). Unlike a sideband interface that remains active, the mainband interface may switch between an active state and an inactive state while the processor is turned on. While the mainband interface is turned on (or while the mainband interface is in an active state), data from the first die may be transmitted to the second die through the mainband interface.

[0068] In one embodiment, when the RDI (415) is used, delay and / or power loss may occur due to a change in state (e.g., switching between a sleep state and an active state). For example, while the mainband interface is off (or in a sleep state), the communication interface may determine or identify whether to transmit data from the first die to the second die through the sideband interface rather than through the mainband interface. For example, the communication interface may transmit the data through the sideband interface if the data is robust to delay. In other words, for data that must be transmitted with low delay, the communication interface may transmit the data through the mainband interface among the mainband interface and the sideband interface. For example, while the mainband interface is in a sleep state (or is off), the communication interface may transmit the data through the sideband interface if the size of the data is small (e.g., smaller than a threshold size). For example, based on sideband transitions, power optimization for RDI (415) can be achieved or delay can be reduced. In other words, the communication interface can transmit data having a size greater than a threshold size through the mainband interface among the mainband interface and the sideband interface.

[0069] Below, exemplary structures of a physical layer (410) for scaling the bandwidth are described with reference to FIGS. 5a to 5c.

[0070] FIGS. 5A, FIGS. 5B, and FIGS. 5C illustrate diagrams for illustrating instances of the UCIe protocol. Referring to FIGS. 5A through 5C, among the layers of the UCIe protocol described above with reference to FIG. 4, a die-to-die adapter (420) is illustrated. Referring to FIGS. 5A through 5C, among the layers of the UCIe protocol, one or more PHY logics (or PHY logic circuits) for implementing the physical layer below the die-to-die adapter (420) are illustrated.

[0071] Referring to FIG. 5a, a first case is illustrated in which a single PHY logic (510) (or PHY logic circuit) is associated with a die-to-die adapter (420). The first case may be referred to as a single instance. The sideband interface of the PHY logic (510) may include a first designated number (e.g., 4) of lanes (411). The mainband interface of the PHY logic (510) may include a second designated number (e.g., 16) of lanes (413) for data communication. To increase bandwidth and / or transmission speed, a plurality of PHY logics may be included in the physical layer (e.g., the physical layer (410) of FIG. 4). For example, the die-to-die adapter (420) may be connected to a group of a plurality of PHY logics (or a set of PHY logic circuits) via RDI (415).

[0072] For example, for high-capacity data communication between the CPU (210) of the second die (132) and the CP of the first die (131), as described with reference to FIG. 2a, a die-to-die link based on a group of multiple PHY logics may be established between the CPU (210) of the second die (132) and the CP of the first die (131). With reference to FIG. 5b, a second case is illustrated in which two PHY logics (521, 522) are included in the physical layer. With reference to FIG. 5c, a third case is illustrated in which four PHY logics (530-0, 530-1, 530-2, 530-3) are included in the physical layer.

[0073] Referring to FIG. 5b, the PHY logics (521, 522) included in the physical layer may each include a sideband interface and a mainband interface. The PHY logics (521, 522) of FIG. 5b may be included in a multi-module PHY logic (520). Referring to FIG. 5b, the multi-module PHY logic (520) and / or a group of PHY logics (521, 522) may be connected to a single die-to-die adapter (420). A communication interface including the PHY logics (521, 522) may establish a communication link with double the bandwidth by utilizing all of the PHY logics (521, 522).

[0074] Referring to FIG. 5c, the four PHY logics (530-0, 530-1, 530-2, 530-3) may have uniquely assigned IDs. Each of the four PHY logics (530-0, 530-1, 530-2, 530-3) may include a sideband interface and a mainband interface, respectively. The four PHY logics (530-0, 530-1, 530-2, 530-3) may be included in a multimodule PHY logic (520). The multimodule PHY logic (520) and / or the four PHY logics (530-0, 530-1, 530-2, 530-3) may be connected to a single die-to-die adapter (420). When the mainband interfaces of the four PHY logics (530-0, 530-1, 530-2, 530-3) include 16 lanes for data communication, if all of the four PHY logics (530-0, 530-1, 530-2, 530-3) are used for data communication, 64 lanes (= 16 × 4) can be used for data communication. For example, a communication interface having the structure of the third case can have a bandwidth four times greater than the bandwidth of a communication interface having the structure of the first case of FIG. 5a, which is a single instance.

[0075] According to one embodiment, the number of PHY logic included in the physical layer is not limited to the embodiments of FIGS. 5a through 5c. Referring to FIGS. 5a through 5c, the die-to-die adapter (420) may be implemented independently of the configuration of the physical layer (e.g., the number of PHY logic and / or PHY logic circuits). The die-to-die adapter (420) may be connected to a physical layer including one or more PHY logics via RDI (415).

[0076] Below, with reference to FIG. 6, an exemplary configuration of lanes extending from the physical layer of a first die (e.g., the first die (131) of FIG. 1) to the physical layer of a second die (e.g., the second die (132) of FIG. 1) is described.

[0077] FIG. 6 is an exemplary block diagram schematically illustrating a communication interface (150) connecting a plurality of semiconductor dies (e.g., a first die (631) and / or a second die (632)) included in a processing chip component (e.g., a standard package module (610)). The communication interface (150) of FIG. 6 may correspond to the communication interface (150) of FIG. 1, FIG. 2a, and / or FIG. 2b. Referring to FIG. 6, a plurality of dies (e.g., a first die (631) and a second die (632)) included in a processing chip component referred to as a standard package module (610) are illustrated. The plurality of dies may be included in a multi-die organic package module (620).

[0078] Referring to FIG. 6, a communication interface (150) may be located between a first die (631) and a second die (632) located on a first layer within a standard package module (610). The communication interface (150) may include a main band interface (650) and a side band interface (660). The communication interface (150) may include a first PHY logic (641), which is a PHY logic circuit located on the first die (631). Similarly, the communication interface (150) may include a second PHY logic (642), which is a PHY logic circuit located on the second die (632). The first PHY logic (641) and the second PHY logic (642) may include buffers for transmitting and / or receiving data. The main band interface (650) may include a plurality of data lanes located on a second layer below the first layer and driven according to a first bandwidth. The sideband interface (660) may include at least one data lane located in the second layer and driven according to a second bandwidth lower than the first bandwidth. The data lanes of the mainband interface (650) and the sideband interface (660) may be located in the RDL for electrical connection between the first die (631) and the second die (632).

[0079] In the present disclosure, the main band interface (650) may be referred to as the first interface and the side band interface (660) as the second interface. Embodiments are not limited thereto, and the main band interface (650) may be referred to as the second interface and the side band interface (660) as the first interface.

[0080] Referring to FIG. 6, lanes (or pins) included in the sideband interface (660) and the mainband interface (650) are illustrated. Referring to FIG. 6, the lanes of the sideband interface (660) may be grouped into ports extending from the first die (631) to the second die (632) (e.g., downstream ports (DSP)), and ports extending from the second die (632) to the first die (631) (e.g., upstream ports (USP)). Similarly, the lanes of the mainband interface (650) may also be grouped into USP and DSP.

[0081] Referring to FIG. 6, each of the USP and DSP of the sideband interface (660) may include a lane for transmitting a clock signal (e.g., a lane named SB clock) and a lane for transmitting readable (digital) data based on said clock signal (e.g., a lane named SB data). Since each of the USP and DSP includes an SB clock lane and an SB data lane, the sideband interface (660) may include at least four lanes.

[0082] Referring to FIG. 6, each of the USP and DSP of the mainband interface (650) may include two lanes for transmitting a clock signal (e.g., lanes designated as 2 Clock). A differential clock signal may be transmitted through these two lanes. Each of the USP and DSP of the mainband interface (650) may include 16 lanes for transmitting readable (digital) data based on the clock signal (e.g., lanes designated as 16 Data). The number of lanes for transmitting data is not limited to the number (16) exemplified above. Each of the USP and DSP of the mainband interface (650) may include a lane for verifying data transmitted through the mainband interface (650) (e.g., a lane designated as 1 Valid). Each of the USP and DSP of the mainband interface (650) may include a lane (e.g., a lane designated as Track 1) for tracking data transmitted through the mainband interface (650). Referring to FIG. 6, the number of lanes of the mainband interface (650) is not limited to the 40 lanes described above.

[0083] According to one embodiment, while the standard package module (610) is active (e.g., while receiving a power signal), the state of the mainband interface (650) and the sideband interface (660) may be controlled individually and / or independently. For example, the sideband interface (660) may be (continuously) activated by power provided from the always-ON domain (or always-ON power) of the standard package module (610). For example, the sideband interface (660) may be activated based on a fixed driving frequency (e.g., a clock of 800 MHz) based on a specified power, independently of the mode and / or state of the mainband interface (650).

[0084] According to one embodiment, the mainband interface (650) may be switched between an active mode and a sleep mode. The active mode may refer to a mode and / or state in which data transmission through the mainband interface (650) is possible by establishing a communication link in the mainband interface (650) (e.g., an initialization operation based on link training). The sleep mode may refer to a mode and / or state that is different from the active mode, in which establishing a communication link in the mainband interface (650) is required for data transmission through the mainband interface (650). According to the UCIe protocol, when there is no data to be transmitted through the mainband interface (650), the mode of the mainband interface (650) may be switched from the active mode to the sleep mode.

[0085] According to one embodiment, while the mainband interface (650) is in active mode, the communication interface (150) may be configured to perform data communication between dies connected by the communication interface (150) (e.g., IPs placed on each of the dies) using a plurality of data lanes within the mainband interface (650). While the mainband interface (650) is in sleep mode, the communication interface (150) may be configured to perform data communication between dies connected by the communication interface (150) (e.g., IPs placed on each of the dies) using at least one data lane of the sideband interface (660). For example, the communication interface (150) may transmit data through at least one data lane of the sideband interface (660). In the above example, since the mainband interface (650) maintains sleep mode, the power consumption of the mainband interface (650) may be reduced. In the above example, data can be transmitted through the sideband interface (660) without any operation (e.g., an initialization operation based on link training) that must be performed at the mainband interface (650) to establish a communication link. In other words, the data can be transmitted more quickly through the sideband interface (660).

[0086] Hereinafter, with reference to FIG. 7, exemplary operation of a mainband interface (650) that switches between active mode and sleep mode and a communication interface (150) including the mainband interface (650) is described.

[0087] FIG. 7 is an exemplary state diagram (700) for describing the state of a communication interface (e.g., a communication interface (150) of FIG. 1, FIG. 2a, and / or FIG. 2b) connecting a plurality of semiconductor dies (e.g., a first die (131) and / or a second die (132) of FIG. 1) within a processing chip component (e.g., a processor (110) of FIG. 1, FIG. 2a, and / or FIG. 2b). Referring to FIG. 7, a state transition diagram of the physical layer (410) of FIG. 4 (or PHY logic and / or PHY logic circuits corresponding to the physical layer (410)) is shown. In terms of switching between finite states, the circuits of the physical layer (410) (e.g., PHY logic and / or PHY logic circuits) may be referred to as a finite state machine (FSM).

[0088] Referring to the state diagram (700) of FIG. 7, state (710) may be referred to as an initial state and / or a reset state. In state (710), the physical layer circuit may switch to state (720). State (720) may be referred to as a state for sideband initialization (e.g., SBINT). In state (720), the sideband interface may be initialized using a control signal transmitted through the sideband interface (e.g., the sideband interface (660) of FIG. 6). Upon completion of the initialization of the sideband interface based on state (720), the physical layer circuit may switch to state (730).

[0089] The state (730) of FIG. 7 may be referred to as a state for mainband initialization (e.g., MBINT). Based on the completion of the initialization of the mainband interface (e.g., the mainband interface (650) of FIG. 6) based on the state (730), the physical layer circuit may switch to the state (740). The state (740) of FIG. 7 may be referred to as a state for performing link training to establish a communication link in the mainband interface (e.g., MBTRAIN). Within the state for performing link training (740), the physical layer circuit may switch to a state (770) (e.g., PHYRETRAIN) for performing link training again in the physical layer. Within the state (770), the physical layer circuit may switch to the state (740) according to the progress of the link training. Within the state (740), based on the completion of the link training, the physical layer circuit may switch to the state (750).

[0090] The state (750) of FIG. 7 may be referred to as a state for initializing a communication link in a communication interface (e.g., LINKINIT). Upon completion of the initialization of the communication link based on the state (750), the circuit of the physical layer may switch to the state (760). The state (760) of FIG. 7 may be referred to as a state for performing data communication through the mainband interface (e.g., data communication through the lanes (413) of FIG. 4) (e.g., ACTIVE). The state (760) of FIG. 7 may be referred to as the L0 state.

[0091] According to one embodiment, the active mode of the mainband interface may include the state (760) of FIG. 7. The embodiment is not limited thereto, and the active mode may include the state (760) of FIG. 7 and a state (e.g., states (720, 730, 740, 750)) that performs a series of initialization operations to switch to the state (760).

[0092] Within the state (760) of FIG. 7, the communication interface may switch to state (770) and / or state (780). For example, when data transmission through the mainband interface is completed or data reception through the mainband interface is completed, the communication interface and / or physical layer circuit may switch to state (780). State (780) may be referred to as a state for at least partially disabling the mainband interface to reduce power consumption.

[0093] According to one embodiment, the sleep mode of the main band interface may include the state (780) of FIG. 7. For example, switching the main band interface from active mode to sleep mode may include switching the state of the communication interface including the main band interface from state (760) to state (780). For example, switching the main band interface from sleep mode to active mode may include switching the state of the communication interface from state (780) to state (760) following the flow of the state diagram (700).

[0094] For example, the state (780) may include a low-power consumption state, referred to as the L1 state, and a three-level low-power consumption state, referred to as the L2 state. The L2 state may be defined to reduce the power consumption of a mainband interface or a communication interface including a mainband interface to less than the power consumption of the communication interface in the L1 state. For example, within the L2 state, the communication interface may turn off or disable a physical layer circuit, including a PLL associated with the mainband interface. A circuit for generating a clock (e.g., a reference clock or a reference clock), such as the PLL, may remain active within the L1 state. The L2 state is defined to reduce the power consumption of the PLL.

[0095] According to one embodiment, within the L1 state, the physical layer circuit may switch to state (740) based on receiving data to be transmitted through the mainband interface. Based on switching from the L1 state to state (740), the physical layer circuit may re-perform operations in states (740, 750) to re-enter state (760).

[0096] Referring to FIG. 7, within the L2 state of state (780), the physical layer circuit can switch to state (710) based on identifying data to be transmitted through the mainband interface. After switching to state (710), the physical layer circuit can sequentially perform operations of states (720, 730, 740, 750) to enter state (760) where the data can be transmitted through the mainband interface. For example, the operation of switching from the L2 state to state (760) may have a higher complexity than the operation of switching from the L1 state to state (760). For example, the L1 state may be referred to as a state that can be switched to state (760) without initializing the sideband interface based on state (720).

[0097] In one embodiment, the state diagram (700) for the communication interface of FIG. 7 may be related to the state of the main band interface among the main band interface and the side band interface of the communication interface, as described above. The side band interface may remain active while the state of the communication interface is switched according to the state diagram (700). That is, it is obvious to a person skilled in the art that die-to-die communication through the side band interface is possible in any state of the state diagram (700).

[0098] In one embodiment, according to the UCIe protocol, the state in which a signal is transmitted or received through the sideband interface within the communication interface is only state (720). For example, the sideband interface is not used in the state after the initial synchronization for link training and the PHY configuration between the USP / DSP. For example, the sideband interface is not used in a state different from the state for link training (e.g., a state for high-speed communication such as L0) and / or a state for USP / DSP data communication. According to the UCIe protocol, the signal transmitted from the first die to the second die through the sideband interface is used only for controlling the PHY logic located on the second die and does not cause the transmission of any data to other circuits (or IPs) on the second die that are different from the communication interface.

[0099] According to one embodiment, a communication interface can perform data communication using the sideband interface by checking conditions that the sideband interface is more suitable for data communication than the mainband interface. For example, in a state different from state (720) (e.g., state (780)), the communication interface can transmit a signal through the sideband interface while maintaining the sleep mode (e.g., state (780)) of the mainband interface and / or the communication interface, instead of switching the mainband interface to an active mode (e.g., state (760)). The conditions may be related to at least one of a delay caused by link training (e.g., state (740)) and / or link initialization (e.g., states (720, 730, 750)) performed when switching from a state (780) including L1 state and / or L2 state to a state (760) which is L0 state, and / or a transmission characteristic of the sideband interface having a narrower bandwidth than the mainband interface.

[0100] Hereinafter, with reference to FIG. 8, exemplary conditions for determining whether a communication interface according to one embodiment performs data communication through a sideband interface while the mainband interface is in sleep mode are described.

[0101] FIG. 8 is an exemplary flowchart for illustrating the operation of a communication interface connecting multiple semiconductor dies within a processing chip component. A processor (110) of FIG. 1, FIG. 2a, and / or FIG. 2b may be included as an example in the processing chip component of FIG. 8. A first die (131) and a second die (132) of FIG. 1, FIG. 2a, and / or FIG. 2b may include multiple (semiconductor) dies of FIG. 8. A communication interface (150) of FIG. 1, FIG. 2a, and / or FIG. 2b may include the communication interface of FIG. 8.

[0102] Referring to FIG. 8, in operation (810), according to one embodiment, a communication interface may be configured to identify a request to transmit data from a first circuit of a first die to a second circuit of a second die through the communication interface. The request may be generated by a circuit corresponding to another layer above the protocol layer (430) of FIG. 4 (e.g., a first circuit included in the first die connected to the communication interface). The request may be a request for die-to-die communication between the first circuit of the first die and the second circuit of the second die. The communication interface that identifies the request of operation (810) may perform operation (820).

[0103] Referring to FIG. 8, within operation (820), a communication interface according to one embodiment may determine or check whether the main band interface is in active mode. If the main band interface is in active mode (820-Yes), the communication interface may perform operation (830). If the main band interface is in a mode different from active mode (e.g., sleep mode) (820-No), the communication interface may perform operation (840). The active mode of operation (820) may correspond to the state (760) of FIG. 7.

[0104] Referring to FIG. 8, in operation (830), according to one embodiment, a communication interface may be configured to transmit data from a first circuit of a first die to a second circuit of a second die through a main band interface. Based on identifying a request of operation (820) while the main band interface is in active mode, the communication interface may perform data communication through the main band interface, among the side band interface and the main band interface. The PHY logic of the first die may transmit an electrical signal to the PHY logic of the second die by controlling lanes included in the main band interface (e.g., at least one of the lanes (412, 413, 414) of FIG. 4). The PHY logic of the second die may transmit data included in the electrical signal to another circuit of the second die connected to the PHY logic of the second die.

[0105] Referring to FIG. 8, within operation (840), a communication interface according to one embodiment may determine or check whether conditions for maintaining the sleep mode of the mainband interface are satisfied. Such conditions may relate to the use of data, size (or throughput), priority, maximum transfer delay associated with the data, or a combination thereof. If data satisfying the conditions of operation (840) is identified (840-Yes), the communication interface may perform operation (850). If data not satisfying the conditions of operation (840) is identified (840-No), the communication interface may perform operation (860).

[0106] For example, if data of a specific use (or specific type) is identified that is allowed to be transmitted through a sideband interface, the communication interface may determine that said data satisfies the conditions of operation (840). For example, if the CP of the first die transmits data to the CPU of the second die to notify information (or events) related to a network handover, the communication interface may determine that said data satisfies the conditions of operation (840). For example, if the sensor hub of the first die transmits data containing the GPS (global positioning system) coordinates of an electronic device (e.g., the electronic device (101) of FIG. 1) to the CPU of the second die, the communication interface may determine that said data satisfies the conditions of operation (840). For example, if data to be stored in a specific register, such as an input / output (I / O) register, is identified, the communication interface may determine that said data satisfies the conditions of operation (840). For example, when the electronic device (101) is operating in a state to reduce the power consumption of a processing chip component including a CPU, such as an always-on display (AOD), if it identifies data (e.g., time and / or date displayed through the AOD screen) for a screen to be displayed on the display (e.g., a screen referred to as an AOD screen), the communication interface may determine that said data satisfies the conditions of operation (840). For example, if it identifies said data for notifying an interrupt, such as a software interrupt, the communication interface may determine that said data satisfies the conditions of operation (840).

[0107] For example, by comparing the threshold size and the size of the data, the communication interface can check whether the data satisfies the conditions of the operation (840). The threshold size may correspond to the size of the buffer included in the PHY logic of the communication interface, or may be less than or equal to the size. The embodiments are not limited thereto, and the threshold size may be set (empirically) to any size suitable for transmission through the sideband interface. If data having a size less than or equal to the threshold size is identified, the communication interface may determine that the data satisfies the conditions of the operation (840). If data having a size exceeding the threshold size is identified, the communication interface may determine that the data does not satisfy the conditions of the operation (840).

[0108] For example, a type and / or category may be set that allows transmission based on a bandwidth less than the bandwidth of the mainband interface. If data corresponding to said type and / or said category is identified, the communication interface may determine that said data satisfies the conditions of operation (840). For example, if data requiring a delay less than the delay occurring while the mainband interface switches from sleep mode to active mode is identified, the communication interface may determine that said data satisfies the conditions of operation (840).

[0109] Referring to FIG. 8, in operation (850), according to one embodiment, a communication interface may be configured to transmit data from a first circuit of a first die to a second circuit of a second die through a sideband interface. For example, based on identifying data having a size less than or equal to a threshold size for maintaining a sleep mode of a mainband interface, the communication interface may transmit data from a first circuit of a first die to a second circuit of a second die through a sideband interface. For example, based on identifying data for an interrupt, the communication interface may transmit data through the sideband interface. For example, based on identifying that data less than or equal to the size of a buffer within the communication interface located in the first die is stored in said buffer, the communication interface may transmit said data through the sideband interface.

[0110] Referring to FIG. 8, in operation (860), according to one embodiment, a communication interface may be configured to switch the mode of a mainband interface from sleep mode to active mode. To switch the mainband interface from sleep mode to active mode, the communication interface may establish a communication link within the mainband interface. To establish a communication link, the communication interface may perform link training. To establish a communication link, the bandwidth of the mainband interface may be set or restored to a bandwidth determined prior to entering sleep mode. The state of the communication interface performing link training may correspond to the state (740) of FIG. 7. Through a mainband interface having a second bandwidth determined based on link training and higher than the first bandwidth of the sideband interface, the communication interface may transmit data from a first circuit of a first die to a second circuit of a second die (e.g., operation (830)).

[0111] For example, based on identifying data having a size exceeding a threshold size, the communication interface may transmit said data through the mainband interface. For example, based on identifying that data exceeding the size of the buffer within the communication interface is stored in said buffer, the communication interface may perform operation (860) to switch the mainband interface from sleep mode to active mode, and transmit said data through the mainband interface in active mode.

[0112] As described above, while the communication interface and / or mainband interface are in sleep mode, the communication interface may perform an operation to maintain the sleep mode of the mainband interface. For example, the communication interface may maintain the sleep mode of the mainband interface by transmitting data transmittable through the sideband interface instead of the mainband interface. In the above example, since the mainband interface maintains the sleep mode, the power consumption of the communication interface including the mainband interface and the processing chip component including the communication interface may be reduced. In the above example, since data is transmitted without the delay that occurs when switching from sleep mode to active mode, unexpected delays that occur when transmitting data may be reduced.

[0113] Below, with reference to FIG. 9, signals transmitted through a communication interface when the operations of FIG. 8 are performed are described.

[0114] FIG. 9 is an exemplary signal flow diagram for illustrating data communication between a plurality of semiconductor dies (e.g., a first die (131) and / or a second die (132)) through a communication interface (e.g., a communication interface (150) of FIG. 1, FIG. 2a, and / or FIG. 2b). The first die (131) and the second die (132) of FIG. 1, FIG. 2a, and / or FIG. 2b may include the first die (131) and the second die (132) of FIG. 9.

[0115] Referring to FIG. 9, an exemplary flow of signals within a communication interface (e.g., signals transmitted between the first die (131) and the second die (132)) is illustrated according to the layers of the communication interface (e.g., the layers of FIG. 4). The portion of the communication interface corresponding to the first die (131) may be divided into a protocol layer (430-1), a die-to-die (D2D) adapter (420-1), and a physical layer (410-1). The first PHY logic (641) of FIG. 6 may correspond to the physical layer (410-1) of the first die (131). The portion of the communication interface corresponding to the second die (132) may be divided into a protocol layer (430-2), a D2D adapter (420-2), and a physical layer (410-2). The second PHY logic (642) of FIG. 6 may correspond to the physical layer (410-2) of the second die (132). The channel (910) between the first die (131) and the second die (132) may correspond to a sideband interface of a communication interface (e.g., the sideband interface (660) of FIG. 6).

[0116] According to one embodiment, while the communication interface and / or mainband interface is in an active mode (e.g., the state (760) of FIG. 7, referred to as the L0 state), the communication interface can perform USP / DSP data communication through the mainband interface. To switch the state of the mainband interface (e.g., switching from active mode to sleep mode), the communication interface can transmit a message to switch the state (e.g., {LinkMgmt.RDI.Req.L1} or {LinkMgmt.RDI.Req.L2} of the UCIe protocol) through the channel (910), i.e., the sideband interface.

[0117] Referring to FIG. 9, a message (915) is shown being transmitted from the physical layer (410-1) of the first die (131) to the physical layer (410-2) of the second die (132) in order to switch from active mode to sleep mode. Embodiments are not limited thereto, for example, while the communication interface is in active mode, a message (920) containing a request for power management (e.g., a PM (power management) request) (e.g., {LinkMgmt.RDI.Req.L1} or {LinkMgmt.RDI.Req.L2} of the UCIe protocol) may be transmitted from the physical layer (410-2) of the second die (132) to the physical layer (410-1) of the first die (131) based on a decision to switch from active mode to sleep mode. The above message (920) may be transmitted to the physical layer (410-2) of the second die (132) and to the physical layer (410-1) of the first die (131) through the channel (910) to switch the state of the communication interface corresponding to the active mode to an L1 state and / or L2 state (e.g., state (780) of FIG. 7). For example, by the message (920) transmitted through a port (e.g., USP) from the second die (132) to the first die (131), all of the different parts of the communication interface located on the different dies (e.g., the first die (131) and the second die (132)) may begin switching from the active mode to the sleep mode.

[0118] Referring to FIG. 9, based on identifying (or receiving) a message (920) through the D2D adapter (420-1) of the first die (131), the communication interface located on the first die (131) may be switched to sleep mode (operation (925)). For example, after the message (920) is transmitted through the channel (910), the state of the communication interface may be switched to the L1 state and / or L2 state included in the state (780) of FIG. 7. For example, based on the transition from the L0 state to the L1 state and / or the transition from the L0 state to the L2 state, the communication interface may enter sleep mode. In sleep mode, the mainband interface of the communication interface (e.g., the circuit of the first die (131) and / or the second die (132) associated with the mainband interface) may be at least partially disabled. In sleep mode, the circuit of the mainband interface (e.g., PLL) may be disabled (e.g., PLL OFF).

[0119] Referring to FIG. 9, in order to support data communication based on the sideband interface (e.g., transmission of data based on operation (850) of FIG. 8) while the communication interface and / or mainband interface is in sleep mode, a message (930) may be transmitted through channel (910) from the D2D adapter (420-1) of the first die (131) to the D2D adapter (420-2) of the second die (132). The message (930) may be transmitted through channel (910) before the communication interface and / or mainband interface enter sleep mode. The message (930) may include a request to set a setting value (e.g., a setting value stored in sideband mailbox registers present) indicating whether to allow transmission of data based on the sideband interface to a specified setting value (e.g., a 1h value defined by the UCIe protocol). The specified setting value may indicate that transmission of data based on the sideband interface is allowed. By message (930), the setting value of a register of a communication interface (e.g., sideband mailbox registers present) may be changed from a setting value indicating read-only (RO) to a specified setting value that allows the transmission of data based on the sideband interface (RP). Message (930) may cause the communication interface to switch to a state where data communication based on the sideband interface is allowed by firmware executed by the communication interface.

[0120] Referring to FIG. 9, after switching to sleep mode based on message (925), a request (940) for transmitting data (945) from the second die (132) to the first die (131) can be identified by a communication interface. Based on identifying the request (940), a message (950) for transmitting data (945) from the D2D adapter (420-2) of the second die (132) to the D2D adapter (420-1) of the first die (131) can be transmitted. The message (950) can be transmitted to the D2D adapter (420-1) of the first die (131) through the D2D adapter (420-2) of the second die (132), the physical layer (410-2), the channel (910), i.e., the sideband interface, and the physical layer (410-1). Based on a message (950) identified using the D2D adapter (420-1) of the first die (131), the communication interface can identify or extract data (955) contained in the message (950). The data (955) can be transmitted through the protocol layer (430-1) to a circuit (or IP) within the first die (131) connected to the communication interface. For example, data (960) transmitted from the communication interface to a circuit of the first die (131) can correspond to the data (955).

[0121] Referring to FIG. 9, after a message (950) is transmitted from the second die (132) to the first die (131) through the channel (910), a message (965) to notify of the reception of the message (950) can be transmitted from the D2D adapter (420-1) of the first die (131) to the D2D adapter (420-2) of the second die (132) through the channel (910).

[0122] As described above, communication between dies can be performed through a channel (910), that is, a sideband interface. Data communication based on the sideband interface can be performed based on a state transition of the mainband interface based on a message (925) (e.g., switching from active mode to sleep mode). Referring to FIG. 9, since data (945) is transmitted through the sideband interface, the mainband interface that has entered sleep mode based on the message (925) can maintain sleep mode independently of the data (945). For example, the frequency of wake-up of the mainband interface from sleep mode to active mode can be reduced. Because the frequency of wake-up of the mainband interface is reduced, the power consumption of the communication interface including the mainband interface and the processing chip component including the communication interface can be reduced. Because the power consumption of the processing chip component is reduced, the power consumption of the electronic device including the processing chip component (e.g., the electronic device (101) of FIG. 1) can also be reduced. Additionally, data (945) can be transmitted quickly through the sideband interface without delay occurring during the wake-up of the mainband interface, or the transmission of data (945) can be started quickly without the said delay.

[0123] FIG. 10 is a block diagram of an electronic device (1001) in a network environment (1000) according to various embodiments. Referring to FIG. 10, in the network environment (1000), the electronic device (1001) may communicate with an electronic device (1002) through a first network (1098) (e.g., a short-range wireless communication network) or may communicate with at least one of an electronic device (1004) or a server (1008) through a second network (1099) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (1001) may communicate with the electronic device (1004) through a server (1008). According to one embodiment, the electronic device (1001) may include a processor (1020), memory (1030), input module (1050), sound output module (1055), display module (1060), audio module (1070), sensor module (1076), interface (1077), connection terminal (1078), haptic module (1079), camera module (1080), power management module (1088), battery (1089), communication module (1090), subscriber identification module (1096), or antenna module (1097). In some embodiments, at least one of these components (e.g., connection terminal (1078)) may be omitted from the electronic device (1001), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (1076), camera module (1080), or antenna module (1097)) may be integrated into a single component (e.g., display module (1060)).

[0124] The processor (1020) can, for example, execute software (e.g., program (1040)) to control at least one other component (e.g., hardware or software component) of the electronic device (1001) connected to the processor (1020) and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (1020) can store commands or data received from other components (e.g., sensor module (1076) or communication module (1090)) in volatile memory (1032), process the commands or data stored in volatile memory (1032), and store the resulting data in non-volatile memory (1034). According to one embodiment, the processor (1020) may include a main processor (1021) (e.g., a central processing unit or an application processor) or an auxiliary processor (1023) that can operate independently or together with it (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, if the electronic device (1001) includes a main processor (1021) and an auxiliary processor (1023), the auxiliary processor (1023) may be configured to use lower power than the main processor (1021) or to be specialized for a specified function. The auxiliary processor (1023) may be implemented separately from the main processor (1021) or as part thereof.

[0125] The auxiliary processor (1023) may control at least some of the functions or states associated with at least one component of the electronic device (1001) (e.g., display module (1060), sensor module (1076), or communication module (1090)) on behalf of the main processor (1021) while the main processor (1021) is in an inactive (e.g., sleep) state, or together with the main processor (1021) while the main processor (1021) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (1023) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (1080) or communication module (1090)). According to one embodiment, the auxiliary processor (1023) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (1001) itself where the artificial intelligence model is executed, or through a separate server (e.g., server (1008)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0126] The memory (1030) can store various data used by at least one component of the electronic device (1001) (e.g., processor (1020) or sensor module (1076)). The data may include, for example, input data or output data for software (e.g., program (1040)) and related commands. The memory (1030) may include volatile memory (1032) or non-volatile memory (1034).

[0127] The program (1040) may be stored as software in memory (1030) and may include, for example, an operating system (1042), middleware (1044), or an application (1046).

[0128] The input module (1050) can receive commands or data to be used for a component of the electronic device (1001) (e.g., processor (1020)) from outside the electronic device (1001) (e.g., user). The input module (1050) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0129] The sound output module (1055) can output a sound signal to the outside of the electronic device (1001). The sound output module (1055) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0130] The display module (1060) can visually provide information to an external (e.g., user) of the electronic device (1001). The display module (1060) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (1060) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0131] The audio module (1070) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (1070) can acquire sound through the input module (1050) or output sound through the sound output module (1055) or an external electronic device (e.g., electronic device (1002)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (1001).

[0132] The sensor module (1076) can detect the operating state of the electronic device (1001) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (1076) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0133] The interface (1077) may support one or more specified protocols that can be used for the electronic device (1001) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (1002)). According to one embodiment, the interface (1077) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0134] The connection terminal (1078) may include a connector through which the electronic device (1001) can be physically connected to an external electronic device (e.g., electronic device (1002)). According to one embodiment, the connection terminal (1078) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0135] The haptic module (1079) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module (1079) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0136] The camera module (1080) can capture still images and video. According to one embodiment, the camera module (1080) may include one or more lenses, image sensors, image signal processors, or flashes.

[0137] The power management module (1088) can manage power supplied to the electronic device (1001). According to one embodiment, the power management module (1088) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0138] The battery (1089) can supply power to at least one component of the electronic device (1001). According to one embodiment, the battery (1089) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0139] The communication module (1090) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (1001) and an external electronic device (e.g., electronic device (1002), electronic device (1004), or server (1008)), and the performance of communication through the established communication channel. The communication module (1090) may include one or more communication processors that operate independently of the processor (1020) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (1090) may include a wireless communication module (1092) (e.g., cellular communication module, short-range wireless communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (1094) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (1004) through a first network (1098) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (1099) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (1092) can identify or authenticate the electronic device (1001) within a communication network such as the first network (1098) or the second network (1099) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (1096).

[0140] The wireless communication module (1092) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The wireless communication module (1092) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The wireless communication module (1092) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The wireless communication module (1092) can support various requirements specified in the electronic device (1001), external electronic device (e.g., electronic device (1004)), or network system (e.g., second network (1099)). According to one embodiment, the wireless communication module (1092) can support a Peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mMTC, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for realizing URLLC.

[0141] An antenna module (1097) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (1097) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (1097) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (1098) or a second network (1099), may be selected from the plurality of antennas, for example, by a communication module (1090). A signal or power may be transmitted or received between the communication module (1090) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (1097).

[0142] According to various embodiments, the antenna module (1097) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0143] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., commands or data) with each other.

[0144] According to one embodiment, commands or data may be transmitted or received between an electronic device (1001) and an external electronic device (1004) through a server (1008) connected to a second network (1099). Each of the external electronic devices (1002, or 1004) may be the same or a different type of device as the electronic device (1001). According to one embodiment, all or part of the operations performed on the electronic device (1001) may be performed on one or more of the external electronic devices (1002, 1004, or 1008). For example, if the electronic device (1001) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (1001) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (1001). The electronic device (1001) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (1001) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device (1004) may include an Internet of Things (IoT) device. The server (1008) may be an intelligent server using machine learning and / or neural networks.According to one embodiment, an external electronic device (1004) or server (1008) may be included within the second network (1099). The electronic device (1001) may be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0145] The electronic device according to the various embodiments disclosed in this document may be of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0146] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish said components from other said components and do not limit said components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as “coupled” or “connected” to another (e.g., 2nd) component, with or without the terms “functionally” or “communicationly,” it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0147] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0148] Various embodiments of the present document may be implemented as software (e.g., program (1040)) comprising one or more instructions stored in a storage medium (e.g., internal memory (1036) or external memory (1038)) readable by a machine (e.g., electronic device (1001)). For example, a processor (e.g., processor (1020)) of the machine (e.g., electronic device (1001)) may call at least one of the one or more instructions stored from the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0149] According to one embodiment, the method according to the various embodiments disclosed herein may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0150] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0151] The electronic device (101) of FIG. 1 may include the electronic device (1001) of FIG. 10.

[0152] In one embodiment, a method for reducing power consumption of a processing chip component in which a plurality of dies are integrated (or packaged) may be required. In one embodiment, a method for reducing power consumption related to data communication between a plurality of dies within the processing chip component may be required. In one embodiment, a method for increasing the speed of data communication between a plurality of dies within the processing chip component may be required. In one embodiment, while a communication interface for communication of a plurality of dies is at least partially in a sleep state (or sleep mode), a method for performing data communication based on said communication interface while maintaining said sleep state may be required. A processing chip component according to one embodiment as described above may include a communication interface (e.g., a communication interface (150) of FIG. 1), comprising a first die (e.g., a first die (131) of FIG. 1), a second die (e.g., a second die (132) of FIG. 1), a main band interface for data communication between the first die and the second die (e.g., a main band interface (650) of FIG. 6), and a side band interface for controlling the main band interface (e.g., a side band interface (660) of FIG. 6). The communication interface may be configured to perform the data communication between the first die and the second die through the main band interface while the main band interface is in an active mode for data communication. The communication interface may be configured to transmit data through the sideband interface based on identifying data to be transmitted from the first die to the second die while the mainband interface is in a sleep mode different from the active mode.Transmitting the above data through the sideband interface may be performed to maintain the sleep mode of the mainband interface. In one embodiment, a processing chip component in which a plurality of dies are integrated (or packaged) may have relatively low power consumption because the power consumption associated with data communication between the plurality of data dies is reduced. According to one embodiment, the processing chip component may perform data communication at a relatively increased speed (or reduced time). According to one embodiment, the processing chip component may perform data communication between the plurality of dies while the sleep state of at least a portion (e.g., the mainband interface) is maintained while the processing chip component is in a sleep state (or sleep mode).

[0153] For example, the first die and the second die may be located in a first layer within the processing chip component. The sideband interface may include at least one data lane located in a second layer below the first layer and driven according to a first bandwidth. The mainband interface may include a plurality of data lanes located in the second layer and driven according to a second bandwidth higher than the first bandwidth.

[0154] For example, the communication interface may be configured to perform data communication through the plurality of data lanes within the main band interface while the main band interface is in the active mode. The communication interface may be configured to transmit data through the at least one data lane within the side band interface while the main band interface is in the sleep mode.

[0155] For example, the second layer may include a Redistribution Layer (RDL) in which the at least one data lane and the plurality of data lanes are located.

[0156] For example, the communication interface may be configured to transmit the data through the sideband interface based on identifying the data below a threshold size while the mainband interface is in the sleep mode.

[0157] For example, the communication interface may be configured to transmit the data through the sideband interface based on identifying the data for an interrupt.

[0158] For example, the communication interface may include a buffer located on the first die. The communication interface may be configured to transmit the data through the sideband interface based on identifying that the data is stored in the buffer with a size less than or equal to the buffer while the mainband interface is in the sleep mode.

[0159] For example, the communication interface may be configured to switch the main band interface from the sleep mode to the active mode in order to transmit the data through the main band interface, based on identifying that the data exceeding the size of the buffer is stored in the buffer while the main band interface is in the sleep mode.

[0160] For example, the communication interface may be configured to perform link training to switch the mainband interface from the sleep mode to the active mode.

[0161] A processing chip component according to one embodiment as described above may include a communication interface comprising a first die, a second die, a mainband interface for data communication between the first die and the second die, and a sideband interface for controlling the mainband interface. The communication interface may be configured to identify a request to transmit data from a first circuit of the first die to a second circuit of the second die through the communication interface. The communication interface may be configured to transmit the data from the first circuit of the first die to the second circuit of the second die through the mainband interface based on identifying the request while the mainband interface is in an active mode. The communication interface may be configured to identify the size of the data based on identifying the request while the mainband interface is in a sleep mode different from the active mode. The communication interface may be configured to transmit the data from the first circuit of the first die to the second circuit of the second die through the sideband interface, based on identifying the size of the data that is less than or equal to the threshold size. The communication interface may be configured to switch the mainband interface from the sleep mode to the active mode in order to transmit the data through the mainband interface, based on identifying the size of the data that exceeds the threshold size. The threshold size may be set to maintain the sleep mode of the mainband interface.

[0162] For example, the communication interface may be configured to perform link training to switch the mainband interface from the sleep mode to the active mode. Based on the link training, the communication interface may be configured to transmit the data from the first circuit of the first die to the second circuit of the second die through the mainband interface having a second bandwidth higher than the first bandwidth of the sideband interface.

[0163] For example, the first die and the second die may be located in a first layer within the processing chip component. The sideband interface may include at least one data lane located in a second layer below the first layer and driven according to a first bandwidth. The mainband interface may include a plurality of data lanes located in the second layer and driven according to a second bandwidth higher than the first bandwidth.

[0164] For example, the communication interface may be configured to perform data communication through the plurality of data lanes within the main band interface while the main band interface is in the active mode. The communication interface may be configured to transmit data through the at least one data lane within the side band interface while the main band interface is in the sleep mode.

[0165] For example, the second layer may include a Redistribution Layer (RDL) in which the at least one data lane and the plurality of data lanes are located.

[0166] For example, the communication interface may be configured to transmit the data through the sideband interface based on identifying the data for an interrupt.

[0167] For example, the communication interface may include a buffer located on the first die and / or the second die, having the threshold size.

[0168] In one embodiment as described above, a method of a processing chip component may be provided. The processing chip component may include a communication interface comprising a first die, a second die, a main band interface for data communication between the first die and the second die, and a side band interface for controlling the main band interface. The method may include an operation of performing the data communication between the first die and the second die through the main band interface while the main band interface is in an active mode for data communication. The method may include an operation of transmitting data to be transmitted from the first die to the second die through the side band interface in order to maintain the sleep mode of the main band interface while the main band interface is in a sleep mode different from the active mode.

[0169] For example, the first die and the second die may be located in a first layer within the processing chip component. The sideband interface may include at least one data lane located in a second layer below the first layer and driven according to a first bandwidth. The mainband interface may include a plurality of data lanes located in the second layer and driven according to a second bandwidth higher than the first bandwidth.

[0170] For example, the operation performed above may include the operation of performing data communication through the plurality of data lanes within the main band interface while the main band interface is in the active mode. The transmitting operation may include the operation of transmitting the data through the at least one data lane within the side band interface while the main band interface is in the sleep mode.

[0171] For example, the second layer may include a Redistribution Layer (RDL) in which the at least one data lane and the plurality of data lanes are located.

[0172] For example, the transmitting operation may include transmitting the data through the sideband interface based on identifying the data below a threshold size while the mainband interface is in the sleep mode.

[0173] For example, the above-mentioned transmitting operation may include the operation of transmitting the data through the sideband interface based on identifying the data for an interrupt.

[0174] For example, the communication interface may include a buffer located on the first die. The transmitting operation may include transmitting the data through the sideband interface based on identifying that the data is stored in the buffer with a size less than or equal to the size of the buffer.

[0175] For example, the above method may include an operation of switching the mainband interface from the sleep mode to the active mode in order to transmit the data through the mainband interface, based on identifying that the data exceeding the size of the buffer is stored in the buffer.

[0176] For example, the switching operation may include an operation to perform link training in order to switch the mainband interface from the sleep mode to the active mode.

[0177] The device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on said operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.

[0178] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or instruct the processing unit independently or collectively. Software and / or data may be embodied in any type of machine, component, physical device, computer storage medium, or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0179] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. In this case, the medium may continuously store a program executable by a computer, or temporarily store it for execution or download. Additionally, the medium may be various recording or storage means in the form of a single or several hardware combined, and may not be limited to a medium directly connected to a computer system but may exist distributed over a network. Examples of media may include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and media configured to store program instructions, including ROM, RAM, and flash memory. Additionally, other examples of media may include recording or storage media managed by app stores that distribute applications or sites and servers that supply or distribute various other software.

[0180] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0181] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

1. Regarding a processing chip component, First die; 2nd die; and A communication interface comprising a mainband interface for data communication between the first die and the second die, and a sideband interface for controlling the mainband interface, and The above communication interface is, While the mainband interface is in an active mode for data communication, the data communication between the first die and the second die is performed through the mainband interface; and Configured to transmit the data through the sideband interface based on identifying the data to be transmitted from the first die to the second die while the mainband interface is in a sleep mode different from the active mode. Processing chip components.

2. In claim 1, the communication interface is, Configured to transmit the data through the sideband interface based on identifying the data below a threshold size while the mainband interface is in the sleep mode. Processing chip components.

3. In claims 1 and 2, the communication interface is, Configured to transmit the data through the sideband interface based on identifying the data for the interrupt, Processing chip components.

4. In claims 1 to 3, the communication interface comprises a buffer located on the first die, and The above communication interface is while the above mainband interface is in the sleep mode: Based on identifying that the data is stored in the buffer with a size less than or equal to the size of the buffer, the data is configured to be transmitted through the sideband interface. Processing chip components.

5. In claims 1 to 4, the first die and the second die are, Located in the first layer within the above-mentioned processing chip component, and The above sideband interface is, It includes at least one data lane located in a second layer below the first layer and driven according to a first bandwidth; and The above mainband interface is, A plurality of data lanes located in the second layer and driven according to a second bandwidth higher than the first bandwidth, Processing chip components.

6. In claim 5, the communication interface is, While the mainband interface is in the active mode, the data communication is performed through the plurality of data lanes within the mainband interface; and Configured to transmit the data through the at least one data lane within the sideband interface while the mainband interface is in the sleep mode, Processing chip components.

7. In claim 5, the second layer is, A Redistribution Layer (RDL) comprising at least one data lane and a plurality of data lanes located thereon, Processing chip components.

8. In claim 4, the communication interface while the mainband interface is in the sleep mode: Based on identifying that data exceeding the size of the buffer is stored in the buffer, the mainband interface is configured to switch from the sleep mode to the active mode in order to transmit the data through the mainband interface. Processing chip components.

9. In claim 8, the communication interface is, A configuration for performing link training to switch the mainband interface from the sleep mode to the active mode, Processing chip components.

10. In a processing chip component, First die; 2nd die; and A communication interface comprising a mainband interface for data communication between the first die and the second die, and a sideband interface for controlling the mainband interface, and The above communication interface is, Identifying a request to transmit data from the first circuit of the first die to the second circuit of the second die through the communication interface; Based on identifying the request while the mainband interface is in active mode, the data is transmitted through the mainband interface from the first circuit of the first die to the second circuit of the second die; and Based on identifying the request while the mainband interface is in a sleep mode different from the active mode: Identify the size of the above data; Based on identifying the size of the data that is less than or equal to a threshold size, the data is transmitted from the first circuit of the first die to the second circuit of the second die through the sideband interface; and Based on identifying the size of the data exceeding the threshold size, configured to switch the mainband interface from the sleep mode to the active mode in order to transmit the data through the mainband interface. Processing chip components.

11. In claim 10, the communication interface is, To switch the mainband interface from the sleep mode to the active mode, link training is performed; Based on the above link training, configured to transmit the data from the first circuit of the first die to the second circuit of the second die through the mainband interface having a second bandwidth higher than the first bandwidth of the sideband interface. Processing chip components.

12. In claims 10 to 11, the first die and the second die are, Located in the first layer within the above-mentioned processing chip component, and The above sideband interface is, It includes at least one data lane located in a second layer below the first layer and driven according to a first bandwidth; and The above mainband interface is, A plurality of data lanes located in the second layer and driven according to a second bandwidth higher than the first bandwidth, Processing chip components.

13. In claim 12, the communication interface is, While the mainband interface is in the active mode, the data communication is performed through the plurality of data lanes within the mainband interface; and Configured to transmit the data through the at least one data lane within the sideband interface while the mainband interface is in the sleep mode, Processing chip components.

14. In claim 12, the second layer is, A Redistribution Layer (RDL) comprising at least one data lane and a plurality of data lanes located thereon, Processing chip components.

15. In claims 10 to 14, the communication interface is, Configured to transmit the data through the sideband interface based on identifying the data for the interrupt, Processing chip components.

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