Semiconductor memory device having pseudo-quantum circuit and method for configuring pseudo-quantum circuit of semiconductor memory device

Abstract

The present invention relates to a semiconductor memory device having a pseudo-quantum circuit, which is implemented by applying a pseudo-qubit to the inside of a memory cell of the semiconductor memory device so as not to require environmental conditions such as extremely low temperatures, and a method for configuring a pseudo-quantum circuit of a semiconductor memory device. The semiconductor memory device having a pseudo-quantum circuit according to the present invention is characterized in that one qubit is stored in at least one memory cell plane among a plurality of memory cell planes each having a memory array in which multiple memory cells are formed.

Description

Semiconductor memory device having a pseudo-quantum circuit and a method for establishing a pseudo-quantum circuit of a semiconductor memory device

[0001] The present invention relates to a semiconductor memory device having a pseudo-quantum circuit and a method for setting the pseudo-quantum circuit of a semiconductor memory device. More specifically, it relates to a semiconductor memory device having a pseudo-quantum circuit that does not require the creation of an environment such as ultra-low temperature by implementing a pseudo-qubit inside a memory cell of a semiconductor memory device, and a method for setting the pseudo-quantum circuit of a semiconductor memory device.

[0002] A quantum computing device is a computing device that processes data using phenomena related to quantum mechanics, such as quantum entanglement and quantum superposition.

[0003] Quantum entanglement refers to a state in which two or more states are quantum-connected and cannot be treated as separate entities. Quantum superposition refers to the probabilistic simultaneous existence of multiple resulting states before a quantum state is measured. Quantum computing devices use qubits as the basic unit of information for processing data by utilizing phenomena related to quantum mechanics.

[0004] A qubit can simultaneously represent values ​​corresponding to multiple bits by utilizing a quantum superposition state. For example, a qubit can represent each value as a probability, such as '0 with a 20% probability and 1 with an 80% probability'. When measured, the quantum superposition state is released, and the qubit is determined to be in only one state.

[0005] By using qubits, which form the basis of quantum computers, applications such as quantum computing and quantum cryptography can be made.

[0006] The fundamental physical elements that constitute a qubit include superconducting devices, the use of electron / nuclear spin, and the polarization of photons (the fundamental particles of light). However, these fundamental physical elements have the disadvantage that it is difficult to create environments such as ultra-low temperatures for operation and that they are vulnerable to noise.

[0007] One other approach is to compute tensors using classical computers (not quantum computers), which, when increasing the number of qubits, for example, 2 for N bits N It is unrealistic because it requires a certain amount of memory space.

[0008] Therefore, even though it is not a qubit based on physical laws, 2 in the aforementioned N bit N There is a need to implement qubits based on existing semiconductors (referred to as pseudo-qubits) that can overcome the limitation of requiring memory space. If even some of the key functions of a quantum computer can be implemented using these 'pseudo-qubits,' various application fields could be found.

[0009] Existing methods for constructing quantum computers include 'superconducting devices,' 'spin utilization,' and the use of polarization of 'photons (the fundamental particles of light).'

[0010] Superconducting devices are difficult to manufacture as easily as conventional personal computers (PCs) due to the difficulty of creating environments such as ultra-low temperatures, and integrating them into existing PCs is also challenging. Therefore, the possibility of utilizing quantum computer functions by integrating them into existing IT infrastructure, such as PCs, is very low.

[0011] A method of simulation using a conventional memory structure that can overcome the aforementioned limitations without being a qubit based on physical laws is proposed in Korean Published Patent Application No. 10-2023-0057246 (Patent Document 1).

[0012] In the above Patent Document 1, each quantum gate operation is 2 N It can be expressed as the update of probability amplitude data, and to simulate a quantum circuit consisting of N qubits, 2 N+4 There is a problem requiring storage space of bytes. That is, in the above-mentioned Patent Document 1, 2 N Must use more than one memory space.

[0013] In addition, there is a technique called a tensor network that reduces memory capacity, but this method also has the problem of being impractical due to accumulated errors.

[0014] The problem that the present invention aims to solve is to implement a pseudo-qubit using a portion of the memory space inside a semiconductor memory device, thereby providing quantum functions in N bits, even though it is not a qubit based on physical laws. N The goal is to implement a semiconductor-based qubit (referred to as a pseudo-qubit) that can overcome the limitation of requiring more than one memory space.

[0015] The present invention has been devised to solve the above-mentioned problems, and its purpose is to provide a semiconductor memory device equipped with a pseudo-quantum circuit that does not require the creation of an environment such as ultra-low temperature by applying a pseudo-qubit inside a memory cell of a semiconductor memory device, and a method for setting the pseudo-quantum circuit of a semiconductor memory device.

[0016] Another objective of the present invention is to provide a semiconductor memory device having a pseudo-quantum circuit and a method for setting the pseudo-quantum circuit of the semiconductor memory device, wherein a plurality of first and second quantum strings among a plurality of strings in which a plurality of memory cells are connected in series are designated to allocate pseudo-qubits to some or all of the plurality of memory cells provided in the memory cell plane of the semiconductor memory device by a quantum processor block provided at the top of a plurality of memory cell planes or outside of the semiconductor memory device, and wherein pseudo-qubit data stored in the plurality of memory cells included in the first and second quantum strings is selected and the selected qubit data is extracted to the data reader / writer connected to the bit line, and at least one virtual quantum gate is controlled to perform a quantum operation on the extracted qubit data.

[0017] Another objective of the present invention is to provide a semiconductor memory device equipped with a pseudo-quantum circuit that can be implemented using a minimum amount of memory space and can reduce quantum computation time when configuring pseudo-qubits in the memory cells of the semiconductor memory device.

[0018] Another objective of the present invention is that the number of Quantum States data required in actual applications is 2 N In most cases, the data cannot be compared (e.g., 1000), but the purpose is to provide a semiconductor memory device equipped with a quasi-quantum circuit that can utilize 3D memory to reduce computation time or easily find a computation method by efficiently tracking changes in the necessary quantum data during quantum computation.

[0019] Another objective of the present invention is to provide a semiconductor memory device equipped with a pseudo-quantum circuit capable of high-speed quantum computation and imparting quantum functions (such as encryption) to digital data stored in a memory cell by implementing a quantum gate using a pseudo-qubit.

[0020] Another objective of the present invention is to provide a semiconductor memory device equipped with a pseudo-quantum circuit that can perform quantum operations to obtain and store necessary input and output digital data quickly and efficiently within a memory chip without the need for data to go outside the memory chip, by positioning qubits and quantum gates in the same memory block storing digital data or in different memory blocks within a single memory chip.

[0021] To achieve the above objective, a semiconductor memory device having a pseudo-quantum circuit according to one embodiment of the present invention comprises a memory array stacked in a three-dimensional (3D) structure and having a plurality of memory cells formed therein, wherein the plurality of memory cells form a plurality of memory cell planes connected in series; a row decoder for selecting at least one of a plurality of word lines connected to each of the plurality of memory cell planes to designate at least one of the plurality of memory cell planes; and a data reader / writer for reading data stored in a memory cell included in the designated string through a plurality of bit lines and writing data when designating one of the plurality of strings. The invention includes a string selection line decoder for designating any first and second quantum strings among the plurality of strings to assign the I0> component and I1> component of the pseudo-qubit, respectively; wherein when the plurality of word lines select a plurality of memory cell planes, the number of pseudo-qubits is set according to the number of selected memory cell planes, and when pseudo-qubit data stored in a plurality of memory cells included in the first and second quantum strings is selected and the selected qubit data is extracted to the data reader / writer connected to the bit line, at least one virtual quantum gate is formed to perform a quantum operation on the extracted qubit data.

[0022] In this case, one qubit is stored in each of the plurality of memory cell planes, and N qubits can be allocated to N memory cell planes.

[0023] In addition, the cell selection line decoder can specify a third cell string for assigning the phase Iφ> component of the pseudo-qubit.

[0024] Furthermore, the plurality of memory cell planes may each be divided into a first memory cell area for representing pseudo-qubits and a second memory cell area for storing digital data.

[0025] The semiconductor memory device according to the present invention is provided at the top of the plurality of memory cell planes or outside the semiconductor memory device and may further include a quantum processor block for obtaining quantum data from pseudo-qubits.

[0026] The quantum processor block can control the row decoder to select at least one memory cell plane by the word line, select first and second quantum string selection lines to which qubit data is assigned by the string selection line decoder, and when extracting qubit data of the first and second strings specified by the selected first and second quantum string selection lines to a data reader and writer connected to the bit line, it can perform quantum operations on the extracted qubit data.

[0027] In addition, quantum states created by a pseudo-quantum circuit that performs quantum operations on the extracted qubit data and quantum state data stored in the quantum states can be obtained.

[0028] The above semiconductor memory device may be either a 3D NAND flash memory device or a 3D DRAM.

[0029] A method for establishing a pseudo-quantum circuit of a semiconductor memory device according to the present invention comprises a memory array stacked in a three-dimensional structure and having a plurality of memory cells formed therein, wherein the plurality of memory cells form a plurality of memory cell planes connected in series; a row decoder for selecting at least one of a plurality of word lines connected to each of the plurality of memory cell planes to designate at least one of the plurality of memory cell planes; a data reader / writer for reading data stored in a memory cell included in a designated string through a plurality of bit lines and writing data when designating one of the plurality of strings; a string selection line decoder for designating any first and second quantum strings among the plurality of strings to assign the I0> component and I1> component of a pseudo-qubit to each of the plurality of strings; and at least one virtual quantum gate for executing a quantum operation on the extracted qubit data when selecting pseudo-qubit data stored in a plurality of memory cells included in the first and second quantum strings and extracting the selected qubit data to the data reader / writer connected to the bit line. The method is characterized by comprising: a step of preparing a semiconductor memory device including a quantum processor block that controls the formation of such a device; a step of creating quantum states and assigning quantum state data to the quantum states by a pseudo-quantum circuit that executes quantum operations on the qubit data by the quantum processor block; and a step of performing quantum operations while passing through the virtual quantum gate and extracting the result when extracting the quantum state data assigned to the quantum states by the quantum processor block.

[0030] The above at least one virtual quantum gate can form a virtual quantum circuit.

[0031] In addition, the quantum processor block can perform a second quantum operation on the quantum operation data extracted through the data reader / writer.

[0032] Furthermore, when the above-mentioned plurality of word lines select a plurality of memory cell planes, the number of pseudo-qubits can be set according to the number of selected memory cell planes.

[0033] As described above, the present invention can be implemented using a semiconductor memory device such as a 3D NAND flash memory, DRAM, or SRAM-type memory having a plurality of memory cell planes, which is known prior to the present invention.

[0034] That is, in the present invention, a semiconductor memory device can be implemented having a pseudo-quantum circuit that controls the formation of at least one virtual quantum gate to perform quantum operations on the extracted qubit data when pseudo-qubit data stored in the plurality of memory cells included in the first and second quantum strings is selected and extracted to the data reader / writer connected to the bit line, by a quantum processor block provided at the top of the plurality of memory cell planes or outside the semiconductor memory device, so as to assign pseudo-qubits to some or all of the plurality of memory cells provided in the memory cell planes of the semiconductor memory device, and when pseudo-qubit data is selected and extracted to the data reader / writer connected to the bit line.

[0035] In this case, the above at least one virtual quantum gate can form a virtual quantum circuit.

[0036] Accordingly, the present invention provides a semiconductor memory device equipped with a pseudo-quantum circuit that does not require the creation of an environment such as ultra-low temperature by implementing a pseudo-qubit inside or outside a memory cell of the semiconductor memory device.

[0037] In the present invention, for example, digital information of 1 and 0 components and phase components representing a single qubit is stored in multiple existing memory cells. To store multiple qubits, quantum functions can be provided by allocating multiple qubits to multiple (N) planes.

[0038] Furthermore, in the present invention, pseudo-qubits can be configured in the memory cells of a semiconductor memory device using a minimum amount of memory space, thereby reducing quantum computation time. That is, in the present invention, a quantum computer can be implemented on an existing semiconductor chip (mainly memory) without using almost any memory space.

[0039] In other words, in principle, the quantum states generated by N qubits are 2 N There are 2, and depending on the need, the memory required to store quantum room data is 2 N In many cases, it is so large that it is necessary to reduce it.

[0040] In this invention, instead of storing all quantum states generated by N qubits, memory can be reduced by shifting or circling each qubit to a memory location of 1 component and 0 component.

[0041] As a simple example, to implement 8 quantum rooms with 3 qubits, the necessary quantum rooms can be extracted only when needed using 3 circle clocks without storing them in memory beforehand.

[0042] In this invention, the number of Quantum States data required for actual applications is 2 NIn most cases, the number of quantum data points cannot be compared (e.g., 1,000 to 100,000), but 3D memory can be used to reduce computation time or easily find a computation method by efficiently tracking changes in the required quantum data points during quantum computation.

[0043] Furthermore, in the present invention, by implementing a quantum gate using a pseudo-qubit, high-speed quantum computation and quantum functions (such as encryption) can be imparted to digital data stored in a memory cell.

[0044] In other words, by locating qubits and quantum gates in the same memory block storing digital data or in different memory blocks within a single memory chip, classical gate circuits can be used to control the input and output of data stored in memory (located inside or on an external chip). This functionality allows quantum principles to serve as a method to ensure the security of classical digital data.

[0045] In other words, the present invention can provide groundbreaking assistance to existing digital data processing, such as security for existing IT systems, by imparting quantum functions to existing semiconductor chips (mainly memory).

[0046] In addition, in the present invention, by using digital data as the input and output of quantum gates, quantum computation can be performed quickly and efficiently within a memory chip.

[0047] In other words, by having qubits and quantum gates located in the same memory block storing digital data or in different memory blocks within a single memory chip, it is possible to obtain and store the input and output digital data required for quantum computation without the need for data to leave the memory chip.

[0048] Furthermore, the semiconductor memory device having quantum functions according to the present invention can be applied to 3D NAND flash memory, DRAM or SRAM-type memory, etc.

[0049] FIGS. 1a and FIGS. 1b are a schematic diagram and an equivalent circuit diagram, respectively, showing an example of applying a pseudo-qubit according to a preferred first embodiment of the present invention to a memory cell plane of a 3D NAND flash memory device.

[0050] FIGS. 2a and FIGS. 2b are circuit diagrams of two-dimensional and three-dimensional DRAMs, respectively, comprising quantum data blocks (pseudo-qubits) in a memory cell according to a preferred second embodiment of the present invention.

[0051] FIGS. 3a and FIGS. 3b are a schematic configuration diagram and a functional block diagram, respectively, of a 3D NAND flash memory device having a quantum processing block for recovering data of a quantum state from a pseudo-qubit according to a preferred third embodiment of the present invention.

[0052] FIGS. 4a and FIGS. 4b each illustrate an example of reproducing data of quantum rooms (000) and (010) from three pseudo-qubits according to a preferred fourth embodiment of the present invention, FIG. 4a shows the quantum rooms and data using three pseudo-qubits, and FIG. 4b is a plan view showing the data flow to a quantum processor block to obtain data of quantum rooms from three pseudo-qubits.

[0053] FIGS. 5A and FIGS. 5B are symbol diagrams showing the application of a Hadamard gate quantum gate to a Q#i qubit in a 3D NAND flash memory device in which pseudo-qubits are applied to a memory cell plane, and flowcharts showing a method for obtaining data of the corresponding qubit quantum room, respectively.

[0054] FIGS. 6a and FIGS. 6b are plan views showing a symbol of a CNOT gate representing quantum entanglement controlled by a quantum processing block in a 3D NAND flash memory device according to the present invention and a data flow for obtaining quantum room data from three pseudo-qubits, respectively.

[0055] FIG. 6c is an explanatory diagram illustrating the operation of a quantum gate and the refresh operation of quantum data for obtaining quantum data when two qubits are entangled with a CNOT quantum gate in a 3-qubit system according to the present invention.

[0056] FIG. 7 is an explanatory diagram illustrating another method of allocating quantum data by specifying arbitrary SSL(m) and SSL(m+1) of a second memory cell region that stores digital data instead of a first memory cell region (quantum memory region) to represent pseudo-qubits according to the present invention.

[0057] FIG. 8 is an explanatory diagram for illustrating another method of allocating data of qubits in a 3D NAND flash memory device according to the present invention.

[0058] Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings. In this process, the size or shape of the components shown in the drawings may be exaggerated for clarity and convenience of explanation.

[0059] When one element is referred to as being "connected to" or "coupled to" another element, it includes cases where it is directly connected or coupled to another element, or cases where another element is interposed in between.

[0060] On the other hand, when one component is referred to as being "directly connected to" or "directly coupled to" another component, it indicates that no other component is interposed in between.

[0061] Throughout the specification, the same reference numerals refer to the same components. "And / or" includes each of the mentioned items and all combinations of one or more.

[0062] When elements or a layer are referred to as being "on" or "on" another element or layer, it includes not only being directly on top of the other element or layer but also cases where another layer or element is interposed in between. On the other hand, when an element is referred to as being "directly on" or "directly on," it indicates that no other element or layer is interposed in between.

[0063] Furthermore, spatial relative terms such as "lower," "lower," "upper," and "upper" are used merely for convenience in describing relationships with other elements or features within this specification and may be interpreted to include various directions of the device during use or operation, in addition to the directions depicted in the drawings. For example, if the device in the drawings is inverted, an element located below another element or feature may then be located above that element or feature. Accordingly, the term "lower" may include both upward and downward directions. The device may be rotated in different directions (rotating 90 degrees or in other directions), and the spatial relative descriptors used herein may be interpreted accordingly.

[0064] Although terms such as "first," "second," etc. are used to describe various elements, components, and / or sections, it goes without saying that these elements, components, and / or sections are not limited by these terms. These terms are used merely to distinguish one element, component, or section from another. Accordingly, it goes without saying that the first element, first component, or first section mentioned below may be a second element, second component, or second section within the technical scope of the present invention.

[0065] The terms used herein are for describing the embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used herein, "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements.

[0066] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0067] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0068] In this specification, the horizontal direction may include a first horizontal direction (X direction) and a second horizontal direction (Y direction) that intersect each other. The direction intersecting the first horizontal direction (X direction) and the second horizontal direction (Y direction) may be referred to as the vertical direction (Z direction). In this specification, the vertical level may be referred to as a height level according to the vertical direction (Z direction) of any configuration.

[0069] A semiconductor memory device equipped with a pseudo-quantum circuit according to the present invention is implemented by applying a pseudo-qubit inside or outside a memory cell of the semiconductor memory device, thereby eliminating the need for environmental conditions such as ultra-low temperatures.

[0070] Furthermore, in the present invention, pseudo-qubits can be configured in the memory cells of a semiconductor memory device using a minimum amount of memory space, and quantum computation time can be reduced by using hardware and software when recovering desired data. In other words, the present invention enables the implementation of a quantum computer on an existing semiconductor chip (primarily memory) with almost no memory storage space.

[0071] Furthermore, in the present invention, by implementing a quantum gate using a pseudo-qubit, high-speed quantum computation and quantum functions (such as encryption) can be imparted to digital data stored in a memory cell.

[0072] The semiconductor memory device to which the present invention can be applied may be applied to DRAM, NAND, or SRAM type memory, and in the following description of the embodiments, a 3D NAND flash memory device having a plurality of memory cell planes in a 3D structure is mainly described as an example.

[0073] In this specification, the selected SSL (0), SSL (1), ..., SSL (K) among the string selection lines (SSL) means to specify a plurality of serially connected memory cells provided in the cell string included in the corresponding specified string selection line (SSL).

[0074] In addition, bit lines (BL(1) to BL(J)) connected to a data reader / writer can be connected to a memory cell provided in one selected memory cell plane, and at the same time, can be connected to a memory cell provided in another memory cell plane in a semiconductor memory device in which a plurality of memory cell planes are formed in a 3D structure.

[0075] Figures 1a and 1b attached are a schematic diagram and an equivalent circuit diagram, respectively, showing an example of applying a pseudo-qubit according to a preferred first embodiment of the present invention to a memory cell plane of a 3D NAND flash memory device.

[0076] Referring to FIG. 1a and FIG. 1b, the 3D NAND flash memory device (100) according to the present invention comprises a plurality of memory cell planes (Q#1 to Q#N) each having a memory array (MA) in which a plurality of memory cells arranged in a matrix are formed.

[0077] The above 3D NAND flash memory device (100) is integrated with a plurality of memory cell planes (Q#1 to Q#N) in a vertical direction in a three-dimensional (3D) structure as shown in FIG. 1a and FIG. 1b, and can be implemented using a silicon (Si) wafer.

[0078] In this case, instead of a structure in which a plurality of memory cells are formed in a matrix arrangement, the memory array (MA) may be composed of a plurality of memory cell blocks, each consisting of a plurality of memory cells.

[0079] The above 3D NAND flash memory device (100) may include a plurality of cell strings (18) formed between bit lines (BL(1) to BL(J)) and a common source line (CSL), as shown in FIG. 1b. The cell strings (18) may include a plurality of memory cells (12) connected in series.

[0080] The gate electrodes of a plurality of memory cells (12) included in one cell string (18) are each connected to different word lines (WL(1) to WL(N)). At both ends of the cell string (18), a ground selection transistor (14) connected to a ground selection line (GSL) and a string selection transistor (16) connected to string selection lines (SSL(0)-SSL(K)) may be disposed.

[0081] The ground selection transistor (14) and string selection transistor (16) control the electrical connection between a plurality of memory cells (12), bit lines (BL(1) to BL(J)) and a common source line (CSL).

[0082] In this case, the memory cell (12) connected to one word line (WL(1) to WL(N)) across the plurality of cell strings (18) can form a page unit or a byte unit.

[0083] A plurality of memory cell planes (Q#1 to Q#N) arranged vertically in the 3D NAND flash memory device (100) are each connected to one of the word lines (WL(1) to WL(N)), and a desired memory cell plane (Q#1 to Q#N) can be selected by a row decoder (10).

[0084] Additionally, each memory array (MA) of the plurality of memory cell planes (Q#1 to Q#N) includes a plurality of memory cells (12) arranged in a matrix, and when a specific memory cell among the plurality of memory cells (12) is designated and read, the read data is retrieved to a data reader / writer (30) through a plurality of bit lines (Bit Line; BL(1) to BL(J)).

[0085] The above data reader / writer (30) can perform the function of writing and erasing data for a specific memory cell selected through a plurality of bit lines (Bit Line; BL(1) to BL(J)).

[0086] Each of the above-mentioned plurality of memory cells (12) can be configured as an electrically eraseable and programmable read-only memory (EEPROM), for example, as a flash memory which is a type of non-volatile memory device, and can be used in various devices.

[0087] Each of the above-mentioned plurality of memory cells (12) can be implemented using, for example, a metal oxide semiconductor-based floating gate transistor (FGT), and can be designed to store one, two, three, or four data bits in the floating gate as needed.

[0088] Recently, instead of a floating gate, it can be produced using Charge Trap Flash (CTF) technology to store charge in the control gate, or by converting a single-layer CTF structure into a three-dimensional cylindrical Gate-All-Around (GAA) structure.

[0089] In addition, a 4D NAND flash memory has been proposed in which a PUC (Peripheral Under Cell) including a row and column decoder, a sense amplifier, and a controller circuit for selecting and controlling a memory cell that stores data is placed at the bottom of the memory cell in the CTF structure of a 3D NAND flash memory device, and as described below, the present invention can be applied not only to the 3D NAND flash memory presented as the first embodiment but also to the 4D NAND flash memory.

[0090] In the present invention, quantum functions are implemented by implementing pseudo qubits using all or part of the memory space inside a semiconductor memory device.

[0091] In the 3D NAND flash memory device (100) according to the present invention, N memory cell planes (Q#1 to Q#N) are planes connected to each word line (WL(1) to WL(N)) and store a plurality of digital bits.

[0092] The 3D NAND flash memory device (100) of the present invention corresponds all or part of these N memory cell planes (Q#1 to Q#N) to quantum qubits. In FIG. 1a and FIG. 1b, N words connected to all N memory cell planes (Q#1 to Q#N) corresponding to SSL (0) and SSL (1) can be used to represent N pseudo-qubits.

[0093] In this case, the embodiment illustrated in FIG. 1a and FIG. 1b can be divided into a first memory cell region (40) used to represent pseudo-qubits to impart quantum functions only to a memory array in which a plurality of memory cells of a first memory cell plane (Q#1) are formed in the uppermost layer among N memory cell planes (Q#1 to Q#N) of a 3D NAND flash memory device (100), and a second memory cell region (50) used to store classical digital data excluding the first memory cell region (40).

[0094] In this case, the first memory cell region (40) used to represent pseudo-qubits to impart the above quantum function can be applied not only to the first memory cell plane (Q#1) placed on the top layer among the N memory cell planes (Q#1 to Q#N), but also to all of the N memory cell planes (Q#1 to Q#N).

[0095] In the case of a 3D NAND flash memory device (100) according to the first embodiment of the present invention, a memory cell (i.e., string) of a first memory cell region (40) provided in a portion of a plurality of memory cell planes (Q#1 to Q#N) selected by a row decoder (10) is assigned to N quantum qubits, and the first three strings (i.e., SSL(0)-SSL(2)) of a plurality of string selection lines (SSL(0)-SSL(K)) of each selected memory cell plane (Q#1 to Q#N) are assigned to the data of the qubits (hereinafter, the string selection lines (SSL) are referred to as quantum SSL).

[0096] In the following description, the above SSL(0) and SSL(1) are abbreviated as SSL(0) and SSL(1) instead of quantum SSL(0) and quantum SSL(1).

[0097] In addition, in the present invention, if necessary, memory bits of bitlines (BL) other than SSL (0) and SSL (1) can also be assigned to similar qubits.

[0098] In the embodiment illustrated in FIG. 1a and FIG. 1b, SSL (0) is the I0> component of the qubit, and SSL (1) is the I1> component of the qubit. The magnitude (1 or less) of each I0> component and I1> component is represented by m digital bits. If it is necessary to represent the phase information of the qubit, it can be stored using SSL (3) in the above format.

[0099] The method illustrated in the embodiments shown in FIGS. 1a and 1b is just one example, and the size and phase of the I0> component and I1> component of the pseudo-qubit can be stored at any location in the NAND flash memory.

[0100] The above plurality of bit lines (BL(1) to BL(J)) are connected to a data reader / writer (30) for reading data stored in a plurality of memory cells and writing data.

[0101] In the case of a 3D NAND flash memory device (100) according to the first embodiment of the present invention, a memory cell (i.e., String) of a first memory cell region (40) provided in some or all of the memory cell planes (Q#1 to Q#N) connected to one of the word lines (WL(1) to WL(N)) and selected is assigned to N quantum qubits, and the first three strings (i.e., SSL(0) to SSL(2)) of the multiple string selection lines (SSL(0) to SSL(K)) of each selected memory cell plane (Q#1 to Q#N) are assigned to the data of the qubits.

[0102] In this case, it is also possible to assign an additional string selection line (SSL) to the data of the qubit, in addition to the first to third string selection lines (SSL(0)-SSL(2)).

[0103] All memory cell data not assigned to the above quantum SSL is ordinary classical digital data. SSL (0) can be assigned to the I0> component of the qubit, SSL (1) to the I1> component, and SSL (2) to the phase (φ) of the qubit. In many cases, SSL (2) can be omitted.

[0104] In the 3D NAND flash memory device (100) according to the first embodiment above, for example, after the first memory cell plane (Q#1) is selected by the word line (WL(0)), the first and second quantum string select lines (SSL(0), SSL(1)) to which qubit data is assigned can be selected by the string select line decoder (20).

[0105] In this case, the qubit data of the selected first and second quantum string selection lines (SSL(0), SSL(1)) can be extracted to a data reader / writer (30) through bit lines (BL(1) to BL(J)).

[0106] FIGS. 2a and FIGS. 2b are circuit diagrams of two-dimensional and three-dimensional DRAMs, respectively, comprising quantum data blocks (pseudo-qubits) in a memory cell according to a preferred second embodiment of the present invention.

[0107] FIG. 2a shows an example of allocating one pseudo-qubit using a 2D DRAM instead of the memory cell plane of the 3D NAND flash memory device (100) shown in FIG. 1a.

[0108] FIG. 2a is an example of a general two-dimensional DRAM (200) comprising M×N memory cells (MC) arranged in a matrix, wherein the memory cells (MC) can specify a particular memory cell by a plurality of word lines (WL(1) to WL(N)) selected by a word line decoder (210) and a plurality of bit lines (BL(1) to BL(N)) selected by a bit line decoder / encoder (220).

[0109] In this case, the bit line decoder / encoder (220) can read multiple data from the memory cell and then select and discharge them one by one.

[0110] Each of the above memory cells (MC) includes a switching transistor (TR) and a data storage capacitor (C).

[0111] The two-dimensional DRAM (200) according to a preferred second embodiment of the present invention is divided into a first memory cell region (i.e., a quantum data region) (230) containing a plurality of bit-line memory required to represent a plurality of qubits to provide quantum functions, and a second memory cell region (240) containing a plurality of bit-line memory cells used to store classical data excluding the first memory cell region (230).

[0112] In addition, the above 2D DRAM (200) can specify multiple bitline memories required to represent multiple qubits to provide quantum functions among the entire memory cell (MC).

[0113] Memory bit lines may be allocated for the number of digital bits (e.g., 8 bits or 16 bits) to indicate the respective sizes of I0> and I1>. In this case, N qubits are stored in FIG. 2a, and the number of classical bits of classical data is (M×N-2×q×N). Here, q represents the number of digital bits to indicate the respective sizes of I0> and I1>.

[0114] In addition, the present invention can also be applied to the three-dimensional DRAM (300) shown in FIG. 2b, similar to the first embodiment.

[0115] The three-dimensional DRAM (300) illustrated in FIG. 2b is implemented using a general three-dimensional DRAM and includes multilayer memory cell planes (Q#1 to Q#N) connected (selected) to each word line (WL(1) to WL(N)), and each memory cell plane (Q#1 to Q#N) has a plurality of memory cells (MC) consisting of a switching transistor (TR) and a data storage capacitor (C) arranged in a matrix.

[0116] A plurality of two-dimensional DRAM blocks (301-N) formed in each of the N memory cell planes (Q#1 to Q#N) are memory cell planes connected to word lines (WL(1) to WL(N)) selected by a word line decoder (310), and a plurality of memory cells (MC) provided in each memory cell plane (Q#1 to Q#N) can store a plurality of digital bits.

[0117] In this case, unlike the 3D NAND flash memory device (100) of the first embodiment, the plurality of 2D DRAM blocks (301-N) are each equipped with a World Line Decoder (310) and a Bit Line Decoder / Encoder (320), and data can be read and written by designating each memory cell (MC) of the plurality of 2D DRAM blocks (301-N) by the World Line Decoder (310) and the Bit Line Decoder / Encoder (320).

[0118] A three-dimensional DRAM (300) according to the second embodiment of the present invention may include a quantum data block (pseudo-qubit) that corresponds all or part of N memory cell planes (Q#1 to Q#N) to quantum qubits.

[0119] A two-dimensional DRAM block (301) implemented in the uppermost first memory cell plane (Q#1) includes a first memory cell (330) with two lines required to represent one qubit to provide quantum functions in a memory array (MA) in which a plurality of memory cells (MC) are formed, and a second memory cell region (340) including a plurality of lines of memory cells used to store Classical Data excluding the first memory cell (330).

[0120] For example, after the first memory cell plane (Q#1) is selected by the word line (WL(0)) in the first memory cell (330), the first and second quantum string select lines (SSL(0), SSL(1)) to which qubit data is assigned can be selected by a string select line decoder (not shown).

[0121] Among the multiple memory cells (330) of the two lines above, the area of ​​the first quantum string selection line (SSL(0)) can be assigned to I0>, and the area of ​​the second quantum string selection line (SSL(1)) can be assigned to I1>.

[0122] In addition, in the second embodiment of the present invention illustrated in FIG. 2b, the memory bit stored in the first memory cell (330) can be input to the pseudo-qubit, and the result of the quantum calculation of the pseudo-qubit circuit can also be stored.

[0123] That is, for quantum gate operations, input is required and output must also be stored. In the present invention, this is not executed through external memory, but can be used after being stored in a second memory cell area (340) where classical data is stored nearby.

[0124] The above-described data processing method can be applied in the same way to the 3D NAND flash memory device (100) shown in FIG. 1a.

[0125] The aforementioned capability can fundamentally resolve the problem of the Memory Wall (i.e., speed delay caused by communication between the computation chip and the memory chip), which is a speed limiting factor in computation.

[0126] The method according to the second embodiment above is just one example, and quantum functions can be assigned from pseudo-qubits existing at other locations in the DRAM memory.

[0127] The embodiment structure applied to add quantum functions to the 3D NAND flash memory device (100) and DRAM (200, 300) shown in FIGS. 1a to 2b above can be equally applied to other memories such as DRAM or SRAM of other structures.

[0128] In this case, one of the N memory cell planes (Q#1 to Q#N) of the 3D NAND flash memory device (100) may correspond to one of the memory blocks among the plurality of memory blocks provided in a 2D structure in DRAM and SRAM. Therefore, N memory blocks may be required to implement N qubits.

[0129] FIGS. 3a and FIGS. 3b are a schematic configuration diagram and a functional block diagram, respectively, of a 3D NAND flash memory device having a quantum processor block for recovering data of a quantum state from a pseudo-qubit according to a preferred third embodiment of the present invention.

[0130] Referring to FIG. 3a and FIG. 3b, the 3D NAND flash memory device (100a) according to the third preferred embodiment of the present invention is identical to the D NAND flash memory device (100) according to the first embodiment except that it is equipped with a quantum processor block (60) for recovering data of a quantum state from a pseudo-qubit.

[0131] Accordingly, when describing the third embodiment illustrated in FIG. 3a and FIG. 3b, the same reference numerals are used for components identical to those in the first embodiment, and redundant descriptions thereof are omitted.

[0132] The 3D memory (110) shown in FIG. 3b represents a multilayer structure memory cell provided in the 3D NAND flash memory device (100) shown in FIG. 1.

[0133] The 3D NAND flash memory device (100a) according to the third preferred embodiment of the present invention illustrated in FIG. 3a may have a Quantum Processor Block (60) provided at the top of the 3D memory device (110) or outside the 3D memory device (110) to recover quantum data from pseudo-qubits in the 3D NAND flash memory device (100) in which pseudo-qubits are applied to the memory cell plane illustrated in FIG. 1a.

[0134] The above quantum processor block (60) can have up to 2 qubits from N qubits. N It performs a scrambler function to replay quantum state data and has the following capabilities.

[0135] First, 2 if necessary N Calculate the quantum data of the quantum room. In many cases, the quantum circuit is 2 NRequests the following number of quantum room data.

[0136] Second, in order to calculate the data for each quantum room, 2 N Performs operations n times.

[0137] Third, the operation has the function of selecting the 'SSL(0) and SSL(1) of each qubit' corresponding to each quantum room, and performing operations such as multiplying and adding the selected qubits.

[0138] The above quantum processor block (60) can be controlled by communicating with each control circuit block of the 3D memory element (110) as shown in FIG. 3b to perform quantum functions.

[0139] Additionally, the above-mentioned quantum processor block (60) can basically contain quantum circuit information composed of quantum gates and can implement a quantum function in hardware and / or software to obtain data of a result quantum circuit or a result value of a qubit from the quantum circuit.

[0140] Furthermore, the quantum processor block (60) has a quantum gate function of a qubit, and from the data of N qubits 2 N It may include an algorithm that includes a computational order necessary to compute data for quantum rooms (or fewer quantum rooms as needed).

[0141] Below, from the 'pseudo-qubits' assigned to SSL (0) and SSL (1) in the 3D NAND flash memory device (100a) according to the third embodiment, a desired number (e.g., 2 N Explains how to obtain data for the quantum states of the number of quantum states.

[0142] Referring to FIG. 3a and FIG. 3b, the 3D NAND flash memory device (100a) according to the third embodiment can first control the row decoder (10) under the control of the quantum processor block (60) to select, for example, the first memory cell plane (Q#1) by the word line (WL(1)), and then select the first and second quantum string select lines (SSL(0), SSL(1)) to which qubit data is assigned by the string select line decoder (20).

[0143] The qubit data of the selected first and second strings (SSL(0), SSL(1)) is then extracted to a data reader / writer (30) through bit lines (BL(1) to BL(J)).

[0144] Qubit data extracted by the above data reader / writer (30) can be stored in a second memory cell area (50) used to store classical digital data through the above data reader / writer (30) after quantum calculation is executed in the quantum processor block (60).

[0145] In other words, in principle, the quantum room generated by N qubits is 2 N The memory required to store quantum room data is 2 N Although it is a large number, the required memory can be reduced by using the algorithm of the Quantum Processor Block (60).

[0146] To this end, in the present invention, instead of storing all quantum rooms generated by N qubits from the beginning of the quantum computation, memory space can be reduced by obtaining the desired quantum room data through shifting or circling the memory locations of the I1> and I0> components for each qubit whenever it passes through a quantum gate in each circuit computation.

[0147] For example, in the present invention, when storing quantum states, in order to implement 8 quantum states of 3 qubits, the necessary quantum states may be extracted only when needed with 3 circle clocks, without storing them in memory in advance.

[0148] This processing method will be explained in detail with reference to FIGS. 4b and FIGS. 6b.

[0149] FIGS. 4a and FIGS. 4b each illustrate an example of obtaining data of quantum rooms (000) and (010) from three pseudo-qubits according to a preferred fourth embodiment of the present invention, FIG. 4a shows the quantum rooms and data using three pseudo-qubits, and FIG. 4b is an explanatory diagram showing the flow of qubit data inside a memory block to obtain data of quantum rooms from three pseudo-qubits.

[0150] Referring to FIGS. 4a and 4b, a method for obtaining quantum room data from three pseudo-qubits according to the present invention is described.

[0151] Figure 4a shows the quantum states and corresponding data generated in a 3-qubit system.

[0152] In Fig. 4a, f(a1,a2,a3), f(b1,b2,b3), etc. are represented as a1×a2×a3 and b1×b2×b3, respectively, during the initial input stage of the quantum circuit.

[0153] The example of the data flow shown in Fig. 4b represents the case of obtaining data for two quantum rooms (000) and (010).

[0154] For the quantum state (000), the above quantum processor block (60) multiplies SSL(i,0)(i=1,2,3) connected to the same bit line (see left arrow flow), and for the data of the quantum state (010), it multiplies SSL(1,0)×SSL(2,1)×(SSL(3,0)) (see right arrow flow).

[0155] Determining this order is an important function of the above-mentioned Quantum Processor Block (60). Instead of storing the data of all the above-mentioned quantum rooms separately, the data of the necessary quantum rooms can be calculated and used for each quantum circuit gate step.

[0156] FIGS. 5A and FIGS. 5B are symbol diagrams showing the application of a Hadamard gate (H gate) to a qubit Q#i in a 3D NAND flash memory device in which a single bit pseudo-qubit is applied to a memory cell plane, and a flowchart showing a method for obtaining data of the corresponding qubit quantum room.

[0157] First, the i-th memory cell plane (Q#i) is specified, and Qi is selected to read the SSL (0) and SSL (1) components of the corresponding qubit (S10, S11).

[0158] Next, quantum gate calculations are performed. In the case where the quantum gate is a Hadamard gate (H gate), the quantum gate calculation is carried out as shown in the following Equations 1 and 2:

[0159]

[0160]

[0161] After the above quantum gate calculation is performed, the contents of the corresponding qubits are refreshed by writing New SSL (0) and New SSL (1) in the refresh cycle (S12).

[0162] At this time, the contents of the other qubits do not change.

[0163] This applies equally to the Pauli gate as well, as it is a gate that receives a single input (qubit) rather than the Hadamard gate.

[0164] When the i-th qubit (Q#i) to which a Hadamard gate is applied is a qubit that constitutes a quantum circuit composed of multiple qubits, when finding the quantum room of the quantum circuit, a superposition state similar to Equation 1 and Equation 2 must be calculated for the two quantum rooms containing the qubit (Q#i).

[0165] For example, in the case of a 3-qubit circuit as shown in Fig. 4b, if a Hadamard gate is applied to Q#2 (i.e., i=2), the data of the new quantum room is calculated as shown in the following Equations 3 and 4.

[0166]

[0167]

[0168] For the above-mentioned operation, as shown in FIG. 5a, a control circuit having a separate read / quantum operation / write back function can be fused within a quantum processor block (60) on the uppermost memory cell plane (Q#1) or positioned to be connected to a circuit at another location.

[0169] In FIGS. 5a and 5b above, a single Hadamard gate (H gate) is illustrated as a quantum gate, but the present invention is not limited thereto and may apply other quantum gates or quantum circuits including multiple quantum gates.

[0170] When constructing a quantum circuit according to the present invention, applicable gates include Pauli Transformation gates, Rotation gates, and Hadamard gates for receiving one input (qubit), CNOT gates and SWAP gates for receiving two inputs, and Toffoli gates and Fredkin gates for receiving three inputs, and a quantum circuit can be constructed by any one of these or a combination thereof as needed.

[0171] FIGS. 6a and FIGS. 6b are plan views showing a symbol of a CNOT gate representing quantum entanglement controlled by a quantum processing block in a 3D NAND flash memory device according to the present invention and a data flow for obtaining quantum room data from three pseudo-qubits, respectively.

[0172] FIG. 6c is an explanatory diagram illustrating the operation of a quantum gate and the operation of quantum operations on quantum data when two qubits are entangled with a CNOT quantum gate in a 3-qubit system according to the present invention.

[0173] With reference to FIGS. 6b and 6c below, the operation of a CNOT quantum gate from qubit #2 to qubit #3 and the operation of quantum operations on quantum data are explained when two qubits are entangled in a 3-qubit system according to the present invention.

[0174] First, among the 8 quantum rooms from I000> to I111>, the quantum room (000) and (010) to be obtained are selected, and a data storage location is allocated for each quantum room. In this case, the data storage location of the quantum room can use internal or external memory within the same 3D memory block (S21).

[0175] Next, when calculating quantum room data, if the SSL (0) of Q#2 is multiplied as in quantum room (000) or (001), the SSL (0) and SSL (1) of Q#3, which are the next terms to be multiplied, are multiplied without change. However, if the SSL (1) of Q#2 is multiplied as in quantum room (010), the SSL (0) and SSL (1) of Q#3 are swapped and multiplied. (S22)

[0176] If you follow the arrows to the positions of SSL(0) and SSL(1) of the corresponding qubits used to calculate the quantum room, you can see that the SSL(0) of qubit #3 is multiplied by the SSL(1) of qubit #2. In this case, the SSL(0) and SSL(1) of qubit #3 are swapped.

[0177] When the SSL(0) and SSL(1) data of qubit #3 is replayed, if it is multiplied with the SSL(1) of qubit #2, the SSL(0) and SSL(1) of qubit #3 are swapped. That is, the data of the (010) quantum room is changed from SSL(0)×SSL(1)×SSL(0) to SSL(0)×SSL(1)×SS(1).

[0178] In the operation illustrated in Fig. 6b, for the CNOT gate, the SSL (0) and SSL (1) of the corresponding qubit #3 subjected to CNOT cannot be refreshed independently, and only affect the data calculation of the corresponding quantum room (010), (011), (110), (111).

[0179] After the above operation is performed, the multiplication result is recorded in the allocated quantum data storage location (S23).

[0180] FIG. 7 is an explanatory diagram for describing another method of assigning quantum data by specifying arbitrary SSL(m) and SSL(m+1) in a second memory cell area that stores digital data, instead of assigning an I0> component to the area of ​​the first quantum string selection line (SSL(0)) of a first memory cell area (quantum memory area) and an I1> component to the area of ​​the second quantum string selection line (SSL(1)) to represent each qubit to represent a pseudo-qubit.

[0181] Referring to FIG. 7, in the present invention, when there is a need to bring data from an external source or transfer data from digital data stored in a second memory cell area (50) of the same memory cell plane to input SSL(0) and SSL(1) of each qubit in order to give quantum functions, the data can be input quickly without the need for programming and data transfer by simply converting the SSL(m) and SSL(m+1) where the data is stored into SSL(0) quantum data.

[0182] By assigning SSL (0) and SSL (1) to the desired digital data location of the second memory cell area (50) of the 3D NAND flash memory device (100) in this way, the degradation phenomenon caused by programming repetition, which is a weakness of the NAND flash memory device, can be reduced.

[0183] Of course, the control circuit of the quantum processor block (60) is responsible for the position change of SSL (0) and SSL (1). Additionally, by changing SSL (0) and SSL (1), the quantum data I0> and I1> can be changed without changing the contents of the actual memory cell.

[0184] FIG. 8 is an explanatory diagram for explaining a method of allocating data of qubits to a 3D NAND flash memory device in a manner different from the first embodiment according to the present invention.

[0185] As shown in FIG. 1a, the 3D NAND flash memory device (100) according to the present invention comprises a plurality of memory cell planes (Q#1 to Q#N) each having a memory array (MA) in which a plurality of memory cells are formed.

[0186] In this case, multiple memory cell planes (Q#1 to Q#N) are memory cell planes connected to word lines (WL(1) to WL(N)).

[0187] Referring to FIG. 8, when allocating quantum data to represent pseudo-qubits, instead of mapping a desired single word line plane (W(i)) to a qubit (Qubit(i)), SSL(0), SSL(1)…SSL(K) are mapped to Q(1), Q(2)…Q(K+1), and W(1) and W(2) of the word line plane (i=1…N) are mapped to SSL(0) and SSL(1) of the qubits.

[0188] In this case, the data in the word line plane for i>3 is usually used to store digital data.

[0189] To read the data of Qi, after selecting SSL (i-1), W (1) is selected, and the J-bit data of the I0> component of qubit i (corresponding to SSL (0) in FIG. 1a) is output to the Data Reader / Writer (30) (see FIG. 1a).

[0190] Likewise, for I1> of Q(i), select W2.

[0191] Whether to choose a structure / method for allocating data of the qubits in Fig. 1a or Fig. 8 depends on the properties of the given quantum circuit. That is, depending on the quantum circuit, a choice can be made that is advantageous for computational efficiency and memory allocation.

[0192] The present invention provides a method for easily implementing data encryption or quantum AI by fusing quantum data of qubits with existing digital data. That is, by imposing the quantum characteristics of qubits on existing digital data, it can be used for quantum cryptography.

[0193] In addition, in the present invention, by using or storing existing digital data as the input and output of a quantum gate, quantum computation can be performed quickly and efficiently within a memory chip without the need to retrieve data from an external source or transmit data to an external device for the input and output of quantum computation.

[0194] Furthermore, the present invention shows that in a 3D NAND flash memory device in which pseudo-qubits are applied to a memory cell plane, the sizes of 1 and 0 of the qubits are stored in SSL (1) and SSL (0), and data encryption can be realized by fusing quantum data and digital data.

[0195] Although the present invention has been illustrated and described above with reference to specific preferred embodiments, the present invention is not limited to the embodiments described above, and various changes and modifications may be made by those skilled in the art without departing from the spirit of the invention.

[0196] The semiconductor memory device having quantum functions according to the present invention can be applied to 3D NAND flash memory, DRAM or SRAM-type memory.

[0197] In this invention, by doing so, many functions of a traditional quantum computer are implemented in classical memory, thereby enabling the hybrid implementation of quantum-classical computation and storage functions.

Claims

1. A memory array is provided, which is stacked in a three-dimensional (3D) structure and has a plurality of memory cells formed therein, wherein the plurality of memory cells form a plurality of memory cell planes connected in series to form a plurality of strings; A row decoder for selecting at least one of a plurality of word lines each connected to the plurality of memory cell planes to designate at least one memory cell plane among the plurality of memory cell planes; A data reader / writer for reading data stored in a memory cell included in the specified string through a plurality of bit lines and writing data when one of the plurality of strings is specified; and A string selection line decoder for designating any first and second quantum strings among the plurality of strings to respectively assign the I0> component and I1> component of a pseudo-qubit; comprising When the above plurality of word lines select a plurality of memory cell planes, the number of pseudo-qubits is set according to the number of selected memory cell planes, and A semiconductor memory device having a pseudo-quantum circuit that forms at least one virtual quantum gate for executing a quantum operation on the extracted qubit data when pseudo-qubit data stored in a plurality of memory cells included in the first and second quantum strings is selected and the selected qubit data is extracted to the data reader / writer connected to the bit line.

2. In Paragraph 1, A semiconductor memory device having a pseudo-quantum circuit that stores one qubit in each of the plurality of memory cell planes and allocates N qubits to N memory cell planes.

3. In Paragraph 1, The above cell selection line decoder is a semiconductor memory device having a pseudo-quantum circuit for assigning a third cell string for assigning the phase Iφ> component of the above pseudo-qubit.

4. In Paragraph 1, A semiconductor memory device having a pseudo-quantum circuit in which each of the above plurality of memory cell planes is divided into a first memory cell region for representing pseudo-qubits and a second memory cell region for storing digital data.

5. In Paragraph 1, A semiconductor memory device having a pseudo-quantum circuit that is provided at the top of the plurality of memory cell planes or outside the semiconductor memory device, and further includes a quantum processor block for obtaining quantum data from a pseudo-qubit.

6. In Paragraph 1, The above quantum processor block is Control the above row decoder to select at least one memory cell plane by a word line, and Selecting the first and second quantum string selection lines to which qubit data is assigned by the string selection line decoder above, and A semiconductor memory device having a pseudo-quantum circuit that performs quantum operations on extracted qubit data when qubit data of the first and second strings specified by selected first and second quantum string selection lines is extracted to a data reader and writer connected to a bit line.

7. In Paragraph 1, A semiconductor memory device comprising quantum states created by a pseudo-quantum circuit that performs quantum operations on the extracted qubit data, and a pseudo-quantum circuit that obtains quantum state data stored in the quantum states.

8. In Paragraph 1, The above semiconductor memory device is a semiconductor memory device equipped with a pseudo-quantum circuit that is either a 3D NAND flash memory device or a 3D DRAM.

9. A semiconductor memory comprising a memory array stacked in a three-dimensional structure and having a plurality of memory cells formed therein, wherein the plurality of memory cells form a plurality of memory cell planes that are connected in series to form a plurality of strings; a row decoder for selecting at least one of a plurality of word lines connected to each of the plurality of memory cell planes to designate at least one of the plurality of memory cell planes; a data reader / writer for reading data stored in a memory cell included in a designated string through a plurality of bit lines and writing data when one of the plurality of strings is designated; a string selection line decoder for designating any first and second quantum strings among the plurality of strings to assign the I0> component and I1> component of a pseudo-qubit, respectively; and a quantum processor block for controlling to form at least one virtual quantum gate that executes a quantum operation on the extracted qubit data when pseudo-qubit data stored in a plurality of memory cells included in the first and second quantum strings is selected and the selected qubit data is extracted to the data reader / writer connected to the bit line. Step of preparing the device; Quantum states created by a pseudo-quantum circuit that executes quantum operations on the qubit data by the above quantum processor block, and the step of assigning quantum state data to the quantum states; and A method for establishing a pseudo-quantum circuit of a semiconductor memory device, comprising the step of performing a quantum operation while passing through the virtual quantum gate and extracting the result when extracting quantum room data assigned to the quantum room by the quantum processor block.

10. In Paragraph 9, A method for establishing a pseudo-quantum circuit of a semiconductor memory device in which at least one virtual quantum gate forms a virtual quantum circuit.

11. In Paragraph 9, A method for establishing a pseudo-quantum circuit of a semiconductor memory device that performs a second quantum operation on quantum operation data extracted through the data reader / writer, using the above quantum processor block.

12. In Paragraph 9, A method for setting a pseudo-quantum circuit of a semiconductor memory device in which the number of pseudo-qubits is set according to the number of selected memory cell planes when the above-mentioned plurality of word lines select a plurality of memory cell planes.

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