System for monitoring the change in a value of at least one operating parameter of a device, corresponding method and program

Abstract

The invention relates to a system (10) for monitoring the change in at least one value associated with an operating parameter of a device (DUS) generating and / or encountering electromagnetic interference, the system comprising: - an acquisition module (300) for acquiring data representative of values associated with the parameter to be monitored, the acquisition module comprising at least one sensor (100), at least one analog-to-digital converter (101) associated with the at least one sensor, an optical transceiver (102), and an optical multiplexer (103); - a collection device (301) for collecting data representative of the values associated with the parameter to be monitored, comprising: an optical multiplexer (107), an optical transceiver (108), and a processing module (109) for processing the data representative of the values associated with the parameter to be monitored, the processing module (109) comprising at least one portion in the form of an FPGA (109-1) and at least one portion in the form of a processor (109-2); - an optical fiber (205) connecting the multiplexer (103) of the acquisition module and the multiplexer (107) of the collection device.

Description

[0001] DESCRIPTION

[0002] Title: System for monitoring the evolution of a value of at least one operating parameter of a device, process and corresponding program

[0003] technical field

[0004] The disclosure relates to a system for monitoring parameter values ​​related to the operation of a device or system. More specifically, the disclosure relates to a system for monitoring parameter values ​​related to the operation of a device or system operating at high frequencies, for example, in an environment experiencing and / or generating electromagnetic fields.

[0005] Previous art

[0006] Many technical systems rely on the implementation of high-frequency signals. Technical systems generating high-frequency signals that are difficult to monitor, detect, or capture with current technologies are numerous and varied. They cover a wide range of applications, from telecommunications and scientific research to medicine and defense.

[0007] For example, in the telecommunications sector, 5G and higher-frequency communication systems present operational monitoring challenges. These networks utilize very high frequencies, including millimeter waves, which pose problems for measuring and monitoring the systems themselves. Similarly, satellite telecommunications systems, with their very high-frequency uplink and downlink signals, are complex to monitor accurately.

[0008] In military and security applications, high-resolution radars also present challenges. These devices, operating at very high frequencies to achieve greater resolution, generate signals that are difficult to characterize precisely. Similarly, directed-energy weapon systems, which use very high-frequency electromagnetic waves, pose comparable challenges in terms of monitoring their operating parameters.

[0009] In the field of scientific research, particle accelerators also pose problems. These systems produce very high-frequency electromagnetic fields, and their operating parameters are complex to measure without disturbing the system itself or being affected by it.

[0010] In the medical field, some advanced imaging technologies use very high frequency signals which pose difficulties for real-time monitoring of systems implementing these imaging technologies.

[0011] In all these systems, the problems are similar: the limited bandwidth of the measuring instruments, the parasitic effects (on these instruments) introduced by the technologies implemented in these systems, and the difficulty of sampling extremely fast signals without degrading them. All of these constraints, imposed on a single system, pose technological problems that must be overcome. Furthermore, existing monitoring systems are expensive, require complex and bulky technologies, and are not necessarily suitable for embedded or long-distance monitoring.

[0012] Moreover, particularly in disturbed environments, monitoring changes in parameter values ​​in such systems can prove complex, especially due to electromagnetic disturbances themselves, particularly for time-sensitive applications, where corrective measures must be implemented as soon as possible when one of the monitored parameter values ​​deviates from predetermined ranges.

[0013] Therefore, it is necessary to have monitoring solutions for the operating parameters of these systems that are efficient, less complex and less expensive to implement than existing solutions, and that offer satisfactory possibilities for processing such data.

[0014] Disclosure provides a solution to this problem.

[0015] Summary of the invention

[0016] More specifically, the disclosure relates to a system for monitoring the evolution of at least one associated value of an operating parameter of a device that generates and / or encounters electromagnetic disturbances.According to the disclosure, such a system includes: a data acquisition module representing values ​​associated with the parameter to be monitored, the acquisition module comprising at least one sensor, at least one analog-to-digital converter associated with said at least one sensor, an optical transceiver and an optical multiplexer; a data collection device representing values ​​associated with the parameter to be monitored, comprising: an optical transceiver and a data processing module representing values ​​associated with the parameter to be monitored, the processing module comprising at least one part in the form of an FPGA and at least one part in the form of a processing processor; Optionally an optical multiplexer may be present; an optical fiber connecting the multiplexer of the acquisition module and the multiplexer of the collection device.

[0017] Thus, data disclosure enables the measurement and / or monitoring of a large number of high-frequency signals from multiple sensors. The disclosure system centralizes this extensive data into a single device (improving usability), which can process it simultaneously—essential for high-frequency signals and time-sensitive applications. Furthermore, the optical medium used to transmit signals from the acquisition module(s) to the data collection device is fiber optics, eliminating the risk of electromagnetic (EM) interference encountered with conventional copper cables.

[0018] According to a particular characteristic, the processing module of the collection device is in the form of an integrated electronic module combining an FPGA and at least one processor.

[0019] According to a particular characteristic, the processing module is configured to receive a master clock signal from a clock signal generation module and to generate at least one drive clock signal from said module, at least one analog-to-digital converter of the acquisition module.

[0020] According to a particular feature, at least one clock signal for driving at least one analog-to-digital converter of the acquisition module is multiplexed within a signal transmitted to the acquisition module via optical fiber. According to a particular feature, at least one clock signal for driving at least one analog-to-digital converter of the acquisition module is generated by the FPGA portion using at least one phase-locked loop.

[0021] According to a particular feature, the part in the form of an FPGA is configured to perform oversampling of said at least one drive clock signal intended for said at least one analog-to-digital converter of the acquisition module before its transmission to said optical transceiver of the collection device.

[0022] According to a particular feature, the part in the form of an FPGA is arranged to perform amplitude shift modulation of said at least one control clock signal intended for said at least one analog-to-digital converter of the acquisition module, before transmission of this signal to said optical transceiver of the collection device.

[0023] According to a particular characteristic, the acquisition module is at least partially in the form of an electronic module comprising a multilayer electronic circuit board configured to preserve the integrity of electrical signals originating from or destined for said at least one analog-to-digital converter.

[0024] According to a particular feature, the acquisition module includes an enclosure for protection against electromagnetic interference of said at least one analog-to-digital converter of said optical transceiver and of said optical multiplexer.

[0025] According to a particular feature, the processing module of the collection device is configured to emit a signal representative of an alarm when a current value associated with the operating parameter of the device is different from an expected value.

[0026] According to a particular characteristic, the processing module of the collection device is configured to transmit all or part of the data collected from said acquisition module to a remote processing device via a communication interface.

[0027] According to a preferred implementation, the various steps of the processes according to this disclosure are implemented by one or more software or computer programs, including software instructions intended to be executed by a data processor of a collection device to control the execution of the various steps of the processes, implemented at the level of the collection device, a remote server and / or a resource consumption management / monitoring system or communicating objects, within the framework of a distribution of the processing to be carried out and determined by a scripted source code or a compiled code.

[0028] Consequently, the present technique also aims at programs, capable of being executed by a computer or by a data processor, these programs comprising instructions to control the execution of the steps of the processes as mentioned above.

[0029] A program can use any programming language, and be in the form of source code, object code, or code somewhere between source code and object code, such as in a partially compiled form, or in any other desirable form.

[0030] The present technique also aims at an information support readable by a data processor, and containing instructions of a program as mentioned above.

[0031] The information medium can be any entity or terminal capable of storing the program. For example, the medium can include a storage means, such as a ROM, for example a CD ROM or a microelectronic circuit ROM, or a magnetic recording means, for example a mobile medium (memory card) or a hard drive or an SSD.

[0032] On the other hand, the information medium can be a transmissible medium such as an electrical or optical signal, which can be transmitted via an electrical or optical cable, by radio, or by other means. The program according to this technique can, in particular, be downloaded from a network such as the Internet.

[0033] Alternatively, the information carrier may be an integrated circuit in which the program is incorporated, the circuit being adapted to execute or to be used in the execution of the process in question.

[0034] In one embodiment, this technique is implemented using software and / or hardware components. In this context, the term "module" may refer in this document to a software component, a hardware component, or a set of hardware and software components.

[0035] A software component corresponds to one or more computer programs, one or more subroutines of a program, or more generally to any element of a program or software capable of implementing a function or set of functions, as described below for the module in question. Such a software component is executed by a data processor of a physical entity (terminal, server, gateway, set-top box, router, etc.) and is capable of accessing the hardware resources of that physical entity (memory, storage media, communication buses, input / output electronic cards, user interfaces, etc.).

[0036] Similarly, a hardware component corresponds to any element of a hardware assembly capable of implementing a function or set of functions, as described below for the module in question. This could be a programmable hardware component or one with an integrated processor for software execution, for example, an integrated circuit, a smart card, a memory card, an electronic board for running firmware, etc.

[0037] Each component of the system described above naturally implements its own software modules.

[0038] The different embodiments mentioned above can be combined with each other for the implementation of this technique.

[0039] Brief description of the figures

[0040] Other purposes, features and benefits of the disclosure will become clearer upon reading the following description, given as a simple illustrative example, and not limiting, in relation to [fig. 1] illustrating the different components of the system according to this disclosure.

[0041] Description of a method of implementation

[0042] As previously explained, the disclosure relates to a remote sensor communication system using a single bidirectional optical link. The system comprises an acquisition module and a data collection device interconnected by a single optical fiber (single-mode or multimode). The acquisition module integrates an analog transducer coupled to a direct-sampling analog-to-digital converter (ADC). The ADC incorporates an optical transceiver compatible with the JESD204 serial interface. The data collection device includes a data collection unit and a corresponding optical transceiver, as well as JESD204 interface circuitry and a digital signal processing unit. The single optical fiber carries the digitized sensor data, the sampling clock signal, and the JESD204 synchronization signal bidirectionally. Wavelength multiplexing (WDM) is implemented to combine these signals on the fiber.The acquisition module's transceiver uses a vertical cavity laser (VCSEL) for data transmission. A photodetector recovers the clock and synchronization signals. However, for requirements of eight receive / transmit channels or fewer, a QSFP-DD connector assembly with fiber optics can also be implemented. On the processing module side (FPGA / processor), a tunable laser generates the optical carriers for clock and synchronization, and oversampling is performed by the FPGA, as explained later. An optical demultiplexer separates the different wavelengths. The JESD204 protocol is used to format the digitized data, enabling high-speed serial transmission without additional protocol overhead. Clock and data overlap is ensured by the integrated features of the JESD204 interface.This single-fiber architecture simplifies interconnection while preserving galvanic and electromagnetic isolation between the remote sensor and the centralized processing unit.

[0043] In relation to Figure 1, the monitoring system 10 comprising remote sensors using a single digital photonic link, notably based on the JESD204 high-speed serial communication protocol, is described.The main elements of the disclosure system 10 are thus: a remote acquisition module 300 comprising: a sensor 100; an analog-to-digital converter ADC 101 located near the sensor 100; a high-speed transmission interface for transmitting the digitized data; an optical connection between the acquisition module 300 and a collection device 301, the optical connection being implemented via a single optical fiber 205; a collection device 301 comprising: a receiving interface for receiving and transmitting data from the optical connection; a processing device for processing the digitized data, the processing device including in particular the SoCFPGA type processing module 109.

[0044] Thus, by using analog-to-digital converters 101 with the JESD204 serial interface, the inventors determined that it was possible to implement a long-range monitoring system 10 fully connected by an optical link 205. According to the disclosure, optical multiplexing (optional) is used to provide several clock, synchronization and / or control signals for sampling the ADC 101. Such multiplexing is implemented, for example, for applications in which the number of JESD transmission channels (and therefore indirectly of sensors) would exceed the capabilities of multi-channel optical transceivers (for example, a QSFP-DD transceiver supports 8 RX / TX channels; in this case, it is possible to monitor up to eight signals without requiring an additional optical multiplexing module).The sampled data from the output CAN 101 is transmitted via optical fiber 205 and routed to the remote, centralized data acquisition unit 301 for collection and analysis. Furthermore, the signals are multiplexed onto a single optical fiber 205. The resulting all-optical fiber 205 connection between the acquisition module 300 and the data acquisition unit 301 is immune to electromagnetic interference and can also be more easily implemented in applications with limited size and power. Moreover, in other systems, such as avionics or space systems, this implementation drastically reduces the weight of existing systems that use numerous copper lines. For example, data from several hundred sensors carried over tens or hundreds of meters can be transmitted via a fiber optic system like the one shown.

[0045] Consequently, this disclosure includes several key points for the real-time monitoring of a system such as those described previously, for example, for the rapid detection of faults in signal synchronization, such as the control signals of these systems. At the heart of this solution is the use of a FPGA-SoC (Field-Programmable Gate Array - System on Chip) processing module. This technological choice by the inventors combines the timing accuracy of an FPGA with the functional flexibility of a microprocessor, all integrated onto a single circuit. This approach makes it possible to achieve both high processing performance and high adaptability to the specific characteristics of systems generating EM disturbances. An important aspect is also the early digitization of high-frequency signals.By placing the analog-to-digital converters (ADCs) 101 as close as possible to the sensor probes 100, the system 10 minimizes the risk of interference and signal degradation. This approach is complemented by the use of the JESD204 protocol for data transmission between the ADC 101 and the FPGA-SoC platform 109, enabling efficient signal serialization. Furthermore, an optical oversampling mechanism allows the low-frequency drive signals and high-frequency acquisition signals to be combined onto a single fiber 205, thus greatly reducing the complexity and cost of the system 10. According to this disclosure, in an illustrative and non-limiting scenario, oversampling could consist of transmitting two high-frequency clock signals (e.g., a few GHz, e.g., 2 GHz) from the FPGA to the acquisition module.A clever clock phase shifting technique is implemented to reconstruct, on the acquisition module side, using an XOR logic gate, a low logic state "0" if the two clocks are in phase (the XOR gate sees 0 / 0 and 1 / 1) and a high logic state "1" if the two clocks are 180° out of phase (in opposition, the XOR gate sees 0 / 1 and 1 / 0). This solution advantageously allows for maintaining a compact acquisition module. Figure 2 schematically illustrates how this oversampling is implemented in a typical configuration. In this system, two clocks, Hr (reference clock) and Hd (out-of-phase clock), are generated within the processing unit (FPGA portion). These clocks operate at high frequencies, typically between 1 and 10 GHz. In the example, these two clock signals have a duty cycle of 50%, meaning that the signal is high for half the time and low for the other half.A controlled phase shift (DePh) between Hr and Hd is implemented. We use two phase shift states: 0° and 180°. When Hd is in phase with Hr (0° phase shift), this corresponds to a logic level 0 of the raw signal being processed. Conversely, when Hd is out of phase with Hr (180° phase shift), this represents a logic level 1 of the raw signal. This phase shifting technique is advantageous for processing these microwave signals. It allows information to be encoded directly in the signal phase, which can improve transmission robustness against interference and noise. To achieve this phase shift, we use phase-locked loops (PLLs), for example, integrated into the FPGA. These PLLs allow us to adjust the phase shift between the clocks.The two high-frequency clock signals, Hr and Hd, generated in the FPGA, are transmitted to the onboard acquisition board via the SFP optical transmitter. The recovery of the raw LF / DC signal relies on a phase comparison method for the two received clocks. When the two signals Hr and Hd are in phase (0° phase difference), a logic state "0" is instantiated. When the clocks are out of phase (180° phase difference), a logic state "1" is instantiated. To perform this phase comparison, an XOR logic gate is used. This gate outputs a "0" when its two inputs are identical and a "1" when the inputs are different.

[0046] Alternatively, or in a complementary or combinational manner, an ASK (Amplitude Shift Keying) modulation technique is implemented. This technique relies on the FPGA-SoC 109 platform managing the modulation of the high-frequency signal to transmit a low-frequency signal through a single optical channel. In this configuration, the FPGA-SoC 109 platform directly generates a digital high-frequency signal, the amplitude of which is modulated according to the data to be transmitted. The FPGA 109-1 generates an HF carrier, the amplitude of which is modulated in an on-off (OOK) fashion to represent binary bits: a carrier present with an "ON" amplitude indicates a logic bit "1", while the absence of a carrier (amplitude "OFF") represents a logic bit "0".This modulation is carried out in such a way as to transmit low frequency data on the high frequency signal: the transmission process is simplified and a single optical fiber can be used again.

[0047] The modulated RF signal is then converted into an optical signal by the optical transmitter 108. The optical signal, carrying the ASK modulation, is transmitted through the optical fiber 205. The optical signal frequency is chosen to be compatible with the capabilities of standard optical receivers, which can operate in the data rate range of 1 Gbps to 10 Gbps. The FPGA-SoC platform 109 and the optical transmitter 108 thus ensure the complete integration of signal generation, modulation, and transmission, reducing the need for complex external processing and decreasing the number of components required.

[0048] In this system, modulated signal recovery and carrier conversion are entirely managed by the optical receiver 102, which captures the optical signal intensity to deduce its binary value. Within this optical receiver 102, the optical signal power, a function of the presence or absence of the RF carrier, is measured by an RF power detector. This detector transforms the received digital spectrum into an analog voltage corresponding to a logic "1" or "0" depending on the carrier's presence. Thanks to this approach, the FPGA-SoC platform 109 enables the transmission of a low-frequency signal over a high-speed optical fiber while optimizing bandwidth utilization and minimizing hardware footprint. This reduces fiber requirements compared to more complex techniques.

[0049] Furthermore, as with oversampling, a phase-locked loop is implemented. Thus, in this ASK system, the phase-locked loop (PLL) is used to generate a carrier signal of a predefined frequency from a local reference. The PLL consists, for example, of a voltage-controlled oscillator (VCO), a phase comparator, and a low-pass filter, all arranged to keep the local oscillator's frequency synchronized with a reference clock frequency. This arrangement ensures that the amplitude-modulated carrier, used as the basis for ASK modulation, has the frequency and phase stability required by the system, regardless of environmental or power supply fluctuations.

[0050] The PLL operates upstream of the modulator to provide the stable carrier wave to be modulated. The carrier frequency from the VCO is continuously adjusted by the PLL's control loop to remain locked to the reference frequency signaled to the phase comparator. The ASK modulation, performed by serialization logic within the FPGA 109-1, then operates on this maintained carrier wave, while frequency synthesis and the temporal stability of the RF signal are ensured by the phase feedback of the PLL, without the PLL's involvement in the direct demodulation of the amplitude-modulated signal.The SFP optical interface therefore only transmits high-frequency signals, i.e., the sampling clock signal which is already high frequency, and raw (SB) BF / DC oversampled or ASK modulated signals such as the CAN configuration interface (SPI or I2C "MHz"), the JESD204 SYSREF synchronization clock ("MHz"), and the JESD204 SYNC data initialization signal (DC).

[0051] System 10 also incorporates a specific architecture, at the level of the Acquisition Module 300, for electromagnetic compatibility (EMC). The printed circuit boards of Acquisition Module 300 are designed with a specific layer arrangement and integrated shielding techniques such as via shielding and via fencing. These features ensure the reliable operation of System 10 in environments with high electromagnetic interference.

[0052] Furthermore, the CAN 101(s) are positioned near the sensors 100 in the disturbed area of ​​the system 10 being monitored (e.g., a particle accelerator), while the FPGA-SoC 109 platform is located remotely in a protected area. Communication between these elements is achieved via optical fiber 205, ensuring galvanic isolation and reliable data transmission. Finally, the disclosure system 10 offers a user-friendly approach to the user interface and data transmission. A client-server type service is implemented on the SoC 109, providing a flexible interface that is easily accessible remotely.

[0053] According to the present, the collection device 301 and the acquisition module 300 are each powered by a different power source 113, 114, 104, 105. This independence of the power supply makes it easier to implement the system 10 by eliminating the need to transmit power to the acquisition module from the collection device 301.

[0054] According to this diagram, the high-speed receive / transmit interfaces for transmitting digitized data and / or receiving parameter and clock signals are similar for both components of the system 10 (namely, the data acquisition device 301 and the data acquisition module 300). Each of these interfaces comprises, on the one hand, an optical transceiver 102, 108 and an optical multiplexer / demultiplexer (Mux / Demux) 103, 107, a passive device that allows combining or separating several optical signals of different wavelengths on a single fiber. An optical circulator (not shown) is optionally implemented in conjunction with the optical multiplexers / demultiplexers 103, 107.

[0055] As previously explained, the processing module 109 of the data acquisition device 301 is an FPGA-SoC, and this processing module is physically connected to a clock source 110, which defines the master clock. According to the disclosure, the processing module 109 is configured to receive a master clock signal from the clock signal generation module 110 and is configured to generate at least one drive clock signal for the analog-to-digital converter 101 of the acquisition module 300. The drive clock signal for the analog-to-digital converter 101 of the acquisition module 300 is multiplexed into a signal transmitted to the acquisition module 300 via optical fiber 205.The clock signal for driving the analog-to-digital converter 101 of the acquisition module 300 is specifically generated by the FPGA 109-1 component using at least one phase-locked loop. Furthermore, in at least one embodiment, the FPGA 109-1 component is configured to oversample the clock signal for driving the analog-to-digital converter 101 of the acquisition module 300 before its transmission to the optical transceiver 108 of the data acquisition device 301. This configuration allows the use of a single optical fiber for all data transmissions and receptions between the two components of the system 10.

[0056] Furthermore, the processing module 109 of the data collection device 301 is equipped with local storage capabilities 111 to record monitoring data over extended periods, thus enabling historical analysis and traceability of the operating parameters of the monitored device. A network interface 112 is also implemented to transmit the processed data, for example, via a web interface to a remote client 115. The processing module 109, through the implementation of an FPGA-SoC, therefore runs a web server for transmitting alert signals when it is detected that a monitored parameter deviates from its assigned value range.

[0057] Furthermore, the monitoring system 10 can include advanced features such as self-calibration of the sensors 100 to maintain measurement accuracy over extended periods. This self-calibration can be performed by the processing module 109 using correction algorithms based on internal or external references. In addition, the system 10 can be configured to perform real-time diagnostics, enabling the immediate detection and reporting of any failures or anomalies in the sensors 100 or transmission modules, as well as issues related to deviations in monitored parameters. These diagnostics can include optical fiber continuity tests 205, signal integrity checks, and performance analyses of the analog-to-digital converters 101.

[0058] The monitoring system 10 can also be integrated into existing communication networks, such as Ethernet or wireless networks, to enable remote monitoring and control. This integration can be facilitated by the use of standardized communication protocols, such as TCP / IP, and by implementing communication gateways within the processing module 109 (in the processor section).

[0059] Finally, the 10 monitoring system is designed to be scalable, allowing the addition of 100 new sensors without requiring major modifications to the existing infrastructure.

[0060] In signal processing, the sensor 100 generates an analog signal 200 which is transmitted to the analog-to-digital converter 101. This analog signal represents the raw data captured, for example, by a transducer. The ADC 101 converts the analog signal into a digital data stream. This digital data is then serialized and formatted according to the JESD204 protocol by the ADC 101 connected to the optical transceiver 102. The optical transceiver 102 of the acquisition module 300 transmits the JESD204-formatted digital data over the single optical fiber 205 towards the data acquisition device 301, after this signal has been multiplexed within the multiplexer / demultiplexer 103 of the acquisition module 300. This optical signal contains the digitally encoded sensor data.The optical transceiver 102 of the acquisition module 300 transmits the CAN 203 control signals and the sampling clock signal 202 to the CAN 101. The optical transceiver 102 of the acquisition module 300 also transmits the synchronization signal to the CAN 101 (this signal is received from the FPGA, which transmits the synchronization signal to all CANs). Conversely, the data acquisition device 301 transmits a sampling clock signal to the acquisition module 300 via the same optical fiber 205. This clock signal synchronizes the operation of the CAN 101 directly from the data acquisition device 301. The data acquisition device 301 also transmits a JESD204 synchronization signal to the acquisition module 300 over the optical fiber. This synchronization signal ensures proper alignment of the JESD204 data frames.The optical transceiver 102 of the acquisition module 300 receives (after processing in the Multiplexer / Demultiplexer 103) the clock and synchronization signals transmitted by the data acquisition device 301. It extracts these signals from the multiplexed optical stream and routes them to the ADC 101. Finally, the optical transceiver 102 of the data acquisition device 301 receives the optical signal containing the digital data from the sensor. It converts this optical signal into an electrical signal and transmits it to the JESD204 interface circuit, configured within the FPGA, for decoding and further processing.

[0061] In system 10 of the disclosure, the synchronization signals are transmitted between the components as follows. The collection device 301 generates a JESD204 synchronization signal, which is transmitted to the acquisition module 300 containing the analog-to-digital converter (ADC) 101. This synchronization signal is transmitted over the same bidirectional optical fiber used to transmit the digitized data from the ADC to the processor (e.g., a double simplex (two fibers within the same cable for a single connector with RX and TX inputs, such as an SFP)). To achieve this, the optical transceiver 102 of the acquisition module 300 and the optical transceiver 107 of the collection device 301 are bidirectional optical transceivers. The synchronization signal is transmitted in the "upstream" direction to the acquisition module 300, while the digitized data is transmitted in the "downstream" direction. At theAcquisition module 300, optical demultiplexer 103, recovers the synchronization and clock signals from the WDM link. The JESD204 protocol integrates clock and data retrieval capabilities, eliminating the need for additional clock multiplication circuitry for synchronization. This approach enables precise synchronization between the ADC 101 and the data acquisition device 301, while maintaining complete galvanic isolation through the use of optical links. The main steps of the measurement process using the system 10 proposed herein are: analog signal acquisition: the sensor 100 generates an analog signal representing the measured physical quantity; signal amplification: the analog signal is optionally amplified by an amplifier located in the immediate vicinity of the sensor 100 in the acquisition module 300; the signal is also filtered to a bandwidth of Fs / 2, where Fs is the frequencyADC sampling; signal digitization: the analog (amplified) signal is converted into a digital signal by the analog-to-digital converter 101 (ADC) located in the acquisition module 300; digital data formatting: the digitized data is formatted according to the JESD204 protocol by the transceiver integrated into the ADC 101; optical data transmission: the formatted digital data is transmitted via the single optical link 205 to the remote data acquisition device 301; data reception and decoding: the data acquisition device 301 receives the optical signal, converts it into an electrical signal, and decodes the JESD204 data; data processing: the decoded data is processed by the processor 109 of the data acquisition device 301 to extract data relating to the evolution of the parameters monitored by the system; real-time processing is performed within the FPGA 109-1 to ensure the most responsive monitoring.possible (less than a microsecond). Semi-real-time processing is carried out at the processor 109-2 and allows monitoring of signal evolution with less reactivity constraint: this processing is slower and not necessarily synchronous, but has the advantage of being able to handle larger amounts of data and more complex tasks; synchronization: clock signals and synchronization signals are transmitted from the collection device 301 to the acquisition module 300 via an optical link, often by wavelength division multiplexing (WDM).

Claims

DEMANDS 1. System (10) for monitoring the evolution of at least one associated value of an operating parameter of a device (DUS) generating and / or encountering electromagnetic disturbances, said system comprising: an acquisition module (300) for data representative of values ​​associated with the parameter to be monitored, the acquisition module comprising at least one sensor (100), at least one analog-to-digital converter (101) associated with said at least one sensor, an optical transceiver (102) and an optical multiplexer (103);a data collection device (301) for representative data of the values ​​associated with the parameter to be monitored, comprising: an optical multiplexer (107), an optical transceiver (108) and a data processing module (109) for representative data of the values ​​associated with the parameter to be monitored, the processing module (109) comprising at least a part in the form of an FPGA (109-1) and at least a part in the form of a processing processor (109-2); an optical fiber (205) connecting the multiplexer (103) of the acquisition module and the multiplexer (107) of the data collection device.

2. Monitoring system (10) according to claim 1, characterized in that the processing module (109) of the collection device (301) is in the form of an integrated electronic module combining an FPGA and at least one processor.

3. Monitoring system (10) according to claim 1 or 2, characterized in that the processing module (109) is configured to receive a master clock signal from a clock signal generation module (110) and to generate at least one drive clock signal for said at least one analog-to-digital converter (101) of the acquisition module (300).

4. Monitoring system (10) according to claim 3, characterized in that said at least one drive clock signal of said at least one analog-to-digital converter (101) of the acquisition module (300) is multiplexed within a signal transmitted to the acquisition module (300) via the optical fiber (205).

5. Monitoring system (10) according to claim 3, characterized in that said at least one drive clock signal of said at least one analog-to-digital converter (101) of the acquisition module (300) is generated by the part in the form of an FPGA (109-1) using at least one phase-locked loop.

6. Monitoring system (10) according to claim 3, characterized in that the part in the form of an FPGA (109-1) is configured to perform oversampling of said at least one drive clock signal intended for said at least one analog-to-digital converter (101) of the acquisition module (300) before its transmission to said optical transceiver (108) of the collection device (301).

7. Monitoring system (10) according to claim 3, characterized in that the part in the form of an FPGA (109-1) is arranged to perform amplitude shift modulation (ASK) of said at least one control clock signal intended for said at least one analog-to-digital converter (101) of the acquisition module (300), before transmission of this signal to said optical transceiver (108) of the collection device (301).

8. A monitoring system (10) according to any one of claims 1 to 7, characterized in that the acquisition module (300) is at least partially in the form of an electronic module comprising a multilayer electronic circuit board configured to preserve the integrity of the electrical signals originating from or 9. for said at least one analog-to-digital converter (101).

10. Surveillance system (10) according to any one of claims 1 to 8, characterized in that the acquisition module (300) comprises an enclosure protecting against electromagnetic interference (EMI) of said at least one analog-to-digital converter (101) of said optical transceiver (102) and of said optical multiplexer (103).

11. Monitoring system (10) according to any one of the preceding claims, characterized in that the processing module (109) of the collection device (301) is configured to emit a signal representative of an alarm when a current value associated with the operating parameter of the device (DUS) is different from an expected value.

12. Surveillance system (10) according to any one of the preceding claims, characterized in that the processing module (109) of the collection device (301) is configured to transmit all or part of the data collected from said acquisition module, to a remote processing device, via a communication interface.

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