Drive circuit

Abstract

Provided is a novel semiconductor device. The present invention includes a shift register, a first buffer, a second buffer, first wiring, and second wiring. The first buffer has a function by which, on the basis of a signal output from a first terminal of the shift register, a signal applied to the first wiring is supplied to a gate line provided to a first pixel region. The second buffer has a function by which, on the basis of a signal output from a second terminal of the shift register, a signal applied to the second wiring is supplied to a gate line provided to a second pixel region. The first pixel region has a function for performing display at a first resolution. The second pixel region has a function for performing display at the first resolution and a function for performing display at a second resolution. The second resolution is lower than the first resolution. When the first pixel region displays at the first resolution and the second pixel region displays at the second resolution, a constant potential or a signal having a pulse width longer than a pulse width of a signal applied to the first wiring is applied to the second wiring.

Description

Drive circuit

[0001] One aspect of the present invention relates to a drive circuit.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, projection devices, illumination devices, optical devices, electro-optical devices, imaging devices, light-receiving devices, detection devices, power supply devices, energy storage devices, communication devices, computing devices, control devices, computing processing devices, memory devices, input devices, output devices, input / output devices, signal processing devices, information processing devices, computers, electronic devices, systems having the same, methods for driving them, or methods for manufacturing them.

[0003] Display devices are used in a variety of applications. Large-scale display devices are used in home television systems and PID (Public Information Display) for digital signage. Small-scale display devices are used in mobile information terminals such as smartphones and tablets, and wearable devices such as VR (Virtual Reality) devices and AR (Augmented Reality) devices. Furthermore, display devices are being enhanced and given higher value by adding functions other than display. For example, display devices with touch panel functionality and display devices with in-screen fingerprint authentication functionality have been developed.

[0004] Furthermore, Patent Document 1 discloses an example of a drive circuit that can be used in a display device. Patent Document 2 also discloses an example of a display device that can change the screen resolution for each display area.

[0005] Japanese Patent Publication No. 2013-211088, International Publication No. 2023 / 084356

[0006] Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] One aspect of the present invention aims to provide a drive circuit that can reduce the power consumption of a display device. Alternatively, one aspect of the present invention aims to provide a drive circuit that can increase the operating speed of a display device. Alternatively, one aspect of the present invention aims to provide a drive circuit that can narrow the bezel width of a display device. Alternatively, one aspect of the present invention aims to provide a drive circuit that can increase the resolution of a display device. Alternatively, one aspect of the present invention aims to provide a drive circuit that can improve the display quality of a display device. Alternatively, one aspect of the present invention aims to provide a drive circuit that can improve the performance of a display device. Alternatively, one aspect of the present invention aims to provide a highly reliable drive circuit. Alternatively, one aspect of the present invention aims to provide a semiconductor device to which the above drive circuit is applied. Alternatively, one aspect of the present invention aims to provide a display device to which the above drive circuit is applied. Alternatively, one aspect of the present invention aims to provide a method for driving the above drive circuit. Alternatively, one aspect of the present invention aims to provide a method for driving the above semiconductor device. Alternatively, one aspect of the present invention aims to provide a method for driving the above-mentioned display device. Alternatively, one aspect of the present invention aims to provide a novel driving circuit. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide a novel display device.

[0008] Furthermore, the above-mentioned problems do not preclude the existence of other problems. Those skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and it is possible to extract other problems from the description in this specification, drawings, claims, etc. Furthermore, one aspect of the present invention does not need to solve all of these problems (the above-mentioned problems and other problems).

[0009] (1) One aspect of the present invention has a shift register, a first buffer, a second buffer, a first wiring, and a second wiring. The first buffer has a function of supplying a signal given to the first wiring to a gate line provided in the first pixel region based on a signal output from a first terminal of the shift register. The second buffer has a function of supplying a signal given to the second wiring to a gate line provided in the second pixel region based on a signal output from a second terminal of the shift register. The first pixel region has a function of displaying at a first resolution. The second pixel region has a function of displaying at a first resolution and a function of displaying at a second resolution. The second resolution is lower than the first resolution. When displaying the first pixel region at the first resolution and the second pixel region at the second resolution, the second wiring is a driving circuit to which a signal having a pulse width longer than the pulse width of the signal given to the first wiring or a fixed potential is given.

[0010] (2) Further, in (1) above, the first pixel region may include the center of the display region.

[0011] (3) Further, in (1) or (2) above, having a gate line selection circuit, the gate line selection circuit is provided between the second buffer and the second pixel region, and the gate line selection circuit may have a function of controlling so that a signal given to the second wiring is supplied to one or a plurality of gate lines provided in the second pixel region.

[0012] (4) Further, in any one of (1) to (3) above, the first buffer includes a first transistor and a second transistor, the second buffer includes a third transistor and a fourth transistor, a first terminal of the first transistor is electrically connected to a first terminal of the second transistor and a gate line provided in the first pixel region, a second terminal of the first transistor is electrically connected to a first wiring, a second terminal of the second transistor is electrically connected to a third wiring, a gate of the first transistor is electrically connected to a first terminal of the shift register, a gate of the second transistor is electrically connected to a terminal where an inverted signal of a signal output from the first terminal of the shift register is output, a first terminal of the third transistor is electrically connected to a first terminal of the fourth transistor and a gate line provided in the second pixel region, a second terminal of the third transistor is electrically connected to a second wiring, a second terminal of the fourth transistor is electrically connected to a third wiring, a gate of the third transistor is electrically connected to a second terminal of the shift register, and a gate of the fourth transistor may be electrically connected to a terminal where an inverted signal of a signal output from the second terminal of the shift register is output.

[0013] (5) Further, in (4) above, each of the first transistor to the fourth transistor may include an oxide semiconductor in a channel formation region.

[0014] (6) Further, in (5) above, the oxide semiconductor may include indium. [[ID=…]] ​According to one aspect of the present invention, a drive circuit can be provided that can reduce the power consumption of a display device. Alternatively, according to one aspect of the present invention, a drive circuit can be provided that can increase the operating speed of a display device. Alternatively, according to one aspect of the present invention, a drive circuit can be provided that can narrow the bezel width of a display device. Alternatively, according to one aspect of the present invention, a drive circuit can be provided that can increase the resolution of a display device. Alternatively, according to one aspect of the present invention, a drive circuit can be provided that can improve the display quality of a display device. Alternatively, according to one aspect of the present invention, a drive circuit can be provided that can improve the performance of a display device. Alternatively, according to one aspect of the present invention, a highly reliable drive circuit can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device to which the above drive circuit is applied can be provided. Alternatively, according to one aspect of the present invention, a display device to which the above drive circuit is applied can be provided. Alternatively, according to one aspect of the present invention, a method for driving the above drive circuit can be provided. Alternatively, according to one aspect of the present invention, a method for driving the above semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a method for driving the above display device can be provided. Alternatively, according to one aspect of the present invention, a novel drive circuit can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a novel display device can be provided.

[0016] Furthermore, the effects described above do not preclude the existence of other effects. Those skilled in the art can naturally derive other effects from the descriptions in this specification, drawings, and claims, and it is possible to extract other effects from the descriptions in this specification, drawings, and claims. Moreover, one aspect of the present invention does not need to have all of these effects (the effects described above and other effects).

[0017] Figure 1 is a circuit diagram illustrating an example configuration of a semiconductor device. Figure 2 is a circuit diagram illustrating an example configuration of a semiconductor device. Figure 3 is a circuit diagram illustrating an example configuration of a semiconductor device. Figure 4 is a circuit diagram illustrating an example configuration of a semiconductor device. Figure 5 is a circuit diagram illustrating an example configuration of a drive circuit. Figure 6 is a circuit diagram illustrating an example configuration of a drive circuit. Figure 7 is a circuit diagram illustrating an example configuration of a drive circuit. Figure 8 is a circuit diagram illustrating an example configuration of a drive circuit. Figure 9 is a circuit diagram illustrating an example configuration of a semiconductor device. Figure 10 is a timing chart illustrating an example operation of a drive circuit. Figure 11 is a timing chart illustrating an example operation of a drive circuit. Figure 12 is a timing chart illustrating an example operation of a drive circuit. Figure 13 is a timing chart illustrating an example operation of a drive circuit. Figure 14 is a circuit diagram illustrating an example configuration of a drive circuit. Figure 15 is a timing chart illustrating an example operation of a drive circuit. Figure 16 is a timing chart illustrating an example operation of a drive circuit. Figure 17 is a timing chart illustrating an example operation of a drive circuit. Figures 18A and 18B are block diagrams illustrating an example configuration of a display device. Figure 19A is a top view illustrating an example configuration of a transistor. Figures 19B and 19C are cross-sectional views illustrating an example of transistor configuration. Figure 20A is a top view illustrating an example of transistor configuration. Figures 20B and 20C are cross-sectional views illustrating an example of transistor configuration. Figure 21A is a top view illustrating an example of transistor configuration. Figures 21B and 21C are cross-sectional views illustrating an example of transistor configuration. Figure 22A is a perspective view illustrating an example of display device configuration. Figures 22B, 22C, 22D, 22E, and 22F are top views illustrating an example of pixel arrangement. Figure 23 is a cross-sectional view illustrating an example of display device configuration. Figures 24A and 24B are cross-sectional views illustrating an example of display device configuration. Figures 25A and 25B are cross-sectional views illustrating an example of display device configuration. Figures 26A and 26B illustrate the carrier concentration dependence of hole mobility. Figure 26C is a cross-sectional view illustrating an indium oxide film. Figures 27A, 27B, 27C, 27D, 27E, 27F, 27G, and 27H show examples of electronic devices.Figures 28A1, 28A2, 28A3, 28A4, 28A5, 28A6, 28A7 and 28B1, 28B2, 28B3, 28B4, 28B5, and 28B6 are diagrams illustrating electrical connections.

[0018] Embodiments of the present invention will now be described. However, it will be readily apparent to those skilled in the art that the embodiments and their details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the contents of the following embodiments.

[0019] Furthermore, the contents of the embodiments can be appropriately combined to form one aspect of the present invention.

[0020] In this specification, the components of the present invention may be classified by function and shown as independent elements. However, it may be difficult to separate the components by function, and a single element may be involved in multiple functions, or a single function may be involved across multiple elements. Therefore, the explanation is not limited to this and may be appropriately rephrased.

[0021] Furthermore, when using the same symbol for multiple elements and explaining them in a way that distinguishes them, identification symbols such as "A", "b", "_1", "[n]", and "[m,n]" may be added. Also, when explaining something common to multiple elements with identification symbols, or when explaining them without distinguishing them, identification symbols may be omitted.

[0022] Furthermore, in drawings, the same reference numeral may be used for identical elements, elements with similar functions, elements of the same material, or elements formed simultaneously, thereby omitting the explanation of repetition. Additionally, the same hatching pattern may omit the use of a reference numeral.

[0023] Furthermore, the drawings are schematic representations intended to aid in understanding the present invention. Therefore, they are not limited to their size, aspect ratio, or shape. Also, some elements may be omitted.

[0024] (Embodiment 1) A drive circuit according to one aspect of the present invention will be described with reference to the drawings. At least a part of the drive circuit according to one aspect of the present invention can be used in a semiconductor device such as a display device.

[0025] <Example of drive circuit configuration 1> Figure 1 is a circuit diagram illustrating a drive circuit according to one aspect of the present invention. Figure 1 shows a semiconductor device 100 having a drive circuit 101 and a pixel unit 102.

[0026] The drive circuit 101 includes a buffer group 111a, a buffer group 111b, a shift register 113, a wiring group 115a, and a wiring group 115b. Buffer group 111a has a plurality of buffers 112a (one buffer 112a is shown as a representative). Buffer group 111b has a plurality of buffers 112b (one buffer 112b is shown as a representative). The shift register 113 has a plurality of terminals to which sequential signals are output (terminals 114a and 114b are shown as representative). Wiring group 115a has a plurality of wires 116a (one wire 116a is shown as a representative). Wiring group 115b has a plurality of wires 116b (one wire 116b is shown as a representative).

[0027] The pixel unit 102 has a pixel area 121a and a pixel area 121b. The pixel area 121a includes a portion of a plurality of pixels 122 arranged in a matrix (two pixels 122 arranged in 1 row and 2 columns are shown as representative). The pixel area 121b includes a portion or all of the remaining portion of the plurality of pixels 122 (specifically, a portion or all of a plurality of pixels 122 arranged outside of the pixel area 121a) (two pixels 122 arranged in 1 row and 2 columns are shown as representative). The plurality of pixels 122 included in the pixel area 121a are connected to gate lines 123a provided in the pixel area 121a. The plurality of pixels 122 included in the pixel area 121b are connected to gate lines 123b provided in the pixel area 121b.

[0028] Buffer 112a has the function of supplying the signal to be given to wiring 116a to gate line 123a based on the signal output from terminal 114a. Buffer 112b has the function of supplying the signal to be given to wiring 116b to gate line 123b based on the signal output from terminal 114b.

[0029] Therefore, in the semiconductor device 100, based on the signals sequentially output from the shift register 113, the signals given to the wiring group 115a are supplied to the gate lines 123a corresponding to each of the multiple buffers 112a via each of the multiple buffers 112b, and the signals given to the wiring group 115b are supplied to the gate lines 123b corresponding to each of the multiple buffers 112b via each of the multiple buffers 112b. As a result, multiple pixels 122 arranged in the pixel unit 102 are sequentially selected one or more rows at a time, and an image signal is written to the selected pixels 122.

[0030] In a display device using the semiconductor device 100, an image can be displayed in each of the pixel areas 121a and 121b at either a first resolution or a second resolution. Therefore, it can be said that each of the pixel areas 121a and 121b has the function of displaying at the first resolution and the function of displaying at the second resolution. Here, the second resolution is assumed to be lower than the first resolution. Note that displaying an image in a pixel area at a resolution lower than the first resolution (in this case, displaying an image at the second resolution) is sometimes referred to as low-resolution display.

[0031] One aspect of the present invention is a display device using a semiconductor device 100, in which an image can be displayed at a first resolution in either a pixel area 121a or a pixel area 121b, and an image can be displayed at a first or second resolution in the other pixel area 121a or a pixel area 121b. For example, an image can be displayed at a first resolution in pixel area 121a, and an image can be displayed at a first or second resolution in pixel area 121b. In this case, pixel area 121b can also be said to be an area capable of low-resolution display.

[0032] For example, in the pixel area 121b, when displaying at a low resolution, the same image signal is written to each pixel 122 in multiple adjacent rows. Therefore, by supplying the same signal to each gate line 123b in multiple adjacent rows, the image signal can be written to each pixel 122 in multiple adjacent rows simultaneously. For example, the image signal can be written to two adjacent rows of pixels 122 simultaneously. Also, for example, the image signal can be written to four adjacent rows of pixels 122 simultaneously. Also, for example, the image signal can be written to eight adjacent rows of pixels 122 simultaneously. This makes it possible to reduce the number of times the image signal is written, and thus reduce the power consumption of the display device.

[0033] In this case, a signal with a pulse width longer than the pulse width of the signal supplied to wiring 116a can be supplied to wiring 116b. This makes the period for selecting pixels 122 included in pixel region 121b longer than the period for selecting pixels 122 included in pixel region 121a. Depending on the configuration of buffer 112b, a constant potential may be supplied to wiring 116b.

[0034] In one aspect of the present invention, the semiconductor device 100 can be used in a display device that supports foveated rendering. In particular, it is preferable to use the semiconductor device 100 in a display device that supports fixed foveated rendering. Alternatively, the semiconductor device 100 may be used in a display device that supports dynamic fixed foveated rendering. For example, when the semiconductor device 100 is used in a display device that supports foveated rendering, the pixel area 121a can be an area that includes the user's gaze point. Also, for example, when the semiconductor device 100 is used in a display device that supports fixed foveated rendering, the pixel area 121a can be an area that includes the center of the display area. Also, for example, when the semiconductor device 100 is used in a display device that supports dynamic fixed foveated rendering, the number of lines on which image signals are written simultaneously in the pixel area 121b can be dynamically changed according to the load of the CPU or GPU performing the rendering.

[0035] Here, the display area refers to the area in a display device using the semiconductor device 100 where an image is displayed. For example, the display area corresponds to the area where the pixel section 102 is provided. Therefore, the center of the display area can be defined as, for example, the point where two diagonals drawn in the area where the pixel section 102 is provided intersect. Thus, the area including the center of the display area can also be said to be the area that includes the pixel 122 located in the m / 2 row and n / 2 column when, for example, a plurality of pixels 122 in the pixel section 102 are arranged in a matrix of m rows and n columns (where m is an integer of 2 or more, and n is an integer of 2 or more).

[0036] A specific example of the drive circuit 101 configuration and an example of its operation during low-resolution display will be described later.

[0037] Figure 2 is a circuit diagram illustrating a modified example of the semiconductor device 100 shown in Figure 1.

[0038] In the semiconductor device 100 shown in Figure 2, the drive circuit 101 includes, in addition to the drive circuit 101 shown in Figure 1, a buffer group 111c and a wiring group 115c. The buffer group 111c has a plurality of buffers 112c (one buffer 112c is shown as a representative). The wiring group 115c has a plurality of wirings 116c (one wiring 116c is shown as a representative).

[0039] Furthermore, in the drive circuit 101 shown in Figure 2, in addition to terminals 114a and 114b, terminal 114c is also shown as one of several terminals from which signals are sequentially output from the shift register 113.

[0040] Furthermore, the pixel section 102 shown in Figure 2 has a pixel region 121c in addition to the pixel section 102 shown in Figure 1. The pixel region 121c includes some or all of the multiple pixels 122 located outside of the pixel regions 121a and 121b (two pixels 122 arranged in a 1x2 grid are shown as representative). The multiple pixels 122 included in the pixel region 121c are connected to gate lines 123c provided in the pixel region 121c.

[0041] Buffer 112c has the function of supplying the signal to the gate line 123c that is given to the wiring 116c based on the signal output from terminal 114c.

[0042] Therefore, in the semiconductor device 100 shown in Figure 2, based on the signals sequentially output from the shift register 113, the signals given to the wiring group 115c are supplied to the gate lines 123c corresponding to each of the multiple buffers 112c via each of the multiple buffers 112c, the signals given to the wiring group 115a are supplied to the gate lines 123a corresponding to each of the multiple buffers 112a via each of the multiple buffers 112b, and the signals given to the wiring group 115b are supplied to the gate lines 123b corresponding to each of the multiple buffers 112b via each of the multiple buffers 112b. As a result, multiple pixels 122 arranged in the pixel unit 102 are sequentially selected one or more rows at a time, and an image signal is written to the selected pixels 122.

[0043] In the pixel section 102 shown in Figure 2, the pixel regions 121c, 121a, and 121b are arranged in this order. Therefore, for example, the pixel region 121c can be the region including the upper end of the display area, the pixel region 121a can be the region including the center of the display area, and the pixel region 121b can be the region including the lower end of the display area.

[0044] One aspect of the present invention is a display device using the semiconductor device 100 shown in Figure 2, in which one or both of the pixel area 121b and the pixel area 121c can be displayed at a low resolution. In this case, each of the pixel area 121b and the pixel area 121c can also be said to be an area capable of low-resolution display.

[0045] For example, in pixel region 121c, similar to pixel region 121b, the same image signal is written to each pixel 122 in multiple adjacent rows when displaying at a low resolution. Therefore, by supplying the same signal to each gate line 123c of multiple adjacent rows, the image signal can be written to each pixel 122 in multiple adjacent rows simultaneously. This reduces the number of times the image signal is written, thereby reducing the power consumption of the display device.

[0046] In this case, the resolution of the image displayed in pixel area 121c may be the same as or different from the resolution of the image displayed in pixel area 121b. For example, the number of lines on which image signals are written simultaneously in pixel area 121c may be the same as or different from the number of lines on which image signals are written simultaneously in pixel area 121b. If the resolution of the images displayed in pixel area 121b and pixel area 121c are different, for example, they may be different depending on the image being displayed, or depending on the area the user is focusing on.

[0047] In one aspect of the present invention, for example, an image can be displayed in pixel area 121a at a first resolution, in either pixel area 121b or pixel area 121c at a second resolution, and in the other pixel area 121b or pixel area 121c at a third resolution. Here, the third resolution is lower than the second resolution. Alternatively, for example, an image can be displayed in pixel area 121a at a first resolution, in either pixel area 121b or pixel area 121c at a first resolution, and in the other pixel area 121b or pixel area 121c at a second resolution.

[0048] Figure 3 is a circuit diagram illustrating a modified example of the semiconductor device 100 shown in Figure 2.

[0049] In the semiconductor device 100 shown in Figure 3, the drive circuit 101 differs from the drive circuit 101 shown in Figure 2 in that the wiring group 115b has wiring 116c, while the wiring group 115c does not.

[0050] In the drive circuit 101 shown in Figure 3, the wiring 116b connected to buffer 112b and the wiring 116c connected to buffer 112c are shared by the wiring group 115b. As a result, the number of lines on which image signals are written simultaneously in the pixel area 121c is the same as the number of lines on which image signals are written simultaneously in the pixel area 121b. Therefore, the resolution of the image displayed in the pixel area 121c is the same as the resolution of the image displayed in the pixel area 121b. For this reason, it is preferable to use the semiconductor device 100 shown in Figure 3 in a display device that supports fixed foveal rendering, for example.

[0051] In one aspect of the present invention, for example, an image can be displayed in pixel area 121a at a first resolution, and images can be displayed in pixel area 121b and pixel area 121c, respectively, at a second resolution.

[0052] Furthermore, in the drive circuit 101 shown in Figure 3, there is no need to generate signals to be supplied to the wiring group 115c, thus reducing the power consumption of the display device. Also, since there is no need to provide the wiring group 115c, the layout area of ​​the drive circuit 101 can be reduced, and the bezel width of the display device can be reduced.

[0053] Figure 4 is a circuit diagram illustrating a modified example of the semiconductor device 100 shown in Figure 3.

[0054] In the semiconductor device shown in Figure 4, the drive circuit 101 includes, in addition to the drive circuit 101 shown in Figure 3, a buffer group 111d, a buffer group 111e, and a wiring group 115d. The buffer group 111d has a plurality of buffers 112d (one buffer 112d is shown as a representative). The buffer group 111e has a plurality of buffers 112e (one buffer 112e is shown as a representative). The wiring group 115d has a plurality of wirings 116d (one wiring 116d is shown as a representative). The wiring group 115d also has a plurality of wirings 116e (one wiring 116e is shown as a representative).

[0055] Furthermore, in the drive circuit 101 shown in Figure 4, in addition to terminals 114a, 114b, and 114c, terminals 114d and 114e are shown as multiple terminals from which signals are sequentially output from the shift register 113.

[0056] Furthermore, the pixel section 102 shown in Figure 4 has, in addition to the pixel section 102 shown in Figure 3, a pixel region 121d and a pixel region 121e. The pixel region 121d includes some of the multiple pixels 122 located outside of pixel region 121a, pixel region 121b, and pixel region 121c (two pixels 122 arranged in 1 row and 2 columns are shown as representative). The pixel region 121e includes some or all of the multiple pixels 122 located outside of pixel region 121a, pixel region 121b, pixel region 121c, and pixel region 121d (two pixels 122 arranged in 1 row and 2 columns are shown as representative). The multiple pixels 122 included in pixel region 121d are connected to gate lines 123d provided in pixel region 121d. The multiple pixels 122 included in pixel region 121e are connected to gate lines 123e provided in pixel region 121e.

[0057] Buffer 112d has the function of supplying the signal to be given to wiring 116d to gate line 123d based on the signal output from terminal 114d. Buffer 112e has the function of supplying the signal to be given to wiring 116e to gate line 123e based on the signal output from terminal 114e.

[0058] Therefore, in the semiconductor device 100 shown in Figure 4, based on the signals sequentially output from the shift register 113, the signals given to the wiring group 115d are supplied to the gate line 123e corresponding to each of the multiple buffers 112e via each of the multiple buffers 112e, the signals given to the wiring group 115b are supplied to the gate line 123c corresponding to each of the multiple buffers 112c via each of the multiple buffers 112c, the signals given to the wiring group 115a are supplied to the gate line 123a corresponding to each of the multiple buffers 112a via each of the multiple buffers 112a, the signals given to the wiring group 115b are supplied to the gate line 123b corresponding to each of the multiple buffers 112b via each of the multiple buffers 112b, and the signals given to the wiring group 115d are supplied to the gate line 123d corresponding to each of the multiple buffers 112d via each of the multiple buffers 112d. As a result, multiple pixels 122 arranged in the pixel unit 102 are sequentially selected one or more rows at a time, and an image signal is written to the selected pixels 122.

[0059] In the pixel section 102 shown in Figure 4, the pixel regions 121e, 121c, 121a, 121b, and 121d are arranged in this order. Therefore, for example, the pixel region 121e can be defined as the region including the upper end of the display area, the pixel region 121a as the region including the center of the display area, the pixel region 121d as the region including the lower end of the display area, the pixel region 121c as the region located between the pixel region 121a and the pixel region 121e, and the pixel region 121b as the region located between the pixel region 121a and the pixel region 121d.

[0060] One aspect of the present invention is a display device using the semiconductor device 100 shown in Figure 4, in which each of the pixel areas 121b, 121c, 121d, and 121e can be displayed at a low resolution. In this case, each of the pixel areas 121b, 121c, 121d, and 121e can also be said to be an area capable of low-resolution display.

[0061] For example, in pixel area 121d and pixel area 121e, similar to pixel area 121b and pixel area 121c, the same image signal is written to each pixel 122 in multiple adjacent rows when displaying at low resolution. Therefore, by supplying the same signal to each gate line (gate line 123d or gate line 123e) of multiple adjacent rows, the image signal can be written to each pixel 122 in multiple adjacent rows simultaneously. This reduces the number of times the image signal is written, thereby reducing the power consumption of the display device.

[0062] Furthermore, in the drive circuit 101 shown in Figure 4, the wiring 116b connected to buffer 112b and the wiring 116c connected to buffer 112c are shared by the wiring group 115b, and the wiring 116d connected to buffer 112d and the wiring 116e connected to buffer 112e are shared by the wiring group 115d. As a result, the number of lines on which image signals are written simultaneously in pixel area 121c is the same as the number of lines on which image signals are written simultaneously in pixel area 121b, and the number of lines on which image signals are written simultaneously in pixel area 121d is the same as the number of lines on which image signals are written simultaneously in pixel area 121e. Therefore, the resolution of the image displayed in pixel area 121c is the same as the resolution of the image displayed in pixel area 121b, and the resolution of the image displayed in pixel area 121e is the same as the resolution of the image displayed in pixel area 121d. For this reason, it is preferable to use the semiconductor device 100 shown in Figure 4 in a display device that supports fixed foveal rendering, for example.

[0063] In one aspect of the present invention, for example, an image can be displayed in pixel area 121a at a first resolution, in pixel area 121b and pixel area 121c at a second resolution, and in pixel area 121d and pixel area 121e at a third resolution. Alternatively, for example, an image can be displayed in pixel area 121a at a first resolution, in pixel area 121b and pixel area 121c at a first resolution, and in pixel area 121d and pixel area 121e at a second resolution.

[0064] Although not shown in the figures, a configuration similar to the semiconductor device 100 shown in Figure 2 may be used, where wiring 116b is provided by wiring group 115b and wiring 116c is provided by wiring group 115c. Alternatively, wiring 116d may be provided by wiring group 115d and wiring 116e may be provided by wiring group 115e (not shown).

[0065] In this case, when displaying at low resolution, the resolution of the images displayed in each of the pixel areas 121b to 121e may be the same or different. For example, the number of lines on which the image signal is written simultaneously in each of the pixel areas 121b to 121e may be the same or different. If the resolution of the images displayed in each of the pixel areas 121b to 121e is different, for example, it may be different depending on the image being displayed, or it may be different depending on the area the user is focusing on.

[0066] In one aspect of the present invention, for example, an image can be displayed in pixel area 121a at a first resolution, in a part of pixel area 121b to 121e at a second resolution, and in the remaining part of pixel area 121b to 121e at a third resolution. Alternatively, for example, an image can be displayed in pixel area 121a at a first resolution, in a part of pixel area 121b to 121e at a first resolution, in the remaining part of pixel area 121b to 121e at a second resolution, and in the remaining part of pixel area 121b to 121e at a third resolution.

[0067] It should be noted that one aspect of the present invention is not limited to the configuration example described above. For example, the number of pixel regions in the pixel unit 102 may be four, or six or more.

[0068] [Specific Example] A specific example of the configuration of the drive circuit 101 will be described.

[0069] Figure 5 is a circuit diagram illustrating a specific example of the drive circuit 101, namely drive circuit 101A.

[0070] In the drive circuit 101A, the shift register 113 has a plurality of registers 117. Some of the plurality of registers 117 are connected to a plurality of buffers 112a of buffer group 111a via the wiring group SRLagp. The remaining portion of the plurality of registers 117 are connected to a plurality of buffers 112b of buffer group 111b via the wiring group SRLbgp. The plurality of buffers 112a are connected to the wiring group PKLagp (corresponding to wiring group 115a). The plurality of buffers 112b are connected to the wiring group PKLbgp (corresponding to wiring group 115b). The plurality of buffers 112a are also connected in a one-to-one correspondence to a plurality of gate lines 123a provided in the pixel region 121a via the wiring group GOLagp (not shown). Multiple buffers 112b are connected in a one-to-one correspondence to multiple gate lines 123b provided in the pixel region 121b via the wiring group GOLbgp (not shown).

[0071] Furthermore, multiple registers 117 are connected to the wiring group CKLgp. Also, each of the multiple registers 117 is connected, for example, to the register 117 of the previous stage. Note that the register 117 of the first stage is connected to wiring SPL.

[0072] Although not shown in the diagram, the wiring group SRLagp has multiple wirings SRLa, the wiring group SRLbgp has multiple wirings SRLb, the wiring group PKLagp has multiple wirings PKLa, the wiring group PKLbgp has multiple wirings PKLb, the wiring group GOLagp has multiple wirings GOLa, the wiring group GOLbgp has multiple wirings GOLb, and the wiring group CKLgp has multiple wirings CKL.

[0073] In the shift register 113, a signal (also called a start pulse signal) supplied to the wiring SPL triggers the output of signals sequentially from multiple registers 117 based on a clock signal supplied from the wiring group CKLgp. As a result, multiple buffers 112a and multiple buffers 112b are selected sequentially.

[0074] Therefore, in the drive circuit 101A, signals are supplied from wiring group PKLagp to wiring group GOLagp via sequentially selected buffer 112a, and signals are supplied from wiring group PKLbgp to wiring group GOLbgp via sequentially selected buffer 112b.

[0075] In the drive circuit 101A, each of the multiple registers 117 may be connected to two or more buffers 112a or two or more buffers 112b. For example, in the drive circuit 101A shown in Figure 5, each of the multiple registers 117 is connected to four buffers 112a or four buffers 112b. This allows the selection of four buffers 112a or four buffers 112b based on the signal output from one register 117. With this configuration, for example, when displaying a pixel area 121b at a low resolution, the same signal can be supplied to each gate line 123b of multiple adjacent rows (here, two to four rows) by changing the signal supplied to the wiring group PKLbgp. Therefore, image signals can be written to each pixel 122 of multiple adjacent rows simultaneously. This reduces the number of times the image signal is written, thereby reducing the power consumption of the display device. Furthermore, since the number of registers 117 in the shift register 113 can be reduced, the layout area of ​​the shift register 113 can be reduced, and the width of the display device's bezel can be reduced.

[0076] Figure 6 is a circuit diagram illustrating specific examples of buffers 112a, 112b, and register 117 of the drive circuit 101A.

[0077] Buffer 112a includes, for example, a transistor M11a and a transistor M12a. One source or drain of transistor M11a is connected to one source or drain of transistor M12a and to wiring GOLa (corresponding to gate wire 123a). The other source or drain of transistor M11a is connected to wiring PKLa (corresponding to wiring 116a shown in Figure 1 above). The other source or drain of transistor M12a is connected to wiring VLS1. The gates of transistor M11a and transistor M12a are each connected to terminals 114a of the shift register 113 via wiring SRLa. Specifically, the gate of transistor M11a is connected to terminal 114a1 included in terminals 114a, and the gate of transistor M12a is connected to terminal 114a2 included in terminals 114a. In this case, the signal output from terminal 114a2 can be the inverted signal of the signal output from terminal 114a1. Therefore, the gates of transistor M11a and M12a can be supplied with signals whose logic is inverted relative to each other (or signals that have a period of logic inversion).

[0078] Buffer 112b includes, for example, transistor M11b and transistor M12b. One source or drain of transistor M11b is connected to one source or drain of transistor M12b and to wiring GOLb (corresponding to gate wire 123b). The other source or drain of transistor M11b is connected to wiring PKLb (corresponding to wiring 116b shown in Figure 1 above). The other source or drain of transistor M12b is connected to wiring VLS1. The gates of transistor M11b and transistor M12b are each connected to terminal section 114b of the shift register 113 via wiring SRLb. Specifically, the gate of transistor M11b is connected to terminal 114b1 included in terminal section 114b, and the gate of transistor M12b is connected to terminal 114b2 included in terminal section 114b. In this case, the signal output from terminal 114b2 can be the inverted signal of the signal output from terminal 114b1. Therefore, the gates of transistor M11b and M12b can be supplied with signals whose logic is inverted relative to each other (or signals that have a period of logic inversion).

[0079] Each of the multiple registers 117 includes, as an example, a transistor M21, a transistor M22, a transistor M23, a transistor M24, a transistor M25, and a transistor M26. One source or drain of transistor M21 is connected to one source or drain of transistor M23 and to the gate of transistor M25. One source or drain of transistor M22 is connected to the gate of transistor M23, one source or drain of transistor M24, and to the gate of transistor M26. One source or drain of transistor M25 is connected to one source or drain of transistor M26 and to wiring OL. The gates of transistor M21 and transistor M24 are each connected to wiring IL1. The gate of transistor M22 is connected to wiring IL2. The other source or drain of transistor M25 is connected to wiring CKL of wiring group CKLgp. The other source or drain of transistor M21 and the other source or drain of transistor M22 are each connected to wiring VLD2. The other source or drain of transistor M23, the other source or drain of transistor M24, and the other source or drain of transistor M26 are each connected to wiring VLS2.

[0080] Here, in the register 117 connected to buffer 112a, one source or drain of transistor M21 and one source or drain of transistor M23 are connected to terminal 114a1, and one source or drain of transistor M22 and one source or drain of transistor M24 are connected to terminal 114a2. Also, in the register 117 connected to buffer 112b, one source or drain of transistor M21 and one source or drain of transistor M23 are connected to terminal 114b1, and one source or drain of transistor M22 and one source or drain of transistor M24 are connected to terminal 114b2.

[0081] Furthermore, in the shift register 113, for example, wiring IL1 of register 117 is connected to wiring OL of register 117 in the previous stage, or two or more stages prior. Also, for example, wiring IL2 of register 117 is connected to wiring OL of register 117 in the next stage, or two or more stages later.

[0082] Furthermore, a constant potential is applied to each of the wirings VLS1, VLS2, and VLD2, for example. Note that the same potential as wiring VLS1 may be applied to wiring VLS2, or a different potential (for example, a potential lower than that of wiring VLS1) may be applied. Also, wiring VLS2 may be connected to wiring VLS1.

[0083] With this configuration, the shift register 113 can sequentially output signals from multiple registers 117 to multiple terminal sections 114a and multiple terminal sections 114b based on the clock signal provided by the wiring group CKLgp.

[0084] Note that the configuration of buffer 112a, buffer 112b, and register 117 is not limited to the above.

[0085] Figure 7 is a circuit diagram illustrating a modified version of the drive circuit 101A shown in Figure 6. The drive circuit 101A shown in Figure 7 differs from the drive circuit 101A shown in Figure 6 in the configuration of buffers 112a, 112b, and register 117.

[0086] The buffer 112a shown in Figure 7 includes, in addition to the buffer 112a shown in Figure 6, a transistor M13a and a capacitive element C11a. The gate of transistor M11a is connected to either the source or drain of transistor M13a and to one terminal of capacitive element C11a. The other terminal of capacitive element C11a is connected to either the source or drain of transistor M11a. The other source or drain of transistor M13a is connected to terminal 114a1. The gate of transistor M13a is connected to wiring VLD1.

[0087] Furthermore, the buffer 112b shown in Figure 7 includes, in addition to the buffer 112b shown in Figure 6, a transistor M13b and a capacitive element C11b. The gate of transistor M11b is connected to either the source or drain of transistor M13b and to one terminal of capacitive element C11b. The other terminal of capacitive element C11b is connected to either the source or drain of transistor M11b. The other source or drain of transistor M13b is connected to terminal 114b1. The gate of transistor M13b is connected to wiring VLD1.

[0088] Furthermore, the register 117 shown in Figure 7 includes, in addition to the register 117 shown in Figure 6, a transistor M27 and a capacitive element C21. The gate of transistor M25 is connected to either the source or drain of transistor M27 and to one terminal of capacitive element C21. The other terminal of capacitive element C21 is connected to either the source or drain of transistor M25. Either the source or drain of transistor M21 and either the source or drain of transistor M23 are connected to the other source or drain of transistor M27. The gate of transistor M27 is connected to wiring VLD2.

[0089] Furthermore, a constant potential is supplied to wiring VLD1, for example. Wiring VLD2 may be supplied with the same potential as wiring VLD1, or with a different potential. Wiring VLD2 may also be connected to wiring VLD1.

[0090] With this configuration, when the buffer 112a outputs a signal from wiring PKLa to wiring GOLa, the gate voltage of transistor M11a is maintained by the bootstrap effect. Therefore, the potential of the signal output to wiring GOLa is suppressed by the threshold voltage of transistor M11a, and the rise and fall times of the signal can be accelerated.

[0091] Furthermore, in buffer 112b, when a signal is output from wiring PKLb to wiring GOLb, the gate voltage of transistor M11b is maintained due to the bootstrap effect. Therefore, the threshold voltage of transistor M11b suppresses the decrease in the potential of the signal output to wiring GOLb, and the rise and fall times of the signal can be accelerated.

[0092] Furthermore, in register 117, when outputting a signal from wiring CKL to wiring OL, the gate voltage of transistor M25 is maintained due to the bootstrap effect. Therefore, the threshold voltage of transistor M25 suppresses a drop in the potential of the signal output to wiring OL, and the rise and fall times of the signal can be accelerated.

[0093] Figure 8 is a circuit diagram illustrating a modified version of the drive circuit 101A shown in Figure 7. The drive circuit 101A shown in Figure 8 differs from the drive circuit 101A shown in Figure 7 in the configuration of the buffer 112b.

[0094] In the buffer 112b shown in Figure 8, the source or drain of transistor M11b is connected to wiring VLD1. As a result, a potential is supplied from wiring VLD1 to wiring GOLb based on the signal output from terminal 114b1. With this configuration, there is no need to provide wiring PKLb (or rather, there is no need to provide a wiring group PKLbgp that includes wiring PKLb), thus reducing the layout area of ​​the drive circuit 101A and allowing for a reduction in the bezel width of the display device.

[0095] Furthermore, various configurations can be applied to buffers 112a, 112b, and register 117, not limited to the configurations described above.

[0096] [Example of Pixel Configuration] An example of the configuration of the pixel unit 102 connected to the drive circuit 101 and the pixels 122 that the pixel unit 102 has will be described.

[0097] Figure 9 is a circuit diagram illustrating an example configuration of the pixel section 102 and the pixel 122.

[0098] Figure 9 illustrates the pixel 122 included in pixel region 121a and the pixel 122 included in pixel region 121b within the pixel section 102. Here, it is assumed that the two pixels 122 shown in Figure 9 are arranged in the same row.

[0099] Pixels 122 in pixel region 121a are connected to gate line 123a and source line 124, and pixels 122 in pixel region 121b are connected to gate line 123b and source line 124.

[0100] Pixel 122, for example, includes transistor M31, transistor M32, and light-emitting element LD.

[0101] A light-emitting element (LD) emits light with an intensity corresponding to the amount of current flowing through it. As the light-emitting element (LD), for example, an electroluminescent element (especially an injection-type electroluminescent element) such as a light-emitting diode (LED) can be used. As the LED, for example, an LED using an inorganic material as the light-emitting substance, or an LED using an organic material as the light-emitting substance (also called an organic EL (Electroluminescence) element or OLED (Organic LED)) can be used. As an LED using an inorganic material as the light-emitting substance, for example, a mini-LED or micro-LED can be used.

[0102] Transistor M32 is provided in the current path from wiring ANO through the light-emitting element LD to wiring CATH, and has the function of controlling the amount of current supplied to the light-emitting element LD. A potential corresponding to the image signal is applied to the gate of transistor M32. Therefore, a gate voltage corresponding to the image signal is applied to transistor M32, a drain current based on the gate voltage flows, and this drain current is supplied to the light-emitting element LD. In this specification, a transistor having a function like that of transistor M32 is sometimes called a driving transistor.

[0103] Transistor M31 functions as a switch that controls whether or not to write the image signal supplied from source line 124 to pixel 122. For example, transistor M31 functions as a switch that controls whether or not to supply a potential corresponding to the image signal supplied from source line 124 to the gate of transistor M32.

[0104] Here, the gate of the transistor M31 in the pixel 122 included in pixel region 121a is connected to the gate line 123a (corresponding to wiring GOLa). Therefore, the pixel 122 included in pixel region 121a is selected by the signal output from buffer 112a. Also, the gate of the transistor M31 in the pixel 122 included in pixel region 121b is connected to the gate line 123b (corresponding to wiring GOLb). Therefore, the pixel 122 included in pixel region 121b is selected by the signal output from buffer 112b.

[0105] Although not shown in the diagram, one terminal of a capacitive element that has the function of stabilizing the gate voltage of transistor M32 may be connected to the gate of transistor M32.

[0106] Furthermore, in addition to the above configuration, the pixel 122 may also have a transistor and a capacitive element. This makes it possible to realize a pixel with various functions, such as a function to correct threshold voltage variations of the driving transistor, a function to suppress the effects of the hysteresis characteristics of the driving transistor, and a function to initialize the voltage applied to the light-emitting element LD.

[0107] In one aspect of the present invention, n-channel transistors can be used as the transistors constituting buffer 112a, buffer 112b, register 117, and pixel 122, respectively. Alternatively, at least one of the transistors constituting buffer 112a, buffer 112b, register 117, and pixel 122 may be a p-channel transistor.

[0108] Furthermore, as transistors constituting buffer 112a, buffer 112b, register 117, and pixel 122, for example, transistors containing a single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor in the channel formation region can be used. In addition, the semiconductor is not limited to a single-element semiconductor whose main component is a single element (such as silicon or germanium), but can also be a compound semiconductor (such as silicon germanium or gallium arsenide), or an oxide semiconductor, for example.

[0109] For example, as transistors constituting buffer 112a, buffer 112b, register 117, and pixel 122, transistors containing silicon in the channel formation region (Si transistors) may be used, transistors containing oxide semiconductors in the channel formation region (OS transistors) may be used, or both Si transistors and OS transistors may be used.

[0110] Furthermore, various types of transistors can be used as the transistors constituting buffer 112a, buffer 112b, register 117, and pixel 122, respectively. For example, MOS field-effect transistors, junction field-effect transistors, or bipolar transistors can be used.

[0111] Furthermore, transistors of various structures can be used as the transistors constituting buffer 112a, buffer 112b, register 117, and pixel 122, respectively. For example, various transistor structures can be used, such as top-gate type (planar type, staggered type, etc.), bottom-gate type (inverse planar type, inverse staggered type, etc.), dual-gate type (a structure in which gates are arranged on both sides (e.g., top and bottom) of the channel formation region), FIN type, TRI-GATE type, or GAA type (gate all-around type). In addition, for example, vertical transistors (transistors whose channel length direction has a component in the vertical direction (also called the height direction or the direction perpendicular to the surface to be formed)) can be used.

[0112] In this case, it is preferable to use a transistor with a small off-current for the transistor M31 in the pixel 122. For example, an OS transistor can be used as a transistor with a small off-current. This allows the image signal written to the pixel 122 to be retained for a long period of time. Therefore, for example, the display device can be operated at a low refresh rate, and power consumption can be reduced.

[0113] Furthermore, in pixel 122, it is preferable to use a transistor with a small hysteresis width for transistor M32. For example, an OS transistor can be used as a transistor with a small hysteresis width. This can improve the display quality of the display device. In addition, in pixel 122, it may not be necessary to have a function to suppress the effects of the hysteresis characteristics of transistor M32, and the configuration of pixel 122 can be simplified. This can reduce the layout area of ​​the pixels and improve the resolution of the display device.

[0114] Furthermore, in the drive circuit 101, it is preferable to use transistors with high on-current as the transistors constituting buffer 112a, buffer 112b, and register 117, respectively. This improves the operating speed of the drive circuit 101. Also, for example, even if the channel width of the transistor is reduced, sufficient on-current can be easily obtained, so the layout area can be reduced. Therefore, the bezel width of the display device can be reduced.

[0115] In this case, it is preferable that the transistors constituting the pixel 122, buffer 112a, buffer 112b, and register 117 are manufactured in the same process. Therefore, it is preferable to use transistors that have characteristics of low off-current, low hysteresis width, and high on-current as the transistors constituting the pixel 122, buffer 112a, buffer 112b, and register 117. Examples of such transistors include transistors that contain indium oxide in the channel formation region.

[0116] Examples of transistor configurations that can be applied to each of the pixels 122, buffer 112a, buffer 112b, and register 117 will be described in Embodiment 2 below.

[0117] <Example of Drive Circuit Operation 1> Next, an example of the operation of the drive circuit 101A shown in Figure 5 will be described. Here, as an example, four operation examples will be described: normal mode, low resolution mode 1, low resolution mode 2, and low resolution mode 3.

[0118] In the description of the operation, it is assumed that the drive circuit 101A is supplied with a potential L and a potential H that is higher than potential L. For example, it is assumed that potential L is supplied to wiring VLS1 and wiring VLS2, and potential H is supplied to wiring VLD1 and wiring VLD2. Furthermore, each signal supplied to the drive circuit 101A is assumed to change between two values: potential L and potential H. It is assumed that a signal is output when a pulse signal that is at potential H for a certain period of time is output.

[0119] [Normal Mode] Figure 10 is a timing chart illustrating an example of operation in normal mode. In normal mode, signals are output sequentially one line at a time to both the wiring group GOLagp and the wiring group GOLBgp. In normal mode, signals are output sequentially one line at a time from both the buffer group 111a and the buffer group 111b.

[0120] As shown in Figure 10, signals are sequentially output from the shift register 113 to the wiring group SRLagp and the wiring group SRLbgp. For each of the four wirings PKLa in the wiring group PKLagp, a signal with a pulse width 1 / 4 of the signal output to the wiring group SRLagp is supplied, with a phase shift of 1 / 4 periods during the period when a signal is output to the wiring group SRLagp. For each of the four wirings PKLb in the wiring group PKLbgp, a signal with a pulse width 1 / 4 of the signal output to the wiring group SRLbgp is supplied, with a phase shift of 1 / 4 periods during the period when a signal is output to the wiring group SRLbgp. As a result, one line of signals is sequentially output to both the wiring group GOLagp and the wiring group GOLbgp.

[0121] The wiring group GOLagp is connected in a one-to-one correspondence to multiple gate lines 123a provided in the pixel area 121a. Therefore, in the pixel area 121a, pixels 122 are selected one row at a time, and image signals are written one row at a time. Similarly, the wiring group GOLBgp is connected in a one-to-one correspondence to gate lines 123b provided in the pixel area 121b. Therefore, in the pixel area 121b, pixels 122 are selected one row at a time, and image signals are written one row at a time.

[0122] [Low Resolution Mode 1] Figure 11 is a timing chart illustrating an example of operation in low resolution mode 1. Low resolution mode 1 is a mode in which signals are output sequentially one row at a time to the wiring group GOLagp and signals are output sequentially two rows at a time to the wiring group GOLBgp. In low resolution mode 1, signals are output sequentially one row at a time from buffer group 111a and signals are output sequentially two rows at a time from buffer group 111b.

[0123] In low-resolution mode 1, the signals output from the shift register 113 to the wiring groups SRLagp and SRLbgp are the same as in normal mode. Furthermore, each of the four wirings PKLa in the wiring group PKLagp is supplied with the same signals as in normal mode. Therefore, the signals output to the wiring group GOLagp are the same as in normal mode.

[0124] As shown in Figure 11, each of the four wirings PKLb in wiring group PKLbgp is supplied with a signal different from the normal mode. Two adjacent wirings PKLb of the four wirings PKLbgp are supplied with a signal having half the pulse width of the signal output to wiring group SRLbgp during the period when a signal is output to wiring group SRLbgp. The remaining two adjacent wirings PKLb are supplied with a signal whose phase is shifted by half the period of the same signal. As a result, signals are output to wiring group GOLbgp in two rows at a time.

[0125] The wiring group GOLbgp is connected in a one-to-one correspondence to the gate line 123b provided in the pixel area 121b. Therefore, in the pixel area 121b, two adjacent rows of pixels 122 are selected and the image signal is written to them.

[0126] [Low Resolution Mode 2] Figure 12 is a timing chart illustrating an example of operation in low resolution mode 2. Low resolution mode 2 is a mode in which signals are output sequentially one row at a time to the wiring group GOLagp and four rows at a time to the wiring group GOLBgp. In low resolution mode 2, one row at a time is output sequentially from buffer group 111a and four rows at a time are output sequentially from buffer group 111b.

[0127] In low-resolution mode 2, the signals output from the shift register 113 to the wiring groups SRLagp and SRLbgp are the same as in normal mode. Furthermore, each of the four wirings PKLa in wiring group PKLagp is supplied with the same signals as in normal mode. Therefore, the signals output to wiring group GOLagp are the same as in normal mode.

[0128] As shown in Figure 12, each of the four wirings PKLb in wiring group PKLbgp is supplied with a signal different from that of normal mode and low-resolution mode 1. For the duration that a signal is output to wiring group SRLbgp, each of the four wirings PKLb in wiring group PKLbgp is supplied with a signal having half the pulse width of the signal output to wiring group SRLbgp, in the same phase. As a result, signals are output to wiring group GOLbgp in four rows at a time.

[0129] The wiring group GOLbgp is connected in a one-to-one correspondence to the gate lines 123b provided in the pixel area 121b. Therefore, in the pixel area 121b, four adjacent rows of pixels 122 are selected and the image signal is written to them.

[0130] [Low Resolution Mode 3] Figure 13 is a timing chart illustrating an example of operation in low resolution mode 3. Low resolution mode 3 is a mode in which signals are output sequentially one row at a time to the wiring group GOLagp and four rows at a time to the wiring group GOLBgp. In low resolution mode 3, one row at a time is output sequentially from buffer group 111a and four rows at a time are output sequentially from buffer group 111b.

[0131] In low-resolution mode 3, the signals output from the shift register 113 to the wiring groups SRLagp and SRLbgp are the same as in normal mode. Furthermore, each of the four wirings PKLa in wiring group PKLagp is supplied with the same signals as in normal mode. Therefore, the signals output to wiring group GOLagp are the same as in normal mode.

[0132] As shown in Figure 13, each of the four wirings PKLb in the wiring group PKLbgp is supplied with a signal different from that of normal mode, low resolution mode 1, and low resolution mode 2. Each of the four wirings PKLb in the wiring group PKLbgp is supplied with a potential H. As a result, signals with the same pulse width as the signals output to the wiring group SRLbgp are sequentially output to the wiring group GOLbgp, one line at a time.

[0133] The wiring group GOLbgp is connected in a one-to-one correspondence to the gate lines 123b provided in the pixel area 121b. Therefore, in the pixel area 121b, four adjacent rows of pixels 122 are selected and the image signal is written to them.

[0134] In low-resolution mode 3, the signals supplied to each of the four wirings PKLb of the wiring group PKLbgp may be stopped, and a constant potential (in this case, always potential H) may be supplied. Thus, so-called clock gating can be performed. This can reduce power consumption.

[0135] Note that the operation examples of the drive circuit 101A are not limited to those described. Here, an example of displaying only the pixel area 121b at a low resolution has been described, but it is also possible to display only the pixel area 121a at a low resolution, or to display both the pixel area 121a and the pixel area 121b at a low resolution. In this case, the above-described operation examples can be applied to each of the buffer groups 111a and 111b. Furthermore, even when there are three or more pixel areas, the above-described operation examples can be applied to each buffer group corresponding to each pixel area.

[0136] Furthermore, the operating mode of the drive circuit 101A can be appropriately changed according to the operating status or usage status of the display device having the drive circuit 101A. For example, it may be set differently depending on the image being displayed, or the operating mode may be changed depending on the area the user is focusing on.

[0137] <Example 2 of drive circuit configuration> A specific example of a drive circuit 101 that differs from the above will be described.

[0138] Figure 14 is a circuit diagram illustrating a specific example of the drive circuit 101, namely drive circuit 101B.

[0139] The drive circuit 101B shown in Figure 14 is a modified version of the drive circuit 101A shown in Figure 5, and includes a gate line selection circuit 118a provided between the buffer group 111a and the wiring group GOLagp, and a gate line selection circuit 118b provided between the buffer group 111b and the wiring group GOLBgp. Therefore, it can also be said that the gate line selection circuit 118a is provided between the buffer 112a and the pixel region 121a (not shown), and the gate line selection circuit 118b is provided between the buffer 112b and the pixel region 121b (not shown).

[0140] The gate line selection circuit 118a has the function of controlling the signal output from one buffer 112a (corresponding to the signal supplied to the wiring 116a shown in Figure 1 above) to be supplied to one gate line 123a or multiple adjacent gate lines 123a provided in the pixel region 121a. The gate line selection circuit 118a has a switch (such as a transistor) for controlling the exchange of signals between one buffer 112a and one wiring GOLa (corresponding to the gate line 123a) corresponding to the buffer 112a. It also has a switch for controlling the exchange of signals between two adjacent wirings GOLa. As a result, the signal output from one buffer 112a can be supplied to one gate line 123a or multiple adjacent gate lines 123a.

[0141] The gate line selection circuit 118b has the function of controlling the signal output from one buffer 112b (corresponding to the signal supplied to the wiring 116b shown in Figure 1 above) to be supplied to one gate line 123b or multiple adjacent gate lines 123b provided in the pixel area 121b. The gate line selection circuit 118b has a switch (such as a transistor) for controlling the exchange of signals between one buffer 112b and one wiring GOLb corresponding to the buffer 112b (corresponding to the gate line 123b). It also has a switch for controlling the exchange of signals between two adjacent wiring GOLb. As a result, the signal output from one buffer 112b can be supplied to one gate line 123b or multiple adjacent gate lines 123b.

[0142] <Example of drive circuit operation 2> Next, we will explain an example of the operation of the drive circuit 101B shown in Figure 14. Here, as an example, we will explain four operation examples: normal mode, low resolution mode 4, low resolution mode 5, and low resolution mode 6.

[0143] In the description of the operation, it is assumed that the drive circuit 101B is supplied with a potential L and a potential H that is higher than potential L. For example, it is assumed that potential L is supplied to wiring VLS1 and wiring VLS2, and potential H is supplied to wiring VLD1 and wiring VLD2. Furthermore, it is assumed that each signal supplied to the drive circuit 101B changes between two values: potential L and potential H.

[0144] [Normal Mode] The normal mode is a mode in which signals are output sequentially to both the wiring group GOLagp and the wiring group GOLBgp, one line at a time. In this mode, the gate line selection circuit 118a is controlled so that the signal output from one buffer 112a is supplied to one wiring GOLa, and the gate line selection circuit 118b is controlled so that the signal output from one buffer 112b is supplied to one wiring GOLB.

[0145] In normal mode, the signals output from the shift register 113 to the wiring groups SRLagp and SRLbgp, the signals given to each of the four wirings PKLa in the wiring group PKLagp, the signals given to each of the four wirings PKLb in the wiring group PKLbgp, the signals output to the wiring group GOLagp, and the signals output to the wiring group GOLBgp are the same as those shown in the timing chart in Figure 10 above. Therefore, the above explanation can be used as a reference.

[0146] [Low Resolution Mode 4] Figure 15 is a timing chart illustrating an example of operation in low resolution mode 4. Low resolution mode 4 is a mode in which signals are output sequentially one row at a time to the wiring group GOLagp and signals are output sequentially two rows at a time to the wiring group GOLbgp. In this mode, the gate line selection circuit 118a is controlled so that the signal output from one buffer 112a is supplied to one wiring GOLa, and the gate line selection circuit 118b is controlled so that the signal output from one buffer 112b is supplied to two adjacent wirings GOLb.

[0147] In low-resolution mode 4, the signals output from the shift register 113 to the wiring group SRLagp and the wiring group SRLbgp are the same as in normal mode. In addition, each of the four wirings PKLa in the wiring group PKLagp is supplied with the same signals as in normal mode. Therefore, the signals output to the wiring group GOLagp are the same as in normal mode.

[0148] As shown in Figure 15, each of the four wirings PKLb in wiring group PKLbgp is supplied with a signal different from the normal mode. One of the four wirings PKLb in wiring group PKLbgp is supplied with a signal having half the pulse width of the signal output to wiring group SRLbgp during the period when a signal is output to wiring group SRLbgp. This wiring PKLb and every other wiring PKLb are supplied with a signal whose phase is shifted by half the period of the above signal. The remaining two wirings PKLb are supplied with a potential L. As a result, signals are output to wiring group GOLbgp in two rows at a time.

[0149] The wiring group GOLbgp is connected in a one-to-one correspondence to the gate line 123b provided in the pixel area 121b. Therefore, in the pixel area 121b, two adjacent rows of pixels 122 are selected and the image signal is written to them.

[0150] [Low Resolution Mode 5] Figure 16 is a timing chart illustrating an example of operation in low resolution mode 5. Low resolution mode 5 is a mode in which signals are output sequentially to the wiring group GOLagp one row at a time, and signals are output sequentially to the wiring group GOLBgp four rows at a time. In this mode, the gate line selection circuit 118a is controlled so that the signal output from one buffer 112a is supplied to one wiring GOLa, and the gate line selection circuit 118b is controlled so that the signal output from one buffer 112b is supplied to four adjacent wirings GOLB.

[0151] In low-resolution mode 5, the signals output from the shift register 113 to the wiring groups SRLagp and SRLbgp are the same as in normal mode. Furthermore, each of the four wirings PKLa in wiring group PKLagp is supplied with the same signals as in normal mode. Therefore, the signal output to wiring group GOLagp is the same as in normal mode.

[0152] As shown in Figure 16, each of the four wirings PKLb in wiring group PKLbgp is supplied with a signal different from that of the normal mode and the low-resolution mode. One of the four wirings PKLb in wiring group PKLbgp is supplied with a signal having half the pulse width of the signal output to wiring group SRLbgp during the period when a signal is output to wiring group SRLbgp. The remaining three wirings PKLb are supplied with a potential L. As a result, signals are output to wiring group GOLbgp in sequence, four lines at a time.

[0153] The wiring group GOLbgp is connected in a one-to-one correspondence to the gate lines 123b provided in the pixel area 121b. Therefore, in the pixel area 121b, four adjacent rows of pixels 122 are selected and the image signal is written to them.

[0154] [Low Resolution Mode 6] Figure 17 is a timing chart illustrating an example of operation in low resolution mode 6. Low resolution mode 6 is a mode in which signals are output sequentially to the wiring group GOLagp one row at a time, and signals are output sequentially to the wiring group GOLBgp four rows at a time. In this mode, the gate line selection circuit 118a is controlled so that the signal output from one buffer 112a is supplied to one wiring GOLa, and the gate line selection circuit 118b is controlled so that the signal output from one buffer 112b is supplied to four adjacent wirings GOLB.

[0155] In low-resolution mode 6, the signals output from the shift register 113 to the wiring groups SRLagp and SRLbgp are the same as in normal mode. Furthermore, each of the four wirings PKLa in wiring group PKLagp is supplied with the same signals as in normal mode. Therefore, the signals output to wiring group GOLagp are the same as in normal mode.

[0156] As shown in Figure 17, each of the four wirings PKLb in the wiring group PKLbgp is supplied with a signal different from that of normal mode, low-resolution mode 4, and low-resolution mode 5. One of the four wirings PKLb in the wiring group PKLbgp is supplied with a potential H. The remaining three wirings PKLb are supplied with a potential L. As a result, signals are output sequentially to the wiring group GOLbgp in groups of four.

[0157] The wiring group GOLbgp is connected in a one-to-one correspondence to the gate lines 123b provided in the pixel area 121b. Therefore, in the pixel area 121b, four adjacent rows of pixels 122 are selected and the image signal is written to them.

[0158] Here, low-resolution modes 4, 5, and 6 in the drive circuit 101B correspond to low-resolution modes 1, 2, and 3 in the drive circuit 101A described above. In the drive circuit 101B, in each of low-resolution modes 4, 5, and 6, the signal supplied to at least one of the four wirings PKLb of the wiring group PKLbgp may be stopped, and a constant potential (here, always potential L) may be supplied. Thus, so-called clock gating or power gating can be performed. This makes it possible to reduce power consumption.

[0159] The operation examples of the drive circuit 101B are not limited to those described here. Here, an example of displaying only the pixel area 121b at a low resolution has been described, but it is also possible to display only the pixel area 121a at a low resolution, or to display both the pixel area 121a and the pixel area 121b at a low resolution. In this case, the above-described operation examples can be applied to each of the buffer groups 111a and 111b. Furthermore, even when there are three or more pixel areas, the above-described operation examples can be applied to each buffer group corresponding to each pixel area.

[0160] Furthermore, the operating mode of the drive circuit 101B can be appropriately changed according to the operating status or usage status of the display device having the drive circuit 101B. For example, it may be set differently depending on the image being displayed, or the operating mode may be changed depending on the area the user is focusing on.

[0161] One aspect of the present invention is all or part of the circuit configuration described herein. Therefore, one aspect of the present invention does not have to include all or part of the operations described herein. Furthermore, one aspect of the present invention is not limited to the operations described herein, and it is possible to appropriately change the potential applied to each wire, the timing of the change in that potential, etc.

[0162] <Example of Display Device Configuration> Next, a display device according to one aspect of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to one aspect of the present invention can be used in the display device.

[0163] Figure 18A is a block diagram illustrating an example of the configuration of a display device 160 according to one aspect of the present invention.

[0164] As shown in Figure 18A, the display device 160 includes a pixel unit 162, a gate driver unit 163, a source driver unit 164, and a control unit 167. The pixel unit 162 has, for example, a plurality of pixels 161 arranged in a matrix of m rows and n columns (where m is an integer of 2 or more, and n is an integer of 2 or more).

[0165] Each pixel 161 has a display element such as a liquid crystal element or a light-emitting element. In this case, the display device 160 can also be said to have the function of an output device. Furthermore, each pixel 161 may have a light-receiving element. In this case, the display device 160 can also be said to have the function of an imaging device (sometimes called an input device). Also, each pixel 161 may have both a display element and a light-receiving element. In this case, the display device 160 can also be said to have the function of both a display device and an imaging device (sometimes called an input / output device).

[0166] In Figure 18A, the pixel 161 located in the first row and first column is shown as pixel 161[1,1], the pixel 161 located in the first row and nth column is shown as pixel 161[1,n], the pixel 161 located in the m row and first column is shown as pixel 161[m,1], and the pixel 161 located in the m row and nth column is shown as pixel 161[m,n]. In some cases, the pixel 161 located in the u row and v column (where u is an integer between 1 and m, and v is an integer between 1 and n) is shown as pixel 161[u,v]. When describing matters common to multiple pixels 161, they may not be described with identification codes such as "[u,v]".

[0167] Furthermore, the display device 160 has m gate lines 165, each arranged in parallel, and whose potential is controlled by a circuit included in the gate driver unit 163. The potential of one gate line 165 is supplied to n pixels 161 arranged in the row direction. Depending on the configuration of the pixels 161, a configuration in which multiple wires are included per gate line 165 is also possible.

[0168] Furthermore, the display device 160 has n source lines 166, each arranged in parallel, and whose potential is controlled by a circuit included in the source driver unit 164. The potential of one source line 166 is supplied to m pixels 161 arranged in the column direction. Depending on the configuration of the pixels 161, each source line 166 may be configured to include multiple wires.

[0169] The circuit included in the gate driver unit 163 functions, for example, as a scan line drive circuit (sometimes called a gate line drive circuit, gate driver, scan driver, or low driver).

[0170] The circuit included in the source driver unit 164 functions, for example, as a signal line drive circuit (sometimes called a source line drive circuit, source driver, data driver, or column driver).

[0171] One of the circuits included in the control unit 167 functions, for example, as a power supply circuit. Another circuit included in the control unit 167 functions, for example, as a signal generation circuit.

[0172] The display device 160 does not necessarily have to have one or both of the source driver unit 164 and the control unit 167. For example, one or both of the source driver unit 164 and the control unit 167 may be provided on an IC (Integrated Circuit) chip located outside the display device 160. In this case, a part of the source driver unit 164 and the control unit 167 may be provided on the display device 160.

[0173] One aspect of the present invention allows the display device 160 to use at least a part of the semiconductor device 100 described above. For example, the drive circuit 101 can be applied to the gate driver unit 163, the pixel unit 102 to the pixel unit 162, and the pixel 122 to the pixel 161. Here, as an example, the case in which the pixel unit 162 has three pixel regions (pixel region 121a, pixel region 121b, and pixel region 121c) is shown. Therefore, the gate driver unit 163 has a shift register 113 and three buffer groups (buffer group 111a, buffer group 111b, and buffer group 111c).

[0174] Furthermore, the control unit 167 has the function of generating signals and constant potentials for operating the drive circuit 101 applied to the gate driver unit 163. For example, the control unit 167 has the function of supplying signals to each of the wiring groups PKLagp, PKLagp, CKLgp, and SPL. It also has the function of supplying constant potentials to each of the wiring VLS1, VLS2, VLD1, and VLD2. When the drive circuit 101B is applied as the drive circuit 101, the control unit 167 may also have the function of generating signals to control the operation of the gate line selection circuit 118a and the gate line selection circuit 118b.

[0175] Figure 18B is a block diagram illustrating a modified example of the display device 160. The display device 160 shown in Figure 18B differs from the display device 160 shown in Figure 18A in that it has two gate driver units 163 arranged to face each other via a pixel unit 162. In the configuration shown in Figure 18B, the potential of m gate lines 165 is controlled by the two gate driver units 163. With this configuration, for example, the actual wiring load (parasitic capacitance and parasitic resistance) can be reduced to 1 / 4 of the wiring load in the display device 160 shown in Figure 18A. Therefore, at least one of the following can be achieved for the display device 160: higher speed, higher resolution, higher resolution, narrower bezel, and larger screen.

[0176] In one aspect of the present invention, various transistors can be used as the transistors constituting the display device 160. For example, a Si transistor (a transistor containing silicon in its channel formation region) may be used, an OS transistor (a transistor containing oxide semiconductor in its channel formation region) may be used, or both a Si transistor and an OS transistor may be used.

[0177] OS transistors can be freely arranged on a silicon substrate, for example, on which Si transistors are mounted, making integration easy. Furthermore, since OS transistors can be manufactured using the same manufacturing equipment as Si transistors, they can be produced at low cost.

[0178] Therefore, in the display device 160, for example, Si transistors containing part of a silicon substrate may be used for the transistors constituting the source driver unit 164, and OS transistors provided on a silicon substrate may be used for the transistors constituting the gate driver unit 163 and the pixel unit 162, respectively. Furthermore, OS transistors may be used for at least a portion of the transistors constituting the source driver unit 164, and Si transistors may be used for at least a portion of the transistors constituting the gate driver unit 163 and the pixel unit 162, respectively.

[0179] Furthermore, various circuits (which may include arithmetic circuits, memory circuits, etc.) for controlling the operation of the display device 160 may be provided using Si transistors that include a portion of the silicon substrate. Thus, in one aspect of the present invention, for example, an OS transistor is arranged on a silicon substrate on which Si transistors are provided, and a display element or light-receiving element is arranged on the layer on which the OS transistors are provided.

[0180] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0181] (Embodiment 2) This embodiment describes a transistor according to one aspect of the present invention. At least a part of the transistor shown in this embodiment can be applied to the drive circuit, semiconductor device, and display device shown in Embodiment 1 described above.

[0182] <Transistor Configuration Example 1> Figure 19A is a top view of a semiconductor device having transistor 200A. Figure 19B is a cross-sectional view between A1 and A2, shown by a dashed line in Figure 19A. Figure 19C is a cross-sectional view between A3 and A4, shown by a dashed line in Figure 19A. Note that some elements have been omitted from the top view of Figure 19A for clarity. Some elements may also be omitted in other top views.

[0183] In the semiconductor device shown in Figures 19A to 19C, an insulating layer 202 is provided on a substrate 201, and a semiconductor layer 203 is provided on the insulating layer 202. Furthermore, an insulating layer 204 is provided on the insulating layer 202 and the semiconductor layer 203. In addition, a conductive layer 205 is provided on the insulating layer 204. In this case, the semiconductor layer 203 and the conductive layer 205 are provided so as to have overlapping regions with respect to the insulating layer 204.

[0184] The semiconductor layer 203 has a region 203a that functions as either the source region or the drain region of the transistor 200A, a channel-forming region 203c, and a region 203b that functions as the other of the source region or the drain region. In the semiconductor layer 203, the region that overlaps with the conductive layer 205 functions as the channel-forming region 203c. Therefore, the region of the conductive layer 205 that overlaps with the channel-forming region 203c functions as the gate electrode of the transistor 200A. Also, the region of the insulating layer 204 that overlaps with the channel-forming region 203c functions as the gate insulating film of the transistor 200A.

[0185] Furthermore, in the semiconductor layer 203, the shortest distance between region 203a and region 203b in the channel formation region 203c can be set to the channel length Lch of the transistor 200A (see Figures 19A and 19B). Also, in the semiconductor layer 203, the length of the portion where region 203a and region 203b face each other in the channel formation region 203c can be set to the channel width Wch of the transistor 200A (see Figures 19A and 19C).

[0186] Furthermore, in the semiconductor device shown in Figures 19A to 19C, an insulating layer 206 is provided on top of the insulating layer 204 and the conductive layer 205. In addition, an opening 207a is provided in the insulating layer 204 and the insulating layer 206 in the region overlapping with region 203a of the semiconductor layer 203. In addition, an opening 207b is provided in the insulating layer 204 and the insulating layer 206 in the region overlapping with region 203b of the semiconductor layer 203. Furthermore, a conductive layer 208a is provided on top of the insulating layer 206 and within the opening 207a, and a conductive layer 208b is provided on top of the insulating layer 206 and within the opening 207b. Furthermore, an insulating layer 209 is provided on top of the insulating layer 206 and the conductive layer 208 (conductive layer 208a and conductive layer 208b).

[0187] The conductive layer 208a is in contact with region 203a of the semiconductor layer 203 at the bottom of the opening 207a. Similarly, the conductive layer 208b is in contact with region 203b of the semiconductor layer 203 at the bottom of the opening 207b. Therefore, the conductive layer 208a functions as either the source electrode or the drain electrode of the transistor 200A, and the conductive layer 208b functions as either the source electrode or the drain electrode of the transistor 200A.

[0188] <Transistor Configuration Example 2> Figure 20A is a top view of a semiconductor device having transistor 200B. The semiconductor device having transistor 200B is a modified version of the semiconductor device having transistor 200A described above. To reduce repetition in the explanation, we will mainly explain the differences between the semiconductor device having transistor 200B and the semiconductor device having transistor 200A.

[0189] Figure 20B is a cross-sectional view between A1 and A2, shown by the dashed line in Figure 20A. Figure 20C is a cross-sectional view between A3 and A4, shown by the dashed line in Figure 20A.

[0190] The semiconductor device shown in Figures 20A to 20C differs from the semiconductor device shown in Figures 19A to 19C in that it has a conductive layer 215 between the substrate 201 and the insulating layer 202. The conductive layer 215 overlaps with the channel formation region 203c via the insulating layer 202. Therefore, the region of the insulating layer 202 that overlaps with the channel formation region 203c functions as the back gate insulating film of the transistor 200B, and the region of the conductive layer 215 that overlaps with the channel formation region 203c functions as the back gate electrode of the transistor 200B.

[0191] The insulating layer 202 may have different film thicknesses in the region overlapping with the conductive layer 215 and the region not overlapping with it, or it may have a uniform film thickness. The conductive layer 215 may also extend beyond the edge of the channel-forming region 203c. Although not shown in the figures, an insulating layer may be provided between the substrate 201 and the conductive layer 215.

[0192] In a transistor with a back gate, the transistor's gate and back gate are positioned so as to sandwich the channel formation region of the semiconductor layer. The back gate can function similarly to the gate. When the gate is used to control the on and off states of the transistor, the potential of the back gate can be the same as that of the gate. Alternatively, it can be set to any potential.

[0193] For example, when turning on a transistor, supplying the potential that turns the transistor on to both the gate and the back gate can increase the on-current compared to supplying it to only one. For example, by connecting the gate and the back gate, it is possible to keep the gate and back gate at the same potential at all times. Furthermore, by controlling the potential of the back gate independently of the gate potential, the threshold voltage of the transistor can be adjusted. For example, supplying the potential that turns the transistor on to the back gate can decrease the threshold voltage of the transistor, and supplying the potential that turns the transistor off to the back gate can increase the threshold voltage of the transistor.

[0194] Furthermore, a constant potential, such as ground potential, may be supplied to the back gate. Since the gate and back gate are formed by conductive layers, sandwiching the channel formation region of the semiconductor layer between the gate and back gate makes it difficult for electric fields generated outside the transistor to act on the channel formation region (also known as the "electric field shielding effect"). For this reason, providing a back gate to a transistor stabilizes its operation. In addition, providing a back gate to a transistor reduces the variation in characteristics between multiple transistors. Providing a back gate to a transistor can improve the reliability of the transistor. Therefore, the reliability of the semiconductor device containing the transistor can be improved. Note that the electric field shielding effect can be obtained even if one or both of the gate and back gate are electrically floating (also known as the "floating state"), but the effect can be enhanced by supplying potential to the gate and back gate.

[0195] <Transistor Configuration Example 3> Figure 21A is a top view of a semiconductor device having a transistor 200C. Figure 21B is a cross-sectional view between A1 and A2, shown by a dashed line in Figure 21A. Figure 21C is a cross-sectional view between A3 and A4, shown by a dashed line in Figure 21A. Note that Figure 21B is a cross-sectional view of transistor 200C in the channel length direction, and Figure 21C is a cross-sectional view of transistor 200C in the channel width direction.

[0196] Figures 21A to 21C show an insulating layer 202 placed on a substrate 201, and an insulating layer 514 placed on top of the insulating layer 202. Also shown are an insulating layer 516 placed on top of the insulating layer 514, a conductive layer 505 placed so as to be embedded in the insulating layer 516, an insulating layer 522 placed on top of the insulating layer 516 and the conductive layer 505, and an insulating layer 524 placed on top of the insulating layer 522. Also shown are a semiconductor layer 520a placed on top of the insulating layer 524, a semiconductor layer 520b placed on top of the semiconductor layer 520a, conductive layers 542a and 542b placed on top of the semiconductor layer 520b at a distance from each other, an insulating layer 580 placed on top of the conductive layers 542a and 542b with an opening formed between the conductive layers 542a and 542b, and a conductive layer 560 placed in the opening, and a semiconductor The diagram shows an insulating layer 550 positioned between layer 520b, conductive layer 542a, conductive layer 542b, insulating layer 580, and conductive layer 560; a semiconductor layer 520c positioned between semiconductor layer 520b, conductive layer 542a, conductive layer 542b, insulating layer 580, and insulating layer 550; and an insulating layer 554 positioned between insulating layer 524, semiconductor layer 520, conductive layer 542a, conductive layer 542b, and insulating layer 580. The diagram also shows an insulating layer 574 positioned on top of insulating layer 580, semiconductor layer 520c, insulating layer 550, and conductive layer 560, and an insulating layer 581 positioned on top of insulating layer 574. The diagram also shows a conductive layer 545a embedded in insulating layer 554, insulating layer 580, insulating layer 574, and insulating layer 581 and positioned in contact with the upper surface of conductive layer 542a; an insulating layer 541a positioned between insulating layer 554, insulating layer 580, insulating layer 574, and insulating layer 581 and conductive layer 545a; a conductive layer 545b embedded in insulating layer 554, insulating layer 580, insulating layer 574, and insulating layer 581 and positioned in contact with the upper surface of conductive layer 542b; and an insulating layer 541b positioned between insulating layer 554, insulating layer 580, insulating layer 574, and insulating layer 581 and conductive layer 545b.

[0197] Here, as shown in Figures 21B and 21C, the height of the upper surface of the conductive layer 505 is the same as the height of the upper surface of the insulating layer 516. Also, the height of the upper surface of the conductive layer 560 is the same as the height of the upper surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. Furthermore, the insulating layer 554 is in contact with the upper and side surfaces of the conductive layer 542a, the upper and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520, and the upper surface of the insulating layer 524. Note that the semiconductor layers 520a, 520b, and 520c are sometimes collectively referred to as the semiconductor layer 520. Also, the conductive layers 542a and 542b are sometimes collectively referred to as the conductive layer 542. Also, the conductive layers 545a and 545b are sometimes collectively referred to as the conductive layer 545. Also, the insulating layers 541a and 541b are sometimes collectively referred to as the insulating layer 541.

[0198] The conductive layer 542a functions as either the source electrode or the drain electrode of the transistor 200C. The conductive layer 542b functions as the other source electrode or drain electrode of the transistor 200C. In the semiconductor layer 520, the region overlapping with the conductive layer 560 functions as the channel formation region of the transistor 200C. Therefore, the conductive layer 560 functions as the gate electrode of the transistor 200C. The insulating layer 550 functions as the gate insulating film of the transistor 200C. The conductive layer 505 functions as the back gate electrode of the transistor 200C. The insulating layers 522 and 524 function as the back gate insulating films of the transistor 200C.

[0199] Here, the channel formation region of transistor 200C is formed in the semiconductor layer 520 between a region that functions as either the source region or the drain region and a region that functions as the other of the source region or the drain region. Therefore, the shortest distance between conductive layer 542a and conductive layer 542b can be set to the channel length Lch of transistor 200C (see Figures 21A and 21B). Also, the length of the portion where conductive layer 542a and conductive layer 542b face each other can be set to the channel width Wch of transistor 200C (see Figures 21A and 21C).

[0200] Figures 21B and 21C show a configuration in which the channel formation region and its vicinity are stacked in three layers: semiconductor layer 520a, semiconductor layer 520b, and semiconductor layer 520c. However, the configuration is not limited to this; for example, the semiconductor layer 520 may be configured as a stacked in two layers: semiconductor layer 520b and semiconductor layer 520c, or as a stacked in four or more layers. Alternatively, each of the semiconductor layers 520a, 520b, and 520c may be configured as a stacked in two or more layers.

[0201] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, and the semiconductor layer 520c has a laminated structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide may have the same composition as the semiconductor layer 520b, and the second metal oxide may have the same composition as the semiconductor layer 520a.

[0202] The conductive layer 560 is formed to be embedded in the opening formed in the insulating layer 580 and in the region sandwiched between the conductive layers 542a and 542b. Here, the arrangement of the conductive layer 560, conductive layer 542a, and conductive layer 542b is self-aligned with respect to the opening formed in the insulating layer 580. Therefore, in the transistor 200C, the gate electrode can be self-aligned between the source electrode and the drain electrode. Thus, the conductive layer 560 can be formed without providing a positioning margin, and the layout area of ​​the transistor 200C can be reduced. This reduces the layout area of ​​the semiconductor device. Furthermore, the integration density of the semiconductor device can be increased.

[0203] Figures 21A to 21C show a configuration in which the conductive layer 560 has a two-layer laminated structure. Specifically, the conductive layer 560 has a conductive layer 560a provided on the insulating layer 550 and a conductive layer 560b provided on the conductive layer 560a, located inside the opening formed in the insulating layer 580. However, it is not limited to this configuration, and for example, the conductive layer 560 may be configured as a single layer or a laminated structure of three or more layers.

[0204] Furthermore, Figures 21A to 21C show a configuration in which the conductive layer 505 has a three-layer laminated structure. Specifically, the conductive layer 505 has a conductive layer 505a provided in contact with the upper surface of the insulating layer 514 and the side surface of the insulating layer 516, a conductive layer 505b provided in contact with the upper surface and side surface of the conductive layer 505a, and a conductive layer 505c provided in contact with the side surface of the conductive layer 505a and the upper surface of the conductive layer 505b. However, it is not limited to this, and for example, the conductive layer 505 may be configured as a single-layer, two-layer laminated structure or a four-layer or more laminated structure.

[0205] Here, when an oxide semiconductor is used as the semiconductor layer 520, insulating layers 514, 522, 554, and 574 may be insulating layers that have the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or hydrogen molecule). For example, insulating layers 514, 522, 554, and 574 may be insulating layers with lower hydrogen permeability than insulating layers 516, 524, 550, and 580. In addition, insulating layers 522 and 554 may be insulating layers that have the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). For example, insulating layers 522 and 554 may be insulating layers with lower oxygen permeability than insulating layers 516, 524, 550, and 580. For insulating layers 514, 522, 554, and 574, for example, silicon nitride, silicon oxide nitride, etc. can be used.

[0206] In this configuration, the insulating layer 524, semiconductor layer 520, and insulating layer 550 are separated from the layers above insulating layer 574 and below insulating layer 522 by insulating layers 522 and 574, respectively. Therefore, it is possible to suppress the mixing of impurities such as hydrogen and excess oxygen contained in the layers above insulating layer 574 and below insulating layer 522 into the insulating layer 524, semiconductor layer 520, and insulating layer 550.

[0207] The conductive layer 545 functions as a plug. In Figure 21B, the conductive layer 545 is shown as a two-layer laminated structure. Specifically, the conductive layer 545 has a first conductive layer provided in contact with the upper surface of the conductive layer 542 and the side surface of the insulating layer 541, and a second conductive layer provided in contact with the upper surface and side surface of the first conductive layer. However, it is not limited to this, and for example, the conductive layer 545 may be configured as a single layer or a laminated structure of three or more layers.

[0208] Furthermore, the thickness of the semiconductor layer 520b in the region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is formed by removing a portion of the upper surface of the semiconductor layer 520b when forming the conductive layer 542. When a conductive film that will become the conductive layer 542 is deposited on the upper surface of the semiconductor layer 520b, a region with low resistance may be formed near the interface with the conductive film. In this case, by removing the region with low resistance located between the conductive layer 542a and the conductive layer 542b in the semiconductor layer 520b, it is possible to prevent the formation of a channel in that region.

[0209] Next, we will explain the detailed configuration of transistor 200C.

[0210] The conductive layer 505 is arranged such that it overlaps with the conductive layer 560 via the semiconductor layer 520. Furthermore, by embedding the conductive layer 505 in the insulating layer 516, the unevenness of the upper surfaces of the conductive layer 505 and the insulating layer 516 is reduced, thereby improving the coverage of the layers formed in subsequent processes.

[0211] The conductive layer 505 comprises conductive layer 505a, conductive layer 505b, and conductive layer 505c. Conductive layer 505a is provided in contact with the bottom and inner wall of an opening provided in the insulating layer 516. Conductive layer 505b is provided so as to be embedded in a recess formed in conductive layer 505a. Here, the height of the upper surface of conductive layer 505b is lower than the height of the upper surface of conductive layer 505a and the height of the upper surface of insulating layer 516. Conductive layer 505c is provided in contact with the upper surface of conductive layer 505b and the side surface of conductive layer 505a. Here, the height of the upper surface of conductive layer 505c is the same as the height of the upper surface of conductive layer 505a and the height of the upper surface of insulating layer 516. As a result, conductive layer 505b is enclosed by conductive layer 505a and conductive layer 505c.

[0212] When an oxide semiconductor is used as the semiconductor layer 520, the conductive layer 505a and conductive layer 505c contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ A conductive material having the function of suppressing the diffusion of impurities such as copper atoms may be used. Alternatively, a conductive material having the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) may be used.

[0213] By using conductive materials that have the function of reducing hydrogen diffusion in conductive layers 505a and 505c, it is possible to suppress the diffusion of impurities such as hydrogen contained in conductive layer 505b into the semiconductor layer 520 via the insulating layer 524, etc. Furthermore, by using conductive materials that have the function of suppressing oxygen diffusion in conductive layers 505a and 505c, it is possible to suppress the oxidation of conductive layer 505b and the resulting decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, conductive layer 505a can be made of the above conductive material in a single layer or a laminate. For example, titanium nitride can be used for conductive layer 505a.

[0214] Furthermore, the conductive layer 505b may be made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten can be used for the conductive layer 505b.

[0215] When the conductive layer 560 is used as the gate electrode, the conductive layer 505 functions as a back gate electrode. In addition, the insulating layers 522 and 524 function as back gate insulating films.

[0216] The conductive layer 505 may also be used as the gate electrode. In this case, the conductive layer 560 functions as the back gate electrode. The insulating layers 522 and 524 function as gate insulating films, and the insulating layer 550 functions as a back gate insulating film.

[0217] The conductive layer 505 may be provided in a size larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Figure 21C, the conductive layer 505 may extend to a region outside the edge of the semiconductor layer 520 that intersects with the channel width direction. As a result, the conductive layer 505 and the conductive layer 560 may be superimposed on the outside of the side surface in the channel width direction of the semiconductor layer 520, with the insulating layer in between.

[0218] With the above configuration, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560, which functions as a gate electrode, and the electric field of the conductive layer 505, which functions as a back gate electrode.

[0219] The conductive layer 505 may extend beyond the edge of the semiconductor layer 520 and be used as wiring. However, it is not limited to this, and a conductive layer that functions as wiring may be provided below the conductive layer 505.

[0220] As the insulating layer 514, an insulating material that functions as a barrier insulating film to suppress the ingress of impurities such as water or hydrogen into the transistor 200C from the substrate side may be used. Therefore, as the insulating layer 514, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N) may be used. ２ O, NO, NO ２An insulating material having the function of suppressing the diffusion of impurities such as copper atoms (which can also be called an insulating material that impurities do not easily permeate) may be used. Alternatively, an insulating material having the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) (which can also be called an insulating material that oxygen does not easily permeate) may be used.

[0221] For example, aluminum oxide or silicon nitride can be used as the insulating layer 514. This suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200C side beyond the insulating layer 514. Alternatively, it suppresses the diffusion of oxygen contained in the insulating layer 524, etc., to the substrate side beyond the insulating layer 514.

[0222] The insulating layers 516, 580, and 581, which function as interlayer films, may be insulating materials with a lower dielectric constant than that of insulating layer 514. By using materials with a low dielectric constant as interlayer films, parasitic capacitance between wiring can be reduced. For example, silicon oxide, silicon oxide-nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide can be used as insulating layers 516, 580, and 581.

[0223] Here, the insulating layer 524 in contact with the semiconductor layer 520 may contain excess oxygen. For example, the insulating layer 524 can be silicon oxide or silicon oxynitride. By providing an oxygen-containing insulating layer in contact with the semiconductor layer 520, oxygen deficiencies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200C is improved.

[0224] As shown in Figure 21C, the thickness of the insulating layer 524 in the region that does not overlap with the insulating layer 554 and the semiconductor layer 520b may be thinner than the thickness of the other regions. In the insulating layer 524, it is preferable that the thickness of the region that does not overlap with the insulating layer 554 and the semiconductor layer 520b be such that the above-mentioned oxygen can diffuse sufficiently.

[0225] As the insulating layer 522, a material that functions as a barrier insulating film to suppress the ingress of impurities such as water or hydrogen into the transistor 200C from the substrate side may be used, similar to the insulating layer 514. For example, a material with lower hydrogen permeability than the insulating layer 524 may be used as the insulating layer 522. By surrounding the insulating layer 524, semiconductor layer 520, and insulating layer 550 with the insulating layer 522, insulating layer 554, and insulating layer 574, it is possible to suppress the ingress of impurities such as water or hydrogen into the transistor 200C from the outside.

[0226] Furthermore, the insulating layer 522 may be made of a material that has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) (it can also be said to be a material that is less permeable to oxygen). For example, the insulating layer 522 may be made of a material with lower oxygen permeability than the insulating layer 524. By having the function of suppressing the diffusion of oxygen in the insulating layer 522, the amount of oxygen that diffuses from the semiconductor layer 520 to the substrate can be reduced. In addition, the reaction of the conductive layer 505 with the oxygen present in the insulating layer 524 or the semiconductor layer 520 can be suppressed.

[0227] As the insulating layer 522, an insulating layer containing an oxide of one or both of the insulating materials aluminum and hafnium may be used. As the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., can be used. When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses the release of oxygen from the semiconductor layer 520 and the incorporation of impurities such as hydrogen from the periphery of the transistor 200C into the semiconductor layer 520.

[0228] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be subjected to nitriding treatment. Furthermore, a structure in which the above insulating layers are laminated with silicon oxide, silicon oxide nitride, or silicon nitride may be used. For example, as the insulating layer 522, a structure in which silicon nitride, silicon oxide, and aluminum oxide are laminated in this order in three layers can be used.

[0229] As the insulating layer 522, a material with a high dielectric constant (high-k) is used (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO)). ３ ) or (Ba, Sr)TiO ３ An insulating layer containing (BST, etc.) may be used in a single layer or in a multilayer configuration. As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as gate leakage current. By using a material with a high dielectric constant for the insulating layer that functions as the gate insulating film, it becomes possible to lower the gate voltage applied during transistor operation while maintaining the physical film thickness.

[0230] Furthermore, the insulating layer 522 and the insulating layer 574 may each have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials.

[0231] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on semiconductor layer 520a, and a semiconductor layer 520c on semiconductor layer 520b. By having semiconductor layer 520a below semiconductor layer 520b, the diffusion of impurities from structures formed below semiconductor layer 520a to semiconductor layer 520b can be suppressed. Furthermore, by having semiconductor layer 520c on semiconductor layer 520b, the diffusion of impurities from structures formed above semiconductor layer 520c to semiconductor layer 520b can be suppressed.

[0232] Furthermore, when an oxide semiconductor is used as the semiconductor layer 520, the semiconductor layer 520 may have a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, if the semiconductor layer 520 contains at least indium (In) and element M, the ratio of the number of atoms of element M contained in semiconductor layer 520a to the total number of atoms of all elements constituting semiconductor layer 520a may be higher than the ratio of the number of atoms of element M contained in semiconductor layer 520b to the total number of atoms of all elements constituting semiconductor layer 520b. Also, the atomic ratio of element M contained in semiconductor layer 520a to In may be higher than the atomic ratio of element M contained in semiconductor layer 520b to In. Here, the semiconductor layer 520c may be a metal oxide that can be used in semiconductor layer 520a or semiconductor layer 520b.

[0233] The energy levels at the lower end of the conduction band of semiconductor layer 520a and semiconductor layer 520c may be higher than the energy levels at the lower end of the conduction band of semiconductor layer 520b. In other words, the electron affinity of semiconductor layer 520a and semiconductor layer 520c may be lower than the electron affinity of semiconductor layer 520b. In this case, a metal oxide that can be used for semiconductor layer 520a may be used as semiconductor layer 520c. Specifically, the ratio of the number of atoms of element M contained in semiconductor layer 520c to the total number of atoms of all elements constituting semiconductor layer 520c may be higher than the ratio of the number of atoms of element M contained in semiconductor layer 520b to the total number of atoms of all elements constituting semiconductor layer 520b. Also, the atomic ratio of element M contained in semiconductor layer 520c to In may be greater than the atomic ratio of element M contained in semiconductor layer 520b to In.

[0234] Here, at the junctions of semiconductor layers 520a, 520b, and 520c, the energy level at the lower edge of the conduction band changes smoothly. Therefore, the energy level at the lower edge of the conduction band at the junctions of semiconductor layers 520a, 520b, and 520c can be said to change continuously or be continuously junctioned. In order to achieve this, the defect level density of the mixed layer formed at the interface between semiconductor layer 520a and semiconductor layer 520b and the interface between semiconductor layer 520b and semiconductor layer 520c may be reduced.

[0235] Specifically, by having semiconductor layers 520a and 520b, and semiconductor layers 520b and 520c share elements other than oxygen, a mixed layer with a low defect level density can be formed. For example, if semiconductor layer 520b is indium gallium zinc oxide (In-Ga-Zn oxide), then semiconductor layers 520a and 520c may be In-Ga-Zn oxide, gallium zinc oxide (Ga-Zn oxide), gallium oxide, etc. Furthermore, semiconductor layer 520c may be a laminated structure. For example, a laminated structure of In-Ga-Zn oxide and an oxide that does not contain In can be used as semiconductor layer 520c. Specifically, for example, a laminated structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a laminated structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used.

[0236] Specifically, as the semiconductor layer 520a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or nearby, or a ratio of 1:1:0.5 or nearby may be used. Also, as the semiconductor layer 520b, a metal oxide with an In:Ga:Zn ratio of 4:2:3 or nearby, or a ratio of 3:1:2 or nearby, or a ratio of 1:1:1 or nearby may be used. Also, as the semiconductor layer 520c, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or nearby, In:Ga:Zn = 4:2:3 or nearby, Ga:Zn = 2:1 or nearby, or Ga:Zn = 2:5 or nearby may be used. Furthermore, specific examples of a laminated structure for the semiconductor layer 520c include a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] or its vicinity and Ga:Zn = 2:1 [atomic ratio] or its vicinity, a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] or its vicinity and Ga:Zn = 2:5 [atomic ratio] or its vicinity, and a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] or its vicinity and gallium oxide.

[0237] In this case, the main carrier path is the semiconductor layer 520b. By configuring semiconductor layers 520a and 520c as described above, the defect level density at the interface between semiconductor layer 520a and semiconductor layer 520b, and at the interface between semiconductor layer 520b and semiconductor layer 520c, can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200C can obtain a large on-current and high frequency characteristics. Furthermore, if semiconductor layer 520c is made into a stacked structure, in addition to the effect of reducing the defect level density at the interface between semiconductor layer 520b and semiconductor layer 520c, it is possible to suppress the diffusion of constituent elements of semiconductor layer 520c towards the insulating layer 550. More specifically, by making semiconductor layer 520c into a stacked structure and positioning an oxide that does not contain In on top of the stacked structure, it is possible to suppress In that could diffuse towards the insulating layer 550. Since the insulating layer 550 functions as a gate insulating film, if In diffuses, it will result in poor transistor characteristics. Therefore, by making the semiconductor layer 520c a stacked structure, it becomes possible to provide a highly reliable semiconductor device.

[0238] A conductive layer 542 (conductive layer 542a and conductive layer 542b) is provided on the semiconductor layer 520b, which functions as a source electrode and a drain electrode. When an oxide semiconductor is used as the semiconductor layer 520b, a conductive material that is resistant to oxidation or a conductive material that maintains its conductivity even when absorbing oxygen may be used as the conductive layer 542.

[0239] The region of the semiconductor layer 520 that is in contact with the conductive layer 542 functions as the source region or drain region of the transistor 200C. Here, the region between the conductive layer 542a and the conductive layer 542b is formed by superimposing it on an opening formed in the insulating layer 580. This allows the conductive layer 560 to be self-aligned between the conductive layer 542a and the conductive layer 542b.

[0240] The insulating layer 550 functions as a gate insulating film. The insulating layer 550 is placed in contact with the upper surface of the semiconductor layer 520c. The insulating layer 550 can be silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. For example, silicon oxide or silicon oxide nitride can be used as the insulating layer 550.

[0241] The insulating layer 550 may be an insulating material with reduced impurity concentrations, such as water or hydrogen, similar to the insulating layer 524. The thickness of the insulating layer 550 may be between 1 nm and 20 nm.

[0242] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. This metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. As a result, oxidation of the conductive layer 560 by oxygen contained in the insulating layer 550 can be suppressed.

[0243] Although the conductive layer 560 is shown as a two-layer structure in Figures 21A to 21C, it may also be a single-layer structure or a laminated structure of three or more layers.

[0244] The conductive layer 560a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ A conductive material having the function of suppressing the diffusion of impurities such as copper atoms may be used. Alternatively, a conductive material having the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) may be used.

[0245] The conductive layer 560a has the function of suppressing oxygen diffusion, thereby preventing the conductive layer 560b from being oxidized by oxygen contained in the insulating layer 550 and thus reducing its conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0246] Since the conductive layer 560 also functions as wiring, a highly conductive layer may be used. For example, the conductive layer 560b may be made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, the conductive layer 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0247] As shown in Figures 21B and 21C, in the region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is covered by the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200C, to act on the side surface of the semiconductor layer 520. Therefore, the on-current of the transistor 200C can be increased and the frequency characteristics can be improved.

[0248] The insulating layer 554 may be made of an insulating material that suppresses the ingress of impurities such as water or hydrogen into the transistor 200C, similar to the insulating layer 514. For example, the insulating layer 554 may be made of an insulating material with lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in Figures 21B and 21C, the insulating layer 554 is provided in contact with the side surface of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and semiconductor layer 520b, and the top surface of the insulating layer 524. This configuration suppresses the ingress of hydrogen contained in the insulating layer 580 into the semiconductor layer 520.

[0249] Furthermore, the insulating layer 554 may be an insulating material that has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) (it can also be called an insulating material that is impermeable to oxygen). For example, the insulating layer 554 may be an insulating material with lower oxygen permeability than the insulating layer 580 or the insulating layer 524.

[0250] When an oxide semiconductor is used as the semiconductor layer 520, the insulating layer 554 may be deposited using a sputtering method. By depositing the insulating layer 554 using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulating layer 524 that is in contact with the insulating layer 554. This allows oxygen to be supplied from that region into the semiconductor layer 520 via the insulating layer 524. Here, the insulating layer 554 has a function to suppress upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. In addition, the insulating layer 522 has a function to suppress downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the substrate side. In this way, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520 and suppresses normally-on formation of the transistor.

[0251] As the insulating layer 554, for example, an insulating layer containing an oxide of one or both of aluminum and hafnium may be formed. As the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., can be used.

[0252] The insulating layer 580 is provided on the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 via the insulating layer 554. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide can be used as the insulating layer 580. In particular, silicon oxide and silicon oxynitride are preferred for use as the insulating layer 580 because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferred for use as the insulating layer 580 because they can easily form regions containing oxygen that is desorbed by heating.

[0253] As the insulating layer 574, an insulating material that functions as a barrier insulating film to suppress the mixing of impurities such as water or hydrogen into the insulating layer 580 from above may be used, similar to the insulating layer 514. As the insulating layer 574, for example, an insulating material that can be used for the insulating layer 514, insulating layer 554, etc., may be used.

[0254] Figures 21A to 21C show an example in which an insulating layer 581, which functions as an interlayer film, is provided on top of the insulating layer 574. As the insulating layer 581, an insulating material with reduced impurity concentrations such as water or hydrogen may be used, similar to the insulating layer 524.

[0255] Conductive layers 545a and 545b are placed in each of the two openings formed in insulating layers 581, 574, 580, and 554. Conductive layers 545a and 545b are provided facing each other with conductive layer 560 in between. The height of the upper surfaces of conductive layers 545a and 545b may be the same as the height of the upper surface of insulating layer 581.

[0256] Furthermore, an insulating layer 541a is provided in contact with one inner wall of one of the two openings formed in insulating layers 581, 574, 580, and 554, and a first conductive layer of conductive layer 545a is formed in contact with its side surface. A conductive layer 542a is located in at least a portion of the bottom of the opening, and conductive layer 545a is in contact with conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the other inner wall of the two openings formed in insulating layers 581, 574, 580, and 554, and a first conductive layer of conductive layer 545b is formed in contact with its side surface. A conductive layer 542b is located in at least a portion of the bottom of the opening, and conductive layer 545b is in contact with conductive layer 542b.

[0257] The conductive layers 545a and 545b may be conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, each of the conductive layers 545a and 545b may have a laminated structure of two or more layers.

[0258] When the conductive layer 545 has a laminated structure, a conductive layer having the function of suppressing the diffusion of impurities such as water or hydrogen may be used in the conductive layer that is in contact with the semiconductor layer 520a, semiconductor layer 520b, conductive layer 542, insulating layer 554, insulating layer 580, insulating layer 574, and insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide can be used. By using such a conductive material, it is possible to suppress the absorption of oxygen contained in the insulating layer 580 into the conductive layer 545a and conductive layer 545b. In addition, it is possible to suppress the mixing of impurities such as water or hydrogen from the layer above the insulating layer 581 into the semiconductor layer 520 through the conductive layer 545a and conductive layer 545b.

[0259] As insulating layers 541a and 541b, insulating layers that can be used for insulating layer 554, for example, may be used. Since insulating layers 541a and 541b are provided in contact with insulating layer 554, it is possible to suppress the incorporation of impurities such as water or hydrogen from insulating layer 580, etc., into semiconductor layer 520 through conductive layer 545a and conductive layer 545b. Furthermore, it is possible to suppress the absorption of oxygen contained in insulating layer 580 into conductive layer 545a and conductive layer 545b.

[0260] <Transistor Components> Next, we will describe the components that can be used in transistor 200 (transistor 200A, transistor 200B, and transistor 200C).

[0261] [Substrate] When a transistor is mounted on a substrate, there are no major restrictions on the material used for the substrate. The material used for the substrate can be determined by considering factors such as whether or not it is translucent and whether it has sufficient heat resistance to withstand heat treatment, depending on the purpose. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used as the substrate. As an insulating substrate, for example, glass substrates such as barium borosilicate glass or aluminoborsilicate glass, ceramic substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates) can be used. In addition, semiconductor substrates, flexible substrates, resin substrates, etc. may be used as the substrate.

[0262] Examples of semiconductor substrates include semiconductor substrates made from silicon or germanium, or compound semiconductor substrates made from silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. In addition, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0263] Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. There are also substrates containing metal nitrides and metal oxides. Furthermore, there are substrates with a conductive or semiconductor layer on an insulating substrate, substrates with a conductive or insulating layer on a semiconductor substrate, and substrates with a semiconductor or insulating layer on a conductive substrate.

[0264] Examples of materials that can be used for flexible substrates, resin substrates, etc. include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofiber, and the like.

[0265] By using the above material as a substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is less prone to damage can be provided. In addition, devices on which elements are provided on these substrates may also be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0266] [Insulating Layer] An inorganic insulating film can be used for the insulating layer (insulating layer 202, insulating layer 204, insulating layer 206, insulating layer 209, insulating layer 514, insulating layer 516, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidized nitride insulating films, and nitrided oxide insulating films. Examples of oxide insulating films include silicon oxide film, aluminum oxide film, magnesium oxide film, gallium oxide film, germanium oxide film, yttrium oxide film, zirconium oxide film, lanthanum oxide film, neodymium oxide film, hafnium oxide film, tantalum oxide film, cerium oxide film, gallium zinc oxide film, and hafnium aluminate film. Examples of nitride insulating films include silicon nitride film and aluminum nitride film. Examples of oxidative nitride insulating films include silicon oxidative nitride films, aluminum oxidative nitride films, gallium oxidative nitride films, yttrium oxidative nitride films, and hafnium oxidative nitride films. Examples of nitride oxide insulating films include silicon oxidative nitride films and aluminum oxidative nitride films. In addition, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0267] In this specification, "oxide nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content. The content of each element can be measured using methods such as Rutherford backscattering (RBS).

[0268] For example, as transistors become smaller and more integrated, the thinning of the gate insulating film can lead to problems such as gate leakage current. Therefore, by using a material with a high relative permittivity (high-k) for the insulating layer that functions as the gate insulating film, it becomes possible to lower the gate voltage applied during transistor operation while maintaining the physical film thickness. Furthermore, it becomes possible to thin the equivalent oxide thickness (EOT) of the gate insulating film. Additionally, by using a material with a high relative permittivity for the insulating layer that functions as the dielectric of a capacitive element, the capacitance per unit area can be increased. On the other hand, by using a material with a low relative permittivity for the insulating layer that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, materials can be selected according to the function of the insulating layer. It should be noted that materials with a low relative permittivity also have high dielectric strength.

[0269] Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0270] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide-nitride, and silicon nitride-oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include, for example, silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Also, for example, silicon oxide with vacancies can be used. These silicon oxides may contain nitrogen.

[0271] [Conductive Layers] For the conductive layers used in the transistor 200 (conductive layers 205, 208, 215, 505, 542, 545, 560, etc.), it is preferable to use metal elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys composed of the above metal elements, or alloys combining the above metal elements. As alloys composed of the above metal elements, nitrides of the alloy or oxides of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Alternatively, highly conductive semiconductors such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide, may be used.

[0272] Furthermore, it is preferable to use conductive materials that are resistant to oxidation, conductive materials that have a function to suppress oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of such materials include nitrogen-containing conductive materials such as tantalum-containing nitrides, titanium-containing nitrides, molybdenum-containing nitrides, tungsten-containing nitrides, ruthenium-containing nitrides, tantalum and aluminum-containing nitrides, and titanium and aluminum-containing nitrides. Examples of oxygen-containing conductive materials include ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Examples of materials containing metallic elements such as titanium, tantalum, and ruthenium are also included. Examples of oxygen-containing conductive materials include materials containing tungsten oxide and indium oxide, materials containing titanium oxide and indium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also known as ITSO), indium zinc oxide (also known as IZO®), and indium zinc oxide containing tungsten oxide. In this specification, a conductive layer formed using an oxygen-containing conductive material may be referred to as an oxide conductive layer.

[0273] Furthermore, it is preferable to use a conductive material with high conductivity, such as one mainly composed of tungsten, copper, or aluminum.

[0274] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

[0275] For example, in transistor 200A or transistor 200B, when an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 203, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing oxygen may be used for conductive layers that function as gate electrodes, such as conductive layer 205 and conductive layer 215. In this case, the conductive material containing oxygen may be provided on the semiconductor layer 203 side. By providing the conductive material containing oxygen on the semiconductor layer 203 side, oxygen detached from the conductive material is more easily supplied to the channel formation region of the semiconductor layer 203.

[0276] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 203 or semiconductor layer 520, the conductive layers 208 and 542 in contact with the semiconductor layer 203 or semiconductor layer 520 may be made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide (also called an oxide conductor), or a conductive material that has the function of suppressing oxygen diffusion, respectively. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of the conductive layers 208 and 542.

[0277] By using conductive materials containing oxygen as the conductive layer 208 and conductive layer 542, conductivity can be maintained even if the conductive layer 208 and conductive layer 542 absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as the insulating layer in contact with the conductive layer 208 and conductive layer 542, conductivity can be maintained for the conductive layer 208 and conductive layer 542. For example, ITO, ITSO, IZO (registered trademark), etc., can be used for the conductive layer 208 and conductive layer 542, respectively.

[0278] [Semiconductor Layer] As semiconductor layers (semiconductor layer 203, semiconductor layer 520, etc.), single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors can be used individually or in combination.

[0279] As the semiconductor layer, a semiconductor composed of a single element or a compound semiconductor may be used. Examples of semiconductors composed of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide, silicon carbide, and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0280] When silicon is used as a semiconductor layer, examples of silicon that can be used for the semiconductor layer include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. As an example of polycrystalline silicon, low-temperature polysilicon (LTPS) is used.

[0281] For example, in transistor 200A or transistor 200B, if silicon is used for the semiconductor layer 203, it is possible to make the transistor function as an n-type transistor by including phosphorus or arsenic as an n-type dopant in regions 203a and 203b of the semiconductor layer 203. Furthermore, it is possible to make the transistor function as a p-type transistor by including boron as a p-type dopant in regions 203a and 203b of the semiconductor layer 203. Note that if both n-type and p-type dopants are present in regions 203a and 203b of the semiconductor layer 203, the conductivity type with the higher dopant concentration is more likely to manifest.

[0282] Furthermore, a two-dimensional material that functions as a semiconductor may be used as the semiconductor layer. Two-dimensional materials are also called layered materials and are a general term for a group of materials that have a layered crystalline structure. Layered materials have high conductivity within a unit layer (also called high two-dimensional conductivity). By using a material that functions as a semiconductor and has high two-dimensional conductivity as the semiconductor layer, it is possible to provide a transistor with a large on-current.

[0283] Examples of the above layer material include graphene, silicene, chalcogenide, etc. A chalcogenide is a compound containing a chalcogen (an element belonging to Group 16). Examples of chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides applicable as the semiconductor layer include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten telluride (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS [[ID=ID=17]] ２ ), zirconium selenide (typically ZrSe ２ ), etc.

[0284] Also, an oxide semiconductor, which is a kind of metal oxide, may be used as the semiconductor layer. At this time, the bandgap of the metal oxide is preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large bandgap as the semiconductor layer, the off-current of the transistor can be significantly reduced. Since the OS transistor has a small off-current, the power consumption of the semiconductor device can be reduced.

[0285] In a transistor using an oxide semiconductor as the semiconductor layer, it is preferable that the channel formation region of the transistor has less oxygen deficiency or a lower impurity concentration (for example, the concentration of hydrogen, nitrogen, metal elements, etc.) than the source region and the drain region. Also, since VH (a defect in which hydrogen enters an oxygen deficiency) may be formed by hydrogen near the oxygen deficiency and electrons serving as carriers may be generated, V Ｏ H (a defect in which hydrogen enters an oxygen deficiency) is formed and electrons serving as carriers may be generated. Therefore, V ＯIt is also preferable that H is low. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be type i (intrinsic) or substantially type i.

[0286] Furthermore, the source and drain regions of the transistor have more oxygen vacancies than the channel formation region. Ｏ It is preferable that there is a high amount of H or a high impurity concentration. Thus, the source region and drain region of the transistor have a higher carrier concentration and are low-resistance n-type regions than the channel formation region.

[0287] <Oxide Semiconductor Layer> Next, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one aspect of the present invention will be described.

[0288] The oxide semiconductor layer preferably contains a crystalline metal oxide. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structure, polycrystalline (Poly-crystal) structure, and microcrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect level density in the oxide semiconductor layer can be reduced. Therefore, the reliability of transistors using oxide semiconductor layers can be improved, and the reliability of semiconductor devices on which such transistors are mounted can be improved.

[0289] The oxide semiconductor layer is preferably a metal oxide having a CAAC structure. A CAAC structure is a crystalline structure in which multiple microcrystals (typically multiple microcrystals having a hexagonal crystal structure) are oriented along the c axis, and in the a-b plane, the multiple microcrystals are linked together without orientation. Furthermore, when a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in layers in the crystalline portion. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure with layered crystalline portions.

[0290] The crystallinity of an oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0291] The crystallinity of the semiconductor material in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more amorphous semiconductors (semiconductors with an amorphous structure), single-crystal semiconductors (semiconductors with a single-crystal structure), or semiconductors with crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in part). The crystallinity of the oxide semiconductor layer may suppress the degradation of transistor characteristics.

[0292] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. Preferably, the metal oxide contains at least indium (In). Preferably, the metal oxide contains at least indium (In) or zinc (Zn). Preferably, the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is a metallic or metalloid element with a high bond energy to oxygen; for example, a metallic or metalloid element with a higher bond energy to oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more selected from the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When element M is gallium, the metal oxide preferably has one or more selected from indium, gallium, and zinc. In this specification, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.

[0293] Examples of metal oxides include indium oxide. Other examples of metal oxides include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also written as IGTO), indium tungsten oxide (In-W oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), and aluminum zinc oxide (Al-Zn oxide, A Examples include indium aluminum zinc oxide (also written as ZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (also written as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO). In addition, examples of metal oxides include indium tin oxide containing silicon oxide (also called ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0294] By increasing the ratio of indium atoms to the sum of all metal element atoms contained in the metal oxide (also called the indium (In) content), the transistor can obtain at least one of a large on-current and high frequency characteristics.

[0295] The metal oxide may contain one or more metal elements with higher periodic numbers in the periodic table, instead of indium. Alternatively, the metal oxide may contain one or more metal elements with higher periodic numbers in the periodic table, in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, including metal elements with higher periodic numbers in the periodic table can sometimes increase the field-effect mobility of the transistor. Examples of metal elements with higher periodic numbers in the periodic table include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specifically, examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0296] Furthermore, metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can sometimes increase the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0297] Furthermore, by increasing the ratio of zinc atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities in the metal oxide. Therefore, fluctuations in the electrical properties of the transistor are suppressed, and reliability can be improved.

[0298] Furthermore, by increasing the ratio of element M atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, resulting in a transistor with low off-current. In addition, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0299] In this embodiment, In-Ga-Zn oxide may be used as an example of a metal oxide in the explanation.

[0300] [Manufacturing Method] The oxide semiconductor layer can be manufactured by forming a metal oxide using one type of film deposition method, or by forming a metal oxide using at least two types of film deposition methods. For example, the oxide semiconductor layer can be manufactured by forming a metal oxide using the first film deposition method or the second film deposition method, or by forming a metal oxide using the first film deposition method and the second film deposition method. Note that an oxide semiconductor layer formed using at least two types of film deposition methods may be called a Hybrid OS.

[0301] An oxide semiconductor layer can be fabricated by forming a metal oxide as a first oxide layer using a first film deposition method, and then forming a second oxide layer on the first oxide layer using a second film deposition method. In this case, it is preferable to use a film deposition method for the first film deposition method that causes less damage to the surface to be formed compared to the second film deposition method. By using a film deposition method that causes less damage to the surface to be formed as the first film deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on which the oxide semiconductor layer is formed can be suppressed. In addition, the mixing of impurities such as silicon into the second oxide layer can be suppressed, thereby increasing the crystallinity of the oxide semiconductor layer.

[0302] Examples of first film deposition methods include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-CVD, and metal-organic CVD (MOCVD). Examples of wet methods include spray coating. Compared to the sputtering method described later, ALD and CVD methods can suppress damage to the surface to be formed, and are therefore preferred as first film deposition methods.

[0303] Examples of ALD methods include thermal ALD, which carries out the reaction between the precursor and reactant using only thermal energy, and plasma ALD (PEALD: Plasma Enhanced ALD), which uses a plasma-excited reactant.

[0304] The ALD method allows for the deposition of atoms layer by layer, enabling the formation of extremely thin films, deposition on structures with high aspect ratios or surfaces with large step differences, deposition with fewer defects such as pinholes, deposition with excellent coverage, and deposition at low temperatures. Furthermore, the PEALD method, by utilizing plasma, can be preferable in some cases as it enables deposition at even lower temperatures. Note that precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher levels of these elements compared to films formed by other deposition methods. The quantitative determination of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS).

[0305] Examples of second film deposition methods include sputtering and pulsed laser deposition (PLD). Metal oxides formed using these second film deposition methods tend to have a CAAC structure.

[0306] Here, the first oxide layer may be, for example, a metal oxide with a microcrystalline or amorphous structure that has lower crystallinity than the CAAC structure. Even in such cases, by forming a second oxide layer (e.g., CAAC) with high crystallinity on the first oxide layer with low crystallinity, or by forming it and then applying heat treatment, the crystallinity of the first oxide layer may be increased with the second oxide layer as a nucleus. This makes it possible to increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the formed surface.

[0307] Furthermore, a third oxide layer can be formed on the second oxide layer. Since the second oxide layer has high crystallinity, the third oxide layer can grow crystals using the crystals of the second oxide layer as nuclei or seeds. Therefore, even if a film deposition method that easily produces crystallinity is not used for the formation of the third oxide layer, the third oxide layer can be crystallized. For example, by forming the third oxide layer using a film deposition method that provides higher coverage compared to the second oxide layer, the oxide semiconductor layer can possess both high crystallinity and high coverage throughout the entire layer.

[0308] An oxide semiconductor layer can be fabricated, for example, by forming a metal oxide as a first oxide layer using a first film deposition method, then forming a metal oxide as a second oxide layer using a second film deposition method, and finally forming a metal oxide as a third oxide layer using the first film deposition method. Specifically, the ALD method can be used as the first film deposition method, and the sputtering method can be used as the second film deposition method. The ALD method is a film deposition method with superior coverage compared to the sputtering method, and by using the ALD method for the first and third oxide layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated over steps, openings, etc., with high aspect ratios.

[0309] Thus, in the metal oxide film deposition method shown in this embodiment, the crystallinity of the first oxide layer and the third oxide layer can be increased by using a highly crystalline second oxide layer (e.g., CAAC) as a nucleus or seed. This makes it possible to increase the overall crystallinity of the oxide semiconductor. An oxide semiconductor formed using such a film deposition method, in this case a CAAC film, can be referred to as Axial Growth CAAC (AG CAAC).

[0310] By improving the crystallinity of the oxide semiconductor layer, the initial characteristics (especially the on-current) of transistors using the oxide semiconductor layer can be improved, making it possible to create transistors suitable for high-speed operation. Furthermore, the reliability of the transistor can be increased, and the on-current can be increased.

[0311] Here, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, oxide semiconductors with a high In content tend to become polycrystalline. Using a polycrystalline metal oxide in a transistor can adversely affect the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the first and third oxide layers, a crystal is formed that reflects the crystal orientation of the second oxide layer, thereby suppressing polycrystallization.

[0312] In this case, it is preferable that the degree of lattice mismatch between the crystals of the second oxide layer and the crystals of the first or third oxide layer is small. This allows the first or third oxide layer to form crystals that reflect the orientation of the crystals of the second oxide layer.

[0313] Furthermore, the crystal structure of the first or third oxide layer is not particularly limited, provided that the degree of lattice mismatch between the crystals of the second oxide layer and the crystals of the first or third oxide layer is small. The crystal structure of the first or third oxide layer may be cubic, tetragonal, orthorhombic, hexagonal, monoclinic, or trigonal.

[0314] [Composition] The second oxide layer preferably has a composition suitable for forming a CAAC structure. The second oxide layer preferably contains, for example, zinc. The inclusion of zinc results in a highly crystalline metal oxide. Furthermore, the second oxide layer preferably contains element M in addition to zinc. The inclusion of element M in the second oxide layer can suppress the formation of oxygen vacancies in the metal oxide, for example. Therefore, the reliability of transistors to which the oxide semiconductor layer is applied can be improved.

[0315] Specifically, the second oxide layer may be a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or nearby, In:M:Zn = 1:1:1.2 [atomic ratio] or nearby, In:M:Zn = 1:1:0.5 [atomic ratio] or nearby, In:M:Zn = 1:1:2 [atomic ratio] or nearby, In:M:Zn = 4:2:3 [atomic ratio] or nearby, In:M:Zn = 1:3:2 [atomic ratio] or nearby, or In:M:Zn = 1:3:4 [atomic ratio] or nearby. Nearby compositions include a range of plus or minus 30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as element M.

[0316] Furthermore, the second oxide layer may have a composition that does not contain element M. For example, it may be In-Zn oxide. Specifically, it can have a composition of In:Zn = 1:1 [atomic ratio] or close to that, In:Zn = 2:1 [atomic ratio] or close to that, or In:Zn = 4:1 [atomic ratio] or close to that. Alternatively, the second oxide layer may have a composition that does not contain elements M and Zn. For example, indium oxide may be used. It may also have a composition that contains trace amounts of element M. For example, it can have a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or close to that, or In:Ga:Zn = 2:0.1:1 [atomic ratio] or close to that. Also, for example, it can have a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or close to that, or In:Sn:Zn = 2:0.1:1 [atomic ratio] or close to that.

[0317] The first and third oxide layers can be metal oxides with a high proportion of In. In particular, it is preferable to use a metal oxide with a higher proportion of In than of element M. By using a metal oxide with a high proportion of In, when the oxide semiconductor layer is applied to a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0318] Furthermore, the first oxide layer and the third oxide layer can be metal oxides with a higher proportion of In compared to the second oxide layer.

[0319] The compositions of the first oxide layer and the third oxide layer may be different. Furthermore, the first and third oxide layers may use metal oxides with the same composition as the second oxide layer.

[0320] Furthermore, the crystallinity of the oxide semiconductor can be improved by increasing the atomic ratio of zinc contained in the oxide semiconductor. It is particularly preferable that the first oxide layer contains zinc. For example, when the first oxide layer is formed by the ALD method and the second oxide layer is formed by the sputtering method, zinc contained in the first oxide layer may diffuse into the second oxide layer. This diffusion can occur during sputtering or subsequent heat treatment. By diffusing zinc from the first oxide layer to the second oxide layer, the crystallinity of the second oxide layer can be improved. Alternatively, by diffusing zinc from the first oxide layer to the second oxide layer, the lateral growth of c-axis oriented crystalline portions in the second oxide layer can promote CAAC formation.

[0321] Furthermore, the first oxide layer and the third oxide layer may be composed without element M. For example, they may be In-Zn oxide. Specifically, the composition can be In:Zn = 1:1 [atomic ratio] or close to that, In:Zn = 2:1 [atomic ratio] or close to that, or In:Zn = 4:1 [atomic ratio] or close to that. Alternatively, the first oxide layer and the third oxide layer may be composed without elements M and Zn. For example, indium oxide may be used. Furthermore, the first oxide layer and the third oxide layer may be composed with trace amounts of element M. Specifically, the composition can be In:Ga:Zn = 4:0.1:1 [atomic ratio] or close to that, In:Ga:Zn = 2:0.1:1 [atomic ratio] or close to that, In:Sn:Zn = 4:0.1:1 [atomic ratio] or close to that, or In:Sn:Zn = 2:0.1:1 [atomic ratio] or close to that.

[0322] Furthermore, for example, metal oxides with a higher proportion of Ga compared to the second oxide layer can be used as the first and third oxide layers. For example, it is preferable to use metal oxides with a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, In:Ga:Zn = 1:3:2 [atomic ratio] or close to that, or In:Ga:Zn = 1:3:4 [atomic ratio] or close to that for the first and third oxide layers, respectively.

[0323] By increasing the proportion of Ga, for example, the band gaps of the first oxide layer and the third oxide layer can be made larger than those of the second oxide layer. As a result, the second oxide layer is sandwiched between the first and third oxide layers, which have larger band gaps, and the second oxide layer functions primarily as a current path. By sandwiching the second oxide layer between the first and third oxide layers, the trap levels at and near the interface of the second oxide layer can be reduced. This makes it possible to realize an embedded channel type transistor in which the channel is farther away from the insulating layer interface, thereby increasing the field-effect mobility.

[0324] Furthermore, even when compositions are used for the first and third oxide layers that make it difficult to form a CAAC structure in single-layer formation, crystal growth occurs with the second oxide layer as a nucleus, thereby enabling a configuration in which the entire oxide semiconductor layer, including the first and third oxide layers, has a CAAC structure. Alternatively, a configuration can be achieved in which a CAAC structure is present in a region encompassing at least a portion of each of the first and third oxide layers, and extending to the second oxide layer.

[0325] In particular, even in compositions where the proportion of In in the first oxide layer and the third oxide layer is high, suitable crystallinity for use as a semiconductor layer in a transistor can be achieved. In the oxide semiconductor layer shown in this embodiment, it is possible to achieve both improved on-characteristics of the transistor by increasing the proportion of In and improved reliability by having a highly crystalline CAAC structure.

[0326] Thus, by using an oxide semiconductor layer having a CAAC structure formed using the two film deposition methods described above in the channel formation region of a transistor, it is possible to realize a transistor with excellent characteristics (for example, a transistor with a large on-current, a transistor with high field-effect mobility, a transistor with a small S-value, a transistor with high frequency characteristics (also called f-characteristics), a transistor with high reliability, etc.).

[0327] For analyzing the composition of the metal oxide used in the oxide semiconductor layer, for example, energy-dispersive X-ray spectroscopy (EDX), XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these methods may be used for analysis.

[0328] [Crystallization] The crystallinity of an oxide semiconductor layer can be evaluated, for example, using crystal orientation.

[0329] Crystal orientation can be obtained from the Fast Fourier Transform (FFT) pattern acquired by performing FFT processing on the TEM image. Specifically, the direction of the crystal axes can be obtained using the FFT pattern. The FFT pattern obtained by the FFT processing reflects reciprocal lattice space information similar to that of the electron diffraction pattern.

[0330] By performing FFT processing on each region within the TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, in the FFT pattern of a region having layered crystalline parts, two spots of high intensity are observed. From the angle of the line segment connecting these two spots, the direction of the crystal axis of that region can be obtained.

[0331] The c-axis orientation ratio can be calculated by determining the proportion of c-axis oriented regions in a map showing crystal orientation.

[0332] In an oxide semiconductor layer, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of the cross-section or planar view of the oxide semiconductor layer. Furthermore, the region in which the FFT is performed (also called the FFT window) can be, for example, a circle with a diameter of 1.0 nm. However, the region in which the FFT is performed is not limited to a circle.

[0333] In an oxide semiconductor layer, when calculating the proportion of regions where the difference from the c-axis is within 20° as the c-axis orientation ratio, the c-axis orientation ratio is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0334] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0335] (Embodiment 3) This embodiment describes a display device according to one aspect of the present invention.

[0336] Furthermore, at least a portion of the drive circuit, semiconductor device, and display device described in Embodiment 1 above can be applied to the display device shown in this embodiment and the module having said display device.

[0337] Here, examples of modules having the display device include modules to which a connector such as a flexible printed circuit board (FPC) or a TCP (Tape Carrier Package) is attached, or modules on which an integrated circuit (IC) is mounted using a COG (Chip On Glass) method or a COF (Chip On Film) method.

[0338] <Example of Display Device Configuration> Figure 22A is a perspective view showing an example of the configuration of a display device 400 according to one aspect of the present invention.

[0339] The display device 400 has a configuration in which substrate 409 and substrate 401 are bonded together. In Figure 22A, substrate 409 is shown with a dashed line.

[0340] The display device 400 includes a display unit 402, a circuit unit 403, a circuit unit 404, a connection unit 405, and a wiring unit 406. Figure 22A shows an example in which an IC chip 407 and an FPC 408 are mounted on the display device 400. Therefore, the configuration shown in Figure 22A can also be described as a display module having a display device 400, an IC chip, and an FPC.

[0341] Furthermore, at least a portion of the semiconductor device 100 and the display device 160 shown in Embodiment 1 above can be applied to the display device 400. For example, at least a portion of the gate driver unit 163 (corresponding to the drive circuit 101), source driver unit 164, and control unit 167 shown in Embodiment 1 above can be applied to the circuit unit 403 and circuit unit 404. Also, for example, at least a portion of the pixel unit 162 (corresponding to the pixel unit 102) shown in Embodiment 1 above can be applied to the display unit 402. Also, for example, at least a portion of the gate driver unit 163 (corresponding to the drive circuit 101), source driver unit 164, and control unit 167 shown in Embodiment 1 above can be applied to the IC chip 407.

[0342] Circuit section 403 includes, for example, a scan line drive circuit (also called a gate driver or scan driver). Circuit section 404 also includes, for example, a signal line drive circuit (also called a source driver or data driver).

[0343] The wiring section 406 has the function of supplying signals and power to the display section 402, the circuit section 403, and the circuit section 404. These signals and power are input to the wiring section 406 from outside the display device 400 via the FPC 408, or from the IC chip 407 to the wiring section 406.

[0344] Figure 22A shows an example in which an IC chip 407 is provided on the substrate 401 using a COG (Camera-Owned Gauge) or COF (Camera-Owned Frame) method. The IC chip 407 can be, for example, an IC chip having one or both of a scan line drive circuit and a signal line drive circuit. The IC chip may also have a power supply circuit, a signal generation circuit, etc. The display device 400 and the display module may be configured without an IC chip. The IC chip may also be mounted on an FPC (Flexible Printed Circuit) using a COF method or the like.

[0345] Furthermore, a scan line driving circuit may be configured in either or both of the IC chip 407 and the circuit section 403. In this case, the IC chip 407 may be referred to as a gate driver IC. Alternatively, a signal line driving circuit may be configured in either or both of the IC chip 407 and the circuit section 404. In this case, the IC chip 407 may be referred to as a source driver IC.

[0346] The display unit 402 is the area in the display device 400 that displays an image, and has a plurality of pixels 411 arranged periodically. Figure 22A shows a magnified view of one pixel 411.

[0347] The pixel 411 shown in Figure 22A has a pixel 412R that emits red (R) light, a pixel 412G that emits green (G) light, and a pixel 412B that emits blue (B) light. Full-color display can be achieved by configuring one pixel 411 with pixels 412R, 412G, and 412B. Pixels 412R, 412G, and 412B each function as sub-pixels. The display device 400 shown in Figure 22A shows an example in which the sub-pixels 412R, 412B, and 412G are arranged in a stripe array. Note that the number of sub-pixels constituting one pixel 411 is not limited to three, but may be four or more. For example, there may be four sub-pixels that emit R, G, B, and white (W) light, respectively. Alternatively, there may be four sub-pixels that emit R, G, B, and yellow (Y) light, respectively.

[0348] In this specification, elements related to red light may be denoted with the identification code "R," elements related to green light with the identification code "G," and elements related to blue light with the identification code "B" to explain each respective matter. In addition, common matters may be explained by not assigning these identification codes. For example, when it is necessary to distinguish between multiple pixels 412, they may be indicated as pixel 412R, pixel 412G, or pixel 412B. Also, when it is not necessary to distinguish between pixels 412R, pixel 412G, and pixel 412B, they may simply be indicated as pixel 412.

[0349] Each pixel 412R, pixel 412G, and pixel 412B includes a display element and a circuit (pixel circuit) that controls the driving of the display element.

[0350] The connection portion 405 is provided on the outside of the display portion 402. The connection portion 405 can be provided along one or more sides of the display portion 402. There may be one or more connection portions 405. Figure 22A shows an example in which the connection portion 405 is provided so as to surround all four sides of the display portion. At the connection portion 405, one of the pair of electrodes of the display element is connected to the wiring portion 406, and a potential can be supplied to one of the pair of electrodes.

[0351] The substrates 401 and 409 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, or semiconductor, respectively. It is preferable to use a light-transmitting material for the substrate that extracts light from the display element (in this case, substrate 409). A polarizing plate may also be used as at least one of the substrates 401 and 409. Furthermore, flexible materials can be used for substrates 401 and 409. This increases the flexibility of the display device, enabling the creation of flexible displays (bendable displays, foldable displays, rollable displays, slidable displays, stretchable displays, etc.).

[0352] Furthermore, a display device according to one aspect of the present invention may also function as a touch panel. For example, various detection elements (also called sensor elements) capable of detecting the proximity or contact of an object to be detected, such as a finger, can be applied to the display device.

[0353] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0354] Examples of capacitance methods include surface capacitance and projected capacitance. Examples of projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferred because it enables simultaneous multi-point detection.

[0355] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting a sensing element are provided on one or both of the substrate supporting the display element (also called a display device) and the opposing substrate.

[0356] [Pixel Arrangement] Figures 22B to 22F are top views illustrating the pixel arrangement. In a display device according to one embodiment of the present invention, there are no particular limitations on the pixel arrangement, and various arrangements can be applied. Examples of pixel arrangements include stripe arrangement (see Figure 22B), S-stripe arrangement (see Figure 22C), delta arrangement (see Figure 22D), zigzag arrangement (see Figure 22E), and pentile arrangement (see Figure 22F). Other examples include mosaic arrangement, diamond arrangement, and Bayer arrangement. The pentile arrangement shown in Figure 22F includes a pixel 411 composed of pixels 412R and 412G, and a pixel 411 composed of pixels 412B and 412G.

[0357] Furthermore, in Figures 22B to 22F, the top surface shape of each sub-pixel (pixel 412R, pixel 412G, and pixel 412B) can be, for example, a triangle, a quadrilateral (including rectangles and squares), a pentagon, a polygon with rounded corners, an ellipse, or a circle. Here, the top surface shape of each sub-pixel corresponds to the top surface shape of the display area of ​​the display element that each sub-pixel possesses. The top surface shape and size of each sub-pixel can be determined independently. Note that the arrangement of pixels 412R, 412G, and 412B may be changed as appropriate. Also, the display elements and the pixel circuits may be arranged in the same way or in different ways.

[0358] [Display Elements] Various elements can be used as display elements, for example, liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type may also be used. Furthermore, QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials may also be used.

[0359] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0360] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and guest host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0361] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, or blue phase. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material.

[0362] As light-emitting elements, for example, field-emitting elements (such as injection-type field-emitting elements) such as LEDs using inorganic materials as the light-emitting material, organic EL elements (also called OLEDs), or semiconductor lasers (also called laser diodes) can be used. As LEDs using inorganic materials as the light-emitting material, for example, mini-LEDs or micro-LEDs can be used.

[0363] Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0364] The light-emitting element can emit light of colors such as red, green, blue, blue-green, reddish-purple, yellow, or white. It may also emit ultraviolet or infrared light. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0365] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode (also called the positive electrode), and the other electrode functions as the cathode (also called the negative electrode).

[0366] In addition, in display devices using liquid crystal elements, the above-mentioned light-emitting elements may be used as the light source of the display device (backlight, edge light, side light, front light, etc.).

[0367] <Example of Cross-Sectional Structure of Display Device> Figure 23 is a cross-sectional view illustrating an example of the cross-sectional structure of a display device according to one embodiment of the present invention.

[0368] In the display device 490 shown in Figure 23, the configurations shown in regions 490a, 490b, and 490c can be used in the display device 400, respectively. For example, the configuration shown in region 490a can be used in the region where the pixels 412 are provided. The configuration shown in region 490b can be used in the region where the circuit sections 403 and 404 are provided. The configuration shown in region 490c can be used in the region where the FPC 408 is provided.

[0369] Region 490a corresponds to the region where the pixel 161 (corresponding to pixel 122) shown in Embodiment 1 described above is provided. Therefore, the transistors provided in region 490a correspond to the transistors (transistor M31, transistor M32, etc.) that the pixel 122 etc. shown in Embodiment 1 described above has. Region 490b corresponds to the region where the gate driver unit 163 (corresponding to the drive circuit 101), source driver unit 164, and control unit 167 etc. shown in Embodiment 1 described above are provided. Therefore, the transistors provided in region 490b correspond to the transistors (transistor M11a, transistor M12a, transistor M13a, transistor M11b, transistor M12b, transistor M13b, transistor M21 to transistor M27, etc.) that the drive circuit 101 etc. shown in Embodiment 1 described above has.

[0370] The display device 490 has a substrate 310 (corresponding to the substrate 401 described above) and a substrate 350 (corresponding to the substrate 409 described above). Furthermore, there is an adhesive layer 340 between the substrates 310 and 350. The substrate 350 faces the substrate 310 via the adhesive layer 340. Note that region 490c does not have the substrate 350 or the adhesive layer 340.

[0371] An insulating layer 312 is provided on the substrate 350 side of the substrate 310. Transistors and light-emitting elements are provided on the insulating layer 312.

[0372] Here, as an example, a configuration is shown in which the transistor 200A shown in Embodiment 2 above is provided in both region 490a and region 490b. Furthermore, a configuration is shown in which the transistor 200B shown in Embodiment 2 above is provided in region 490a.

[0373] Note that the transistors provided in regions 490a and 490b are not limited to structures like transistor 200A and transistor 200B. Various transistor structures (such as transistor 200C shown in Embodiment 2 above) can be provided in regions 490a and 490b. In this case, one type of transistor structure may be provided, or two or more different types of transistor structures may be provided.

[0374] Furthermore, a conductive layer 364 is provided in region 490c. The conductive layer 364 can be formed using the same process as the conductive layer 208 (conductive layer 208a, conductive layer 208b, etc.) in transistors 200A and 200B.

[0375] An insulating layer 218 is provided so as to cover transistors 200A and 200B.

[0376] In region 490a, a pixel electrode 321 is provided on the insulating layer 218. The pixel electrode 321 is in contact with the conductive layer 208b at openings provided in the insulating layer 218 and the insulating layer 209. In addition, an insulating layer 322 is provided on the insulating layer 218. The insulating layer 322 has a region that covers the end of the pixel electrode 321.

[0377] Furthermore, an EL layer 324 is provided so as to cover the insulating layer 322 and the pixel electrode 321. A common electrode 327 is provided so as to cover the EL layer 324. A protective layer 328 is provided so as to cover the common electrode 327.

[0378] The pixel electrode 321 and the common electrode 327 overlap via the EL layer 324, and the region where the pixel electrode 321 and the EL layer 324 are in contact with each other, and where the EL layer 324 and the common electrode 327 are in contact, functions as a light-emitting element 320. The pixel electrode 321 functions as one electrode (or first terminal) of the light-emitting element 320, and the common electrode 327 functions as the other electrode (or second terminal). The EL layer 324 has the function of emitting light with a brightness corresponding to the amount of current flowing between the pixel electrode 321 and the common electrode 327 via the EL layer 324.

[0379] The light-emitting element 320 corresponds to the light-emitting element LDs found in the pixels 122 and the like, as shown in Embodiment 1 described above.

[0380] A light-shielding layer 352 is provided on the substrate 310 side of the substrate 350.

[0381] In region 490a, the light-shielding layer 352 is provided with an opening that overlaps with the light-emitting element 320. Therefore, the light emitted from the light-emitting element 320 is emitted to the outside of the display device 490 through the opening in the light-shielding layer 352. In Figure 23, this is represented by a dashed arrow and the label "Light".

[0382] In region 490c, a conductive layer 366 is provided on a portion of the insulating layer 218. The conductive layer 366 is in contact with the conductive layer 364 at openings provided in the insulating layer 218 and the insulating layer 209.

[0383] The conductive layer 364 can be provided in the same layer as the conductive layer 208. Therefore, the conductive layer 364 can have the same material as the conductive layer 208 and can be formed in the same process. For example, the conductive layer 208 and the conductive layer 364 can be formed by processing the same conductive film. Also, the conductive layer 366 can be provided in the same layer as the pixel electrode 321. Therefore, the conductive layer 366 can have the same material as the pixel electrode 321 and can be formed in the same process. For example, the pixel electrode 321 and the conductive layer 366 can be formed by processing the same conductive film. In region 490c, the conductive layer 366 is exposed. This allows the conductive layer 366 and the FPC 408 to be connected via the connecting layer 368.

[0384] As the connecting layer 368, an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP) can be used.

[0385] <Examples of light-emitting element configurations> In one aspect of the present invention, when a display device has a light-emitting element, various configurations of light-emitting elements can be used.

[0386] Figures 24A, 24B, 25A, and 25B are cross-sectional views illustrating various configurations of light-emitting elements.

[0387] [Configuration Example 1] The display device 490A shown in Figure 24A has light-emitting elements 320R, 320G, and 320B between the substrate 310 and the substrate 350. Light-emitting element 320R is a display element with a pixel that emits red light, light-emitting element 320G is a display element with a pixel that emits green light, and light-emitting element 320B is a display element with a pixel that emits blue light. When describing things common to light-emitting elements 320R, 320G, and 320B, they may simply be referred to as light-emitting element 320.

[0388] Note that in Figure 24A, some details of the configuration between the substrate 310 and the light-emitting element 320, and the configuration between the substrate 350 and the light-emitting element 320 are omitted. The display device 490A has, for example, transistors constituting a pixel circuit and an insulating layer 218 provided to cover the transistors between the substrate 310 and the light-emitting element 320.

[0389] The display device 490A employs an SBS (Side By Side) structure. The SBS structure is fabricated using a metal mask (or fine metal mask). This increases the degree of freedom in selecting materials and configurations for each light-emitting element. Therefore, since the materials and configurations can be optimized for each light-emitting element, it becomes easier to improve at least one of the following: increased light intensity and improved reliability.

[0390] The display device 490A is a top-emission type. In the top-emission type, transistors and other components can be placed overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0391] A light-emitting element 320R, a light-emitting element 320G, and a light-emitting element 320B are provided on the insulating layer 218.

[0392] The light-emitting element 320R has a pixel electrode 321R on the insulating layer 218, an EL layer 324R on the pixel electrode 321R, and a common electrode 327 on the EL layer 324R. The light-emitting element 320R shown in Figure 24A emits red (R) light. The EL layer 324R has a light-emitting layer that emits red light.

[0393] The light-emitting element 320G has a pixel electrode 321G on the insulating layer 218, an EL layer 324G on the pixel electrode 321G, and a common electrode 327 on the EL layer 324G. The light-emitting element 320G shown in Figure 24A emits green (G) light. The EL layer 324G has a light-emitting layer that emits green light.

[0394] The light-emitting element 320B has a pixel electrode 321B on the insulating layer 218, an EL layer 324B on the pixel electrode 321B, and a common electrode 327 on the EL layer 324B. The light-emitting element 320B shown in Figure 24A emits blue (B) light. The EL layer 324B has a light-emitting layer that emits blue light.

[0395] In Figure 24A, EL layers 324R, 324G, and 324B are shown to be of the same thickness, but this is not limited to this. The thicknesses of EL layers 324R, 324G, and 324B may be different. For example, it is preferable to set the thickness of EL layers 324R, 324G, and 324B so that the optical path length is such that the light emitted by each is intensified. This makes it possible to realize a microcavity structure and improve the color purity of the light emitted from each of the light-emitting elements 320R, 320G, and 320B.

[0396] When describing matters common to pixel electrode 321R, pixel electrode 321G, and pixel electrode 321B, they may simply be referred to as pixel electrode 321. Similarly, when describing matters common to EL layer 324R, EL layer 324G, and EL layer 324B, they may simply be referred to as EL layer 324.

[0397] The pixel electrode 321 is connected to a transistor (not shown) in the pixel circuit corresponding to the light-emitting element 320 at an opening provided in the insulating layer 218 or the like.

[0398] The ends of the pixel electrodes 321 are covered by an insulating layer 322. The insulating layer 322 functions as a partition. The insulating layer 322 can be provided in a single-layer or multi-layer structure using one or both of inorganic insulating materials and / or organic insulating materials. For example, the insulating layer 322 can be made of the same material that can be used for the insulating layer 218. The insulating layer 322 can insulate the pixel electrodes from the common electrodes. In addition, the insulating layer 322 can insulate adjacent light-emitting elements 320 from each other.

[0399] The common electrode 327 is a continuous film provided in common to multiple light-emitting elements 320. Although not shown in the figures, the common electrode 327, which is common to multiple light-emitting elements 320, is connected to a conductive layer formed from the same material and using the same process as the pixel electrode 321 in areas where no light-emitting elements 320 are provided.

[0400] Of the pixel electrode 321 and the common electrode 327, it is preferable to use a conductive film that transmits visible light for the electrode that extracts light to the outside of the display device 490A (in this case, the common electrode 327). It is also preferable to use a conductive film that reflects visible light for the electrode that does not extract light (in this case, the pixel electrode 321). In this case, a conductive film that transmits visible light may also be used for the electrode that does not extract light. In this case, a reflective layer may be arranged so as to face the EL layer 324 via the conductive film. As a result, the light emitted from the EL layer 324 may be reflected by the reflective layer and extracted to the outside of the display device 490A.

[0401] As the material for forming the pixel electrode 321 and the common electrode 327, metals, alloys, conductive compounds, or mixtures thereof can be used as appropriate.

[0402] It is preferable that the light-emitting element 320 has a microcavity structure. Therefore, for example, it is preferable that the common electrode 327 is an electrode that has transmittance and reflectivity to visible light (also called a semi-transmissive / semi-reflective electrode), and the pixel electrode 321 is preferable that it is an electrode that has reflectivity to visible light (also called a reflective electrode). By having a microcavity structure in the light-emitting element 320, the light emitted from the light-emitting layer can be made to resonate between the two electrodes, thereby strengthening the light emitted from the light-emitting element 320.

[0403] For example, the transmittance of the semi-transparent / semi-reflective electrode for visible light (light with a wavelength of 400 nm or more and less than 750 nm) shall be 40% or more. The reflectance of the semi-transparent / semi-reflective electrode for visible light shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of the reflective electrode for visible light shall be 40% or more and less than 100%, preferably 70% or more and less than 100%.

[0404] The EL layers 324 are arranged in an island-like configuration. In Figure 24A, the ends of adjacent EL layers 324 overlap. However, this is not the only arrangement; adjacent EL layers 324 may not overlap and may be separated from each other. Furthermore, there may be both areas where adjacent EL layers 324 overlap and areas where adjacent EL layers 324 do not overlap and are separated from each other.

[0405] The EL layer 324 has at least an emissive layer. The emissive layer has one or more types of emissive materials. As the emissive material, a material that exhibits an emission color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the emissive material.

[0406] The luminescent material may be an organic material. However, the luminescent material may also be an inorganic material. Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0407] The light-emitting layer may contain one or more types of organic compounds (such as a host material and an assist material) in addition to the light-emitting substance (guest material). One or more of the organic compounds may be substances with high hole transport properties (hole transport materials) and / or substances with high electron transport properties (electron transport materials). Alternatively, one or more of the organic compounds may be bipolar substances (substances with high electron and hole transport properties) or TADF materials.

[0408] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0409] In addition to the light-emitting layer, the EL layer 324 may have one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer 324 may contain either or both a bipolar material and a TADF material.

[0410] The light-emitting element 320 may be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may also contain an inorganic compound. The layers constituting the light-emitting element 320 can be formed by methods such as vapor deposition (vacuum deposition, etc.), transfer, printing (inkjet, etc.), or coating (spin coating, etc.).

[0411] The light-emitting element 320 may be a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. The tandem structure is a configuration in which multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of emitting light with high light intensity can be made. In addition, compared to a single structure, the tandem structure can reduce the current required to obtain the same light intensity, thus improving reliability. The tandem structure can also be called a stack structure.

[0412] In Figure 24A, when a tandem structure is used as the light-emitting element 320, it is preferable that the EL layer 324R has a structure having multiple light-emitting units that emit red light, the EL layer 324G has a structure having multiple light-emitting units that emit green light, and the EL layer 324B has a structure having multiple light-emitting units that emit blue light.

[0413] A protective layer 328 is provided on the light-emitting element 320. The protective layer 328 and the substrate 350 are bonded together via an adhesive layer 340. A light-shielding layer 352 is provided on the substrate 350.

[0414] For sealing the light-emitting element 320, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 24A, the space between the substrate 350 and the substrate 310 is filled with an adhesive layer 340, indicating that a solid sealing structure is applied. Alternatively, a hollow sealing structure may be applied, in which the space is filled with an inert gas (such as nitrogen or argon). In this case, the adhesive layer 340 may be provided so as not to overlap with the light-emitting element 320. Furthermore, the space may be filled with a resin different from the adhesive layer 340, which is provided in a frame shape.

[0415] As the adhesive layer 340, various types of curing adhesives can be used, such as UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. For these adhesives, materials with low moisture permeability, such as epoxy resins, are preferred.

[0416] By providing the protective layer 328 on the light-emitting element 320, the reliability of the light-emitting element can be enhanced. The protective layer 328 may have a single-layer structure or a laminated structure of two or more layers. Also, the conductivity of the protective layer 328 is not limited. As the protective layer 328, at least one of an insulating film, a semiconductor film, and a conductive film can be used. When the light emitted from the light-emitting element 320 is taken out to the outside of the display device 490A through the protective layer 328, it is preferable that the protective layer 328 has high transparency to visible light. For example, an inorganic material with high transparency to visible light such as ITO, IGZO, or aluminum oxide is preferable.

[0417] The light emitted by the light-emitting element 320 is emitted toward the substrate 350 side. Therefore, it is preferable to use a material with high transparency to visible light for the substrate 350.

[0418] It is preferable to provide a light-shielding layer 352 on the surface of the substrate 350 on the substrate 310 side. The light-shielding layer 352 can be provided, for example, between adjacent light-emitting elements 320.

[0419] Although not shown, a colored layer such as a color filter may be provided on the surface of the substrate 350 on the substrate 310 side or on the protective layer 328. When a color filter is provided overlapping the light-emitting element 320, the color purity of the light taken out to the outside of the display device 490A can be enhanced.

[0420] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. For each colored layer, one or more of a metal material, a resin material, a pigment, and a dye can be used. The colored layer can be formed at a desired position by, for example, a printing method, an inkjet method, or an etching method using a photolithography method.

[0421] [Configuration Example 2] The display device 490B shown in Figure 24B includes a light-emitting element 320R, a light-emitting element 320G, a light-emitting element 320B, a colored layer 354R that transmits red light, a colored layer 354G that transmits green light, and a colored layer 354B that transmits blue light. The display device 490B mainly differs from the display device 490A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 324W and a colored layer (color filter, etc.). Note that explanations of parts that are the same as those of the display device 490A described above may be omitted.

[0422] The light-emitting element 320R includes a pixel electrode 321R, an EL layer 324W on the pixel electrode 321R, and a common electrode 327 on the EL layer 324W. The light emitted by the light-emitting element 320R is extracted as red light to the outside of the display device 490B via the colored layer 354R.

[0423] The light-emitting element 320G includes a pixel electrode 321G, an EL layer 324W on the pixel electrode 321G, and a common electrode 327 on the EL layer 324W. The light emitted by the light-emitting element 320G is extracted as green light to the outside of the display device 490B via the colored layer 354G.

[0424] The light-emitting element 320B includes a pixel electrode 321B, an EL layer 324W on the pixel electrode 321B, and a common electrode 327 on the EL layer 324W. The light emitted by the light-emitting element 320B is extracted as blue light to the outside of the display device 490B via the colored layer 354B.

[0425] Each of the light-emitting elements 320R, 320G, and 320B has an EL layer 324W and a common electrode 327. The configuration in which a common EL layer 324W is provided for each sub-pixel of each color reduces the number of manufacturing steps compared to the configuration in which different EL layers (EL layer 324R, EL layer 324G, and EL layer 324B) are provided for each sub-pixel of each color.

[0426] For example, the light-emitting elements 320R, 320G, and 320B shown in Figure 24B emit white light. The white light emitted by the light-emitting elements 320R, 320G, and 320B passes through the colored layers 354R, 354G, and 354B, thereby obtaining light of a desired color.

[0427] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light using two light-emitting layers, the light-emitting layers may be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration can be obtained in which the entire light-emitting element emits white light. Alternatively, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers combine to produce a configuration in which the entire light-emitting element emits white light.

[0428] The EL layer 324W preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 324W preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 324W preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0429] For light-emitting elements that emit white light, a tandem structure is preferable. Examples of such light-emitting elements include a two-stage tandem structure having a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, a two-stage tandem structure having a light-emitting unit that emits red (R) light and green (G) light and a light-emitting unit that emits blue light, and so on. Furthermore, examples of such light-emitting elements include a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light in that order, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and red light, and a light-emitting unit that emits blue light in that order.

[0430] For example, the light-emitting elements 320R, 320G, and 320B shown in Figure 24B may emit blue light. In this case, the EL layer 324W has one or more light-emitting layers that emit blue light. In pixels that emit blue light, the blue light emitted by the light-emitting element 320B can be extracted. In pixels that emit red light and pixels that emit green light, a color conversion layer can be provided between the light-emitting element 320R or 320G and the substrate 350 to convert the blue light emitted by the light-emitting element 320R or 320G into longer wavelength light, thereby extracting red or green light. Furthermore, it is preferable to provide a coloring layer 354R between the color conversion layer and the substrate 350 on the light-emitting element 320R, and a coloring layer 354G between the color conversion layer and the substrate 350 on the light-emitting element 320G. Some of the light emitted by the light-emitting element 320 may be transmitted without being converted by the color conversion layer. Therefore, by extracting the light that has passed through the color conversion layer via the colored layer, the colored layer absorbs light of colors other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.

[0431] [Configuration Example 3] The display device 490C shown in Figure 25A is an example of a display device having a light-emitting element to which an MML (metal maskless) structure is applied. The display device 490C has a light-emitting element manufactured without using a metal mask (or fine metal mask). Note that the configuration between the substrate 310 and the insulating layer 218, and the configuration between the protective layer 328 and the substrate 350 are the same as those of the display device 490A, so their explanation is omitted.

[0432] In this case, in a light-emitting element to which an MML structure is applied, the layer containing the light-emitting layer is not formed using a metal mask, but rather formed by depositing the layer containing the light-emitting layer onto one surface and then processing it using photolithography. For example, if the display device 490C is composed of three types of light-emitting elements, such as a blue light-emitting element, a green light-emitting element, and a red light-emitting element, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by photolithography three times. Therefore, it is possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layer can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality. In addition, by providing a sacrificial layer on the light-emitting layer, the damage that the light-emitting layer receives during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0433] Furthermore, MML-structured light-emitting elements can be manufactured without using a metal mask. Therefore, it is possible to realize display devices that exceed the resolution limits imposed by the alignment accuracy of metal masks. Additionally, the equipment required for manufacturing metal masks and the metal mask cleaning process can be eliminated. Moreover, mass production of display devices can be achieved.

[0434] Furthermore, by applying an MML structure, it is possible to realize a display device that integrates fine light-emitting elements. For example, without artificially increasing the resolution by applying a special pixel arrangement such as a pentile arrangement, it is possible to apply a so-called stripe arrangement in which R, G, and B are each arranged in one direction, and realize a display device with a resolution of 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more.

[0435] In Figure 25A, light-emitting elements 320R, 320G, and 320B are provided on the insulating layer 218.

[0436] The light-emitting element 320R includes a conductive layer 331R on an insulating layer 218, a conductive layer 333R on the conductive layer 331R, an EL layer 334R on the conductive layer 333R, a common layer 337 on the EL layer 334R, and a common electrode 327 on the common layer 337. The light-emitting element 320R shown in Figure 25A emits red (R) light. The EL layer 334R has a light-emitting layer that emits red light. In the light-emitting element 320R, the EL layer 334R and the common layer 337 can also be collectively called the EL layer. In addition, one or both of the conductive layers 331R and 333R can be called pixel electrodes.

[0437] The light-emitting element 320G includes a conductive layer 331G on an insulating layer 218, a conductive layer 333G on the conductive layer 331G, an EL layer 334G on the conductive layer 333G, a common layer 337 on the EL layer 334G, and a common electrode 327 on the common layer 337. The light-emitting element 320G shown in Figure 25A emits green (G) light. The EL layer 334G has a light-emitting layer that emits green light. In the light-emitting element 320G, the EL layer 334G and the common layer 337 can also be collectively called the EL layer. In addition, one or both of the conductive layers 331G and 333G can be called pixel electrodes.

[0438] The light-emitting element 320B includes a conductive layer 331B on the insulating layer 218, a conductive layer 333B on the conductive layer 331B, an EL layer 334B on the conductive layer 333B, a common layer 337 on the EL layer 334B, and a common electrode 327 on the common layer 337. The light-emitting element 320B shown in Figure 25A emits blue (B) light. The EL layer 334B has a light-emitting layer that emits blue light. In the light-emitting element 320B, the EL layer 334B and the common layer 337 can also be collectively called the EL layer. In addition, one or both of the conductive layers 331B and 333B can be called pixel electrodes.

[0439] In Figure 25A, EL layers 334R, 334G, and 334B are all shown to be the same thickness, but this is not the only option. The thicknesses of EL layers 334R, 334G, and 334B may be different.

[0440] When describing matters common to the light-emitting element 320R, light-emitting element 320G, and light-emitting element 320B, it may simply be referred to as light-emitting element 320. When describing matters common to the conductive layer 331R, conductive layer 331G, and conductive layer 331B, it may simply be referred to as conductive layer 331. Also, when describing matters common to the conductive layer 333R, conductive layer 333G, and conductive layer 333B, it may simply be referred to as conductive layer 333. Furthermore, when describing matters common to the EL layer 334R, EL layer 334G, and EL layer 334B, it may simply be referred to as EL layer 334.

[0441] The conductive layer 331 is connected to a transistor (not shown) in the pixel circuit corresponding to the light-emitting element 320 at an opening provided in the insulating layer 218 or the like.

[0442] The conductive layer 331 is formed to cover the openings provided in the insulating layer 218 and the like. A planarizing layer 332 is embedded in each recess of the conductive layer 331.

[0443] The planarization layer 332 has the function of flattening the recesses of the conductive layer 331. A conductive layer 333 is provided on the conductive layer 331 and the planarization layer 332, in contact with the conductive layer 331. Therefore, the region overlapping with the recesses of the conductive layer 331 can also be used as a light-emitting region, thereby increasing the aperture ratio of the pixels.

[0444] The planarization layer 332 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the planarization layer 332. In particular, it is preferable that the planarization layer 332 be formed using an insulating material, and it is especially preferable that it be formed using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 322 described above can be applied to the planarization layer 332.

[0445] Although Figure 25A shows an example where the upper surface of the flattening layer 332 has a flat portion, the shape of the flattening layer 332 is not particularly limited. The upper surface of the flattening layer 332 can have at least one of a convex curved surface, a concave curved surface, and a flat surface. Furthermore, the height of the upper surface of the flattening layer 332 and the height of the upper surface of the conductive layer 331 may be the same or different. For example, the height of the upper surface of the flattening layer 332 may be lower or higher than the height of the upper surface of the conductive layer 331.

[0446] The end of the conductive layer 333 may be aligned with the end of the conductive layer 331, or it may cover the side surface of the end of the conductive layer 331. Preferably, the ends of the conductive layer 331 and the conductive layer 333 have a tapered shape. This improves the coverage of the EL layer 334 provided along the side surfaces of the conductive layer 331 and the conductive layer 333.

[0447] It is preferable to use conductive layers that function as reflective electrodes in conductive layers 331 and 333.

[0448] The upper and side surfaces of the conductive layer 333 are covered by the EL layer 334. Therefore, the entire region where the conductive layer 333 is provided can be used as the light-emitting region of the light-emitting element 320, thereby increasing the aperture ratio of the pixels.

[0449] The EL layer 334 is provided in an island-like manner for each light-emitting element 320. Therefore, adjacent EL layers 334 are separated from each other. This prevents current from flowing between adjacent light-emitting elements 320. As a result, unintended light emission caused by crosstalk can be prevented, and a display device with extremely high contrast can be realized.

[0450] Between adjacent light-emitting elements 320, a portion of the upper surface and sides of the EL layer 334 are covered by insulating layers 335 and 336. A common layer 337 is provided on the EL layer 334, insulating layer 335, and insulating layer 336, and a common electrode 327 is provided on the common layer 337. The common layer 337 and the common electrode 327 are each continuous films provided in common to multiple light-emitting elements 320.

[0451] In FIG. 25A, an insulating layer (corresponding to the insulating layer 322 shown in FIG. 24A etc.) that functions as a partition wall is not provided between the conductive layer 333 and the EL layer 334. Therefore, the interval between adjacent light-emitting elements 320 can be made extremely narrow. Thus, a high-definition and high-resolution display device can be achieved. Also, a mask (for example, a photomask) for forming the insulating layer becomes unnecessary, and the manufacturing cost of the display device can be reduced.

[0452] In addition to the light-emitting layer, the EL layer 334 can have one or more of an electron transport layer, an electron blocking layer, a hole transport layer, and a hole blocking layer. The common layer 337 can have an electron injection layer or a hole injection layer. Note that the common layer 337 may have an electron transport layer and an electron injection layer, or a hole transport layer and a hole injection layer.

[0453] A part of the upper surface and the side surface of the EL layer 334 are covered by at least one of the insulating layer 335 and the insulating layer 336. Therefore, it is possible to suppress the common layer 337 and the common electrode 327 from coming into contact with the side surfaces of the conductive layer 331, the conductive layer 333, and the EL layer 334 and short-circuiting between the pair of electrodes of the light-emitting element 320. Thereby, the reliability of the light-emitting element can be enhanced.

[0454] Also, by adopting a configuration in which the insulating layer 335 contacts the side surface of the EL layer 334, peeling of the film of the EL layer 334 can be prevented. Thereby, the reliability of the light-emitting element can be enhanced.

[0455] Also, the insulating layer 336 is provided on the insulating layer 335 so as to fill the concave portion of the insulating layer 335. The insulating layer 336 preferably covers at least a part of the side surface of the insulating layer 335. By providing the insulating layer 335 and the insulating layer 336 in this way, the region between adjacent island-shaped EL layers 334 can be filled. Therefore, the step difference of the formation surfaces of the common layer 337 and the common electrode 327 can be reduced and made flat. Thereby, the covering property of the common layer 337 and the common electrode 327 can be enhanced. Thus, it is possible to suppress connection failure due to step breakage of the common layer 337 and the common electrode 327, or an increase in electrical resistance due to local thinning of the common electrode 327.

[0456] The upper surface of the insulating layer 336 preferably has a shape that is more flat. The upper surface of the insulating layer 336 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 336 preferably has a convex curved shape with a large radius of curvature.

[0457] An inorganic insulating film can be used for the insulating layer 335. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxidized nitrides, and nitride oxides. It is preferable that the insulating layer 335 has the function of protecting the EL layer 334 in the formation of the insulating layer 336. For example, by applying an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD method as the insulating layer 335, an insulating layer 335 can be formed that has few pinholes and excellent function in protecting the EL layer 334.

[0458] Furthermore, it is preferable that the insulating layer 335 functions as a barrier insulating layer against at least one of water and oxygen. Therefore, it is preferable that the insulating layer 335 has the function of suppressing the diffusion of at least one of water and oxygen. It is also preferable that the insulating layer 335 has the function of capturing or fixing (also called gettering) at least one of water and oxygen. By having the insulating layer 335 function as a barrier insulating layer, it is possible to suppress the intrusion of impurities (typically at least one of water and oxygen) that can diffuse from the outside into each light-emitting element 320. With this configuration, it is possible to provide a highly reliable light-emitting element and, furthermore, a highly reliable display device.

[0459] An insulating layer having an organic material can be used as the insulating layer 336. Preferably, a photosensitive organic resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin is preferred. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0460] Furthermore, the insulating layer 336 may be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element 320, the insulating layer 336 can suppress light leakage (stray light) to adjacent light-emitting elements 320 through the insulating layer 336. This improves the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, at least one of the following can be achieved: the display device can be made lighter and thinner.

[0461] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used as color filters (color filter materials). In particular, it is preferable to use a resin material which is made by laminating or mixing two or more color filter materials, as this can enhance the visible light shielding effect. In particular, by mixing three or more color filter materials, it is possible to create a black or near-black resin layer.

[0462] [Configuration Example 4] The display device 490D shown in Figure 25B includes a light-emitting element 320R, a light-emitting element 320G, a light-emitting element 320B, a colored layer 354R that transmits red light, a colored layer 354G that transmits green light, and a colored layer 354B that transmits blue light. The display device 490D differs from the display device 490C in that each sub-pixel of each color uses a light-emitting element having an EL layer 334W and a colored layer (such as a color filter). Note that explanations of parts that are the same as those of the display device 490C described above may be omitted.

[0463] The light emitted by the light-emitting element 320R is extracted as red light to the outside of the display device 490D via the colored layer 354R. Similarly, the light emitted by the light-emitting element 320G is extracted as green light to the outside of the display device 490D via the colored layer 354G. The light emitted by the light-emitting element 320B is extracted as blue light to the outside of the display device 490D via the colored layer 354B.

[0464] Each light-emitting element 320R, 320G, and 320B has an EL layer 334W. The EL layers 334W of each color are formed using the same material and the same process. Furthermore, the EL layers 334W of each color are spaced apart from each other. By providing the EL layers 334W in an island-like manner for each light-emitting element 320, it is possible to suppress the flow of current between adjacent light-emitting elements 320. This prevents unintended light emission caused by crosstalk, and enables the realization of a display device with extremely high contrast.

[0465] For example, the light-emitting elements 320R, 320G, and 320B shown in Figure 25B emit white light. The white light emitted by the light-emitting elements 320R, 320G, and 320B passes through the colored layers 354R, 354G, and 354B, respectively, to obtain light of a desired color.

[0466] For example, the light-emitting elements 320R, 320G, and 320B shown in Figure 25B may emit blue light. In this case, the EL layer 334W has one or more light-emitting layers that emit blue light. In pixels that emit blue light, the blue light emitted by the light-emitting element 320B can be extracted. In pixels that emit red light and pixels that emit green light, a color conversion layer can be provided between the light-emitting element 320R or 320G and the substrate 350 to convert the blue light emitted by the light-emitting element 320R or 320G into longer wavelength light, thereby extracting red or green light. Furthermore, it is preferable to provide a coloring layer 354R between the color conversion layer and the substrate 350 on the light-emitting element 320R, and a coloring layer 354G between the color conversion layer and the substrate 350 on the light-emitting element 320G. Some of the light emitted by the light-emitting element 320 may be transmitted without being converted by the color conversion layer. Therefore, by extracting the light that has passed through the color conversion layer via the colored layer, the colored layer absorbs light of colors other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.

[0467] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0468] (Embodiment 4) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor according to one aspect of the present invention.

[0469] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0470] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0471] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 26A shows silicon (Si) and indium oxide (InO Ｘ Figure 26B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0472] First, as indicated by the arrows in Figure 26B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 26A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 1). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 26A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 26A.

[0473] In Figure 26A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0474] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0475] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0476] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0477] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In IGZO, however, strain can form in the source and drain regions due to stress on the electrodes in contact with the IGZO, sometimes resulting in the formation of an n-type region. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 26A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0478] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0479] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0480] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0481] The crystallinity of indium oxide can be analyzed, for example, by XRD, TEM, or ED. Alternatively, a combination of these methods may be used for analysis.

[0482] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0483] Unless otherwise specified, the channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating film, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0484] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0485] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0486] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0487] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 26C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0488] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0489] Furthermore, as shown in Figure 26C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２It is released as ) or, by reacting with oxygen contained in the membrane, it is released as water molecules.

[0490] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0491] Table 1 shows single crystal indium oxide (here, In ２ O ３ The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0492]

[0493] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0494] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0495] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0496] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0497] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0498] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0499] (Embodiment 5) This embodiment describes an electronic device according to one aspect of the present invention.

[0500] The electronic device shown in this embodiment has a display unit that uses a display device according to one aspect of the present invention, or a semiconductor device according to one aspect of the present invention. The display device according to one aspect of the present invention facilitates either or both high resolution and high definition. Therefore, it can be used in the display units of various electronic devices.

[0501] Furthermore, a semiconductor device according to one aspect of the present invention can be applied to devices other than the display unit of an electronic device. For example, using a semiconductor device according to one aspect of the present invention in the control unit of an electronic device is preferable because it enables lower power consumption.

[0502] Examples of electronic devices include those with relatively large screens, such as television sets, desktop or notebook computers, computer monitors, digital signage, and large game machines like pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0503] In particular, a display device according to one aspect of the present invention can be used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wearable devices that can be worn on the wrist (watch-type information terminals, bracelet-type information terminals, etc.), wearable devices that can be worn on the head (VR devices such as head-mounted displays, AR devices such as glasses, SR (Substitutional Reality) devices, MR (Mixed Reality) devices, devices that implement spatial computing such as spatial computers, etc.).

[0504] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display device according to one aspect of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device having high resolution and / or high detail, it is possible to enhance at least one of the following: a sense of presence and a sense of depth. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention, and various aspect ratios such as 1:1 (square), 4:3, 16:9, or 16:10 can be used.

[0505] The electronic device shown in this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0506] The electronic device shown in this embodiment may include a processing unit, a memory device, an input device, an output device, a control device, and the like. A semiconductor device according to one aspect of the present invention may be applied to the processing unit, memory device, input device, output device, control device, and the like of the electronic device.

[0507] The electronic device shown in this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of the electronic device are not limited to these and can have a variety of functions. The electronic device may have multiple display units. The electronic device may also have a camera and may have a function to take still images or videos with the camera, a function to save the captured images to a recording medium provided outside or inside the camera, a function to display the captured images on a display unit, etc.

[0508] Figure 27A shows an example of an electronic device that can be used as a portable information terminal, such as a smartphone.

[0509] The electronic device 8100 includes a housing 8101, a display unit 8102, a power button 8103, operation buttons 8104, a speaker 8105, a microphone 8106, a camera 8107, and a light source 8108. The display unit 8102 may also function as a touch panel.

[0510] A display device according to one embodiment of the present invention can be applied to the display unit 8102.

[0511] Figure 27B shows an example of an electronic device that can be used as a smartwatch or other wristwatch-type information terminal.

[0512] The electronic device 8200 includes a housing 8201, a display unit 8202, a power key 8203, operation keys 8204, a speaker 8205, a microphone 8206, a sensor 8207, and connection terminals 8208. The display unit 8202 is curved.

[0513] A display device according to one embodiment of the present invention can be applied to the display unit 8202.

[0514] Furthermore, the electronic device 8200 can communicate with a wireless headset to enable hands-free calling. The electronic device 8200 can also transmit data to other electronic devices and be charged via its connection terminal 8208. Charging may be performed via wireless power supply.

[0515] Figure 27C shows an example of an electronic device that can be used as a television system, etc.

[0516] The electronic device 8300 includes a housing 8301 and a display unit 8302, etc. The housing 8301 is supported by a stand 8303.

[0517] A display device according to one aspect of the present invention can be applied to the display unit 8302.

[0518] The electronic device 8300 can be operated using the operation switches on the housing 8301 or a separate remote control. The display unit 8302 may also function as a touch panel, and the electronic device 8300 can be operated by touching the display unit 8302 with a finger or other object.

[0519] The electronic device 8300 may also include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver only) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0520] Figure 27D shows an example of an electronic device that can be used as a notebook computer or the like.

[0521] The electronic device 8400 includes a housing 8401, a display unit 8402, a keyboard 8403, a pointing device 8404, and an external connection port 8405.

[0522] A display device according to one embodiment of the present invention can be applied to the display unit 8402.

[0523] Figure 27E shows an example of an electronic device that can be used as digital signage, etc.

[0524] The electronic device 8500 includes a display unit 8501, etc. The electronic device 8500 is mounted along the curved surface of a cylindrical column 8509.

[0525] A display device according to one embodiment of the present invention can be applied to the display unit 8501.

[0526] Furthermore, the display unit 8501 of the electronic device 8500 may also function as a touch panel. This allows the electronic device 8500 to be operated intuitively. For example, when the electronic device 8500 is used to provide information such as route information or traffic information, intuitive operation can enhance usability.

[0527] Furthermore, the electronic device 8500 may be able to communicate wirelessly with an information terminal 8508, such as a smartphone, owned by the user. For example, information from advertisements displayed on the display unit 8501 can be displayed on the screen of the information terminal 8508. Also, the display on the display unit 8501 can be switched by operating the information terminal 8508. In addition, the electronic device 8500 can be made to run a game using the screen of the information terminal 8508 as a control means (controller). This allows multiple users to participate in and enjoy the game simultaneously.

[0528] Figure 27F shows an example of electronic equipment installed around the windshield inside a car.

[0529] The electronic device 8600 includes a display unit 8601, a display unit 8602, and a display unit 8603 mounted on the dashboard, a display unit 8604 mounted on the pillar, and a main body 8605.

[0530] A display device according to one embodiment of the present invention can be applied to each of the display units 8601, 8602, 8603, and 8604.

[0531] Furthermore, each of the display units 8601 to 8604 can display various information transmitted from the main unit 8605 via wired or wireless communication. For example, each of the display units 8601 to 8603 can display various information such as navigation information, speedometer, tachometer, mileage, fuel gauge, gear status, and air conditioning settings. Display unit 8604 can display images from an imaging device installed on the outside of the vehicle to enhance safety by supplementing the view obstructed by the pillars (blind spots).

[0532] Figure 27G shows an example of a glasses-type electronic device that can be used for AR (augmented reality) equipment and the like.

[0533] The electronic device 8700 includes a main body 8701, a display unit 8702, a mounting unit 8703, and a lens 8704. A battery 8705 is provided in the mounting unit 8703. The battery 8705 is connected to the main body via a cable 8706.

[0534] A display device according to one embodiment of the present invention can be applied to the display unit 8702.

[0535] Furthermore, in the electronic device 8700, for example, if the main unit 8701 has a wireless receiver, video information such as received image data can be displayed on the display unit 8702. Also, for example, if the main unit 8701 has a camera, it can capture the movement of the user's eyeballs or eyelids, and by calculating the user's gaze based on that information, the user's gaze can be used as an input means.

[0536] Furthermore, in the electronic device 8700, the attachment portion 8703 may be provided with multiple electrodes at a position that touches the user. As a result, the electronic device 8700 may have a function to recognize the user's gaze by detecting the current flowing through the electrodes in accordance with the user's eye movements. It may also have a function to monitor the user's pulse by detecting the current flowing through the electrodes.

[0537] Furthermore, the electronic device 8700 may have various sensors to display the user's biometric information on the display unit 8702. It may also have a function to detect the user's head movements and change the image displayed on the display unit 8702 in accordance with those movements.

[0538] Figure 27H shows an example of a head-mounted display type electronic device that can be used for VR equipment and the like.

[0539] The electronic device 8800 includes a housing 8801, a display unit 8802, operation buttons 8803, and a fixing device 8804. A battery 8805 is provided in the fixing device 8804.

[0540] A display device according to one embodiment of the present invention can be applied to the display unit 8802.

[0541] Furthermore, since the electronic device 8800 has two display units 8802, the user can view one display unit with each eye. This allows for the display of high-resolution images even when performing 3D displays using parallax.

[0542] Furthermore, the contents of this embodiment can be combined as appropriate. Also, the contents of this embodiment can be combined as appropriate with the contents of other embodiments, etc.

[0543] (Notes regarding the description in this specification, etc.) The above embodiments and descriptions of each component in the embodiments are provided below.

[0544] In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor properties. For example, semiconductor elements such as transistors, electronic circuits containing semiconductor elements, chips with electronic circuits formed on a substrate, electronic components with chips housed in a package, and electronic devices on which electronic components are mounted are examples of semiconductor devices. In addition, display devices, light-emitting devices, projection devices, illumination devices, optical devices, electro-optical devices, imaging devices, light-receiving devices, detection devices, power supply devices, energy storage devices, communication devices, arithmetic units, control devices, arithmetic processing units, memory devices, input devices, output devices, input / output devices, signal processing devices, information processing devices, computers, and electronic devices may have semiconductor devices and can be said to be semiconductor devices themselves.

[0545] In this specification, a "transistor" has three terminals called the "gate" (also called the gate terminal, gate region, or gate electrode), the "source" (also called the source terminal, source region, or source electrode), and the "drain" (also called the drain terminal, drain region, or drain electrode). A transistor also has a region where a channel is formed between the drain and the source (also called the channel formation region). A transistor can pass current between the source and the drain through the channel formation region. Furthermore, a transistor can generate electrical signals or potential interactions between the source and the drain through the channel formation region. The channel formation region is the region where current primarily flows. The gate is a control terminal that controls the amount of current flowing through the channel formation region. The two terminals that function as the source or drain are input / output terminals that input or output the current flowing through the channel formation region.

[0546] The two input / output terminals function as either a source or a drain, depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to its three terminals. Furthermore, the source and drain functions may be reversed when the direction of current changes during circuit operation. Therefore, the terms "source" and "drain" are interchangeable. When describing the connections of a transistor, the expressions "one of the source or drain" (or first electrode, first terminal, etc.) and "the other of the source or drain" (or second electrode, second terminal, etc.) should be used.

[0547] In addition to the three terminals mentioned above, transistors may have a terminal called a "back gate" (also called the back gate terminal, back gate region, or back gate electrode). In this case, one of the gates or back gate of the transistor may be called the first gate, and the other of the gates or back gate may be called the second gate. Also, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, each gate may be called the first gate, second gate, third gate, and so on.

[0548] Furthermore, the voltage between the gate and source (gate-source) (unless otherwise specified, the potential of the source is used as the reference) is sometimes called the "gate voltage," the voltage between the drain and source (drain-source) (unless otherwise specified, the potential of the source is used as the reference) is sometimes called the "drain voltage," and the voltage between the back gate and source (back gate-source) (unless otherwise specified, the potential of the source is used as the reference) is sometimes called the "back gate voltage." Also, the current flowing between the drain and source (unless otherwise specified, the direction from drain to source is considered positive) is sometimes called the "drain current." Note that in n-channel transistors, expressions such as high gate voltage, high drain voltage, and high back gate voltage can be appropriately substituted for each other, and in p-channel transistors, expressions such as low gate voltage, low drain voltage, and low back gate voltage can be appropriately substituted for each other. Similarly, in n-channel transistors, expressions such as low gate voltage, low drain voltage, and low back gate voltage can be appropriately substituted for each other, and in p-channel transistors, expressions such as high gate voltage, high drain voltage, and high back gate voltage can be appropriately substituted for each other.

[0549] The "conducting state" and "on state" of a transistor refer to states such as: a state in which the source and drain of the transistor can be considered electrically short-circuited; a state in which current can flow between the source and drain (also called a state in which current can flow); a state in which the gate voltage is higher than the threshold voltage in an n-channel transistor; and a state in which the gate voltage is lower than the threshold voltage in a p-channel transistor. The "non-conducting state," "blocked state," and "off state" of a transistor refer to states such as: a state in which the source and drain of the transistor can be considered electrically blocked; a state in which the gate voltage is lower than the threshold voltage in an n-channel transistor; and a state in which the gate voltage is higher than the threshold voltage in a p-channel transistor.

[0550] Furthermore, unless otherwise specified, the "off-current" of a transistor refers to the drain current when the transistor is in the off state. Note that the off-current and the current flowing between the gate, source, and drain (also called gate leakage current) are sometimes collectively referred to as leakage current.

[0551] In this specification, "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. For example, "capacitive element" refers to a circuit element having a configuration in which a pair of electrodes are provided with a dielectric material in between. However, capacitive elements are not limited to this and may include, for example, parasitic capacitance occurring between two wires, gate capacitance occurring between the source and drain of a transistor and the gate, etc. In some cases, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be substituted for terms such as "capacitance" and "electrostatic capacitance." In some cases, terms such as "pair of electrodes," "pair of wires," "pair of terminals," and "pair of conductive layers" of a capacitive element can be substituted for each other.

[0552] In this specification, "switch" refers to a circuit element having multiple terminals and having the function of switching (selecting) the conduction or non-conductivity between those terminals. A switch can be said to have the function of controlling whether or not to allow current to flow between multiple terminals, or the function of controlling whether or not to generate the transmission or reception of electrical signals or the interaction of potentials between multiple terminals. For example, if a switch has two terminals, the state in which the two terminals can be considered to be electrically short-circuited is called the "conducting state" or "on state". Also, the state in which the two terminals can be considered to be electrically blocked is called the "non-conducting state" or "off state". Switching the switch to either the conducting state or the non-conducting state, or maintaining either the conducting state or the non-conducting state, is sometimes referred to as "controlling the conducting state". Therefore, "switch" refers to something that has the function of controlling whether or not to allow current to flow. Also, "switch" refers to something that has the function of selecting and switching the path through which current flows. Note that electrical switches, mechanical switches, etc., can be used as switches. Therefore, "switch" is not limited to a specific type.

[0553] In this specification, a single circuit element shown in a circuit diagram includes cases where multiple such circuit elements are connected in series, parallel, or series-parallel.

[0554] In this specification, a signal line refers to wiring to which a signal is supplied, and a power line refers to wiring to which a constant potential is supplied. Therefore, the terms "signal line" and "power line" can sometimes be replaced with the term "wiring." For example, a signal line can be considered to have a constant potential if the signal supplied to it does not change. Similarly, a power line can be considered to have a signal if the potential supplied to it changes. Therefore, the terms "potential" and "signal" supplied to wiring can sometimes be interchangeable.

[0555] In this specification, voltage refers to the potential difference from a reference potential (such as ground potential). Therefore, the terms "voltage" and "potential" can sometimes be used interchangeably.

[0556] In this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit these components. Therefore, an electrode may be part of wiring or a terminal, wiring may be part of an electrode or a terminal, and a terminal may be part of an electrode or wiring. Furthermore, "electrode or wiring" includes cases where multiple electrodes or multiple wirings are integrated. Similarly, "terminal" includes cases where multiple electrodes, multiple wirings, or multiple terminals are integrated. Additionally, the terms "electrode," "wiring," and "terminal" may be replaced with terms such as "region" or "conductive layer."

[0557] In this specification, the term "node" may be replaced with terms such as "electrode," "wiring," "terminal," "region," or "conductive layer," depending on the circuit configuration, device structure, etc. Conversely, terms such as "electrode," "wiring," and "terminal" may be replaced with the term "node."

[0558] In this specification, terms containing the words "layer" and "film" may be interchangeable. For example, the terms "conductive layer" and "conductive film" may be interchangeable. For example, the terms "insulating layer" and "insulating film" may be interchangeable. For example, the terms "semiconductor layer" and "semiconductor film" may be interchangeable. Furthermore, in terms containing the words "layer" and "film," these terms may be replaced with other terms. For example, the terms "conductive layer" and "conductive film" may be interchangeable with the term "conductor." For example, the terms "insulating layer" and "insulating film" may be interchangeable with the term "insulator."

[0559] In this specification, terms such as "above" and "below" are used for convenience to describe the positional relationships of the constituent elements. Therefore, these terms can be replaced with other terms and the expression can be appropriately modified. For example, the expression "Element B is located above Element A, and Element C is located below Element A" can be changed to "Element B is located below Element A, and Element C is located above Element A." Similarly, the expression "Element B is located above Element A, and Element C is located below Element A" can be changed to "Element B is located to the left (or right) of Element A, and Element C is located to the right (or left) of Element A." It should be noted that when using the terms "above" or "below," the positional relationship of the constituent elements is not limited to directly above or directly below. Therefore, the term "above" can be replaced with terms such as "upper," "upper side," or "upper layer," and the term "below" can be replaced with terms such as "downward," "lower side," or "lower layer." Furthermore, for example, the expression "element B on element A" is not limited to cases where element B is placed in contact with element A, but also includes cases where other elements (including space) are provided between element A and element B.

[0560] In this specification, "parallel" does not mean strictly parallel. Unless otherwise specified, "parallel" may include a state in which two lines or planes are positioned at an angle of -5° to 5°. Alternatively, it may include a state in which two lines or planes are positioned at an angle of -10° to 10°. Or, it may include a state in which two lines or planes are positioned at an angle of -30° to 30°. Therefore, the term "parallel" may be replaced with terms such as "approximately parallel" or "substantially parallel." Also, "parallel" may mean "parallel or approximately parallel."

[0561] In this specification, "perpendicular" does not mean strictly perpendicular. Unless otherwise specified, "perpendicular" may include a state in which two lines or planes are positioned at an angle of 85° to 95°. Alternatively, it may include a state in which two lines or planes are positioned at an angle of 80° to 100°. Or, it may include a state in which two lines or planes are positioned at an angle of 60° to 120°. Therefore, the term "perpendicular" may be replaced with terms such as "approximately perpendicular" or "substantially perpendicular." Also, "perpendicular" may mean "perpendicular or approximately perpendicular."

[0562] In this specification, when terms such as "identical," "same," "equal," "simultaneous," "consistent," and "uniform" (including their synonyms) are used in reference to count values, measured values, etc., these terms shall include errors. Therefore, unless otherwise specified, these terms may include an error of plus or minus 10%, or an error of plus or minus 20%. Thus, "identical" may mean "identical or approximately identical," "same" may mean "same or approximately the same," "equal" may mean "equal or approximately equal," "simultaneous" may mean "simultaneous or approximately simultaneous," "consistent" may mean "consistent or approximately consistent," and "uniform" may mean "uniform or approximately uniform."

[0563] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components, their order, etc. For example, a component referred to as "first" in one embodiment may be referred to as "second" in other embodiments, claims, etc. Also, for example, a component referred to as "first" in one embodiment may be omitted in other embodiments, claims, etc. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims. Also, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0564] In this specification, one of the source or drain (also called the two input / output terminals) of a transistor may be referred to as the first terminal, and the other of the source or drain of a transistor may be referred to as the second terminal. Therefore, a transistor has at least a gate (also called the gate terminal), a first terminal, and a second terminal. In addition, one terminal of a capacitive element (also called one of a pair of terminals) may be referred to as the first terminal, and the other terminal of a capacitive element (also called the other of a pair of terminals) may be referred to as the second terminal. In addition, one terminal of a display element may be referred to as the first terminal, and the other terminal of a display element may be referred to as the second terminal. In addition, one terminal of a liquid crystal element may be referred to as the first terminal, and the other terminal of a liquid crystal element may be referred to as the second terminal. In addition, one terminal of a light-emitting element may be referred to as the first terminal, and the other terminal of a light-emitting element may be referred to as the second terminal. In addition, one terminal of a light-receiving element may be referred to as the first terminal, and the other terminal of a light-receiving element may be referred to as the second terminal. In addition, one of the anode or cathode of a diode (also called one of the pair of terminals) is sometimes called the first terminal, and the other of the anode or cathode of a diode (also called the other of the pair of terminals) is sometimes called the second terminal.

[0565] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship of circuit elements as a physical object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" means, for example, that A and B are connected without the use of a circuit element (e.g., a transistor or a switch; however, wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected via one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0566] Here, when we define "A and B are indirectly connected," it refers to the following type of connection, as an example: That is, assuming the circuit is operating, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then such a circuit can be defined as having "A and B indirectly connected" as a physical object. Even if there are times when no electrical signals are exchanged or potential interactions occur between A and B, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined as having "A and B indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a physical object. Therefore, for example, even if no power supply voltage is supplied to the circuit and the circuit is not operating, the circuit can still be defined as having "A and B indirectly connected" as a physical object (however, as an example, this is limited to cases where, when power supply voltage is supplied to the circuit and the circuit is operating, electrical signals are exchanged or potential interactions occur between A and B during the circuit's operation).

[0567] The following are specific examples of "indirect connections". First, an example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in Figures 28A1 and 28A2. Another example of a case where "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected", assuming the circuit is operating, one transistor between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. Note that when "A and B are indirectly connected", this includes the case where one transistor between A and B is in an OFF state or a non-conducting state. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state at the same time or at different times. As another example, as shown in Figure 28A3, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0568] Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in Figure 28A4. Another example of when A and B are connected via an insulator is when a transistor gate insulating film is interposed between A and B, as shown in Figure 28A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0569] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, as shown in Figures 28A6 and 28A7, multiple transistors are connected via sources and drains in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND. In this case, it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." In Figure 28A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, then the connection relationship is the same as in Figures 28A6 and 28A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

[0570] As shown above, we have provided an example of "indirect connection." As an example, the provisions for "indirect connection" are included in the provisions for "electrical connection," so if "A and B are indirectly connected," then "A and B are electrically connected."

[0571] Next, we will show specific examples of "direct connection." Examples of cases where "A and B are directly connected" include cases where A and B are connected without a circuit element in between, as shown in Figures 28B1, 28B2, and 28B3. Furthermore, as shown in Figures 28B4 and 28B5, when A and B are connected to a power source that supplies a constant potential V, or to GND, without a circuit element in between, we can say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Furthermore, as shown in Figure 28B6, even when A (or B) is connected to a constant potential V via the source and drain of a transistor, we can say that "A and B are directly connected." Furthermore, since A and V, or B and V, are connected via the source and drain of a transistor, they cannot be said to be directly connected, and we can say that "A and V are indirectly connected," or "B and V are indirectly connected."

[0572] As shown above, an example of "direct connection" has been given, but as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," if "A and B are directly connected," then "A and B are electrically connected."

[0573] 100: Semiconductor device, 101: Drive circuit, 101A: Drive circuit, 101B: Drive circuit, 102: Pixel section, 111a: Buffer group, 111b: Buffer group, 111c: Buffer group, 111d: Buffer group, 111e: Buffer group, 112a: Buffer, 112b: Buffer, 112c: Buffer, 112d: Buffer, 112e: Buffer, 113: Shift register, 114a: Terminal section, 114a1: Terminal, 114a2: Terminal, 114b: Terminal section, 114b1: Terminal, 114b2: Terminal, 114c: Terminal section, 114d: Terminal section, 114e: Terminal section, 115 a: Wiring group, 115b: Wiring group, 115c: Wiring group, 115d: Wiring group, 115e: Wiring group, 116a: Wiring, 116b: Wiring, 116c: Wiring, 116d: Wiring, 116e: Wiring, 117: Register, 118a: Gate line selection circuit, 118b: Gate line selection circuit, 121a: Pixel area, 121b: Pixel area, 121c: Pixel area, 121d: Pixel area, 121e: Pixel area, 122: Pixel, 123a: Gate line, 123b: Gate line, 123c: Gate line, 123d: Gate line, 123e: Gate line, 124: Source line, 160: Display device, 161: Image Element, 162: Pixel part, 163: Gate driver part, 164: Source driver part, 165: Gate line, 166: Source line, 167: Control unit, M11a: Transistor, M11b: Transistor, M12a: Transistor, M12b: Transistor, M13a: Transistor, M13b: Transistor, M21: Transistor, M22: Transistor, M23: Transistor, M24: Transistor, M25: Transistor, M26: Transistor, M27: Transistor, M31: Transistor, M32: Transistor, C11a: Capacitance element, C11b: Capacitance Capacitive element, C21: Capacitive element, LD: End-point, SRLagp: Wiring group, SRLbgp: Wiring group, PKLagp: Wiring group, PKLbgp: Wiring group, GOLagp: Wiring group, GOLbgp: Wiring group, CKLgp: Wiring group, SPL: Wiring, SRLa: Wiring, SRLb: Wiring, PKLa: Wiring, PKLb: Wiring, GOLa: Wiring, GOLb: Wiring, CKL: Wiring, IL1: Wiring, IL2: Wiring, OL: Wiring, VLD1: Wiring, VLD2: Wiring, VLS1: Wiring, VLS2: Wiring, ANO: Wiring, CATH: Wiring, 200: Transistor, 200A: Transistor,200B: Transistor, 200C: Transistor, 320: Light-emitting element, 320R: Light-emitting element, 320G: Light-emitting element, 320B: Light-emitting element, 400: Display device, 411: Pixel, 412: Pixel, 412R: Pixel, 412G: Pixel, 412B: Pixel, 490: Display device, 490A: Display device, 490B: Display device, 490C: Display device, 490D: Display device,

Claims

It has a shift register, a first buffer, a second buffer, a first wiring, and a second wiring. The first buffer has the function of supplying a signal to the first wiring to a gate line provided in the first pixel area, based on a signal output from the first terminal of the shift register. The second buffer has the function of supplying a signal to the second wiring, based on the signal output from the second terminal of the shift register, to the gate line provided in the second pixel area. The first pixel region has the function of displaying at a first resolution, The aforementioned second pixel region has the function of displaying at the first resolution and the function of displaying at the second resolution. The second resolution is a lower resolution than the first resolution. When the first pixel region is displayed at the first resolution and the second pixel region is displayed at the second resolution, the second wiring is supplied with a signal having a pulse width longer than the pulse width of the signal supplied to the first wiring, or with a constant potential. Drive circuit. 　 In claim 1, The first pixel region includes the center of the display region. Drive circuit. 　 In claim 1, It has a gate line selection circuit, The gate line selection circuit is provided between the second buffer and the second pixel region. The gate line selection circuit has the function of controlling the signal supplied to the second wiring to be supplied to one or more gate lines provided in the second pixel region. Drive circuit. 　 In any one of claims 1 to 3, The first buffer comprises a first transistor and a second transistor, The second buffer comprises a third transistor and a fourth transistor, The first terminal of the first transistor is electrically connected to the first terminal of the second transistor and to the gate line provided in the first pixel region. The second terminal of the first transistor is electrically connected to the first wiring, The second terminal of the second transistor is electrically connected to the third wiring. The gate of the first transistor is electrically connected to the first terminal of the shift register. The gate of the second transistor is electrically connected to the terminal to which the inverted signal of the signal output from the first terminal of the shift register is output. The first terminal of the third transistor is electrically connected to the first terminal of the fourth transistor and to the gate line provided in the second pixel region. The second terminal of the third transistor is electrically connected to the second wiring, The second terminal of the fourth transistor is electrically connected to the third wiring, The gate of the third transistor is electrically connected to the second terminal of the shift register. The gate of the fourth transistor is electrically connected to the terminal to which the inverted signal of the signal output from the second terminal of the shift register is output. Drive circuit. 　 In claim 4, Each of the first to fourth transistors includes an oxide semiconductor in its channel formation region. Drive circuit. 　 In claim 5, The oxide semiconductor contains indium, Drive circuit.

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