Semiconductor device and method of manufacturing same

Abstract

A method for manufacturing a semiconductor device includes: forming a recess having a flat bottom surface in a glass substrate; irradiating a first main surface of a single crystal silicon substrate with ions, thus forming an embrittlement layer in the single crystal silicon substrate; placing the single crystal silicon substrate in the recess so that a portion between the embrittlement layer and the first main surface is sandwiched between the embrittlement layer and the glass substrate, thus bonding the glass substrate and the single crystal silicon substrate; and peeling the single crystal silicon substrate from the glass substrate, thus forming, as a single crystal silicon film, the portion in the recess.

Description

Semiconductor devices and their manufacturing methods

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] In recent years, a method for forming a single-crystal silicon film on an amorphous glass substrate has been developed. In this method, an embrittlement layer is formed by implanting ions such as hydrogen ions into the single-crystal silicon substrate, and after bonding the single-crystal silicon substrate and the amorphous glass substrate, the single-crystal silicon substrate is peeled off, thereby transferring the single-crystal silicon film on the embrittlement layer to the glass substrate (see Patent Document 1). This method is called smartcut, and various semiconductor devices can be provided by utilizing the single-crystal silicon film obtained by this method.

[0003] Special Publication No. 2011-501431

[0004] One embodiment of the present invention aims to provide a semiconductor element having a novel structure and a method for manufacturing the same. Alternatively, one embodiment of the present invention aims to provide a semiconductor element exhibiting excellent properties and a method for manufacturing this semiconductor element with high yield. Alternatively, one embodiment of the present invention aims to provide a semiconductor device having the above-mentioned semiconductor element and a method for manufacturing the same. Alternatively, one embodiment of the present invention relates to a functional substrate for manufacturing the above-mentioned semiconductor element.

[0005] One embodiment of the present invention is a method for manufacturing a semiconductor device. This manufacturing method includes forming a recess with a flat bottom surface in a glass substrate, forming an embrittlement layer in a single-crystal silicon substrate by ion irradiation of a first main surface of a single-crystal silicon substrate, joining the glass substrate and the single-crystal silicon substrate by arranging the single-crystal silicon substrate in the recess such that the portion between the embrittlement layer and the first main surface is sandwiched between the embrittlement layer and the glass substrate, and forming the above portion as a single-crystal silicon film in the recess by peeling the single-crystal silicon substrate from the glass substrate.

[0006] One embodiment of the present invention is a semiconductor device. This semiconductor device comprises a glass substrate having at least one recess with a flat bottom surface, and a semiconductor element on the glass substrate. The semiconductor element includes a single-crystal silicon film located within the recess.

[0007] One embodiment of the present invention is a functional substrate. This functional substrate comprises a glass substrate having at least one recess with a flat bottom surface, and a single-crystal silicon film located in the recess.

[0008] A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic perspective view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. An equivalent circuit diagram of a pixel in a semiconductor device according to one embodiment of the present invention. An equivalent circuit diagram of a pixel in a semiconductor device according to one embodiment of the present invention. A schematic top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. A schematic end view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0009] The embodiments of the present invention will be described below with reference to the drawings and other materials. However, the present invention can be implemented in various forms without departing from its spirit, and is not to be interpreted as being limited to the embodiments described below.

[0010] While drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same function as those described in previously shown drawings may be denoted by the same reference numeral, and redundant explanations may be omitted. This reference numeral is used to collectively represent multiple identical or similar structures.

[0011] In this specification and claims, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the term "on top of" includes both cases: when one structure is placed directly on top of another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0012] In this specification and claims, the expression "a structure is exposed from another structure" means a portion of a structure that is not covered by another structure, and this portion that is not covered by another structure may also be covered by yet another structure. Furthermore, the expression also includes a portion of a structure that is not in contact with another structure.

[0013] In this invention, when a single film is processed to form multiple films, these multiple films may have different functions and roles. However, these multiple films originate from a film formed as the same layer in the same process, and have substantially the same layer structure, the same material, and the same morphology. Therefore, these multiple films are defined as existing in the same layer.

[0014] <First Embodiment> One embodiment of the present invention is a method for manufacturing a semiconductor device. This semiconductor device utilizes the properties of a single-crystal silicon film formed on a glass substrate having amorphous morphology. Therefore, a single-crystal silicon film is formed on the glass substrate during the manufacturing of the semiconductor device. In this embodiment, a method for fabricating a single-crystal silicon film on a glass substrate will be described.

[0015] 1. A schematic top view of the glass substrate 100 is shown in the processing diagram 1 of the glass substrate. The glass substrate 100 is a substrate having amorphous morphology, and can be used as a glass substrate containing silicon oxide, alumina, and alkaline earth metal oxides, called an alkaline earth aluminoborosilicate glass substrate; a glass substrate containing silicon oxide, sodium oxide, alumina, and boron oxide, called a borosilicate glass substrate; a glass substrate containing silicon oxide, potassium oxide, and lead oxide, also called a lead glass substrate; or a glass substrate containing silicon oxide, alumina, lithium oxide, titanium oxide, and zirconium oxide. Preferably, the coefficient of thermal expansion is 3.5 × 10⁻⁶. －６ K －１ The above 3.9 x 10 －６ K －１ The density is as follows: 2.51 g / cm³ ３ 2.62g / cm or more ３A glass substrate is used. The thickness of the glass substrate 100 can also be arbitrarily determined, for example, 100 μm or more and 1000 μm or less, typically 400 μm.

[0016] There are no restrictions on the size of the glass substrate 100. A small substrate of about 120 mm x 120 mm may be used, or a glass substrate of a size of 600 mm x 720 mm, known as third-generation glass, a size of 730 mm x 920 mm, known as fourth-generation glass, a size of 1500 mm x 1850 mm, or larger may be used. There are also no restrictions on the shape of the glass substrate 100. The glass substrate 100 may be a polygon including a square or rectangle, or its outline may be formed only by curves or by curves and straight lines. Preferably, a square or rectangular substrate that is easy to handle is used as the glass substrate 100.

[0017] Alignment markers 102 may be formed on the glass substrate 100 to form recesses (also called counterbores), which will be described later. The alignment markers 102 can be formed by sputtering, chemical vapor deposition (CVD), or vapor deposition, using, for example, metals with relatively high melting points such as molybdenum, tungsten, or tantalum, or alloys containing these metals. Alternatively, the alignment markers 102 may be formed by irradiating the glass substrate 100 with laser light emitted from a laser such as a femtosecond laser. Since the refractive index of the glass substrate 100 can be changed by laser light irradiation, the irradiated portion can be used as an alignment marker 102 by irradiating it with polarized light and reading the reflected light. Alternatively, the alignment markers 102 may be formed by removing the irradiated portion with laser light by wet etching. An example of an etchant in this case is an aqueous potassium hydroxide solution.

[0018] In the manufacture of a semiconductor device according to an embodiment of the present invention, first, as shown in a schematic view of an end face (FIG. 2) along the chain line A - A' in FIG. 1, the glass substrate 100 is processed to form one or more recesses 100a. The recess 100a is a portion recessed from one main surface 100b of the glass substrate 100, and its flat bottom surface 100c is parallel to the main surface 100b. The depth D of the recess 100a １ is defined as the distance from the main surface 100b to the bottom surface 100c in a direction parallel to the normal line of the main surface 100b or the bottom surface 100c, and is selected from the range of 0.1% or more and 10% or less of the thickness T of the glass substrate 100. By setting the depth D within this range, it is possible to suppress a decrease in the strength of the glass substrate 100 caused by the formation of the recess 100a. The depth D １ may be the same as the thickness of a single-crystalline silicon substrate described later, or may be larger or smaller than the thickness of the single-crystalline silicon substrate. １ １

[0019] Although not shown, the recess 100a can be formed by photolithography. For example, a resist (liquid photosensitive resist or solid photosensitive resist film, the same applies hereinafter) is formed on the glass substrate 100, and then the resist is exposed through a photomask. At this time, alignment of the photomask may be performed using the alignment marker 102. Then, by performing development, a resist mask having an opening that exposes the region where the recess 100a is to be formed is formed. Then, by performing etching with an etchant containing hydrofluoric acid, the portion of the glass substrate 100 exposed from the resist mask is removed, and the recess 100a is formed.

[0020] The side wall 100d extending parallel to the normal direction from the bottom surface 100c of the recess 100a may be directly connected to the main surface 100b, as shown in Figure 2, but the recess 100a may be chamfered. Specifically, as shown in Figure 3, the side wall 100d and the main surface 100b may be connected via an inclined surface 100e that is inclined with respect to the side wall 100d and the main surface 100b. The angle θ between the side wall 100d and the inclined surface 100e can be arbitrarily determined, for example, between 120° and 150°, typically 135°. Height H of the side wall 100d １ For example, depth D １ The value should be set to 30% to 70%. As will be described in detail later, by forming a chamfer, the single-crystal silicon substrate can be easily and accurately placed in the recess 100a. As shown in the schematic perspective view of Figure 4, the inclined surface 100e may be formed around the entire circumference of each recess 100a, or it may be formed only on a part of it. For example, if the bottom surface 100c is rectangular, the inclined surface 100e may be provided on all sides of the recess 100a, or it may be provided only on some sides. The chamfer can be formed by polishing the main surface 100b and side walls 100d of the glass substrate 100 along its periphery after the recess 100a has been formed.

[0021] 2. The ion-implanted single-crystal silicon substrate is a substrate made substantially of silicon, and its main surface is composed of a (100) crystal plane or a (111) crystal plane of single-crystal silicon. There are no restrictions on the shape of the single-crystal silicon substrate (i.e., the shape of its main surface, hereafter the same). However, as will be described later, since the single-crystal silicon substrate is placed in the recess 100a, the shape and area of ​​the single-crystal silicon substrate are the same as or substantially the same as the shape and area of ​​the recess 100a (more specifically, the shape of the bottom surface 100c, hereafter the same). Therefore, if the recess 100a is rectangular, the single-crystal silicon substrate 110 will also be rectangular. Also, the length L of two mutually orthogonal sides of the recess 100a (or the bottom surface 100c if chamfered) is also the length L. １ , L ２ (See Figure 1) The lengths l of two mutually orthogonal sides of the single-crystal silicon substrate 110 are shown. １ , l ２(See Figure 5) It will be identical or substantially identical to the one shown. However, length L １ and l １ They do not have to be exactly the same, and their lengths l １ is length L １ It is also acceptable for the ratio to be between 98% and 100%. Similarly, for length L ２ and l ２ They do not have to be completely identical to each other, and their length l ２ is length L ２ For this, a percentage between 98% and 100% is also acceptable.

[0022] After the single-crystal silicon substrate 110 is appropriately cleaned, ion implantation is performed from one main surface 110a of the single-crystal silicon substrate 110, as shown in Figure 6. Hydrogen ions are an example of ions, but helium ions and argon ions may also be implanted. In ion implantation, a single type of ion obtained by mass separation may be implanted, or multiple types of ions may be implanted simultaneously without mass separation.

[0023] Ion implantation creates a layer containing minute voids inside the single-crystal silicon substrate 110. This layer is called the embrittlement layer 112 and is formed inside the single-crystal silicon substrate 110, almost parallel to the main surface 110a (Figure 7). The depth of the embrittlement layer 112 (distance from the main surface 110a) can be adjusted by appropriately controlling the ion acceleration voltage. The depth of the embrittlement layer 112 can be appropriately set according to the thickness of the single-crystal silicon film formed on the glass substrate 100, for example, between 10 nm and 500 nm. The ion dose is, for example, 3 × 10⁻⁶ １６ ions / cm ２ The above 1 x 10 １７ ions / cm ２ The following is correct.

[0024] 3. Formation of Single-Crystalline Silicon Film Next, the glass substrate 100 and the single-crystalline silicon substrate 110 are bonded. Specifically, as shown in FIGS. 8 and 9, the portion 114 sandwiched between the embrittlement layer 112 and the main surface 110a is sandwiched between the embrittlement layer 112 and the glass substrate 100, and the single-crystalline silicon substrate 110 is arranged in the concave portion 100a so as to contact the bottom surface 100c. At this time, by chamfering the concave portion 100a, even when the single-crystalline silicon substrate 110 is slightly inclined with respect to the glass substrate 100, the single-crystalline silicon substrate 110 can be accurately arranged in the concave portion 100a. The thickness of the single-crystalline silicon substrate 110 and the depth D of the concave portion 100a １ also depend on the relationship therebetween. When the single-crystalline silicon substrate 110 is arranged in the concave portion 100a, the upper surface of the single-crystalline silicon substrate 110 (that is, the main surface 110b facing the main surface 110a) and the main surface 100b of the glass substrate 100 may be located on the same plane (FIG. 9), or the former may be below the latter (on the side of the bottom surface 100c) or the latter may be below the former (FIGS. 10 and 11).

[0025] At the time of bonding, appropriate pressure treatment and heat treatment may be performed on the glass substrate 100 and the single-crystalline silicon substrate 110. The pressure in the pressure treatment is appropriately selected within the range of 7 Pa or more and 35 Pa or less. The heat treatment is performed below the strain point of the glass substrate 100, and for example, the heat treatment is performed at a temperature selected from the range of 50 ° C or more and 200 ° C or less.

[0026] In bonding, anodic bonding may be further used. Specifically, as shown in FIG. 12, electrodes 120 and 122 are connected to the single-crystalline silicon substrate 110 and the glass substrate 100, respectively, and a voltage is applied between the electrodes 120 and 122. At this time, the voltage is applied so that the electrodes 120 and 122 function as the positive electrode and the negative electrode, respectively. The voltage is, for example, 30 V or more and 1000 V or less. At this time, heat may be applied simultaneously. By performing anodic bonding, a strong electrostatic attraction acts between the glass substrate 100 and the single-crystalline silicon substrate 110, and as a result, the glass substrate 100 and the single-crystalline silicon substrate 110 can be bonded more firmly.

[0027] Thereafter, the single-crystalline silicon substrate 110 is peeled off from the glass substrate 100. The peeling may be physically performed. As a result, the portion 114 between the embrittlement layer 112 and the main surface 110a peels off with the embrittlement layer 112 as a cleavage plane, and as a result, a single-crystalline silicon film 116 having a single-crystalline morphology is formed on the bottom surface 100c of the recess 100a (FIG. 13). The thickness of the single-crystalline silicon film 116 is smaller than the depth D of the recess 100a. The thickness of the single-crystalline silicon film 116 can be adjusted by the depth from the main surface 110a of the embrittlement layer 112. For example, it may be 0.01% or more and 1% or less of the thickness of the glass substrate 100, or 10 nm or more and 500 nm or less. Although it also depends on the depth of the embrittlement layer 112 and the depth D of the recess 100a, when the glass substrate 100 is chamfered, a space is generated between the inclined surface 100e and the single-crystalline silicon substrate 110, so it is also possible to insert a jig into this space as appropriate to perform the peeling. １ In this step, the embrittlement layer 112 is used as a cleavage plane. Therefore, the ion-implanted main surface 110a is located on the glass substrate 100 side, and the upper surface of the single-crystalline silicon film 116 (the surface opposite to the glass substrate 100) is on the embrittlement layer 112 side. Since voids are generated in the single-crystalline silicon substrate 110 by ion implantation, the crystallinity of the embrittlement layer 112 decreases, and as a result, a part of the upper surface of the single-crystalline silicon film 116 may have a polycrystalline or amorphous morphology. In order to remove the polycrystalline or amorphous silicon present on the upper surface of the single-crystalline silicon film 116 and form a single-crystalline surface, a cleaning process may be performed on the single-crystalline silicon film 116 using a cleaning liquid containing hydrofluoric acid. By this cleaning process, a single-crystalline morphology is realized over the entire single-crystalline silicon film 116. １

[0028]

[0029] Through the above steps, a functional substrate according to one embodiment of the present invention can be manufactured, in which a single-crystal silicon film 116 is arranged in a recess 100a on the glass substrate 100. In conventional smart cutting, it is relatively difficult to precisely control the position of the single-crystal silicon substrate when joining the glass substrate and the single-crystal silicon substrate, and the alignment accuracy when joining the single-crystal silicon substrate is on the order of several hundred micrometers to several meters. Such large alignment deviations have a significant impact on subsequent processes, including the processing of the resulting single-crystal silicon film, and this is a major cause of reduced characteristics and yield of semiconductor elements and semiconductor devices containing the single-crystal silicon film. However, as described above, in the semiconductor device manufacturing method according to the embodiment of the present invention, the glass substrate 100 and the single-crystal silicon substrate 110 are joined by placing the single-crystal silicon substrate 110 in a recess 100a formed on the glass substrate 100 by photolithography. Generally, the processing accuracy by photolithography is extremely high and can be kept to several micrometers to 20 micrometers or less. Therefore, by applying the embodiments of the present invention, it is possible to bond the glass substrate 100 and the single-crystal silicon substrate 110 with high alignment accuracy. As a result, the resulting single-crystal silicon film 116 can be processed with high precision. This contributes to improving the characteristics and yield of semiconductor elements and semiconductor devices containing the processed single-crystal silicon film 116.

[0030] 4. Other Processes (1) Alignment Marker As described above, the recess 100a can be formed by photolithography on the glass substrate 100. Therefore, by using the alignment marker 102, the recess 100a can be formed with good positional accuracy. However, when forming the recess 100a, it is difficult to avoid extremely small alignment deviations of a few μm. Furthermore, due to the low processing accuracy of the single crystal silicon substrate 110, it is not easy to form a recess 100a that has a shape and area that precisely matches the shape and area of ​​the single crystal silicon substrate 110. Therefore, if the processes performed after forming the single crystal silicon film 116 are carried out using the alignment marker 102, the alignment accuracy in each process will decrease, which will lead to a decrease in the characteristics and yield of semiconductor elements and semiconductor devices. Therefore, as an optional step, an alignment marker 104 (see Figure 1), which is different from the alignment marker 102, may be formed simultaneously with or after the formation of the recess 100a, and the alignment marker 104 may be used to process the single-crystal silicon film 116 or perform subsequent processes.

[0031] The alignment marker 104 may be formed by wet etching or by laser irradiation. Alternatively, the alignment marker 104 may be formed by a combination of laser irradiation and wet etching. In wet etching, as shown in Figure 14, a resist 124 is formed on the main surface 100b and exposure is performed through a photomask 128. If the resist 124 is negative type, a light-shielding portion is provided in the photomask 128 that overlaps with the area where the recess 100a and the alignment marker 104 are formed. If the resist 124 is positive type, a light-transmitting portion is provided in the photomask 128 that overlaps with the area where the alignment marker 104 is formed. After exposure, the resist 124 is developed to obtain a resist mask 126. After this, etching is performed with an etchant containing hydrofluoric acid, which removes the portion exposed from the resist mask 126, and the recess 100a and the alignment marker 104 are formed simultaneously. Since the positions of the recess 100a and the alignment marker 104 are determined by the photomask 128, even if the photomask 128 is misaligned, it does not affect the positional relationship between the recess 100a and the alignment marker 104, that is, the positional relationship between the single-crystal silicon film 116 formed in the recess 100a and the alignment marker 104.

[0032] When using a laser, as shown in Figure 15, after forming a recess 100a, laser light is irradiated onto the main surface 100b. Examples of lasers include femitosecond lasers. As a result, the irradiated portion is altered, and a modified layer 100f is generated. Since the modified layer 100f has different optical properties, such as refractive index, from other parts, it can be used as an alignment marker 104 by irradiating it with polarized light and reading the reflected light. Alternatively, the modified layer 100f may be removed using an etchant such as an aqueous potassium hydroxide solution, and this portion may be used as an alignment marker 104. The laser alignment during laser irradiation is performed with the recess 100a as the reference. Therefore, any misalignment during the formation of the recess 100a does not affect the relative relationship between the recess 100a and the irradiated position of the laser light. Consequently, even if a misalignment occurs during the formation of the recess 100a, the positional relationship between the single-crystal silicon film 116 and the alignment marker 104 can be maintained.

[0033] The method described above makes it possible to eliminate or significantly reduce misalignment between the recess 100a and the alignment marker 104. As a result, the alignment marker 104 can be precisely positioned relative to the single-crystal silicon film 116 formed in the recess 100a, enabling high-precision processing of the single-crystal silicon film 116 and, furthermore, allowing subsequent processes to be carried out with high precision.

[0034] (2) Protective film and insulating film As shown in Figure 16, a protective film 106 containing or made of aluminum nitride may be formed on the surface of the glass substrate 100 after the recess 100a has been formed. The protective film 106 may be formed over the entire surface of the glass substrate 100, or it may be selectively formed on the main surface 100b, bottom surface 100c, side wall 100d, and inclined surface 100e (see Figures 2 and 3). As described above, cleaning may be performed using a cleaning solution containing hydrofluoric acid after the formation of the single crystal silicon film 116, but by forming the protective film 106, it is possible to prevent the glass substrate 100 from dissolving or deforming in this process.

[0035] Furthermore, the protective film 106 covering the recess 100a may be pre-treated. The pre-treatment is performed by irradiating the protective film 106 with ions (for example, argon ions, helium ions, etc.). By performing the pre-treatment, the surface of the protective film 106 is activated and aluminum dangling bonds are generated, so that Al-Si bonds are easily formed when bonding with the single-crystal silicon substrate 110. As a result, the glass substrate 100 and the single-crystal silicon substrate 110 can be bonded more firmly.

[0036] Similarly, an insulating film 118 containing or made of aluminum nitride may be formed on the single-crystal silicon substrate 110. The insulating film 118 may be provided over the entire surface of the single-crystal silicon substrate 110, as shown in Figure 17, or it may be selectively provided on the main surface 110a that is joined to the glass substrate 100. The insulating film 118 may be formed before ion implantation or after ion implantation. The thickness of the insulating film 118 is, for example, 16 nm or more and 110 nm or less. It is preferable that the insulating film 118 be provided such that its (0002) crystal plane constitutes the upper surface.

[0037] Furthermore, the insulating film 118 may be irradiated with argon ions to activate its surface. Surface activation generates aluminum dangling bonds, which facilitate the formation of Al-Si bonds when bonding with the glass substrate 100. As a result, the glass substrate 100 and the single-crystal silicon substrate 110 can be bonded more strongly. In addition, if a protective film 106 is formed on the glass substrate 100, Al-N bonds are easily formed between the glass substrate 100 and the protective film 106 when bonding, thereby increasing the bonding strength between the glass substrate 100 and the single-crystal silicon substrate 110.

[0038] 5. Modifications In the example described above, the shape of the recess 100a is rectangular, but the shape of the recess 100a is not limited to a rectangle, and various shapes can be adopted. For example, the recess 100a may have the shape of a circle (including a circle with a part cut off) or a polygon. In the case of a polygon, all sides may be of the same length, or at least one side may be of a different length from the other sides. Also, multiple recesses 100a may all be of the same shape, or some may have different shapes. For example, the recess 100a may be an equilateral triangle as shown in Figure 18, or a regular hexagon as shown in Figure 19. In the case of a regular hexagon, the single crystal silicon film 116 can be arranged at high density by forming the recesses 100a in a honeycomb pattern. To reiterate, the shape of the single crystal silicon substrate 110 is the same as or substantially the same as the recess 100a.

[0039] When the glass substrate 100 and the recess 100a are square or rectangular, as shown in Figure 1, one side of the recess 100a may be parallel to one side of the glass substrate 100. However, as shown in Figure 20, the recess 100a may be positioned such that all sides of the recess 100a are inclined from all sides of the glass substrate 100. In this case, by using a single-crystal silicon substrate 110 whose upper surface is composed of the (100) crystal plane of single-crystal silicon, has a square or rectangular shape, and whose

[001] crystal axis and

[010] crystal axis are parallel to the sides of the square or rectangle, these crystal axes can be positioned in a direction inclined from the sides of the glass substrate 100 (Figure 20). By adopting this arrangement, the

[001] crystal axis and

[010] crystal axis can be controlled in any direction, and as will be described later, strain can be easily generated in the channel of a transistor equipped with a single-crystal silicon film 116. As shown in Figure 21, a single-crystal silicon substrate 110 may be used in which the sides of the square or rectangular recess 100a are arranged parallel to the sides of the square or rectangular glass substrate 100, the upper surface is composed of the (100) crystal plane of single-crystal silicon, the substrate has a square or rectangular shape, and the

[001] crystal axis and

[010] crystal axis are tilted from the sides of the square or rectangle. A transistor with channel strain can be easily realized using such a single-crystal silicon substrate 110.

[0040] As described above, in the semiconductor device manufacturing method according to the embodiment of the present invention, a recess 100a is formed in the glass substrate 100, and a single-crystal silicon substrate 110 is placed in the recess 100a to bond the glass substrate 100 and the single-crystal silicon substrate 110. Therefore, the single-crystal silicon substrate 110 can be placed on the glass substrate 100 with high alignment accuracy. As a result, the single-crystal silicon film 116 formed by peeling off the single-crystal silicon substrate 110 can be accurately placed on the glass substrate 100. Due to these features, a decrease in the characteristics and manufacturing yield of semiconductor elements and semiconductor devices caused by misalignment is suppressed. Therefore, by applying the embodiment of the present invention, semiconductor elements and semiconductor devices with superior characteristics compared to semiconductor elements and semiconductor devices that utilize the characteristics of amorphous silicon films or polycrystalline silicon films can be manufactured at low cost.

[0041] <Second Embodiment> There are no restrictions on the type, structure, or function of the semiconductor element according to the embodiment of the present invention. Here, a transistor is given as an example of a semiconductor element, and its manufacturing method will be described. This transistor can be applied to various semiconductor devices such as display devices, lighting devices, radio wave reflectors, electrowetting devices, and sensors. In the following description, the structure of a display device and its manufacturing method will also be described as a semiconductor device on which the transistor is mounted. Descriptions of configurations that are the same as or similar to those described in the first embodiment may be omitted.

[0042] 1. Configuration of the Display Device Figure 22 shows a schematic top view of a display device 130, which is an example of a semiconductor device according to an embodiment of the present invention. The display device 130 comprises an amorphous glass substrate 100, on which a plurality of pixels 132, drive circuits for driving the plurality of pixels 132 (scan line drive circuit 134, signal line drive circuit 136), a plurality of terminals 138, etc. are formed. The terminals 138 are electrically connected to the scan line drive circuit 134 and the signal line drive circuit 136. In addition to a power supply, control signals for driving the display device 130 are input to the scan line drive circuit 134 and the signal line drive circuit 136 from an external circuit (not shown) via the terminals 138. The scan line drive circuit 134 and the signal line drive circuit 136 generate various signals (gate signals, video signals, reset signals, initialization signals, etc.) for driving the pixels 132 based on the control signals and supply them to the pixels 132. As a result, an image corresponding to the control signals can be reproduced by the plurality of pixels 132. The transistors according to the embodiment of the present invention may be incorporated into the drive circuit, or / or into each pixel 132.

[0043] 2. Method for Manufacturing a Display Device As described in the first embodiment, first, a recess 100a is formed in the glass substrate 100. Specifically, as shown in Figure 23, the recess 100a is formed in the region where the plurality of pixels 132 described above, as well as the scan line drive circuit 134, the signal line drive circuit 136, and the plurality of terminals 138 are provided. In other words, the scan line drive circuit 134, the signal line drive circuit 136, and the plurality of terminals 138 are provided in the recess 100a. After that, an undercoat, not shown in Figure 23, is provided so as to cover at least the entire recess 100a. The undercoat is provided to prevent impurities such as alkali metals and alkaline earth metals contained in the glass substrate 100 from penetrating the single-crystal silicon film 116. The undercoat is composed of one or more films containing silicon-containing inorganic compounds such as silicon oxide and silicon nitride, and can be formed using sputtering or CVD methods. Next, the single-crystal silicon substrate 110 is placed in the recess 100a via an undercoat, and the glass substrate 100 and the single-crystal silicon substrate 110 are bonded together. Subsequently, the single-crystal silicon substrate 110 is peeled off according to the process described in the first embodiment, thereby forming a single-crystal silicon film 116 in the recess 100a (Figure 24).

[0044] Subsequently, taking into consideration the arrangement of the scan line drive circuit 134, the signal line drive circuit 136, the pixels 132, and the structure and arrangement of the transistors provided therein, the single-crystal silicon film 116 is divided into multiple single-crystal silicon films 116 by etching. Figure 25 is a schematic end view including the undercoat 140 on the glass substrate 100, and one single-crystal silicon film 116 formed by etching and provided in contact with the undercoat 140.

[0045] Next, a gate insulating film 142 is formed to cover the single-crystal silicon film 116, and then a gate electrode 144 is formed that overlaps the single-crystal silicon film 116 via the gate insulating film 142. The gate insulating film 142 is one or more films containing silicon-containing inorganic compounds and can be formed by sputtering or CVD. The gate electrode 144 contains a metal or alloy thereof with a relatively high melting point, such as molybdenum, tungsten, tantalum, or titanium, and can be formed by sputtering or CVD. After this, the portion of the single-crystal silicon film 116 exposed from the gate electrode 144 may be subjected to heat treatment for doping and dopant activation to form a source / drain region 116b. The portion of the single-crystal silicon film 116 sandwiched between the source / drain region 116b functions as the channel 116a of the transistor 160. Although not shown, a low-concentration doped region with a lower dopant concentration compared to the source / drain region 116b may be formed between the source / drain region 116b and the channel 116a.

[0046] Subsequently, an interlayer insulating film 146 is formed to cover the gate electrode 144 (Figure 26). The interlayer insulating film 146 can be formed in the same manner as the undercoat 140. After this, an opening is formed in the gate insulating film 142 and the interlayer insulating film 146 that reaches the single-crystal silicon film 116, and then terminals 148 and 150 are formed to cover this opening. This electrically connects terminals 148 and 150 to the single-crystal silicon film 116, and the transistor 160 is fabricated. Terminals 148 and 150 contain metals such as molybdenum, tungsten, tantalum, titanium, aluminum, copper, or alloys thereof, and are formed by applying sputtering or CVD methods. Terminals 148 and 150 function as the source electrode and drain electrode of the transistor 160.

[0047] After this, a planarization film 162 is formed to absorb the irregularities caused by the transistor 160 and provide a flat surface. The planarization film 162 can be formed using a polymer material such as polyimide, polyamide, acrylic resin, silicone resin, or epoxy resin, by a wet deposition method such as spin coating, inkjet, or spray coating. The planarization film 162 is provided with an opening 162a that exposes one terminal (in this case, terminal 150), and an electrical connection to the display element is made through this opening.

[0048] As the display elements, known liquid crystal elements and electroluminescent elements (organic electroluminescent elements, inorganic electroluminescent elements) can be used, so a detailed explanation will be omitted. When using liquid crystal elements, as shown in the equivalent circuit diagram of Figure 28, each pixel 132 is configured to have a switching transistor 186, a capacitive element 188, and a liquid crystal element 190. The gate electrode of the switching transistor 186 is electrically connected to the gate line 182 extending from the scan line driving circuit 134. One terminal of the switching transistor 186 is electrically connected to the signal line 180 extending from the signal line driving circuit 136, and the other terminal is electrically connected to one electrode of the capacitive element 188 and one electrode of the liquid crystal element 190 (pixel electrode). The other electrode of the capacitive element 188 and the other electrode of the liquid crystal element 190 (common electrode) are electrically connected to a common wiring 184 to which a constant potential is supplied. Transistor 160 can be incorporated into each pixel 132 as this switching transistor 186. This makes it possible to provide a display device 130 capable of high-speed response.

[0049] When using an electroluminescent element, as shown in the equivalent circuit diagram of Figure 29, each pixel 132 is configured to have a switching transistor 208, a driving transistor 210, a capacitive element 212, and an electroluminescent element 214. The gate electrode of the switching transistor 208 is electrically connected to the gate line 202 extending from the scan line driving circuit 134. One terminal of the switching transistor 208 is electrically connected to the signal line 200 extending from the signal line driving circuit 136, and the other terminal is electrically connected to one electrode of the capacitive element 212 and the gate electrode of the driving transistor 210. One terminal of the driving transistor 210 is connected to the current supply line 206 to which a constant potential is supplied via terminal 138, and the other terminal is electrically connected to the other electrode of the capacitive element 212 and one electrode (pixel electrode or anode) of the electroluminescent element 214. The other electrode (counter electrode or cathode) of the electroluminescent element 214 is electrically connected to a common wiring 204 to which a constant potential lower than the potential applied to the current supply line 206 is supplied. The transistor 160 can be incorporated into each pixel 132 as either or both of the switching transistor 208 and the driving transistor 210. This makes it possible to provide a display device 130 that is capable of high-speed response and high-brightness display.

[0050] When a protective film 106 is formed on the glass substrate 100, and / or an insulating film 118 is formed on the single-crystal silicon substrate 110, the undercoat 140 is formed on the protective film 106 and / or the insulating film 118 (Figure 27). Since the protective film 106 and the insulating film 118 also function as an undercoat, a structure may be adopted in which the single-crystal silicon film 116 is in contact with the protective film 106 or the insulating film 118 without providing an undercoat 140.

[0051] As described above, the crystal axis of the single-crystal silicon substrate 110 bonded to the glass substrate 100 can be controlled in any direction. Therefore, by appropriately setting the arrangement of the recess 100a, the crystal axis of the single-crystal silicon substrate 110, and the arrangement of the gate electrode 144 and terminals 148 and 150, the

[001] crystal axis and

[010] crystal axis of the single-crystal silicon can be tilted at an angle θ (0° < θ < 90°) with respect to the channel length direction (CD), as shown in Figure 30. In the fabrication of the transistor 160, heat treatment such as dopant activation is performed, and due to the large difference in the coefficient of thermal expansion between the gate electrode 144 and the single-crystal silicon film 116, a large tensile strain is generated in the single-crystal silicon film 116. At this time, by tilting the

[001] crystal axis and

[010] crystal axis with respect to the channel length direction, a larger tensile strain can be generated in the single-crystal silicon film 116 along the

[001] crystal axis and

[010] crystal axis. Therefore, the transistor 160 functions as a so-called distortion transistor, enabling it to achieve extremely high on-current and mobility. By utilizing such a distortion transistor 160 in channel 116a, it becomes possible to provide a high-performance display device 130 capable of high-speed operation.

[0052] <Third Embodiment> In this embodiment, an electroluminescent element is given as an example of a semiconductor element including a single-crystal silicon film 116, and its manufacturing method will be described. A display device on which the electroluminescent element is mounted and its manufacturing method will also be described. Configurations that are the same as or similar to those described in the first and second embodiments may be omitted from the description.

[0053] The electroluminescent element according to this embodiment is a so-called inorganic electroluminescent element (LED) and includes an electroluminescent layer containing a compound semiconductor. In the fabrication of the electroluminescent element, first, as described in the first embodiment, a single-crystal silicon film 116 is formed on a glass substrate 100. At this time, it is preferable to use a single-crystal silicon substrate 110 whose upper surface is composed of a (111) crystal plane. This makes it possible to configure the upper surface of the single-crystal silicon film 116 (the surface on which the electroluminescent layer is formed) as a (111) crystal plane of single-crystal silicon.

[0054] Subsequently, a buffer layer 220 is formed on the single-crystal silicon film 116 formed in the recess 100a (Figure 31). The buffer layer may also be formed by applying CVD or sputtering as appropriate. The buffer layer 220 contributes to promoting the crystallization of the electroluminescent layer provided thereon and improves the adhesion between the electroluminescent layer and the single-crystal silicon film 116. This prevents deformation (warping) of the glass substrate 100 under the manufacturing conditions of the electroluminescent element, and effectively suppresses peeling of the electroluminescent layer and the occurrence of cracks and crystal defects in the electroluminescent layer.

[0055] The buffer layer 220 may include an insulating material and / or a conductive material having a hexagonal close-packed structure, a face-centered cubic structure, or a structure similar thereto. Here, a hexagonal close-packed structure or a structure similar to a face-centered cubic structure includes a crystal structure in which the c axis is not orthogonal to the a axis and b axis. Therefore, in this structure, the buffer layer 220 is oriented such that its c axis is parallel to the normal of the single-crystal silicon film 116. Furthermore, the buffer layer 220 having a face-centered cubic structure or a structure similar thereto has its upper surface as a crystal plane oriented in the (0001) direction. As described above, it is preferable that the upper surface of the single-crystal silicon film 116 is composed of the (111) crystal plane of the single-crystal silicon. In this case, due to the similarity of the crystal lattices of the buffer layer 220 and the single-crystal silicon film 116, the crystallinity of the buffer layer 220 can also be improved. Furthermore, the compound semiconductor contained in the electroluminescent layer, such as a gallium nitride-based semiconductor, adopts a wurtzite-type structure and undergoes crystal growth in the c-axis direction to minimize its surface energy. Therefore, by forming the electroluminescent layer containing the compound semiconductor on the buffer layer 220 with improved crystallinity, crystal growth in the c-axis direction of the functional layer is further promoted, resulting in the electroluminescent layer exhibiting extremely high crystallinity and having few crystal defects. These characteristics contribute to further improvement of the characteristics of the electroluminescent element (luminescent efficiency and reliability).

[0056] The buffer layer 220 may contain metal nitrides such as indium aluminum nitride, aluminum nitride, aluminum oxynitride, indium aluminum nitride, and gallium nitride, or metal oxides such as aluminum oxide. By using such materials, an insulating buffer layer 220 can be formed. In particular, by using aluminum nitride or indium aluminum nitride, the misalignment of the lattice constant between the buffer layer 220 and the electroluminescent layer in contact can be reduced, thereby promoting a more effective c-axis orientation of the electroluminescent layer. Alternatively, the buffer layer 220 may contain metals such as titanium, aluminum, silver, nickel, copper, strontium, rhodium, palladium, iridium, platinum, and gold.

[0057] To more effectively grow the electroluminescent layer in the c-axis direction, the buffer layer 220 preferably has high surface flatness. Specifically, the arithmetic mean roughness (Ra) of the surface of the buffer layer 220 is preferably less than 2.3 nm. Also, the root mean square roughness (Rq) of the surface of the buffer layer 220 is preferably less than 2.9 nm. To obtain high surface flatness, the thickness of the buffer layer 220 is preferably 110 nm or less, for example, the buffer layer 220 is formed with a thickness of 16 nm or more and 110 nm or less.

[0058] The buffer layer 220 may have a single-layer structure or a multilayer structure. Although not shown, preferably the buffer layer 220 is composed of a first layer containing or made of aluminum, and a second layer provided on the first layer, in contact with the first layer, and containing or made of aluminum nitride. The thickness of the first layer is, for example, 1 nm to 10 nm. The second layer is thicker than the first layer, and its thickness is, for example, 15 nm to 100 nm. By adopting such a multilayer structure, aluminum combines with oxygen present on the surface of the single-crystal silicon film 116, forming stable aluminum oxide. The formed aluminum oxide prevents the diffusion of oxygen during the formation of the second layer, thereby suppressing the formation of aluminum oxynitride.

[0059] Subsequently, an electroluminescent layer containing a compound semiconductor is formed on the buffer layer 220. There are no restrictions on the configuration of the electroluminescent layer; for example, a structure in which an electron injection layer 222, an emissive layer 224, and a hole injection layer 226 are stacked in this order can be adopted (Figure 31). Although not shown, an electron transport layer may be provided between the electron injection layer 222 and the emissive layer 224, and a hole transport layer may be provided between the emissive layer 224 and the hole injection layer 226. Examples of compound semiconductors include those containing aluminum, gallium, and / or indium, as well as nitrogen, phosphorus, and / or arsenic. Typically, gallium-based materials are used. For example, gallium nitride-based materials such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), and indium gallium nitride (InGaN), and gallium phosphide-based materials such as gallium phosphide (GaP) and aluminum indium gallium phosphide (AlGaInP) are used. The electron injection layer 222 and / or hole injection layer 226, which are carrier injection layers, may further contain dopants. Examples of dopants include elements such as silicon, germanium, magnesium, zinc, cadmium, and beryllium. By adding these elements, it becomes possible to control the valence electrons of each layer, enabling control of the band gap and the imparting of p-type or n-type conductivity.

[0060] The electron injection layer 222 uses a compound semiconductor with n-type conductivity, and the hole injection layer 226 uses a compound semiconductor with p-type conductivity. For example, the electron injection layer 222 can be configured to contain n-type gallium nitride or n-type aluminum gallium nitride, and the hole injection layer 226 can be configured to contain p-type aluminum gallium nitride or p-type gallium nitride. The electron injection layer 222 and the hole injection layer 226 may each have a single-layer structure or a stacked structure in which multiple layers are stacked.

[0061] The light-emitting layer 224 is configured to emit red light, green light, or blue light. Here, red light, green light, and blue light are emission exhibiting one or more emission peak wavelengths in the ranges of 630 nm to 760 nm, 500 nm to 620 nm, and 400 nm to 480 nm, respectively. The light-emitting layer 224 may have a single-layer structure or a multi-quantum well structure. A multi-quantum well structure is a structure in which multiple thin films with different band gaps and thicknesses of about 2 to 12 nm are alternately stacked. That is, in a multi-quantum well structure, multiple high-bandgap layers and low-bandgap layers are alternately stacked. Preferably, high-bandgap layers are provided at the top and bottom layers. Examples of multi-quantum well structures include alternating laminates of indium gallium nitride and gallium nitride, alternating laminates of indium gallium phosphide (GaInAsP) and indium phosphide (InP), and alternating laminates of aluminum indium arsenide (AlInAs) and indium gallium arsenide (InGaAs). In the case of alternating laminates of indium gallium nitride and gallium nitride, the preferred composition of indium is 35% by mass or less.

[0062] The size of the electroluminescent layer, that is, the area of ​​the electroluminescent layer on a plane parallel to the upper surface of the single-crystal silicon film 116, can also be arbitrarily set. A preferred area of ​​the electroluminescent layer is, for example, 2 × 10⁻⁶. ２ μm ２ The above 2 x 10 ５ μm ２ The following or 1 x 10 ３ μm ２ The above 2 x 10 ５ μm ２ The following applies:

[0063] The electroluminescent layer may be formed using a sputtering method. For example, each layer constituting the electroluminescent layer may be formed by sputtering a target containing a compound semiconductor film, which is the material contained therein, with argon. If each layer contains a compound semiconductor containing multiple metal elements, each layer may be formed by co-sputtering using multiple targets, each containing a single type of compound semiconductor, or each layer may be formed by sputtering a target containing a compound semiconductor containing multiple metal elements. Alternatively, each layer may be formed by reactive sputtering or reactive co-sputtering using a target containing a metal (a zero-valent metal) and nitrogen as the reactive gas. For example, a layer containing indium gallium nitride can be obtained by co-sputtering with nitrogen using a target containing metallic gallium and a target containing metallic indium. If each layer contains a dopant, a corresponding target containing the dopant may be used.

[0064] A heat treatment to activate the dopant may be performed after each layer is formed, or after the electroluminescent layer has been formed. The heat treatment may be performed, for example, at a temperature of 500°C to 700°C for 3 minutes to 60 minutes.

[0065] Compared to methods using CVD, when forming an electroluminescent layer using the sputtering method, the high temperatures required for epitaxial growth are not necessary, and the electroluminescent layer can be formed at a temperature below the strain point or glass transition temperature of the glass substrate 100. Therefore, the electroluminescent layer can be formed without deformation of the glass substrate 100. In addition, since the electroluminescent layer is formed on the buffer layer 220, the crystallization of each layer is promoted. For this reason, even when applying the sputtering method, which is performed at relatively low temperatures, it is possible to form an electroluminescent layer with few crystal defects.

[0066] As shown in Figure 31, the electroluminescent layer is provided over almost the entire surface of the buffer layer 220. Therefore, when forming multiple light-emitting elements using a single glass substrate 100, etching is performed to isolate the elements. The etching may be dry etching such as plasma etching, or wet etching. In the latter case, an etching method called photoelectrochemical etching (PEC etching) may be used. In this case, after forming a hard mask (not shown in Figure 31) containing a metal such as titanium, gold, or platinum on the electroluminescent layer, the glass substrate 100, on which the electroluminescent layer has been formed, is irradiated with light with an energy greater than the band gap of the electroluminescent layer (for example, light with a wavelength of less than 365 nm) in an electrolyte containing alkali metal hydroxide. This causes the electroluminescent layer to be anodized using holes emitted from the electroluminescent layer. By removing the generated oxide by wet etching, the portion exposed from the metal mask can be removed. Alternatively, contactless PEC etching may be used. In this method, an electrolyte containing an aqueous solution of potassium peroxodisulfate is used, and ultraviolet light with a wavelength of 310 nm or less is irradiated onto the electrolyte to generate sulfuric acid radicals, which act as an oxidizing agent. Of the electrons and holes generated by the light irradiation of the electroluminescent layer, the electrons are consumed by the sulfuric acid radicals, and the excess holes can oxidize the electroluminescent layer. Contactless PEC etching eliminates the need for current flow for anodic oxidation, making etching simpler. Furthermore, since etching damage caused by dry etching (such as the generation of crystal defects) can be avoided, the electroluminescent layer can be processed and molded while maintaining high crystallinity, and device isolation can be performed (Figure 32).

[0067] After separating the elements by etching, etching is performed to form the cathode. Specifically, as shown in Figure 33, a mask (hard mask or resist mask) 240 is provided to cover a part of each electroluminescent layer, and layers other than the electron injection layer 222 (hole injection layer 226 and light-emitting layer 224) are partially etched. This allows the electron injection layer 222 to be exposed from the other layers, as shown in Figure 34. Although not shown, a part of the electron injection layer 222 may also be etched at this time. This etching can be dry etching or wet etching. In the latter case, a hard mask containing a metal such as titanium, gold, or platinum may be used as the mask 240, and the electroluminescent layer may be etched by PEC etching or contactless PEC etching. As described above, by using PEC etching or contactless PEC etching, precise etching can be performed on the electroluminescent layer while suppressing etching damage to the electroluminescent layer that may occur during dry etching.

[0068] After etching the electroluminescent layer to remove the mask 240, the anode 228 and cathode 230 are formed (Figure 35). The anode 228 and cathode 230 can also be formed using sputtering, CVD, vapor deposition, or other appropriate methods. The anode 228 is positioned in contact with the hole injection layer 226. On the other hand, the cathode 230 is positioned in contact with the electron injection layer 222. The electroluminescent element 250 is manufactured through the above process.

[0069] As an optional step, after forming the anode 228 and cathode 230, a passivation film 232 may be formed to cover them (Figure 36). The passivation film 232 contains a silicon-containing inorganic compound such as silicon nitride and can be formed using CVD, sputtering, or vapor deposition. After this, the portion of the passivation film 232 that overlaps with the anode 228 and cathode 230 is removed by etching.

[0070] A display device can be manufactured by providing an electroluminescent element 250 in the pixels of a display device. For example, a display device can be manufactured by connecting an anode 228 to a drive transistor 210 provided in pixel 132 of the display device 130 shown in the second embodiment, and electrically connecting a cathode 230 to a common wiring 204. However, in a display device in which an electroluminescent element 250 is arranged, the semiconductor film constituting the drive transistor 210 and the switching transistor 208 does not have to be a single-crystal silicon film. For example, the electroluminescent element 250 may be arranged in a pixel where a transistor containing amorphous silicon or polycrystalline silicon, or a transistor containing an oxide semiconductor in its channel, is arranged.

[0071] As described above, when manufacturing an electroluminescent element 250 by applying an embodiment of the present invention, a buffer layer 220 can be formed on a single-crystal silicon film 116 whose upper surface is composed of a (111) crystal plane of single-crystal silicon, and an electroluminescent layer can be formed on top of the buffer layer 220. As a result, since the electroluminescent layer is formed on the buffer layer 220 which has a highly crystalline (001) crystal plane on its upper surface, even if the electroluminescent layer is formed by sputtering, the electroluminescent layer exhibits extremely high crystallinity and has few crystal defects. Therefore, an electroluminescent element with excellent properties can be provided. Accordingly, by using the electroluminescent element 250, it is possible to manufacture a display device with excellent properties.

[0072] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on these embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0073] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0074] 100: Glass substrate, 100a: Recess, 100b: Main surface, 100c: Bottom surface, 100d: Side wall, 100e: Inclined surface, 100f: Modified layer, 102: Alignment marker, 104: Alignment marker, 106: Protective film, 110: Single crystal silicon substrate, 110a: Main surface, 110b: Main surface, 112: Embrittlement layer, 114: Part, 116: Single crystal silicon film, 116a: Channel, 116b: Source / drain region, 118: Insulating film, 120: Electrode, 122: Electrode, 124: Resist, 126: Resist mask, 128: Photomask, 130: Display device, 132: Pixel, 134: Scan line driving circuit, 136: Signal line driving circuit, 138: Terminal, 140: Undercoat, 142: G 144: Interlayer insulating film, 146: Gate electrode, 148: Terminal, 150: Terminal, 160: Transistor, 162: Planarization film, 162a: Aperture, 180: Signal line, 182: Gate line, 184: Common wiring, 186: Switching transistor, 188: Capacitive element, 190: Liquid crystal element, 200: Signal line, 202: Gate line, 204: Common wiring, 206: Current supply line, 208: Switching transistor, 210: Drive transistor, 212: Capacitive element, 214: Electroluminescent element, 220: Buffer layer, 222: Electron injection layer, 224: Light-emitting layer, 226: Hole injection layer, 228: Anode, 230: Cathode, 232: Passivation film, 240: Mask, 250: Electroluminescent element

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a recess with a flat bottom surface in a glass substrate; forming an embrittlement layer within a single-crystal silicon substrate by ion irradiation of a first main surface of a single-crystal silicon substrate; joining the glass substrate and the single-crystal silicon substrate by arranging the single-crystal silicon substrate in the recess such that the portion between the embrittlement layer and the first main surface is sandwiched between the embrittlement layer and the glass substrate; and forming the portion as a single-crystal silicon film within the recess by peeling the single-crystal silicon substrate from the glass substrate.

2. The manufacturing method according to claim 1, wherein the shape and area of ​​the bottom surface are the same as the shape and area of ​​the first main surface of the single crystal silicon substrate.

3. The manufacturing method according to claim 1, wherein the depth of the recess is 0.1% or more and 10% or less of the thickness of the glass substrate.

4. The manufacturing method according to claim 1, wherein the thickness of the single-crystal silicon film is 0.01% or more and 1% or less of the thickness of the glass substrate.

5. The manufacturing method according to claim 1, wherein the thickness of the single-crystal silicon film is 10 nm or more and 500 nm or less.

6. The manufacturing method according to claim 1, wherein the depth of the recess is greater than the thickness of the single-crystal silicon film.

7. The manufacturing method according to claim 1, further comprising chamfering at least a portion of the recess.

8. The manufacturing method according to claim 1, further comprising forming a protective film on the surface of the glass substrate in which the recess is formed, after the recess is formed and before the single crystal silicon substrate is placed in the recess, wherein the protective film comprises aluminum nitride.

9. The manufacturing method according to claim 8, further comprising irradiating the protective film with argon ions.

10. The manufacturing method according to claim 1, further comprising forming an insulating film on the first main surface of the single crystal silicon substrate before placing the single crystal silicon substrate into the recess, wherein the insulating film comprises aluminum nitride.

11. The manufacturing method according to claim 10, further comprising irradiating the insulating film with argon ions.

12. The manufacturing method according to claim 1, wherein the first main surface of the single-crystal silicon substrate is composed of a (111) crystal plane or a (100) crystal plane of the single-crystal silicon.

13. The manufacturing method according to claim 1, further comprising treating the single-crystal silicon film with a cleaning solution containing hydrofluoric acid.

14. The manufacturing method according to claim 1, further comprising processing the single-crystal silicon film into a plurality of single-crystal silicon films, forming a gate insulating film on the plurality of single-crystal silicon films, forming a plurality of gate electrodes on the gate insulating film that overlap with the plurality of single-crystal silicon films, forming an interlayer insulating film on the plurality of gate electrodes, and forming a plurality of pairs of terminals that are electrically connected to the plurality of single-crystal silicon films, respectively, to produce a plurality of transistors.

15. The manufacturing method according to claim 14, further comprising creating a drive circuit for controlling the plurality of transistors on the bottom surface of the recess.

16. The manufacturing method according to claim 1, further comprising forming a buffer layer on the single-crystal silicon film, forming an electroluminescent layer containing a compound semiconductor on the buffer layer, and forming a pair of electrodes electrically connected to the electroluminescent layer, wherein the buffer layer contains aluminum nitride.

17. The manufacturing method according to claim 1, further comprising forming the recess and simultaneously forming an alignment marker on the glass substrate.

18. The manufacturing method according to claim 1, further comprising forming an alignment marker on the glass substrate after forming the recess.

19. A semiconductor device comprising a glass substrate having at least one recess with a flat bottom surface, and a semiconductor element on the glass substrate, wherein the semiconductor element includes a single-crystal silicon film located within the recess.

20. The semiconductor device according to claim 19, wherein the semiconductor element is a transistor or a light-emitting element.

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