Method and system with real-time stimulation artifact removal for closed-loop neuromodulations

Abstract

A system and method are disclosed that supports closed-loop neuromodulation while avoiding stimulation artifact complications. Specifically, the system employs front-end spatial filtering, which removes stimulation artifacts in real time. It preserves the evoked neural responses by considering the differences in propagation speed and the spatial distribution and correlation of artifact signals. This technology can be used in various medical applications that benefit from operating in a closed-loop manner, such as pain management, motor function restoration, retinal prostheses, gastrointestinal implants, vagus nerve stimulation, sciatic nerve stimulation, and cortical neuromodulation.

Description

METHOD AND SYSTEM WITH REAL-TIME STIMULATION ARTIFACT REMOVAL FOR CLOSED-LOOP NEUROMODULATIONSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to, and the benefit of, U.S. provisional patent application serial number 63 / 702,568 filed on October 2, 2024, incorporated herein by reference in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under NS118301 awarded by the National Institutes of Health. The government has certain rights in the invention.NOTICE OF MATERIAL SUBJECT TO COPYRIGHT PROTECTION

[0003] A portion of the material in this patent document may be subject to copyright protection under the copyright laws of the United States and of other countries. The owner of the copyright rights has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the United States Patent and Trademark Office publicly available file or records, but otherwise reserves all copyright rights whatsoever. The copyright owner does not hereby waive any of its rights to have this patent document maintained in secrecy, including without limitation its rights pursuant to 37 C. F. R. § 1.14.BACKGROUND

[0004] 1. Technical Field

[0005] The technology of this disclosure pertains generally to closed-loop medical neuromodulation, and more particularly to removing stimulation artifacts in real time.

[0006] 2. Background Discussion

[0007] Multiple neuroscience and neuromodulation applications utilize evokedUC-2024-010-3-LA-PCT -1-neural responses, such as evoked Compound Action Potentials (eCAPs) for protocol optimization in a closed-loop or human-in-the-loop manner. Due to the interconnected nature of neurons, eCAPs influence intrinsic neural activities across higher-order neural structures beyond the immediate vicinity of the electrodes. These eCAPs are a composite of responses from various neurons, each with distinct characteristics in shape, propagation speed and direction. Recording eCAPs offers immediate observation of brain reaction, enabling fine-tuning of the stimulation protocol.

[0008] However, the presence of artifact signals complicate eCAP recording and impact the ability to make proper stimulation adjustments.

[0009] Accordingly, a need exists for addressing these artifact complications in real time, so that accurate neuromodulation can be performed. The present disclosure fulfills that need and provides additional benefits over existing systems.BRIEF SUMMARY

[0010] A front-end spatial filtering architecture is disclosed, sometimes referred to herein for short as a Spatial-Method Artifact Removal Technology (SMART). By way of example, and not of limitation, this disclosure presents an apparatus, system and method that supports closed-loop neuromodulation while avoiding stimulation artifact complications. The system employs frontend spatial filtering, which removes stimulation artifacts in real time. It preserves the evoked neural responses by considering the differences in propagation speed and the spatial distribution and correlation of artifact signals. This technology can be used in various medical applications that benefit from operating in a closed-loop manner, such as pain management, motor function restoration, retinal prostheses, gastrointestinal implants, vagus nerve stimulation, sciatic nerve stimulation, and cortical neuromodulation.

[0011] Further aspects of the technology described herein will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the technology without placing limitations thereon.UC-2024-010-3-LA-PCT -2-BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The technology described herein will be more fully understood by reference to the following drawings which are for illustrative purposes only:

[0013] FIG. 1 is a block diagram of a front-end artifact cancellation apparatus, according to at least one embodiment of the present disclosure.

[0014] FIG. 2A and FIG. 2B illustrate simulation artifact characterization setup, and a graph of an artifact recorded from different locations, according to at least one embodiment of the present disclosure.

[0015] FIG. 3A and FIG. 3B are a block diagram and waveforms conceptualizing the operation of the front-end spatial filtering recording system, according to at least one embodiment of the present disclosure.

[0016] FIG. 4 is an on-line extraction of artifact template through spatial averaging, according to at least one embodiment of the present disclosure.

[0017] FIG. 5A and FIG. 5B is a schematic of the front-end spatial filtering recording system, according to at least one embodiment of the present disclosure.

[0018] FIG. 6 is a schematic of one neuron recording channel with two amplification stage, according to at least one embodiment of the present disclosure.

[0019] FIG. 7 is a schematic for a CAR and AFRR hardware circuit, according to at least one embodiment of the present disclosure.

[0020] FIG. 8 is a Bode plot of the transfer function of the front-end amplifier with tunable high pass corner for fast settling, according to at least one embodiment of the present disclosure.

[0021] FIG. 9A and FIG. 9B is a plot of artifact rejection ratio (ARR), according to at least one embodiment of the present disclosure.

[0022] FIG. 10A through FIG. 10E are plots of various aspects of artifact removal, according to at least one embodiment of the present disclosure.

[0023] FIG. 11 is a schematic of an alternative implementation of an artifact removal system using two spatial reference points to perform adaptive operations, according to at least one embodiment of the present disclosure.

[0024] FIG. 12 is a block diagram of a system architecture which integrates the front-end spatial filtering recording system, stimulator, powerUC-2024-010-3-LA-PCT -3-management, and Wi-Fi communications, according to at least one embodiment of the present disclosure.

[0025] FIG. 13A and FIG. 13B are block diagrams of downlink and uplink configuration, according to at least one embodiment of the present disclosure.

[0026] FIG. 14 is a plot of a configuration for the stimulator SoC, according to at least one embodiment of the present disclosure.

[0027] FIG. 15 is a waveform diagram of NeuralKey controller dynamically adjusting the pulse location in each TITR window to independently configure stimulation frequency of each channel, according to at least one embodiment of the present disclosure.

[0028] FIG. 16 is a plot of measurement results of four independent channel firing at four different periods, according to at least one embodiment of the present disclosure.

[0029] FIG. 17 is a plot of measurement results on four channels all firing stimulus with exponentially randomized inter-arrival time, according to at least one embodiment of the present disclosure.

[0030] FIG. 18 is a plot of measured results on four channel burst stimulation, according to at least one embodiment of the present disclosure.

[0031] FIG. 19 is a waveform diagram of NeuralKey stimulator delivering arbitrary stimulations by combining two interleaving channels, according to at least one embodiment of the present disclosure.

[0032] FIG. 20 is a plot of measured results on four stimulation outputs following a human EMG waveform, according to at least one embodiment of the present disclosure.DETAILED DESCRIPTION

[0033] 1. Introduction

[0034] Recent advancements in electrical stimulation within neuroscience have focused on enhancing our understanding of neural dynamics to improve treatments. Neural scientists use biphasic / monophasic current / voltage pulses to evoke compound action potentials. Due to the interconnected nature of neurons, evoked Compound Action Potentials (eCAPs) influence intrinsic neural activities across higher-order neural structures beyond the immediateUC-2024-010-3-LA-PCT -4-vicinity of the electrodes. These eCAPs are a composite of responses from various neurons, each with distinct characteristics in shape, propagation speed and direction. Recording eCAPs offers immediate observation of brain reaction, enabling fine-tuning of the stimulation protocol for restoring natural proprioception, increased neural specificity and reduced off-target effects.

[0035] Multiple neuroscience and neuromodulation applications utilize evoked neural responses, such as eCAPs for protocol optimization in a closed-loop or human-in-the-loop manner. The applications range from peripheral stimulation, cochlear implant, artificial retina, spinal cord stimulation to cortical and deep brain stimulations. As an example, eCAPs have been used in spinal cord stimulation for pain suppression. The effectiveness of open-loop treatment can be compromised by the patient’s movement. Postural change can cause the stimulation to become either too strong, thus causing discomfort when the electrode is pressed against the spinal cord, or too weak, reducing its effectiveness when the electrode is depressed away from the spinal cord. To address these challenges, eCAPs are used to deliver closed- loop stimulation in human trials. This closed-loop system records the amplitude of the eCAPs and adjusts the stimulation protocol to maintain therapeutic activation. A similar approach is also proposed in a cochlear implant, which monitors the eCAPs at the hearing-related neural structure and adjusts for stimulus strength, tone discrimination, and speed recognition.

[0036] FIG. 1 illustrates a conceptual diagram 10 of front-end artifact cancellation apparatus to overcome the challenges in eCAP recording and preventing stimulation contamination from stimulus artifacts. The figure depicts evoked response 14 to a sum junction 16 with a1 , outputting 17 to the front-end spatial filtering (e.g. SMART) cancellation system 12. An artifact source 18 is shown being averaged 20 with average outputs going to Weighting 22, and to perform a gradient descent operation (e.g., Least-Mean- Square (LMS)) operation 24 which also outputs to the Weighting function 22. Amplifier 26 receives a positive input 17 and weighting output 23 - with analog output directed to an analog-to-digital converter 28, with a digital output 30.

[0037] Typically, an eCAP occupies a frequency band ranging from 1 Hz toUC-2024-010-3-LA-PCT -5-about 10 kHz; and exhibits relatively small amplitudes, generally between 20 pV to 200 pV. Stimulation artifacts can range from 50 mV to as much as 1.5V, which is significantly larger than the neural signals themselves. Conventional neural recording systems are prone to be saturated by the artifacts and portions of the eCAP signals are lost during active stimulation. The signal loss reduces accuracy of the closed-loop strategy and requires artifact removal in a real-time manner to obtain proper operation. The stimulation artifacts induced during closed-loop operation are typically nonstationary and often spill into the signal band, making them challenging to filter out using conventional frequency-selective filters, such as band-pass filters or interleaved sampling.

[0038] To address this issue, various advanced technologies and architectures have been developed to record evoked neural responses. Among these, several Analog Front-End (AFE) architectures have been introduced to improve artifact tolerance, which can generally be classified as either wide dynamic range front-ends or digital-template cancellation.

[0039] The wide dynamic range topology, however, incurs trade-offs between tracking speed and resolution to maintain low power operation for implantable applications. This approach is particularly effective in voltage-mode stimulation, where the artifact appears as a voltage step. The front-end tracks at the edge of the artifact and records the signal when the artifact levels out. With separate tracking and signal acquisition phases in time, wide dynamic range systems can minimize signal loss, yet the signal is still subject to contamination if both tracking and acquisition phases cannot be clearly separated. However, in current-mode stimulation, the artifact presents as a Randel cell response. The lack of clear separation between the tracking and acquisition phases reduce resolution, causing signal loss.

[0040] Alternatively, digital-template cancellation methods operate by generating a counter template to subtract the artifact as a common mode signal. The generation of digital templates is not immediate and thus requires knowing the stimulus in advance for accommodating initiation, generation, and driver delay. Each recording system must actively coordinate with the stimulator to precisely deliver the digital template, which restricts the system'sUC-2024-010-3-LA-PCT -6-scalability. Additionally, digital templates take several seconds to adapt to protocol changes. In closed-loop operation, the stimulation protocol can shift significantly within sub-second intervals. The adaptation latency limits the method’s effectiveness in removing artifacts. Moreover, when stimulation is delivered in consecutive bursts, overlapping artifacts create complex patterns with durations that exceed the available tap length of the digital template.

[0041] Consequently, there remains a significant demand for technologies that can reliably recover evoked neural responses. Specifically, there are unmet needs for systems that can: (1 ) recover evoked neural responses during and after current-mode stimulation, (2) operate independently from the stimulator, (3) record evoked responses in a full-spectrum from 1 Hz to 10 kHz, and (4) that adapt and function effectively under varying stimulation protocols.

[0042] 2. Multi-Channel Recording System With Front-End Artifact Removal

[0043] 2.1. Operational Principal, Propagation Speed of Electrical Signals, and Spatial Correlation

[0044] Stimulation artifacts propagate in biological tissue as Electro-Magnetic (EM) waves. The speed of EM waves is frequency dependent and tissue dependent. In the frequency range between 1 Hz to 10 kHz, where the artifact directly contaminates the neural response, the EM wave travels at a speed around 3.5*107m / s in saline. However, the neural response has its characteristics speed based on their physical characteristics like the nerve thickness, myelin thickness, and channel characteristics (Table 1 ). The signal from the thickest A-alpha fiber travels the fastest at 50 to 100 m / s and for the thinnest unmyelinated C-fiber, the speed is 0.5 to 2.0 m / s.

[0045] This significant difference in propagation speed results in timing discrepancies at sensor front ends, with artifacts and various bioelectrical signals arriving at different times. Artifacts, traveling as EM waves, reach spatially separated channels almost simultaneously and remain spatially correlated across the body despite attenuation.

[0046] FIG. 2A and FIG. 2B illustrate a stimulation artifact characterization setup 50 (FIG. 2A), and depicts recorded artifacts from different locations 70 (FIG. 2B). Table 2 and Table 3 illustrate stimulation artifacts measured at different channels and their arithmetic average having high cross correlation.UC-2024-010-3-LA-PCT -7-The artifacts exhibit linear relationship with amplitude difference. Specifically, Table 2 indicates a cross correlation between channels and averages, while Table 3 depicts Amplitude differences for the same channels (r-GM, r-PL, I- PL, l-GM).

[0047] To characterize the spatial distribution of artifacts, the disclosed system shown in FIG. 2A delivers four electrical stimulations at the spinal L4, L5 section of a rat. All stimulation is cathodic first, biphasic 300 us pulse with no inter-pulse interval. Each stimulation (S1 through S4) is skewed by 500 us to isolate their respective artifact contribution. The amplitude of S1 to S4 are 500 uA, 400 uA, 300 uA, and 200 uA, respectively. In FIG. 2B four recordings are shown of artifacts at right Gluteus Maximus (r-GM), left Gluteus Maximus (l-GM), right peroneus longus (r-PL) and, left peroneus longus (l-PL). The stimulation artifact propagates along the multi-path heterogeneous medium that includes skin, fat, muscle, and bone. Artifacts are highly cross correlated with amplitude differences. In contrast to the correlation of artifacts, the temporal dispersion de-correlates the eCAPs readout from each front-end. The distinct correlation patterns between eCAPs and artifacts provides a robust basis for developing the front-end spatial filtering to recover evoked neural responses.

[0048] 2.2. System Operation

[0049] The front-end spatial filtering (e.g., SMART) removes artifacts by eliminating the correlated components across input channels while preserving the uncorrelated ones. Each input is represented as Xi = Sj + (2, where xtrepresents the channel input, strepresents the channel signal, atrepresents the artifact contaminating the i-th channel front-end. The front-end spatial filtering system weights an artifact reference (a) to generate cancellation signals (y , which are then subtracted from each channel inputs: s)(t) = xf(t) - yf(t)

[0050] The weight (<wf) is iteratively updated using a gradient descent operation (e.g., Least-Mean-Square (LMS)). The LMS algorithm uses theUC-2024-010-3-LA-PCT -8-channel output (s and the artifact reference (a) to update the weight according to the following formula:where A is the step size parameter.

[0051] Once gradient descent (e.g., LMS) converges, the front-end spatial filtering minimizes the artifact components in xtto avoid front-end saturation. SMART operates in the mixed-signal domain; in which update weighting is computed in the digital domain, while artifact removal and reference weighting occur in the analog domain. The artifact (a and the cancellation signal (y aligns in continuous time, allowing the system to function independently without requiring communication with the stimulator.

[0052] It should be noted that in physiological stimulation, parameters of the stimulus may be continuously changing depending on different experimental circumstances. Under the condition that the geometrical position of the electrode array remains the same, the weight will remain the same. Thus, the neural recording will not be disturbed because of the variations of the stimulation protocol.

[0053] It should be noted that in case the movement of an experimental subject changes the geometrical property of the electrode array, and the iterative calibration will adapt to the new configuration. It should also be noted that the disclosed apparatus can recover from sudden positional shifts of electrodes. Furthermore, the electrodes utilized may comprise one, two or three dimensional electrode arrays, which may include any desired combination of recording, reference and / or ground electrodes.

[0054] FIG. 3A and FIG. 3B illustrate an example 110, 140 of artifact removal according to the present disclosure. A response is summed with an artifact producing a corrupted electrode channel input (xi). The electrode input is corrected according to the disclosure by subtracting the artifacts in two stages.

[0055] Referring to FIG. 3A a channel input (x) 116 is shown being processed. The first stage involves Common Artifact Removal (CAR) 112 showing a first amplifier 118 receiving channel input 116 on a first input and an artifactUC-2024-010-3-LA-PCT -9-reference signal 120 on a negative feedback second input, toward eliminating artifacts common to the entire array to avoid saturation. The second stage performs Adaptive Feedforward Residual Removal (AFRR) exemplified with a second amplifier 122 receiving the output from the first amplifier, and a negative feedback signal 124 from the Weight determination 126, to adaptively remove the residual artifacts that arise from geometrical mismatch in the electrode array.

[0056] On the right side of FIG. 3A is seen an artifact reference 120 received by a weighting process 126, along with an update from update process 128 determined in response to receiving signal conversions from A / Ds 132a, 132b of channel output 134 and artifact reference 120, with the digital data used in an LMS determination 130.

[0057] By this two-stage artifact subtraction process from the electrode input, the neural signal can be ideally recovered. The first-stage amplification effectively increases the cancellation resolution of the analog weight circuit. In the disclosed system, the weight circuit comprises a resistive network with 256 quantized levels, at a full +100% to -100% range. Thus having 0.78% resolution. With a first stage gain of 25, the resolution is improved to 0.0312%. The pre-amplification stage increases the effective resolution, increasing the accuracy of artifact removal.

[0058] 2.3. Artifact Reference Selection and Common Average Template

[0059] The artifact reference plays a critical role in the front-end spatial filtering system. It serves two major functions: (1 ) it generate the cancellation signal, and (2) it determines whether a signal component within the input channel is an artifact based on its correlation with the reference. A poorly selected reference can lead to misclassification, either mistakenly identifying evoked responses as artifacts or allowing significant artifact content to pass through unfiltered.

[0060] An ideal reference should predominantly capture artifacts with minimal neural signal contamination. In biological systems, such a reference can be obtained from connective tissues adjacent to muscles when recording evoked Electromyography (EMG) signals. However, in cortical recording, the reference may need to be placed further away, such as on the Dural surface,UC-2024-010-3-LA-PCT -10-a bone screw on the skull, or other locations with minimal cortical activity. This spatial separation could lead to a significant difference in artifact strength, potentially saturating the first stage amplifier and making it challenging for the front-end spatial filtering system to effectively remove the artifact.

[0061] One alternative is to average the input channels to create a more effective artifact reference. This process preserves only the artifacts common across all channels while averaging out uncorrelated evoked responses:a represents the mean artifact shape across the selected channels and e is the attenuated signal component in the average template.FIG. 4 illustrates 150 on-line extraction of an artifact template through spatial averaging. The correlated artifact is extracted while the neural response is averaged out. The artifact template can be used as an artifact reference in case an ideal reference node is not accessible near the electrode array. The figure depicts a neuron 158, an artifact source 156, spaced electrodes 154 and obtaining a common average 152 toward obtaining an average template 160.The larger the number of channels included in the averaging process, the smaller 6 becomes. Previous analysis has shown that using a four channel common average significantly improves the Signal-to-Noise Ratio (SNR) of the average template, while expanding to a 16-channel average offers only a marginal SNR improvement.

[0062] The averaging method acquires the common artifact in real-time and in the analog domain. Compared with other approaches, the disclosed method avoids the digitization process during template generation. The disclosed method completely removes quantization error, digital latency, and the need of storing memory. The disclosed method also relaxes the synchronization requirement as the artifacts are generated in real-time and are intrinsically synchronized.

[0063] It is worth noting that the disclosed method acquires artifact templates in any shape, regardless of the type of stimulation protocol used to generateUC-2024-010-3-LA-PCT -1 1-them. This means that the method can process artifacts from different kinds (forms) of stimulation, such as random, periodic, biomimetic, burst, singlepulse, biphasic, or monophasic, and whether they are delivered in current or voltage mode.

[0064] 3. Circuit Implementation and Measurement Results

[0065] FIG. 5A and FIG. 5B illustrates the two stage front-end spatial filtering recording system 210 having multiple channels. The example depicts multiple channels 212a through 212n, which is exemplified in this example as having 8 channels. On each channel, the first stage 218 performs CAR and the second stage 220 performs AFRR. An on-chip average circuit extracts the common average of all 8 channel inputs for adaptive operation.

[0066] Each channel is an independent pseudo-differential channel that simultaneously records neural signals from all of the multiple (e.g., 8) distinct electrodes, which all share a common reference. Each amplifier is divided into two operational stages. The first stage 218 amplifies the neural signal by 25 times. The second stage 220 incorporates adaptive feedforward residual removal (AFRR) to eliminate residual artifacts caused by the asymmetrical arrangement of the recording electrodes. In at least one embodiment, the gain of the second stage is configurable, such as ranging from a gain of 3 to a gain of 8.

[0067] In the initial converging process, the system may become saturated due to the stimulation artifact. The duration of this saturation depends on the high-pass corner of the amplifier and can delay system convergence. To address this, a tunable high-pass filter is implemented to reduce the time it takes for the recording system to recover from saturation and resume normal operation. This filter also effectively removes flicker noise from the eCAPs recording. This filter is implemented using a DC-servo loop with a tunable pseudo resistor (RDSL) and a capacitor (CDSL).

[0068] 4. First Stage Amplifier For CAR Operation

[0069] The following describes this first stage amplifier 218 for CAR operation of a single neuron recording channel. The initial stage is shown with inputs 222 (xi, ref) connected through capacitors (Cin) (AC-coupled) to amplifier 224, and provides a mid-band amplification ratio (Ai) of 25X in this example. TheUC-2024-010-3-LA-PCT -12-negative terminal of this amplifier serves as the reference pin (ref), which interfaces with the average template for CAR operation. By using the AC- coupled amplifier, the DC offset from the recording electrode is effectively eliminated.

[0070] The positive input of amplifier 224 is coupled through a bias circuit 226, exemplified with voltage VCM connecting through parallel Capacitor Ct and resistance Ri to the positive input of amplifier 224. A similar circuit 228 can be utilized in the feedback path with capacitor Cf in parallel with resistance Ri , that can be in the form of a pseudo resistor comprising back-to-back transistors (e.g., MOS or bipolar) from the output to the inverting input of amplifier 224.

[0071] The high-pass corner of the first stage amplifier is set by the feedback capacitor (Cf). The low pass corner (fi_p) of the bandpass filter can be adjusted by switching the value of the load capacitor (CLI ) 230. In this specific example the values of Cin and Cf are chosen to be 10 pF and 400 fF for balancing input impedance, noise and power tradeoffs.

[0072] 5. Second Stage Amplifier Design For AFRR Cancellation And FastSettling

[0073] The second stage 220 of the amplifier performs the operations of an Operational Trans-conductance Amplifier (OTA) and a Trans-lmpedance Amplifier (TIA) for boosting output driving capability and wide output swing. An additional current mode DC-servo loop is implemented at the second stage for a tunable high pass corner.

[0074] As shown in FIG. 5A and FIG. 5B, Gmi 232 is used as artifact cancellation for AFRR. To avoid the loading effect, the artifact cancellation pin is designed to have a high impedance, which relaxes the driving requirement of the selection of weighted template generator, reducing both quiescent and dynamic current and avoiding signal distortion from the loading effect.

[0075] Then amplifier cell Gm2 234, in combination with output Gmi 232, is directed to an inverting amplifier / buffer 242 to capacitor C12245 and output s) 244. The output of amplifier / buffer 242 has a feedback path through a resistorUC-2024-010-3-LA-PCT -13-ladder 234 (e.g., 1 / 5 Rfb and 4 / 5 Rfb) with its center tap connecting to variable resistance RDSL 238 directed to the input of amplifier / buffer 240, whose output VDSL is directing to the input of amplifier cell Gm2 234. Amplifier / buffer 240 has capacitive feedback through capacitor 241. Thus, the amplifier cell Gm2 234 provides a DC-servo loop combined with Gm1 232 as shown in the figure for current reuse, lowering overall power consumption. By way of example and not limitation, both Gm1 and Gm2 cells are implemented as differential pair trans-conductance amplifiers.

[0076] The source degenerative resistance (Rgmi) 236 linearizes the OTA. By carefully configuring / designing the ratio between the source degenerative resistance Rgmiand Rf, the second stage gain can be set accurately, such as to either 3X or 8X depending on the configuration of the system. The tunable high-pass corner is achieved through a tunable pseudo-resistor (RDSL) 238.

[0077] FIG. 6 illustrates a one neuron recording channel 250 with two amplification stages showing an example implementation of the tunable pseudo-resistor shown as RDSL 238 in FIG. 5A and FIG. 5B. This pseudoresistor 250 of FIG. 6 is shown having connections 254, 256 and a tuning input Vtune 274. In at least one embodiment RDSL is formed by a pair of back- to-back PMOS transistors, MDSLI 264 and MDSL2 266. A control signal (Vtune) 274 adjusts the current sources 262, 272 in both branches of the tunable pseudo-resistor. The tuned current source is scaled, 100 times in this example, using current mirrors (transistors 260, 260 and associated drivers / buffers 258, 268), setting the RDSL within the MQ to GO range, allowing a tunable high-pass corner between 1 to 100Hz.

[0078] Returning now to the discussion of FIG. 5A and FIG. 5B, this tunable high-pass corner is implemented in the second stage of the amplifier, following the AFRR cancellation process. As a result, tuning the high-pass corner for fast settling does not impact the performance of either the CAR or AFRR stages. Instead, it enhances the removal of residual noise or artifacts that persist after these two artifact removal stages.

[0079] If the cross voltage of the transistor-based RDSL exceeds threshold voltage VTP(~600mV), the MDSLI - MDSL2 transistor pair 264, 266 of FIG. 6, may enter the linear region, resulting in a significant reduction of the RDSL.UC-2024-010-3-LA-PCT -14-This reduction can cause distortion in the output signal and limits the output swing. To maintain a rail-to-rail output swing for the amplifier, the DSL feedback node is carefully selected at the VFB node. In this example this selection limits the cross voltage of the RDSL to be 5 times less than that of the output voltage. As a result, the swing at the VFB node remains below 500mVpp even for a full-swing (2.5V) output signal. This approach ensures that the cross voltage of the tunable pseudo-resistor stays within the threshold voltage of the transistors, preventing unwanted distortion and clamping issues.

[0080] Before proceeding, it should be noted that in FIG. 5A and FIG. 5B amplifiers 240, 242 and their associated passive components (CDSL, 1 / 5 Rfb, 4 / 5 Rfb, CL2, form a tunable Bandpass (BP) filter driving output 244.

[0081] Off chip in FIG. 5A and FIG. 5B is shown a controller (e.g., MCU and test board) 214 receiving CAR outputs 216 d+, d_ , to both data acquisition 245 and ratio generator 246. The data acquisition section 245 receives output from each of the channels, outputs through gradient descent operation (e.g., (LMS) update 248 to the control ratio generator 246, which is a common signal directed back to the channels.

[0082] 6. Average Circuitry and Analog Weight

[0083] An on-chip averaging circuit extracts the template through averaging all input channels. The template is generated differentially, having positive template (a+) and negative template (a_) which represent a simple averaging of all channel inputs with a gain of +1 and -1 , respectively. The channel output, and the differential artifact templates are sent to an off-chip circuit (e.g., microcontroller (MCU)) for processing and data visualization. An online Least-Mean Square (LMS), or other gradient descent operation, adaptively configures the ratio generator to produce proper cancellation signals (n) for each channel. The ratio is configured once per data sample, but is ratelimited to avoid instability of the system during large stimulus artifacts.

[0084] FIG. 7 illustrates an average template 310 having a two-stage architecture. In the first stage, inputs 312 are capacitively 316 averaged to the inverting input of inverting amplifier 318, whose non-inverting input isUC-2024-010-3-LA-PCT -15-biased such as with VDC. Amplifier 318 has a feedback circuit with capacitor 322 (e.g., 6.4 pF) in parallel with resistor (or equivalent) 320. This averaging is performed with an inverting output. This inverting configuration creates a pseudo ground at the summing node, effectively minimizing any crosschannel contamination. It will be noted that the first stage inverts the artifact template and the second stage inverts it back.

[0085] The second stage of the averaging circuit consists of a capacitive inverting buffer used to recover the inverted signal. Inverting input of amplifier 326 receives the inverted output from amplifier 318, through a capacitor 324 (e.g., 6.4 pF). The non-inverting input of amplifier 326 is likewise connected to a suitable bias, such as VDC. Feedback on the second stage amplifier is through parallel capacitor 330 (e.g., 6.4 pF) and resistor 328. Optional buffers 332, 334 are shown on the differential outputs. To maintain the DC operating point (VDC) of the averaging circuit, each stage is implemented with a pseudoresistor.

[0086] The differential average template 336 is connected to the positive and negative terminals of the weighted template generator. The weighted template generator is a passive electronic component that works by adjusting the position of a sliding contact 338 along a uniform resistance, in response to data stored in a register 340 from an MCU update.

[0087] The relationship between the sliding contact position (di) and the output signal (n) can be described as follows:0 < dt< 1Here, di represents the percentage of the sliding contact position relative to the total length of the potentiometer resistor at the i-th channel. By adjusting the position of the digital potentiometer, it linearly scales the artifact reference to generate n, which is then fed into the second stage amplifier for AFRR operation.

[0088] 7. Measurement Results

[0089] A prototype chip was fabricated with 65nm TSMC 1 P6M process. TheUC-2024-010-3-LA-PCT -16-system has two sets of 8 channel recording systems and occupies an area of 0.975mm2or 0.06 mm2. Each set has an independent bias generator and averaging circuitry. The feedforward resistive Digital-to-Analog Converter (DAC) is implemented as a digital potentiometer AD5144 (Analog Device). A TMS320F28379D C2000 microcontroller samples the recording output with the built-in ADC and performs LMS, or other gradient descent operation for artifact removal.

[0090] FIG. 8 illustrates a Bode plot 350 of the transfer function of the frontend amplifier with tunable high pass corner for fast settling. Frequency response of the recording channel was measured at two gain settings: 75x (LowGain (LG)), and 200x (HighGain (HG)). Each of the gain settings maintains a bandwidth of 0.8 Hz to 10 kHz. The figure depicts pole locations and the legend shows the Vtune gain modes. The high pass corner is tunable with different biasing voltage. The transfer function was measured with 35670A Dynamic signal analyzer (Agilent). The Artifact Removal Ratio (ARR) is measured as:SNRin= 10 log Q2 / >2)ARR = SNRin- SNR0Ut“s” represents the input signal, “a” represents the tested artifact, and “s” is the output signal after artifact removal.FIG. 9A and FIG. 9B illustrates a block diagram 370 (FIG. 9A) of how ARR is measured, and a plot is shown of measured artifact removal 390 (FIG. 9B).In FIG. 9A artifacts 372 and a signal 374 are received at summing junction 376 to be received as Ch1 of the front-end spatial filtering (e.g., SMART) system 378 which also receives an average of artifact signal levels over the multiple channels (e.g., Ch 1-8) and outputs a result 380.In FIG. 9B it is shown that ARR of the front-end spatial filtering system is measured at 80 dB under a 1.3V p-p artifact stress and maintained a performance above 70 dB from artifact levels from 500 mVP-Pto 1 ,6VP-PasUC-2024-010-3-LA-PCT -17-seen in FIG. 9B, described below.

[0091] FIG. 10A through FIG. 10E are graphs of measured performance. In FIG. 10A is shown converging performance 410 of the proposed amplifier which was measured in-vivo and demonstrated in an EMG recording setup. The graphs also show the converging process of artifact cancellation. Artifact-contaminated plot 430 at the initial converging process in FIG. 10B, Artifact-clean plot 450 after converging in FIG. 10C, the artifact template plot 470 at the initial converging process is shown along with an artifact template plot 490 after converging in FIG. 10D and FIG. 10E, respectively.

[0092] As seen in FIG. 10E, the stimulus created a 1 ,2V artifact, which saturates the amplifier. The system takes around 3 seconds for the filter weight to converge to steady-state value. At steady state, the artifact is reduced to around 0.35 mV as shown in FIG. 10C, which is a reduction of 70.6 dB. It should be noted that these measurements were obtained with varying stimulation waveforms to emulate a closed-loop environment, which the stimulation protocol varies constantly.

[0093] The stimulation protocol was designed with a leading pulse and a lagging pulse. The leading pulse is kept constant at 1 ms, 200 us, and the lagging pulse swept from 1 ms to 10 ms delay and 100 us to 4 ms pulse width, with a sweep rate of 50 ms, as seen in FIG. 10B, FIG. 10D and FIG. 10E. The amplifier converged during a varying protocol; and removed the stimulation artifact while preserving the evoked neural response.

[0094] Table 4A continued into Table 4B compares the disclosed front-end spatial filtering system with state-of-the-art technologies, demonstrating how the disclosed system uniquely meets all four critical requirements for artifact- tolerant recording systems. The front-end spatial filtering system achieves an artifact rejection ratio of 80 dB in benchtop tests and 70.6 dB for in-vivo experiments, effectively reducing a 1.2V artifact to 0.35mV, recovering the evoked EMG, and preventing front-end saturation. The disclosed system operates independently without requiring active communication with the stimulator, as artifact removal occurs entirely in the analog domain. The system has a signal bandwidth of 11 .5 kHz, enabling full spectrum evoked neural response recording with minimal information loss. Notably, the systemUC-2024-010-3-LA-PCT -18-continues to function effectively after protocol changes, allowing for continuous recording of evoked responses during dynamic and closed-loop stimulation protocols.

[0095] FIG. 11 illustrates an alternative configuration 510 of the front-end spatial filtering recording system, using two spatial references (refi and ref2) interface with each recording channel. In the figure is seen multiple channels 512a, 512b through to 512n. Inputs refi and ref2 pass through capacitors to the non-inverting input of amplifier 528, which also has biasing 526 from VCM through a parallel Resistor and capacitor (Ri and Ct). Input Xi passes through capacitor Cin as signal 522 to the inverting input of amplifier 528. A feedback circuit 530, exemplified with parallel resistor and capacitor (Ri and Ct), is coupled between amplifier output 534 and its positive input 522. It should be noted that the channel output is inverted, but can be digitally reversed to noninverted, or an inverting buffer can be added between amplifier 528 and output 534.

[0096] There is also shown on-chip, an inverting amplifier 516 receiving refi and ref2 and outputting through a buffer 517 for LMS update 518, or other gradient descent operation. Output from the channels are directed to a multiple channel ADC 514 (exemplified here with 8 channels) which also outputs to LMS update 518 which outputs to a thermometer to binary 520 for controlling the variable capacitors of each channel.

[0097] The system amplifies the difference between the input signal and the weighted average of refi and ref2 as a measure of evoked neural response without amplifier saturation. The weighted average ratio is adjusted in realtime by a control unit. The control unit samples the difference between the two spatial references and each channel output for LMS adaptive operation.

[0098] In conclusion, a novel stimulation artifact cancellation I removal technique has been described for simultaneous recording and stimulation. With this method and apparatus, a multi-channel recording system can be made tolerant to arbitrary or varying stimulation protocol. When the stimulation protocol changes, the neural acquisition system will reliably record neural signals without disturbance.UC-2024-010-3-LA-PCT -19-

[0099] 8. System Integration, Wireless Relay, and NeuralKey Stimulator control

[0100] 8.1. System Operation

[0101] FIG. 12 illustrates a high level view 610 of the system. The system integrates together the front-end spatial filtering recording system, the stimulator, power management, and Wi-Fi communication 611 , with a Graphic User Interface 622.

[0102] The disclosure describes a Biomimetic Inspired Neural Device (BIND) 611 that can support simultaneous stimulation and recording with real-time stimulation artifact removal. Blocks are shown for power management 612, such voltage regulators / converters, and optional battery backup. By way of example, the figure depicting a 3.3V and 2.5V linear regulator, +12V and +1 ,8V converters as well as a rechargeable power source (e.g., Lithium-ion battery). There is a stimulus generation section 620 shown with System-on- Chip (SoC) digital controller and Stimulation Driver outputting for output to a stimulus connector. There is also a recording connection to an recording input section 618 shown with amplifiers and the AFRR analog processing. Both output block 620 and input block 618 being connected to a controller section 614 (i.e., C2000 controller) which is shown preferably containing at least two processors and configured for performing the front-end spatial filtering (e.g., SMART) operations and NeuralKey controller process steps. In addition, the controller section is configured for one or more forms of external communication, herein exemplified as WiFi transmit and receive 616, such as to external unit 622.

[0103] Thus, the architecture of the system integrates with the NeuralKey stimulator, the front-end spatial filtering recording system, an integrated central controller, a wireless Wi-Fi link, and a custom-designed user interface for parametric specifications. By way of example and not limitation, the present example NeuralKey stimulator provides independent control for up to 160 stimulation channels, and provides wireless communications operating at a sufficient data rate, such as 9.68 Mbps in this example, using the 802.11 b / g / n Wi-Fi protocol. In the example, a 3 Mbps LIART interface links the C2000 controller to the Wi-Fi module (CC3200).UC-2024-010-3-LA-PCT -20-

[0104] The C2000 controller (e.g., TMS320F28379D) updates the stimulator System-on-Chip (SoC) every 2 ms at a 2 MHz bit rate and the recording system via a 12 Mbps SPI interface. The neural signal is sampled at a rate of 20 kHz. The stimulator delivers an output current ranging from -500 to +500 pA per channel with an output compliance voltage of ±12 V.

[0105] FIG. 13A and FIG. 13B illustrate 710 and 810 a bidirectional data flow for stimulation (downlink) in FIG. 13A, and recording (uplink) in FIG. 13B. Downlink is shown with WiFi Tx / Rx 712 receiving information from user interface (e.g., GUI) 714 and directing the operations of the controller 716, with its CPU1 , and CPU2 performing the NeuralKey and outputting a binary sequence 718 to stimulator SoC 720 which outputs to connector 722. Similarly and simultaneously, uplink 810 is being performed with inputs at recording connector 820 to a front-end spatial filtering (e.g., SMART) recording system 818, to the control section 816 having ADCs with CPU1 and performing data serialization, and outputting to the communications module 812 to user interface (e.g., GUI) 814.

[0106] More specifically, the NeuralKey controller in CPU2 is preferably configured for accessing the Wi-Fi commands via memory sharing. The recording data is sampled, serialized, and sent through the communication link (e.g., Wi-Fi).

[0107] The dual-core capability of the C2000 controller is fully utilized in this system. CPU1 and CPU2 operate independently, accessing a shared memory section for data exchange. For downlink operations, CPU1 receives high-level stimulation parameters from the laptop GUI via Wi-Fi and transfers them to CPU2 through the designated memory segment. Each channel’s behavior within its time window (e.g., 2ms) is defined by a high-level data command (e.g., 16-byte command). The NeuralKey controller running on CPU2 then processes these high-level commands into detailed configuration sequences that control the stimulator SoC. For a 24-channel stimulator that updates every 2ms, the downlink traffic is calculated as: / bitsx / byte \ / channeh update™down= 8 — - * 16 -r2— r * 24 — — ** 500(— - ) = 1.536MbpsKbyte / Kchannel / \ update / sUC-2024-010-3-LA-PCT -21-

[0108] For uplink operations, CPLI1 interleaves the three built-in ADCs to sample the amplified neural signals at a resolution of 12 bits from the recording front-end and updates the weights for artifact removal. The sampled neural data is then transmitted back to the external device (e.g., a laptop) via the Wi-Fi module. The most significant bits (MSB) of the ADC sample are used for characterizing the artifact for front-end spatial filtering artifact removal. After convergence, the MSB carries little information, and the 12-bit samples can be truncated to 8-bit for efficient data transmission. For 8-channel recording, the uplink data traffic is: / bits \ samplesBW„„ = 8(channel) * 8 - ; - - * 20000( - i-— ) = 1.28Mbps \channel * sample / seconds

[0109] The total bandwidth consumption isBWtotal= BWup+ BWdown= 282Mbps

[0110] It should be noted that if a faster Universal Asynchronous Receiver Transmitter (UART) module can be accessed, the system can accommodate additional recording channels and / or faster stimulator updates.

[0111] 8.2. Neural-Key Stimulator Control

[0112] FIG. 14 illustrates waveforms 850 of the stimulator SoC. The configuring sequence contains information on Configuration 854, Real-time 856, and Firing 858. The NeuralKey controller specifies the status, location, and shape of the stimulus within each TITR window 852. Digital waveforms are shown exemplifying output for 16 channels.

[0113] The NeuroKey controller refreshes each channel every 2 ms window (TITR). In each refresh window, the controller issues a configuring sequence to the stimulator, defining the operation of the stimulus within the following window. Each refresh sets the following parameters: (1 ) the on / off status of the stimulus, (2) the location of the stimulus within the window, and (3) the specific parameters of the current pulse. The status determines whether a stimulus is triggered within that window. The timing parameter marks the onset of the stimulus relative to the end of the firing packet. The stimulus parameters includes a series of defining properties for the bi-phasic current pulse, such as anodic pulse width, cathodic pulse width, anodic amplitude, cathodic amplitude, polarity, and other relevant features. It should be notedUC-2024-010-3-LA-PCT -22-that the location parameter is referenced to the end of the firing packet.

[0114] The configuring sequence includes configuration data, real-time data, and firing data. In at least one embodiment, the configuration data packet consists of a 19-bit header marker, a 19-bit header, a channel-dependent sequence, followed by a 19-bit checksum and a 19-bit cyclic redundancy check (CRC). For a system with 24 channels, the total length of the configuration data packet is calculated as:Lc= 19 + 19 + 19 x 24 + 19 + 19 = 532 bits

[0115] In at least one embodiment, the real-time data packet follows the same format as the configuration data packet, while the firing packet occupies only 76 bits. For a 24-channel stimulator, the total length of the configuring sequence is totai = Lc+ LR+ Lp= 1140 where Ltotaiis the total bit required for each update. Lc, LR, and LFrepresents the length required for configuration data, real-time data, and fire packet, respectively.

[0116] 8.3. Stimulation Waveforms

[0117] The NeuralKey controller accurately controls the location of each pulse, allowing the neuroscientist to utilize a low power, miniaturized tool for investigating temporal coding. It can also be reconfigured to deliver multifrequency stimulation, random inter-arrival times, and arbitrary stimulation waveforms.

[0118] FIG. 15 illustrates how the NeuralKey controller dynamically adjusts 870 the location of the pulse in each TITR window to independently configure the stimulation frequency of each channel. Five channels are shown by way of example and not limitation.

[0119] For multi-frequency stimulation, each user-defined stimulation period (T) is divided into fixed cycles of TITR with sub-window skew (AT). A wrap- back counter integrates the skews from each period until the skews sum to more than a full TITR. When this occurs, the controller skips the next TITR window as seen in the figure.UC-2024-010-3-LA-PCT -23-

[0120] For example, consider a stimulation period of 33.1 ms. This stimulation period can be divided into 16 TITR window with 1 .1 ms skew. The first pulse fires at the location of 1.1 ms into the 16thTITR window. The second pulse fires at the location of 0.2 ms into the 33rdwindow. This is because the two 1 .1 ms skews have accumulated to 2.2 ms, which is larger than a full TITR window causing the controller to skip the entire 32ndwindow.

[0121] FIG. 16 illustrates measurement results 890 of four independent channels exemplified (but not limited to) firing at periods of 5 ms 892, 9ms 894, 15ms 896, and 24ms 898. The controller can also be configured to deliver stimulation with randomized inter-arrival times (e.g., according to a Poisson’s distribution). Each inter-arrival time is divided into fixed TITR windows with sub-window skews. A wrap-back counter integrates the subwindow skews until the total skew exceeds a full TITR window.

[0122] FIG. 17 illustrates four-channel stimulation 910 with random interarrival times based on an exponential distribution. The traces 912, 914 represent two randomized stimulations with a mean rate of 15 Hz, each based on independent random variables. The traces 916, 918 represent exponential randomized stimulation delivered with mean firing rates of 23 Hz and 31 Hz, respectively.

[0123] FIG. 18 illustrates the use of burst stimulations 930, wherein each channel can be delivered by the controller through configuring the pulse period, number of pulses per train, and train period. The figure shows four- channel burst stimulation with four sets of configurations 932, 934, 936 and 938.

[0124] Alternatively / additionally, the controller can configure the stimulator to deliver arbitrary stimulation by combining two interleaved stimulation channels.

[0125] FIG. 19 illustrates the use of arbitrary stimulation 950 with Configuration, Real Time, and Fire commands in the TITR intervals 952 with Ch1 954 and Ch2 956 combined in a combined output 958.

[0126] FIG. 20 illustrates measured waveforms 970 from four arbitrary stimulation outputs 972, 974, 976, 978 with each following a segment of human EMG waveform. EMG stimulation has been shown in rat in-vivo studyUC-2024-010-3-LA-PCT -24-to enhance spinal excitability.

[0127] 9. General Scope of Implementations

[0128] Embodiments of the technology of this disclosure may be described herein with reference to flowchart illustrations of methods and systems according to embodiments of the technology. Embodiments of the technology of this disclosure may also be described with reference to procedures, algorithms, steps, operations, formulae, or other computational depictions, which may be included within the flowchart illustrations or otherwise described herein. It will be appreciated that any of the foregoing may also be implemented as computer program instructions. In this regard, each block or step of a flowchart, and combinations of blocks (and / or steps) in a flowchart, as well as any procedure, algorithm, step, operation, formula, or computational depiction can be implemented by various means, such as hardware, firmware, and / or software including one or more computer program instructions embodied in computer-readable program code. As will be appreciated, any such computer program instructions may be executed by one or more computer processors, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer processor(s) or other programmable processing apparatus create means for implementing the function(s) specified.

[0129] Accordingly, blocks of the flowcharts, and procedures, algorithms, steps, operations, formulae, or computational depictions described herein support combinations of means for performing the specified function(s), combinations of steps for performing the specified function(s), and computer program instructions, such as embodied in computer-readable program code logic means, for performing the specified function(s). It will also be understood that each block of the flowchart illustrations, as well as any procedures, algorithms, steps, operations, formulae, or computational depictions and combinations thereof described herein, can be implemented by special purpose hardware-based computer systems which perform the specified function(s) or step(s), or combinations of special purpose hardwareUC-2024-010-3-LA-PCT -25-and computer-readable program code.

[0130] Furthermore, these computer program instructions, such as embodied in computer-readable program code, may also be stored in one or more computer-readable memory or memory devices that can direct a computer processor or other programmable processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory or memory devices produce an article of manufacture including instruction means which implement the function specified in the block(s) of the flowchart(s). The computer program instructions may also be executed by a computer processor or other programmable processing apparatus to cause a series of operational steps to be performed on the computer processor or other programmable processing apparatus to produce a computer- implemented process such that the instructions which execute on the computer processor or other programmable processing apparatus provide steps for implementing the functions specified in the block(s) of the flowchart(s), procedure (s) algorithm(s), step(s), operation(s), formula(e), or computational depiction(s).

[0131] It will further be appreciated that the terms "programming" or "program executable" as used herein refer to one or more instructions that can be executed by one or more computer processors to perform one or more functions as described herein. The instructions can be embodied in software, in firmware, or in a combination of software and firmware. The instructions can be stored local to the device in non-transitory media, or can be stored remotely such as on a server, or all or a portion of the instructions can be stored locally and remotely. Instructions stored remotely can be downloaded (pushed) to the device by user initiation, or automatically based on one or more factors.

[0132] It will further be appreciated that as used herein, the terms controller, microcontroller, processor, microprocessor, hardware processor, computer processor, central processing unit (CPU), and computer are used synonymously to denote a device capable of executing the instructions and communicating with input / output interfaces and / or peripheral devices, and that the terms controller, microcontroller, processor, microprocessor, hardwareUC-2024-010-3-LA-PCT -26-processor, computer processor, CPU, and computer are intended to encompass single or multiple devices, single core and multicore devices, and variations thereof.

[0133] 10. General Implementations

[0134] From the description herein, it will be appreciated that the present disclosure encompasses multiple implementations of the technology which include, but are not limited to, the following.

[0135] An apparatus or method of stimulation artifact suppression during electrophysiological electrical stimulation and recording.

[0136] A current mode neural stimulator coupled to a control unit for real-time arbitrary stimulation in a closed-loop or open-loop setting.

[0137] An apparatus for recording neural network responses and suppressing artifacts during concurrent electrical stimulation, comprising: (a) a stimulation circuit configured for generating neural stimulation to multiple electrodes; (b) multiple channels of analog circuitry, each channel of said multiple channels configured for receiving evoked responses as neural signals from an electrode; (c) wherein each said channel of analog circuitry has amplifiers for amplifying the signal and both removing common artifacts and adaptive feedforward residual removal in response to receiving a weighted signal processed with gradient descent processing of an artifact reference; (d) wherein the artifact reference is generated in response to averaging received neural signals and averaging them across the multiple channels to preserve only artifacts common across all channels while averaging out uncorrelated evoked responses; (e) at least one processor in said apparatus and at least one non-transitory memory storing instructions executable by the processor;(f) wherein said instructions, when executed by the processor, perform steps to suppress artifacts in the received evoked responses, comprising: (f)(i) measuring output from each channel of analog circuitry and the artifact references to continuously update these signals into digital representations; (f)(ii) wherein the weighted signal is determined in the digital domain by eliminating the correlated components across input channels while preserving the uncorrelated ones; (f)(iii) performing a spatial method of artifact removal that removes stimulation artifacts in real time, while preserving the evokedUC-2024-010-3-LA-PCT -27-neural responses by considering the differences in propagation speed and the spatial distribution and correlation of artifact signals and removing artifacts by eliminating correlated components of those artifact signals across multiple channels while preserving the uncorrelated ones; and (f)(iv) outputting processed neural signals having reduced artifact levels, for each channel as neural signals.

[0138] A system for controlling stimulus generation, artifact suppression, and recording of neural network responses, comprising: (a) a neural recording electrode; (b) a multi-channel neural recording amplifier configured to amplify an output from the neural recording electrode; (c) an artifact template that generates weighted cancellation signals, which are then subtracted from each channel input; (d) wherein the artifact template is referenced through an electrode placed on connective tissue close to a target neural structure during neural recording; (e) wherein the artifact template is generated by averaging circuits that perform real-time signal averaging; (f) a first response amplification stage configured to amplify the difference between the recording electrode signal and the artifact template, measured as the stimulus response; (g) a second response amplification stage configured to perform second-stage amplification of the difference between the measured stimulus response signal and a subtraction signal selected by a control unit; (h) wherein the subtraction signal is generated by coupling the average signal to a voltage divider with a calibrated dividing ratio; (i) wherein the system is configured to (A) set the dividing ratio for second-stage subtraction, (B) monitor the output and calibrate the dividing ratio in real-time, (C) reconfigure the averaging circuit to remove detached or broken electrodes, (D) perform simultaneous stimulation and recording, and (E) implement common average referencing and subtraction of the calibrated signal to remove artifacts from the measured stimulus response signal.

[0139] An apparatus for controlling stimulus generation, artifact suppression, and recording of neural network responses, comprising: (a) a stimulator control circuit configured for being connecting to neural stimulation electrodes for generating stimulation waveforms comprising synchronized control commands and dynamically configured pulse location for independent timingUC-2024-010-3-LA-PCT -28-control, and allowing combining stimulation outputs for arbitrary stimulation;(b) a neural recording amplifier having multiple channels configured to amplify received neural signals from multiple neural recording electrodes; (c) wherein said neural recording amplifier generates an artifact template in real time, in response to averaging received neural signals across the multiple channels to preserve only artifacts common across all channels while averaging out uncorrelated evoked responses; (d) wherein the artifact template is referenced through an electrode placed on connective tissue close to a target neural structure during neural recording; (e) a first response amplification stage configured to amplify the difference between the received neural signals and the artifact template; (f) a second response amplification stage, receiving input from the first response amplification stage, wherein said second response amplification stage is configured to perform second-stage amplification of the difference between the measured stimulus response signal and a subtraction signal selected by a control unit; (g) wherein the subtraction signal is generated by coupling the average signal to a voltage divider with a calibrated dividing ratio, and generating resultant analog outputs for each channel; (h) wherein digital control circuitry receives said analog outputs for each channel and performs operations, comprising: (h)(i) setting the dividing ratio for subtractions performed in said second response amplification stage; (h)(ii) monitoring the output and calibrating the dividing ratio in real-time; (h)(iii) reconfiguring the averaging circuit to ignore inputs from detached and non-functioning electrodes; (h)(iv) performing simultaneous stimulation and neural recording, and (h)(v) performing common average referencing and subtraction of the calibrated signals to remove artifacts from the received neural signals and output corrected neural signals with reduced levels of artifacts.

[0140] A method of recording neural network responses and suppressing artifacts during concurrent electrical stimulation, comprising: (a) receiving neural signals on multiple channels of recording electrodes; (b) estimating an artifact template by averaging received neural signals and averaging them across the multiple channels to preserve only artifacts common across all channels while averaging out uncorrelated evoked responses; and (c)UC-2024-010-3-LA-PCT -29-performing subtraction in real time of the artifact template, after it is weighted, from the received neural signals collected by the recording electrodes to recover neural signals with minimized levels of artifacts.

[0141] A method and system for controlling stimulus generation, artifact suppression, and recording of neural network responses, comprising one or more of the following: (a) a multi-channel neural recording amplifier for amplifying an output from the neural recording electrode; (b) an artifact template that generates weighted cancellation signals, which are then subtracted from each channel input; (c) the artifact template is referenced through an electrode placed on connective tissue close to the target neural structure during neural recording; (d) in another application, one or more additional reference electrode may be placed, where the artifact template is generated as a weighted average of the reference electrodes; (e) in another application, the artifact template can be generated by the arithmetic average of signals from at least three electrodes that experiencing similar strength of stimulation artifact, wherein the electrodes used for averaging can be any combination of input, reference, or ground electrodes; (f) an artifact template generated by averaging circuits that perform real-time signal averaging; (g) a first response amplification stage configured to amplify the difference between the recording electrode signal and the artifact template, measured as the stimulus response; (h) a second response amplification stage designed to perform second-stage amplification of the difference between the measured stimulus response signal and a subtraction signal selected by the control unit;(i) The subtraction signal is generated by coupling the average signal to a voltage divider with a calibrated dividing ratio; and (j) the system is configured to: set the dividing ratio for second-stage subtraction; monitor the output and calibrate the dividing ratio in real-time; reconfigure the averaging circuit to remove detached or broken electrodes; perform simultaneous stimulation and recording; Implement common average referencing and subtraction of the calibrated signal to remove artifacts from the measured stimulus response signal.

[0142] The apparatus or method as described in any preceding or following implementation, wherein the electrodes used for averaging can be selectedUC-2024-010-3-LA-PCT -30-from any combination of input, reference, or ground electrodes.

[0143] The apparatus or method as described in any preceding or following implementation, wherein one or more of the received neural signals is obtained from a dedicated reference electrode or ground electrode.

[0144] The apparatus or method as described in any preceding or following implementation, wherein said averaging of received neural signals can be performed as a simple or weighted average.

[0145] The apparatus or method as described in any preceding or following implementation, wherein the artifact template is generated as a weighted average across multiple of said neural recording electrodes as well as one or more reference electrodes.

[0146] The apparatus or method as described in any preceding or following implementation, wherein the artifact template can be generated by the arithmetic average of signals from at least three electrodes experiencing a similar strength of stimulation artifact.

[0147] The apparatus or method as described in any preceding or following implementation, wherein the electrodes used for averaging can be any combination of input, reference, or ground electrodes.

[0148] The apparatus or method as described in any preceding or following implementation, wherein the averaging circuit can scale and connect to different numbers of recording electrodes to extract a common artifact template.

[0149] The apparatus or method as described in any preceding or following implementation, wherein the artifact template can be applied to either a subset or an extended set of recording electrodes connected to the averaging circuitry.

[0150] The apparatus or method as described in any preceding or following implementation, wherein calibrating the dividing ratio can be performed any number of times to achieve the desired accuracy.

[0151] The apparatus or method as described in any preceding or following implementation, wherein the calibrating of the dividing ratio is updated automatically.

[0152] The apparatus or method as described in any preceding or followingUC-2024-010-3-LA-PCT -31-implementation, wherein the apparatus can record neural signals with or without concurrent stimulation.

[0153] The apparatus or method as described in any preceding or following implementation, wherein the apparatus can record neural signals during both open-loop or closed-loop stimulation.

[0154] The apparatus or method as described in any preceding or following implementation, wherein the apparatus can record neural signals with voltagemode or current-mode stimulation.

[0155] The apparatus or method as described in any preceding or following implementation, wherein amplifier saturation is avoided, allowing for low latency closed-loop algorithm implementation, or additional post-signal processing.

[0156] The apparatus or method as described in any preceding or following implementation, wherein the control circuitry comprises a computer processor, memory, divider circuit, and analog-to-digital conversion circuitry.

[0157] The apparatus or method as described in any preceding or following implementation, wherein said averaging of received neural signals can be performed as a simple or weighted average.

[0158] The apparatus or method as described in any preceding or following implementation, wherein the averaging circuit can scale and connect to different numbers of recording electrodes to extract a common artifact template.

[0159] The apparatus or method as described in any preceding or following implementation, wherein the artifact template can be applied to either a subset or an extended set of recording electrodes connected to the averaging circuitry.

[0160] The apparatus or method as described in any preceding or following implementation, wherein the same electrode array is utilized for both stimulation and recording.

[0161] The apparatus or method as described in any preceding or following implementation, wherein a separate electrode array is utilized for stimulation and recording.

[0162] The apparatus or method as described in any preceding or followingUC-2024-010-3-LA-PCT -32-implementation, wherein the calibration algorithm runs continuously or intermittently for optimized operation.

[0163] The apparatus or method as described in any preceding or following implementation, wherein calibrating the dividing ratio can be performed any number of times to achieve the desired accuracy.

[0164] The apparatus or method as described in any preceding or following implementation, wherein the calibration ratio is updated automatically in realtime.

[0165] The apparatus or method as described in any preceding or following implementation, wherein the apparatus separates artifact and neural signals, even if they overlap in time or frequency domains.

[0166] The apparatus or method as described in any preceding or following implementation, wherein the apparatus can record neural signals with or without concurrent stimulation.

[0167] The apparatus or method as described in any preceding or following implementation, wherein the apparatus can record neural signals during both open-loop or closed-loop stimulation.

[0168] The apparatus or method as described in any preceding or following implementation, wherein the apparatus can record neural signals with voltagemode or current-mode stimulation.

[0169] The apparatus or method as described in any preceding or following implementation, wherein amplifier saturation is avoided, allowing for low latency closed-loop algorithm implementation.

[0170] The apparatus or method as described in any preceding or following implementation, wherein amplifier saturation is avoided, thus allowing for additional post-signal processing.

[0171] The apparatus or method as described in any preceding or following implementation, wherein any connected electrode channel can be enabled or disabled.

[0172] The apparatus or method as described in any preceding or following implementation, wherein the control circuitry comprises a computer processor, memory, divider circuit, and analog-to-digital conversion circuitry.

[0173] The apparatus or method as described in any preceding or followingUC-2024-010-3-LA-PCT -33-implementation, wherein the apparatus is integrated into an integrated circuit or system on-chip (SoC).

[0174] As used herein, the term "implementation" is intended to include, without limitation, embodiments, examples, or other forms of practicing the technology described herein.

[0175] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. Reference to an object in the singular is not intended to mean "one and only one" unless explicitly so stated, but rather "one or more."

[0176] Phrasing constructs, such as “A, B and / or C”, within the present disclosure describe where either A, B, or C can be present, or any combination of items A, B and C. Phrasing constructs indicating, such as “at least one of” followed by listing a group of elements, indicates that at least one of these groups of elements is present, which includes any possible combination of the listed elements as applicable.

[0177] References in this disclosure referring to “an embodiment”, “at least one embodiment” or similar embodiment wording indicates that a particular feature, structure, or characteristic described in connection with a described embodiment is included in at least one embodiment of the present disclosure. Thus, these various embodiment phrases are not necessarily all referring to the same embodiment, or to a specific embodiment which differs from all the other embodiments being described. The embodiment phrasing should be construed to mean that the particular features, structures, or characteristics of a given embodiment may be combined in any suitable manner in one or more embodiments of the disclosed apparatus, system, or method.

[0178] As used herein, the term "set" refers to a collection of one or more objects. Thus, for example, a set of objects can include a single object or multiple objects.

[0179] Relational terms such as first and second, top and bottom, upper and lower, left and right, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0180] The terms "comprises," "comprising," "has", "having," "includes",UC-2024-010-3-LA-PCT -34-"including," "contains", "containing" or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, apparatus, or system, that comprises, has, includes, or contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, apparatus, or system. An element proceeded by "comprises . . . a", "has . . . a", "includes . . . a", "contains . . . a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, apparatus, or system, that comprises, has, includes, contains the element.

[0181] As used herein, the terms "approximately", "approximate", "substantially", "substantial", "essentially", and "about", or any other version thereof, are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. When used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ± 10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1 %, less than or equal to ±0.5%, less than or equal to ±0.1 %, or less than or equal to ±0.05%. For example, "substantially" aligned can refer to a range of angular variation of less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1 °, less than or equal to ±0.5°, less than or equal to ±0.1 °, or less than or equal to ±0.05°.

[0182] Additionally, amounts, ratios, and other numerical values may sometimes be presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. For example, a ratio in the range of about 1 to about 200UC-2024-010-3-LA-PCT -35-should be understood to include the explicitly recited limits of about 1 and about 200, but also to include individual ratios such as about 2, about 3, and about 4, and sub-ranges such as about 10 to about 50, about 20 to about 100, and so forth.

[0183] The term "coupled" as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is "configured" in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

[0184] Benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of the technology described herein or any or all the claims.

[0185] In addition, in the foregoing disclosure various features may be grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Inventive subject matter can lie in less than all features of a single disclosed embodiment.

[0186] The abstract of the disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

[0187] It will be appreciated that the practice of some jurisdictions may require deletion of one or more portions of the disclosure after the application is filed. Accordingly, the reader should consult the application as filed for the original content of the disclosure. Any deletion of content of the disclosure should not be construed as a disclaimer, forfeiture, or dedication to the public of any subject matter of the application as originally filed.

[0188] All text in a drawing figure is hereby incorporated into the disclosure and is to be treated as part of the written description of the drawing figure.

[0189] The following claims are hereby incorporated into the disclosure, with each claim standing on its own as a separately claimed subject matter.UC-2024-010-3-LA-PCT -36-

[0190] Although the description herein contains many details, these should not be construed as limiting the scope of the disclosure, but as merely providing illustrations of some of the presently preferred embodiments. Therefore, it will be appreciated that the scope of the disclosure fully encompasses other embodiments which may become obvious to those skilled in the art.

[0191] All structural and functional equivalents to the elements of the disclosed embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed as a "means plus function" element unless the element is expressly recited using the phrase "means for". No claim element herein is to be construed as a "step plus function" element unless the element is expressly recited using the phrase "step for".UC-2024-010-3-LA-PCT -37-Table 1Propagation Speed Of Different Electrical Signal In TissueUC-2024-010-3-LA-PCT -38-Table 2Cross Correlation Between Channels and AveragesUC-2024-010-3-LA-PCT -39-Table 3Amplitude DifferencesUC-2024-010-3-LA-PCT -40-Table 4A Comparison Table w / State-Of-The-Art Front-End Artifact Cancellersb - Requires manual switching, c - Theoretical performanceUC-2024-010-3-LA-PCT -41-Table 4B Comparison Table w / State-Of-The-Art Front-End Artifact Cancellers* 5.3 uV without template, and 9.2 uV with template a - Measured w / power consumption b - Requires manual switchingUC-2024-010-3-LA-PCT -42-

Claims

CLAIMSWhat is claimed is:1 . An apparatus for recording neural network responses and suppressing artifacts during concurrent electrical stimulation, comprising:(a) a stimulation circuit configured for generating neural stimulation to multiple electrodes;(b) multiple channels of analog circuitry, each channel of said multiple channels configured for receiving evoked responses as neural signals from an electrode;(c) wherein each said channel of analog circuitry has amplifiers for amplifying the signal and both removing common artifacts and adaptive feedforward residual removal in response to receiving a weighted signal processed with gradient descent processing of an artifact reference;(d) wherein the artifact reference is generated in response to averaging received neural signals and averaging them across the multiple channels to preserve only artifacts common across all channels while averaging out uncorrelated evoked responses;(e) at least one processor in said apparatus and at least one non-transitory memory storing instructions executable by the processor;(f) wherein said instructions, when executed by the processor, perform steps to suppress artifacts in the received evoked responses, comprising:(i) measuring output from each channel of analog circuitry and the artifact references to continuously update these signals into digital representations;(ii) wherein the weighted signal is determined in the digital domain by eliminating the correlated components across input channels while preserving the uncorrelated ones;(iii) performing a spatial method of artifact removal that removes stimulation artifacts in real time, while preserving the evoked neural responses by considering the differences in propagation speed and the spatial distribution and correlation of artifact signals and removing artifacts byUC-2024-010-3-LA-PCT -43-eliminating correlated components of those artifact signals across multiple channels while preserving the uncorrelated ones; and(iv) outputting processed neural signals having reduced artifact levels, for each channel as neural signals.

2. The apparatus of claim 1 , wherein the electrodes used for averaging can be selected from any combination of input, reference, or ground electrodes.

3. The apparatus of claim 1 , wherein one or more of the received neural signals is obtained from a dedicated reference electrode or ground electrode.

4. The apparatus of claim 1 , wherein said averaging of received neural signals can be performed as a simple or weighted average.

5. An apparatus for controlling stimulus generation, artifact suppression, and recording of neural network responses, comprising:(a) a stimulator control circuit configured for being connecting to neural stimulation electrodes for generating stimulation waveforms comprising synchronized control commands and dynamically configured pulse location for independent timing control, and allowing combining stimulation outputs for arbitrary stimulation;(b) a neural recording amplifier having multiple channels configured to amplify received neural signals from multiple neural recording electrodes;(c) wherein said neural recording amplifier generates an artifact template in real time, in response to averaging received neural signals across the multiple channels to preserve only artifacts common across all channels while averaging out uncorrelated evoked responses;(d) wherein the artifact template is referenced through an electrode placed on connective tissue close to a target neural structure during neural recording;(e) a first response amplification stage configured to amplify the difference between the received neural signals and the artifact template;(f) a second response amplification stage, receiving input from the first response amplification stage, wherein said second response amplification stage is configured to perform second-stage amplification of the difference between theUC-2024-010-3-LA-PCT -44-measured stimulus response signal and a subtraction signal selected by a control unit;(g) wherein the subtraction signal is generated by coupling the average signal to a voltage divider with a calibrated dividing ratio, and generating resultant analog outputs for each channel;(h) wherein digital control circuitry receives said analog outputs for each channel and performs operations, comprising:(i) setting the dividing ratio for subtractions performed in said second response amplification stage;(ii) monitoring the output and calibrating the dividing ratio in realtime;(iii) reconfiguring the averaging circuit to ignore inputs from detached and non-functioning electrodes;(iv) performing simultaneous stimulation and neural recording, and(v) performing common average referencing and subtraction of the calibrated signals to remove artifacts from the received neural signals and output corrected neural signals with reduced levels of artifacts.

6. The apparatus of claim 5, wherein the artifact template is generated as a weighted average across multiple of said neural recording electrodes as well as one or more reference electrodes.

7. The apparatus of claim 5, wherein the artifact template can be generated by the arithmetic average of signals from at least three electrodes experiencing a similar strength of stimulation artifact.

8. The apparatus of claim 7, wherein the electrodes used for averaging can be any combination of input, reference, or ground electrodes.

9. The apparatus of claim 5, wherein the averaging circuit can scale and connect to different numbers of recording electrodes to extract a common artifact template.UC-2024-010-3-LA-PCT -45-10. The apparatus of claim 5, wherein the artifact template can be applied to either a subset or an extended set of recording electrodes connected to the averaging circuitry.11 . The apparatus of claim 5, wherein calibrating the dividing ratio can be performed any number of times to achieve the desired accuracy.

12. The apparatus of claim 11 , wherein the calibrating of the dividing ratio is updated automatically.

13. The apparatus of claim 5, wherein the apparatus can record neural signals with or without concurrent stimulation.

14. The apparatus of claim 5, wherein the apparatus can record neural signals during both open-loop or closed-loop stimulation.

15. The apparatus of claim 5, wherein the apparatus can record neural signals with voltage-mode or current-mode stimulation.

16. The apparatus of claim 5, wherein amplifier saturation is avoided, allowing for low latency closed-loop algorithm implementation, or additional postsignal processing.

17. The apparatus of claim 5, wherein the control circuitry comprises a computer processor, memory, divider circuit, and analog-to-digital conversion circuitry.

18. The apparatus of claim 5, wherein said averaging of received neural signals can be performed as a simple or weighted average.

19. A method of recording neural network responses and suppressing artifacts during concurrent electrical stimulation, comprising:(a) receiving neural signals on multiple channels of recording electrodes;UC-2024-010-3-LA-PCT -46-(b) estimating an artifact template by averaging received neural signals and averaging them across the multiple channels to preserve only artifacts common across all channels while averaging out uncorrelated evoked responses; and(c) performing subtraction in real time of the artifact template, after it is weighted, from the received neural signals collected by the recording electrodes to recover neural signals with minimized levels of artifacts.

20. The method of claim 19, wherein performing said averaging of received neural signals is performed as a simple or weighted average.UC-2024-010-3-LA-PCT -47-

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