Array substrate and display panel

Abstract

An array substrate, comprising a first base substrate (10), and a first conductive layer (20), a buffer layer (BUF), a semiconductor layer (30), a gate insulating layer (GI), and a second conductive layer (40) sequentially arranged in a direction away from the first base substrate (10). The first conductive layer (20) comprises a plurality of data signal lines (DL), and the plurality of data signal lines (DL) are distributed at intervals along a first direction and extend along a second direction as a whole. The semiconductor layer (30) is located on the side of the buffer layer distant from the first base substrate (10) and comprises a first semiconductor pattern (31). The second conductive layer (40) is located on the side of the gate insulating layer (GI) distant from the first base substrate (10), and comprises a first source (S1), a first drain (D1), and a first gate (G1). The array substrate comprises a first via hole (V1), and the first via hole (V1) runs through the gate insulating layer (GI) and the buffer layer (BUF) and exposes at least part of the data signal line (DL). The array substrate comprises a plurality of first transistors (T1) located in a display area; each first transistor (T1) comprises the first semiconductor pattern (31), the first gate (G1), the first source (S1), and the first drain (D1); and the first source (S1) passes through the first via hole (V1) to be electrically connected to the data signal line (DL).

Description

Array substrate and display panel

[0001] This application claims priority to international patent application No. PCT / CN2024 / 124923, filed on October 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0003] Liquid crystal display (LCD) panels have been widely used. Typically, an LCD panel includes a color filter substrate and an array substrate disposed opposite each other, and a liquid crystal layer between the color filter substrate and the array substrate. The array substrate may include thin-film transistors, gate lines, signal lines, pixel electrodes, and the color filter substrate or array substrate may also include a common electrode and a common electrode signal line. With the continuous development of display technology, the requirements for LCD panels are becoming increasingly stringent, with high pixel density being a crucial development direction for display devices. Increasing the aperture ratio of the LCD panel is an important way to improve its pixel density, and how to improve the aperture ratio of the LCD panel is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] On one hand, an array substrate is provided. The array substrate has a display area and a peripheral area located on at least one side of the display area. The array substrate includes a first substrate, a first conductive layer, a buffer layer, a semiconductor layer, a gate insulating layer, and a second conductive layer. The first conductive layer is located on one side of the first substrate and includes a plurality of data signal lines spaced apart along a first direction and generally extending along a second direction. The first direction and the second direction intersect each other. The buffer layer is located on the side of the first conductive layer away from the first substrate. The semiconductor layer is located on the side of the buffer layer away from the first substrate and includes a first semiconductor pattern. The gate insulating layer is located on the side of the semiconductor layer away from the first substrate. The second conductive layer is located on the side of the gate insulating layer away from the first substrate and includes a first source, a first drain, and a first gate. The array substrate further includes a first via penetrating the gate insulating layer and the buffer layer and exposing at least a portion of the data signal lines. The array substrate includes a plurality of first transistors located within the display area. Each first transistor includes a first semiconductor pattern, a first gate, a first source, and a first drain. A portion of the first source passes through the first via and is electrically connected to the data signal line.

[0005] In some embodiments, the second conductive layer further includes a plurality of gate lines extending along the first direction and spaced apart along the second direction. The orthographic projections of the plurality of gate lines and the plurality of data signal lines onto the first substrate intersect to form a grid structure. Each grid of the grid structure defines a sub-pixel, and the sub-pixel includes an opening region. The data signal lines include first extension segments and second extension segments alternately connected along the second direction. The first extension segment and the opening region are disposed opposite to each other in the first direction. The linewidth of the first extension segment is equal at all points along the second direction. The second extension segment includes a first sub-segment and a second sub-segment. The first sub-segment is electrically connected to the first source electrode, and the linewidth of the first sub-segment is greater than the linewidth of the second sub-segment.

[0006] In some embodiments, the line width of the first sub-segment is greater than the line width of the first extension segment; and / or, the line width of the second sub-segment is less than or equal to the line width of the first extension segment.

[0007] In some embodiments, the linewidth of the first extension segment is 2μm to 4μm.

[0008] In some embodiments, the linewidth of the first extension segment is 2 μm to 2.5 μm.

[0009] In some embodiments, a first extension segment includes at least two third sub-segments; the extension direction of the third sub-segments has a first angle with the second direction, the first angle being 5° to 11°; wherein two adjacent third sub-segments along the second direction have opposite inclination directions to the second direction.

[0010] In some embodiments, the first included angle is 8° to 11°.

[0011] In some embodiments, the orthographic projection of the first semiconductor pattern on the first substrate at least partially coincides with the orthographic projection of the data signal line on the first substrate. The first via includes a first region, a second region, and a third region sequentially connected along a direction away from the first source electrode. The orthographic projection of the first region on the first substrate partially coincides with the orthographic projection of the first semiconductor pattern on the first substrate, but does not coincide with the orthographic projection of the data signal line on the first substrate. The orthographic projection of the second region on the first substrate partially coincides with the orthographic projections of both the first semiconductor pattern and the data signal line on the first substrate. The orthographic projection of the third region on the first substrate does not coincide with the orthographic projection of the first semiconductor pattern on the first substrate, but coincides with the orthographic projection of the data signal line on the first substrate. The first source electrode covers at least a portion of the second region and at least a portion of the third region, and the first source electrode does not coincide with at least a portion of the first region.

[0012] In some embodiments, the first source electrode covers the second region, the third region, and a portion of the first region, and the first source electrode does not overlap with at least a portion of the first region.

[0013] In some embodiments, in the first region, the array substrate includes the buffer layer, the first semiconductor pattern, and the first source electrode stacked together. In the second region, the array substrate includes the data signal line, the buffer layer, the first semiconductor pattern, and the first source electrode stacked together. In the third region, the array substrate includes the data signal line and the first source electrode stacked together.

[0014] In some embodiments, in the second region, at least one of the buffer layer, the first semiconductor pattern, and the first source electrode forms a protrusion structure that protrudes toward a side away from the first substrate relative to the first region and / or the third region.

[0015] In some embodiments, the first semiconductor pattern includes a serrated structure at the edge of the second region near the first region.

[0016] In some embodiments, the second conductive layer further includes a plurality of gate lines extending along the first direction and distributed along the second direction, the first gate being electrically connected to the gate lines. The first semiconductor pattern includes a first portion, a second portion, and a third portion sequentially connected along the first direction, the first portion being located on the side of the second portion near the first via. The ends of the first portion, the second portion, and the third portion along the second direction near the gate lines are substantially flush, and the ends of the first portion and the third portion along the second direction away from the gate lines extend beyond the boundary of the second portion along the second direction.

[0017] In some embodiments, the orthographic projection of the boundary of the second portion away from the gate line onto the first substrate is approximately an arc, the arc being concave towards the side closer to the gate line.

[0018] In some embodiments, the maximum dimension of the first portion along the first direction is smaller than the maximum dimension of the third portion along the first direction. And / or, the maximum dimension of the first portion along the second direction is not equal to the maximum dimension of the third portion along the second direction.

[0019] In some embodiments, the first conductive layer further includes a plurality of first light-shielding patterns, wherein the portions of the first gate and the first semiconductor pattern whose orthogonal projections on the first substrate overlap are located within the range of the orthogonal projections of the first light-shielding patterns on the first substrate. The orthogonal projections of the second portion on the first substrate are located within the range of the orthogonal projections of the first light-shielding patterns on the first substrate; at least portions of the first portion away from the second portion and at least portions of the third portion away from the second portion whose orthogonal projections on the first substrate do not overlap with the orthogonal projections of the first light-shielding patterns on the first substrate.

[0020] In some embodiments, the orthographic projections of the two ends of the second portion along the first direction onto the first substrate generally coincide with the orthographic projections of the two ends of the first light-shielding pattern along the first direction onto the first substrate. The orthographic projections of the two ends of the second portion along the second direction onto the first substrate are spaced apart from the orthographic projections of the two ends of the first light-shielding pattern along the second direction onto the first substrate.

[0021] In some embodiments, the portions where the orthographic projections of the first gate and the first semiconductor pattern on the first substrate overlap are spaced apart from the ends of the first light-shielding pattern along the first direction at both ends.

[0022] In some embodiments, in a sub-pixel, along the second direction and away from the gate line, the first portion includes a first end portion away from the gate line, the third portion includes a second end portion away from the gate line, the first light-shielding pattern includes a third end portion away from the gate line, and at least one of the first end portion and the second end portion is at a greater distance from the gate line than the distance between the third end portion and the gate line.

[0023] In some embodiments, the orthographic projection of the first gate on the first substrate is located within the range of the orthographic projection of the first light-shielding pattern on the first substrate, and the end of the first gate away from the gate line is spaced from the boundary of the first light-shielding pattern away from the gate line.

[0024] In some embodiments, the array substrate further includes a first passivation layer, a planarization layer, a first electrode layer, a second passivation layer, and a second electrode layer. The first passivation layer is located on the side of the second conductive layer away from the first substrate; the planarization layer is located on the side of the first passivation layer away from the first substrate; the first electrode layer is located on the side of the planarization layer away from the first substrate; the second passivation layer is located on the side of the first electrode layer away from the first substrate; the second electrode layer, located on the side of the second passivation layer away from the first substrate, includes a plurality of second electrodes, which are electrically connected to the first drain through a second via. The array substrate further includes a second via that penetrates the second passivation layer, the first electrode layer, and the first passivation layer, and exposes at least a portion of the first drain. The line connecting the first transistor, the first via, and the second via on the first substrate, as projected onto the first substrate, is arranged along the first direction or is generally U-shaped.

[0025] In some embodiments, the second conductive layer further includes a plurality of gate lines extending along the first direction and spaced apart along the second direction. Each gate line includes a third extension and a fourth extension. The third extension and the second via are disposed opposite to each other along the second direction, and the fourth extension is offset from the data signal line, the first via, and the first gate in the first direction. The line width of the third extension is smaller than the line width of the fourth extension.

[0026] In some embodiments, the gate line further includes a fifth extension, the orthographic projection of which on the first substrate at least partially coincides with the orthographic projection of the data signal line on the first substrate. The linewidth of the fifth extension is equal to, or equal to, the linewidth of the fourth extension, or greater than the linewidth of the third extension and less than the linewidth of the sixth extension.

[0027] In some embodiments, the boundaries of the third extension, the fourth extension, and the fifth extension are flush with the side of the first gate that is electrically connected to the gate line.

[0028] In some embodiments, the second via includes a first sub-via and a second sub-via. The first sub-via penetrates the planarization layer, and at least a portion of the second passivation layer is located within the first sub-via and contacts the sidewall of the first sub-via. The second sub-via penetrates both the second and first passivation layers, and the orthographic projection of the second sub-via onto the first substrate lies within the range of the orthographic projection of the first sub-via onto the first substrate, and the boundary of the second sub-via does not at least partially coincide with the boundary of the first sub-via.

[0029] In some embodiments, the center of the orthographic projection of the first sub-hole onto the first substrate is spaced apart from the center of the orthographic projection of the second sub-hole onto the first substrate.

[0030] In some embodiments, the orthographic projections of the second sub-via and the first drain on the first substrate coincide, and the orthographic projection of the second sub-via on the first substrate is located outside the range of the orthographic projection of the first drain on the first substrate.

[0031] In some embodiments, the array substrate further includes a third via that penetrates the gate insulating layer and exposes a portion of the first semiconductor pattern; the first drain is electrically connected to the first semiconductor pattern through the third via. The orthographic projections of the third via and the first drain on the first substrate coincide, and the orthographic projection of the third via on the first substrate is located outside the range of the orthographic projection of the first drain on the first substrate.

[0032] In some embodiments, the portion of the orthographic projection of the third via on the first substrate that does not coincide with the orthographic projection of the first drain on the first substrate is located on the side of the first drain away from the first gate.

[0033] In some embodiments, the orthographic projection of the third via on the first substrate partially overlaps with the orthographic projection of the first sub-via on the first substrate, and is partially located outside the orthographic projection of the second sub-via on the first substrate.

[0034] In some embodiments, the orthographic projection of the first via on the first substrate is one of a circle and an ellipse; and / or, the orthographic projection of the third via on the first substrate is one of a circle and an ellipse.

[0035] In some embodiments, the sidewall of the second via is in contact with the second passivation layer, the planarization layer, and the first passivation layer, respectively.

[0036] In some embodiments, two adjacent data signal lines along the first direction are respectively a first data signal line and a second data signal line. In the first transistor located between the two adjacent data signal lines, the first source is electrically connected to the first data signal line, the first drain is located between the first gate and the second data signal line, and the spacing between the first drain and the first gate is smaller than the spacing between the first drain and the second data signal line.

[0037] In some embodiments, in the same first transistor, the distance between the first gate and the first source along the first direction is a first distance, the distance between the first gate and the first drain along the first direction is a second distance, and the difference between the second distance and the first distance is greater than or equal to 4 μm.

[0038] In some embodiments, in the same first transistor, the distance between the first gate and the first source along the first direction is greater than the distance between the first gate and the first drain along the first direction.

[0039] In some embodiments, the semiconductor layer includes a first semiconductor layer and a second semiconductor layer stacked together. The second semiconductor layer is disposed on the side of the first semiconductor layer away from the first substrate, and the orthographic projection of the second semiconductor layer on the first substrate lies within the orthographic projection of the first semiconductor layer on the first substrate. The first semiconductor pattern includes a first pattern located on the first semiconductor layer and two second patterns located on the second semiconductor layer. The two second patterns are respectively located on both sides of the first gate along the first direction and are electrically connected to the first source and the first drain, respectively.

[0040] In some embodiments, a portion of the gate insulating layer is included between the first source and the second pattern; and / or, a portion of the gate insulating layer is included between the first drain and the second pattern.

[0041] In some embodiments, the first source includes a fourth end that contacts the first semiconductor pattern and a fifth end that does not contact the first semiconductor pattern; at least a portion of the surface of the fifth end near the first substrate contacts the gate insulating layer.

[0042] In some embodiments, the array substrate further includes a second transistor located in the peripheral region. The second transistor includes a second semiconductor pattern located in the semiconductor layer, a second gate, a second source, and a second drain located in the second conductive layer. The second semiconductor pattern includes a plurality of second sub-semiconductor patterns spaced apart along the channel width direction of the second transistor. The second gate, the second source, and the second drain each form a second sub-transistor in the plurality of second sub-semiconductor patterns, and the plurality of second sub-transistors are connected in parallel.

[0043] In some embodiments, the first conductive layer further includes a second light-shielding pattern located in the peripheral region, wherein the orthographic projection of the second semiconductor pattern on the first substrate is within the range of the orthographic projection of the second light-shielding pattern on the first substrate.

[0044] In some embodiments, the first conductive layer further includes a second light-shielding pattern located in the peripheral region. The second light-shielding pattern includes a plurality of openings. The orthographic projections of the second source and the second drain on the first substrate respectively coincide with at least one of the openings on the first substrate, and the orthographic projection of the second gate on the first substrate does not coincide with the openings on the first substrate.

[0045] In some embodiments, the second light-shielding pattern is electrically connected to the second gate.

[0046] In some embodiments, the spacing between the second gate and the second source along the channel length direction of the second transistor is not equal to the spacing between the second gate and the second drain along the channel length direction of the second transistor.

[0047] In some embodiments, the array substrate further includes a first passivation layer, which is located on the side of the second conductive layer away from the first substrate and is in contact with the first passivation layer; the first passivation layer includes a plurality of sublayers with different materials, and the stress of the first passivation layer is in the range of -4000Pa to -100Pa.

[0048] In some embodiments, the first passivation layer includes a first sublayer and a second sublayer stacked together, the second sublayer being located on the side of the first sublayer away from the first substrate; one of the first sublayer and the second sublayer is made of a silicon oxide compound (e.g., silicon monoxide and / or silicon dioxide), and the other is made of a silicon nitride compound (Si). x N y ).

[0049] In some embodiments, the second sublayer comprises 0.3% to 2.0% w / w of silicon-hydrogen; or, the second sublayer comprises 8% to 15% w / w of silicon-hydrogen; or, the second sublayer comprises 1% to 10% w / w of silicon-hydrogen.

[0050] In some embodiments, the thickness of the first sublayer is 100 nm to 300 nm; and / or, the thickness of the second sublayer is 150 nm to 500 nm.

[0051] In some embodiments, the first passivation layer further includes a third sublayer located on the side of the second sublayer away from the first substrate, the material of the third sublayer being silicon nitride.

[0052] In some embodiments, the second sublayer comprises 0.3% to 2.0% w / w of silicon-hydrogen; and the third sublayer comprises 8% to 15% w / w of silicon-hydrogen.

[0053] In some embodiments, the thickness ratio of the second sublayer to the third sublayer is 1:4 to 1:1. The thickness of the first sublayer is 100 nm to 300 nm. The total thickness of the second and third sublayers is 150 nm to 500 nm.

[0054] In some embodiments, the array substrate further includes a first passivation layer, a planarization layer, a second passivation layer, and a second electrode layer, sequentially disposed on the side of the second conductive layer away from the first substrate along a direction away from the first substrate. The array substrate also includes multiple touch signal lines, multiple touch electrodes located on the first electrode layer, and multiple connection electrodes located on the second electrode layer. The connection electrodes are electrically connected to the corresponding touch signal lines and touch electrodes, respectively.

[0055] In some embodiments, the array substrate further includes a fourth via, through which the connection electrode is electrically connected to the touch signal line and the touch electrode. The orthographic projection of the touch electrode on the first substrate partially coincides with the orthographic projection of the connection electrode on the first substrate. The touch signal line and the touch electrode are located on two different layers.

[0056] In some embodiments, the array substrate further includes a third passivation layer and a touch electrode layer. The third passivation layer is located on the side of the second electrode layer away from the first substrate. The touch electrode layer is located on the side of the third passivation layer away from the first substrate. The plurality of touch signal lines are located on the touch electrode layer, and the touch signal lines are connected to the connection electrode through a fifth via penetrating the third passivation layer. The connection electrode is electrically connected to the touch electrode through a sixth via penetrating the second passivation layer.

[0057] On the other hand, a display panel is provided, comprising an array substrate, a color filter substrate, and a liquid crystal layer as described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is disposed between the color filter substrate and the array substrate. In some embodiments,

[0058] In another aspect, a display device is provided. The display device may include the aforementioned display panel and backlight module. The backlight module is disposed on the backlight side of the display panel. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0060] Figure 1 is a schematic diagram of the structure of a display device according to some embodiments;

[0061] Figure 2 is a structural diagram of a display device according to some embodiments;

[0062] Figure 3 is a schematic diagram of a planar structure of an array substrate according to some embodiments;

[0063] Figure 4 is a planar structural diagram of an array substrate according to some embodiments;

[0064] Figure 5A is one of the cross-sectional views based on section line AA in Figure 4;

[0065] Figure 5B is another sectional view based on section line AA in Figure 4;

[0066] Figure 6 is a structural diagram of a data line according to some embodiments;

[0067] Figure 7 is a scanning electron microscope image of a data line according to some embodiments;

[0068] Figure 8 is a connection structure diagram of the first source, data line, and first semiconductor pattern according to some embodiments;

[0069] Figure 9 is a scanning electron microscope image of the first source, data line, and first semiconductor pattern;

[0070] Figure 10 is a cross-sectional view of the first through hole according to some embodiments;

[0071] Figure 11 is a scanning electron microscope image of the first via according to some embodiments;

[0072] Figure 12 is a planar structural diagram of a first semiconductor pattern and a first light-shielding pattern according to some embodiments;

[0073] Figure 13 is a planar structural diagram of a first transistor and a first light-shielding pattern according to some embodiments;

[0074] Figure 14 is a structural diagram of a gate line according to some embodiments;

[0075] Figure 15 is another structural diagram of the gate wires according to some embodiments;

[0076] Figure 16 is a planar structural diagram of the second via according to some embodiments;

[0077] Figure 17 is a cross-sectional structural diagram of the second through hole according to some embodiments;

[0078] Figure 18 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0079] Figure 19 is another planar structure diagram of the array substrate according to some embodiments;

[0080] Figure 20 is another cross-sectional view of the array substrate according to some embodiments;

[0081] Figure 21 is another cross-sectional view of an array substrate according to some embodiments;

[0082] Figure 22 is a planar structural diagram of a second transistor according to some embodiments;

[0083] Figure 23 is another sectional view based on section line BB in Figure 22;

[0084] Figure 24 is a planar structural diagram of a second transistor according to some embodiments;

[0085] Figure 25 is another sectional view based on section line CC in Figure 24;

[0086] Figure 26. Scanning electron microscope image of an array substrate with inorganic layer and gate separated;

[0087] Figure 27 Scanning electron microscope image of an array substrate where the gates have not separated;

[0088] Figure 28 is a schematic diagram of the structure of an array substrate according to some embodiments;

[0089] Figure 29 is a scanning electron microscope image of an array substrate according to some embodiments;

[0090] Figure 30 shows the IV (current-voltage) curves of the transistors in the relevant array substrate;

[0091] Figure 31 is an IV (current-voltage) curve of a transistor in an array substrate according to some embodiments;

[0092] Figure 32 is a structural diagram of an array substrate according to some embodiments;

[0093] Figure 33 is a structural diagram of a portion of the peripheral region of an array substrate according to some embodiments;

[0094] Figure 34 is a cross-sectional view along line EE in Figure 33;

[0095] Figure 35 is an IV (current-voltage) curve of a third transistor in the peripheral region of an array substrate according to some embodiments;

[0096] Figure 36 is an IV (current-voltage) curve of a second transistor in the peripheral region of an array substrate according to some embodiments;

[0097] Figure 37 is a structural diagram of an array substrate according to some embodiments;

[0098] Figure 38 is another structural diagram of the array substrate according to some embodiments;

[0099] Figure 39 is another structural diagram of an array substrate according to some embodiments;

[0100] Figure 40 is another structural diagram of an array substrate according to some embodiments. Detailed Implementation

[0101] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0102] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0103] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0104] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0105] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0106] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0107] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0108] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0109] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0110] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0111] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0112] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0113] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0114] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0115] Referring to FIG1, an embodiment of the present disclosure provides a display device, the display device 1000 being a product having image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0116] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.

[0117] In some embodiments, the above-mentioned display device may be a liquid crystal display (LCD). Referring to FIG2, the liquid crystal display device 1000 may include a display panel 1100, a backlight module 1200, and a driving circuit board 1300. The display panel 1100 is disposed on the light-emitting side of the backlight module 1200. The driving circuit board 1300 may be electrically connected to the backlight module 1200 and the display panel 1100 respectively. The driving circuit board 1300 may be used to transmit control signals to the backlight module 1200 and the display panel 1100 to control the backlight module 1200 to emit light and to control the display panel 1100 to adjust the grayscale of each sub-pixel. In addition, the display device 1000 may also include, but is not limited to, a touch structure, an under-display camera, and an under-display fingerprint recognition sensor, so that the display device 1000 can realize various functions such as touch, photography, video recording, or fingerprint recognition, which will not be listed here.

[0118] Referring to Figure 2, the driver circuit board 1300 may include, for example, a timing controller (TCON), a power management chip (DC / DC), a gate driver chip, and an adjustable resistor voltage divider circuit (generating Vcom). Of course, the driver circuit board 1300 may also include other circuit structures, which will not be listed here. The driver circuit board 1300 may be located on the side of the backlight module 1200 away from the display panel 1100, or it may be at least partially located on the side of the backlight module 1200. The position of the driver circuit board 1300 shown in the figure is only one example.

[0119] The backlight module 1200 can be a direct-lit backlight module 1200 or an edge-lit backlight module 1200, wherein the backlight module 1200 is used to emit light and provide a light source for the display panel 1100. Exemplarily, the driving circuit board 1300 can control the brightness of the backlight module 1200 and the grayscale of each sub-pixel in the display panel. In one example, the backlight module 1200 may include multiple light-emitting chips, which can be light-emitting diodes, such as mini-LEDs or micro-LEDs, where the size of a mini-LED is approximately 100μm to 300μm and the size of a micro-LED is approximately less than 100μm. Of course, the type of light-emitting chip is not limited to these, and any other suitable light-emitting chip can be used.

[0120] Referring again to Figure 2, the display panel 1100 may include an array substrate 100 and a color filter substrate 200 disposed opposite to each other, and a liquid crystal layer 300 located between the array substrate 100 and the color filter substrate 200. Of course, the structure of the display panel 1100 is not limited to this, and the display panel 1100 may also include other structures, as long as the same technical concept is adopted.

[0121] For example, the display panel 1100 may further include a first alignment film (not shown) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown) disposed on the side of the color filter substrate 200 near the liquid crystal layer 300. The color filter substrate 200 may include a second substrate, a black matrix disposed on the second substrate, and a color filter layer. The color filter layer may include at least two different color filters to enable the display panel to display in color; for example, the color filter layer may include a red filter, a blue filter, and a green filter.

[0122] Referring to FIG3, the array substrate 100 may include a display area AA and a peripheral area BB located on at least one side of the display area AA. Exemplarily, the peripheral area BB may be disposed around the display area AA.

[0123] In this context, the display area AA refers to the area of ​​the array substrate 100 in the display panel that is actually used to display images. For example, the display area AA may include a plurality of sub-pixels P arranged in an array, where each sub-pixel P is the smallest light-emitting unit of the display panel. The display area AA may include open areas and non-open areas. An open area refers to the actual light-emitting area of ​​the sub-pixel P; for example, in a liquid crystal display panel, the open area may be approximately the area where the pixel electrodes of the array substrate are located. A non-open area refers to the area between adjacent open areas; for example, in a liquid crystal display panel, the area where the black matrix of the color filter substrate is located, where the orthographic projection of the black matrix onto the array substrate may cover signal lines (such as data signal lines, gate lines, and touch signal lines), pixel circuits (first transistors), and at least a portion of the edges of the pixel electrodes.

[0124] The peripheral area BB refers to the area of ​​the array substrate 100 in the display panel where various circuits (including but not limited to gate drive circuit 110, source drive circuit 120, and switching circuit T2, etc.) and signal lines (including but not limited to clock signal lines and power supply voltage signal lines) are arranged to transmit signals to the display area. Of course, the structure and function of the peripheral area BB are not limited to this, and will not be listed here. In order to increase the transparency of the display panel, opaque or light-blocking components of the display device (including but not limited to batteries, printed circuit boards, and metal frames) can be arranged in the peripheral area BB instead of the display area AA.

[0125] The display panel 1100 includes multiple rows of sub-pixels P arranged in an array along a first direction X. The display panel 1100 also includes multiple columns of sub-pixels P arranged along a second direction Y. The first direction Y intersects the second direction X; for example, the first direction Y and the second direction X are perpendicular to each other.

[0126] Sub-pixel P may include pixel circuitry, pixel electrodes, and a common electrode. Pixel circuitry may include at least one thin-film transistor (TFT) and a capacitor. For example, pixel circuitry may include a data first transistor, and a capacitor may be formed between the pixel electrodes and the common electrode.

[0127] The array substrate 100 also includes multiple gate lines GL and multiple data signal lines DL. Each gate line GL is electrically connected to the pixel circuit of a row of sub-pixels P, for example, the gate line GL is electrically connected to the first transistor T1 of the row of pixel circuits; each gate line is also electrically connected to a gate driving circuit. Each data signal line DL is electrically connected to the pixel circuit of a column of sub-pixels P, for example, to the first transistor of the column of sub-pixels P. The first transistor is configured to be turned on or off (disconnected) under the control of the scan signal of the gate line GL. When the first transistor is on, it transmits the data signal from the data signal line DL to the pixel electrode. When the first transistor is off, the voltage of the pixel electrode remains constant under the action of the capacitor, and an electric field can be formed between the pixel electrode and the common electrode. This electric field can drive the liquid crystal molecules in the liquid crystal layer to deflect, thereby adjusting the grayscale of the sub-pixel.

[0128] Referring to Figures 4, 5A and 5B, in some embodiments, the array substrate 100 may include a first substrate 10, and a first conductive layer 20, a buffer layer BUF, a semiconductor layer 30, a gate insulating layer GI and a second conductive layer 40 sequentially disposed along a direction perpendicular to and away from the first substrate 10 (from bottom to top in Figure 5A).

[0129] For example, the first substrate 10 can be a transparent substrate, such as a glass substrate. In this way, the light emitted by the backlight module can pass through the first substrate 10, which helps to improve the light transmittance of the array substrate 100.

[0130] The first conductive layer 20 is located on one side of the first substrate 10 (such as the upper side in FIG5A). The first conductive layer 20 includes multiple data signal lines DL, which are distributed at intervals along the first direction X and extend along the second direction Y in general.

[0131] The statement that the data signal line DL extends along the second direction Y means that, macroscopically, the data signal line DL extends along the second direction Y; for example, the line connecting the two ends of the data signal line DL along the second direction Y can be parallel or approximately parallel to the second direction Y. However, from a microscopic structural perspective, the extension direction of the data signal line DL can have a certain angle with the second direction Y. For example, within the range corresponding to the opening area 101 of a row of sub-pixels, the extension direction of the data signal line DL has a first angle α with the second direction Y (see below for the specific structure of the data signal line DL). The data signal line DL can be configured to transmit data signals. The first direction X intersects the second direction Y; for example, the first direction X and the second direction Y are perpendicular to each other.

[0132] The buffer layer BUF is located on the side of the first conductive layer 20 away from the first substrate 10, for example, the buffer layer BUF is located between the first conductive layer 20 and the semiconductor layer 30. The buffer layer BUF can be used to separate the first conductive layer 20 and the semiconductor layer 30 to prevent short circuits between the first conductive layer 20 and the semiconductor layer 30.

[0133] The semiconductor layer 30, also referred to as the active layer or semiconductor material layer, may include a plurality of first semiconductor patterns 31. One first semiconductor pattern 31 may be used to form a first transistor T1. The first semiconductor pattern 31 may include a channel region and a conductor region. The channel region and the conductor region may include the same semiconductor material. The conductor region differs from the channel region in that it undergoes a process to make it more conductive (conductivity enhancement process). The conductor enhancement process includes, but is not limited to, doping and annealing processes. The conductivity of the conductor region differs from that of the channel region. Exemplarily, the channel region may include semiconductor material, and the conductor region may include doped semiconductor material.

[0134] The gate insulating layer GI is located on the side of the semiconductor layer 30 away from the first substrate 10. For example, the gate insulating layer GI can be located between the semiconductor layer 30 and the second conductive layer 40.

[0135] The second conductive layer 40 is disposed on the side of the gate insulating layer GI away from the first substrate 10. The second conductive layer 40 includes a first source S1, a first drain D1 and a first gate G1.

[0136] The second conductive layer 40 further includes multiple gate lines GL extending along the first direction X and spaced apart along the second direction Y. The multiple gate lines GL and multiple data signal lines DL intersect each other on the first substrate 10 to form a grid structure. Each grid of the grid structure defines a sub-pixel P. The sub-pixel P includes an opening region 101, and a non-opening region 102 is included between two adjacent sub-pixels P. The first gate GL of the first transistor T1 is electrically connected to the gate line GL, for example, the first gate GL and the gate line GL are integrally disposed.

[0137] The array substrate 100 also includes a first via V1, which penetrates the gate insulating layer GI and the buffer layer BUF, and exposes at least a portion of the data signal line DL. The array substrate 100 also includes a plurality of first transistors T1 located within the display area AA. Each first transistor T1 includes a first semiconductor pattern 31, a first gate G1, a first source S1, and a first drain D1. A portion of the first source S1 passes through the first via V1 and is electrically connected to the data signal line DL. The first gate G1 of the first transistor T1 is connected to the data signal line DL through the first via, and the first gate G1 of the first transistor T1 is located on the side of the first semiconductor pattern 31 away from the first substrate 10; that is, the first transistor T1 is a top-gate transistor.

[0138] Furthermore, the first source S1 and the first drain D1 of the first transistor T1 are necessarily connected to the first semiconductor pattern 31. For example, the first source S1 and the first drain D1 are respectively connected to the two ends (conductor regions of the first semiconductor pattern 31) along the first direction. For instance, the first via V1 also exposes at least a portion of the first semiconductor pattern 31, and the first source S1 is electrically connected to the first semiconductor pattern 31 through the first via V1. As shown in FIG5A, the array substrate 100 also includes a third via V3. The third via V3 penetrates the gate insulating layer GI and exposes a portion of the first semiconductor pattern 31; the first drain D1 is electrically connected to the first semiconductor pattern 31 through the third via V3.

[0139] In related technologies, data signal lines are typically located on the side of the semiconductor layer away from the substrate; that is, the signal lines are generally located on the upper side of the semiconductor layer. This results in a smaller gap between the signal lines and other electrodes or electrode traces, such as a common electrode (located on the side of the semiconductor layer away from the substrate), which can lead to a large parasitic capacitance between the signal lines and the common electrode. Furthermore, this parasitic capacitance becomes a significant factor limiting the improvement of pixel density and refresh rate in array substrates, and it also increases the power consumption of the array substrate.

[0140] As shown in Figures 4 and 5A, the array substrate 100 provided in the embodiments of this disclosure has data signal lines DL disposed on the side of the semiconductor layer 30 near the first substrate 10. This facilitates increasing the spacing between the data signal lines DL and the common electrode, thereby reducing the parasitic capacitance between the data signal lines DL and the common electrode. This is beneficial for increasing the pixel density and refresh rate of the array substrate 100, and also helps to reduce the power consumption of the data signal lines DL, thus reducing the overall power consumption of the array substrate 100. Furthermore, the first transistor T1 in the display area AA adopts a top-gate transistor design. Compared with a bottom-gate transistor, the top-gate transistor has lower parasitic capacitance and higher on-state current, which can improve the performance of the first transistor T1.

[0141] In some embodiments, the first conductive layer 20 may include a metallic material. The metallic material may include a single-layer metallic structure formed of a single metallic material, such as one of titanium, aluminum, copper, molybdenum, niobium, nickel, and alloys thereof.Alternatively, the metallic material may include a multilayered metallic structure, such as aluminum and aluminum alloy structures and their stacks with metal buffer layers, such as titanium-aluminum-titanium (Ti / Al / Ti) stacked structures, molybdenum-aluminum (Mo / Al) stacked structures, aluminum-molybdenum (Al / Mo) stacked structures, molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structures, molybdenum-aluminum alloy (Mo / Al alloy) stacked structures, aluminum alloy-molybdenum (Al alloy / Mo) stacked structures, and molybdenum-aluminum alloy-molybdenum (Mo / Al) stacked structures. Molybdenum alloy / Mo (Mo) stacked structures can include copper and copper alloys, as well as stacks with metal buffer layers, such as molybdenum-niobium-copper (MoNb / Cu) stacked structures, molybdenum-titanium-copper (MoTi / Cu) stacked structures, molybdenum-nickel-titanium-copper (MTD / Cu) stacked structures, etc.; such as molybdenum-niobium-copper-molybdenum-niobium (MoNb / Cu / MoNb) stacked structures, molybdenum-niobium-copper-molybdenum-nickel-titanium (MoNb / Cu / MTD) stacked structures, and molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD) stacked structures. Molybdenum-titanium-copper-molybdenum-nickel-titanium (MoTi / Cu / MTD) stacked structures, molybdenum-titanium-copper-molybdenum-titanium (MoTi / Cu / MoTi) stacked structures, and other molybdenum alloy-copper-molybdenum alloy structures; these can include copper and copper alloys, as well as their stacks with metal oxide buffer layers, such as indium tin oxide-copper-indium tin oxide (ITO / Cu / ITO), zinc tin oxide-copper-zinc tin oxide (IZO / Cu / IZO), indium oxide-copper-indium oxide (InOx / Cu / InOx), molybdenum alloy-copper-indium tin oxide (MoAlloy / Cu / ITO), titanium-copper-indium tin oxide (Ti / Cu / ITO), and copper alloy-indium tin oxide (CuTi). Mo alloys include, but are not limited to, MoNd, MTD, and MoTi, while Cu alloys include CuTi alloys. Examples of MoNb / Ti alloys include: MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, MoNb / Ti / Cu alloys, and MoNb / Ti / Cu alloys. The following are some of the following stacked structures: molybdenum-titanium-copper (MoTi / Cu) stacked structure, molybdenum-titanium-copper-molybdenum-niobium-titanium (MoTi / Cu / MTD) stacked structure, molybdenum-titanium-copper-molybdenum-titanium (MoTi / Cu / MoTi) stacked structure, molybdenum-neodymium-copper stacked structure, MoNb-copper-MoNb stacked structure, AlNb-molybdenum-AlNd stacked structure, titanium-copper (Ti / Cu) stacked structure, copper-titanium (Cu / Ti) stacked structure, titanium-copper-titanium (Ti / Cu / Ti) stacked structure, and single or stacked CuTi alloys, or combinations thereof.

[0142] The buffer layer (BUF) can be a single-layer structure (such as a single layer of silicon oxide), a two-layer structure (such as a stacked structure of silicon nitride and silicon oxide), or a three-layer structure (such as a stacked structure of silicon nitride, silicon oxynitride, and silicon oxide). The thickness of the buffer layer (BUF) can be... Within a certain range. For example, silicon nitride can be a single layer or stacked into layers with a thickness ranging from... Two or three layers; the thickness of silicon oxynitride is... Within a certain range; silicon dioxide can be located on the top layer, in contact with the film layer (semiconductor layer 30) subsequently formed on the buffer layer BUF, and the thickness can be [missing information].

[0143] The semiconductor layer 30 may be made of metal oxide materials and / or metal oxide nitride materials. Metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In₂O₃:Sn, In₂O₃:Mo, Cd₂SnO₄, ZnO:Al, TiO₂:Nb, and Cd-Sn-O. Metal oxide nitride materials include, but are not limited to: zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. The material of the semiconductor layer 30 can be amorphous, partially crystalline, single-crystal or polycrystalline. In addition, the semiconductor layer 30 can be a single-layer film structure or a multi-layer film structure.

[0144] The gate insulating layer GI can be a single-layer structure (e.g., a single-layer silicon oxide), a two-layer structure (e.g., a stacked structure of silicon nitride and silicon oxide), or a three-layer structure (e.g., a stacked structure of silicon nitride, silicon oxynitride, and silicon oxide). The thickness of the gate insulating layer GI is... Within a certain range. Silicon oxide can be a single layer or stacked into two or three layers. The thickness of silicon oxynitride is within... to Within a certain range. Silicon dioxide can be located at the top layer, in contact with the subsequently formed semiconductor layer, with a thickness of [missing information]. to The gate insulating layer GI may extend only within a portion of the second conductive layer 40 (as shown in Figure 5A), and the fabrication process of the array substrate includes patterning the gate insulating layer GI using the second conductive layer 40 as a mask. Alternatively, the gate insulating layer GI may extend substantially over the entire array substrate, meaning that the fabrication process of the array substrate does not include patterning the gate insulating layer GI using the second conductive layer 40 as a mask (as shown in Figure 5B).

[0145] The second conductive layer 40 can be a single-layer metal structure or a metal stack structure formed by multiple metal layers. The single-layer metal structure and the metal stack structure can be referred to the first conductive layer 20 above, and will not be repeated here in the embodiments of this disclosure.

[0146] As shown in FIG5A, in some embodiments, the array substrate 100 may further include a first passivation layer PVX1, a planarization layer PLN, a first electrode layer 51, a second passivation layer PVX2, a second via V2, and a second electrode layer 52. The first passivation layer PVX1 is located on the side of the second conductive layer 40 away from the first substrate 10. The planarization layer PLN is located on the side of the first passivation layer PVX1 away from the first substrate 10. The first electrode layer 51 is located on the side of the planarization layer PLN away from the first substrate 10. The second passivation layer PVX2 is located on the side of the first electrode layer 51 away from the first substrate 10. The second electrode layer 52 is located on the side of the second passivation layer PVX2 away from the first substrate 10. That is, the first passivation layer PVX1, the planarization layer PLN, the first electrode layer 51, the second passivation layer PVX2, the second via V2, and the second electrode layer 52 are sequentially arranged along a direction away from the first substrate 10. The first electrode layer 51 can be a common electrode layer (COM electrode layer), and the second electrode layer 52 can be a pixel electrode layer, which includes a plurality of pixel electrodes 521.

[0147] The array substrate also includes a second via V2, which penetrates the second passivation layer PVX2, the planarization layer PLN, and the first passivation layer PVX1, and exposes at least a portion of the first drain D1. A second electrode 53 passes through the second via V2 and is electrically connected to the first drain D1. The first electrode layer 51 can be a common electrode layer, and the second electrode 53 can be a pixel electrode.

[0148] Referring to Figures 4, 6, and 7, in some embodiments, the data signal line DL includes a first extension segment DL1 and a second extension segment DL2 alternately connected along a second direction Y. The first extension segment DL1 is disposed opposite to the opening region 101 in the first direction X, or in other words, the first extension segment DL1 and the opening region 101 are disposed side by side along the first direction X. The second extension segment DL2 is located between two adjacent first extension segments DL1. For example, the second extension segment DL2 may be disposed opposite to structures such as the first transistor T1, the first via V1, and the second via V2 in the first direction X, and the second extension segment DL2 coincides with the orthographic projection portion of the gate line GL on the first substrate 10.

[0149] The line width (dimension perpendicular to the extension direction of the first extension segment DL1) D1 is equal at all points along the second direction Y of the first extension segment DL1, meaning that the portion of the data signal line DL located between the opening regions 101 (the first extension segment DL1) has a uniform line width. The second extension segment DL2 includes a first sub-segment DL21 and a second sub-segment DL22. The line width L2 of the first sub-segment DL21 is greater than the line width L3 of the second sub-segment DL22, i.e., L2 is greater than L3. Furthermore, the line width L2 of the first sub-segment DL21 is greater than the line width L1 of the first extension segment DL1; i.e., L2 is greater than L1. The first sub-segment DL21 is configured to be electrically connected to the first source S1. Setting the linewidth of the first sub-segment DL21 to be greater than that of the second sub-segment DL22 is beneficial to increasing the area of ​​the first sub-segment DL21, thereby increasing the overlap area between the first source S1 and the first sub-segment DL21, reducing the contact resistance between them, and also reducing the positional accuracy requirements between the first semiconductor pattern 31 and the first sub-segment DL21. It is also easier to make the orthographic projection of part of the first semiconductor pattern 31 on the first substrate 10 only cover part of the orthographic projection area of ​​the first sub-segment DL21 on the first substrate 10.

[0150] Referring again to Figures 4 and 6, the linewidth L2 of the first sub-segment DL21 is greater than the linewidth L1 of the first extension segment DL1 (L2 is greater than L1), which also helps to reduce the linewidth L1 of the first extension segment DL1. By setting the data signal line DL to have different linewidths at different positions, and ensuring that the linewidth of the first extension segment DL1 is uniform, it is beneficial to reduce the linewidth L2 of the first extension segment DL1, making the linewidth L1 of the first extension segment DL1 extremely narrow. This helps to increase the aperture ratio of the array substrate 100, that is, to increase the area ratio of the aperture region 101 in the display area AA of the array substrate 200.

[0151] In addition, the first sub-segment DL22 is used to connect with the first source S1. Setting the line width L2 of the first sub-segment DL21 to be greater than the line width L3 of the second sub-segment DL22 is beneficial to increase the area of ​​the first sub-segment DL21, thereby increasing the overlap area between the first source S1 and the first sub-segment DL21 and reducing the contact resistance between them.

[0152] The second sub-segment DL22 and the gate line GL at least partially overlap in their orthographic projections on the first substrate 10. The linewidth L3 of the second sub-segment DL22 is less than or equal to the linewidth L1 of the first extension segment DL1, i.e., L3 is less than L1. This reduces the facing area between the second sub-segment DL22 and the gate line GL, thereby reducing the parasitic capacitance generated between them and helping to reduce the power consumption of the array substrate.

[0153] As shown in Figures 4, 6, and 7, in some embodiments, the linewidth L1 of the first extension segment DL1 can be 2 μm to 4 μm. The first extension segment DL is located between two adjacent opening regions 101 along the first direction X. The linewidth L1 of the first extension segment DL directly affects the area of ​​the opening region 101. When the linewidth L1 of the first extension segment DL1 is in the range of 2 μm to 4 μm, the influence of the first extension segment DL1 on the aperture ratio of the array substrate 100 can be greatly reduced, which is beneficial to improving the aperture ratio of the array substrate 100.

[0154] For example, the line width L1 of the first extension segment DL1 can be 2μm to 2.5μm; for instance, the line width L1 of the first extension segment DL1 can be 2μm, 2.2μm, 2.3μm or 2.5μm, etc.

[0155] For example, the line width L1 of the first extension segment DL1 can be 2.5μm to 3μm. For instance, the line width L1 of the first extension segment DL1 can be 2.5μm, 2.6μm, 2.8μm or 3.0μm, etc.

[0156] For example, the line width L1 of the first extension segment DL1 can be 2μm to 3μm. For instance, the line width L1 of the first extension segment DL1 can be 2μm, 2.3μm, 2.5μm, 2.8μm or 3.0μm, etc.

[0157] For example, the line width L1 of the first extension segment DL1 can be 3μm to 4μm. For instance, the line width L1 of the first extension segment DL1 can be 3μm, 3.3μm, 3.5μm, 3.8μm or 4μm, etc.

[0158] Referring to Figures 4 and 6, in some embodiments, a first extension segment DL1 includes at least two third sub-segments DL11. The extension direction of the third sub-segments DL11 forms a first angle α with the second direction Y, that is, the third sub-segments DL11 are inclined relative to the second direction Y, and the inclination directions of two adjacent third sub-segments DL11 along the second direction Y are opposite. For example, in the same first extension segment DL1, the upper end of the upper third sub-segment DL11 is inclined to the right relative to the lower end, and the upper end of the lower third sub-segment DL11 is inclined to the left relative to the lower end. This is beneficial for increasing the transmittance and aperture ratio of the array substrate.

[0159] In some embodiments, the first included angle α between the first extension segment DL1 and the second direction Y can be 5° to 11°. When the first included angle is in the range of 5° to 11°, the transmittance and aperture ratio of the array substrate 100 can reach a large value.

[0160] For example, the first included angle α can be 5° to 8°, such as 5°, 6°, 7.5° or 8°. Alternatively, for example, the first included angle α can be 8° to 11°, such as 8°, 9°, 10° or 11°, etc. The embodiments of this disclosure will not be listed one by one.

[0161] Referring to Figures 8 and 9, in some embodiments, the orthographic projection of the first semiconductor pattern 31 onto the first substrate 10 at least partially overlaps with the orthographic projection of the data signal line DL onto the first substrate 10. Thus, during the fabrication of the array substrate 100 (see below), the formation of a deep first via V1 between the first semiconductor pattern 31 and the first signal line DL can be avoided, reducing the difficulty of the first source S1 climbing the sidewall of the first via V1, ensuring the continuity of the first source S1 within the first via V1, and guaranteeing the connection stability between the first semiconductor pattern 31 and the first signal line DL.

[0162] For example, the orthographic projection of the end of the first semiconductor pattern 31 near the data signal line DL (the left end of the first semiconductor pattern 31 in Figures 8 and 9) onto the first substrate 10 is located within the orthographic projection range of the data signal line DL onto the first substrate 10. Furthermore, the orthographic projection of the first semiconductor pattern 31 onto the first substrate 10 does not completely cover the data signal line DL in the first direction X; that is, the portion along the first direction X where the orthographic projections of the first semiconductor pattern 31 and the data signal line DL overlap is smaller than the linewidth of the data signal line DL. This ensures that the first via V1 simultaneously exposes a portion of the first semiconductor pattern 31 and a portion of the data signal line DL, which is beneficial for the first source S1 to overlap with both the first semiconductor pattern 31 and the data signal line DL.

[0163] The first via V1 includes a first region Z1, a second region Z2, and a third region Z3 connected sequentially along a direction away from the first source S1 (from left to right in Figures 8 and 9). The orthographic projection of the first region Z1 onto the first substrate 10 partially coincides with the orthographic projection of the first semiconductor pattern 31 onto the first substrate 10, but does not coincide with the orthographic projection of the data signal line DL onto the first substrate 10. In other words, the first region Z1 is the portion of the first via V1 that overlaps only with the first semiconductor pattern 31. The orthographic projection of the second region Z2 onto the first substrate 10 coincides with the orthographic projections of both the first semiconductor pattern 31 and the data signal line DL onto the first substrate 10; that is, the second region Z2 is the area within the first via V1 where the first semiconductor pattern 31 and the data signal line DL overlap. The orthographic projection of the third region Z3 onto the first substrate 10 does not coincide with the orthographic projection of the first semiconductor pattern 31 onto the first substrate 10, but coincides with the orthographic projection of the data signal line DL onto the first substrate 10.

[0164] Referring to Figures 8 and 10, the first source S1 covers at least a portion of the second region Z2 and at least a portion of the third region Z3. This ensures that the first source S1 is in contact with the first semiconductor pattern 31 and the data signal line DL, respectively. Furthermore, the first source S1 does not overlap with at least a portion of the first region Z1. Thus, during the doping process of the semiconductor layer 30 using the second conductive layer 40 as a mask, the portion of the first semiconductor pattern 31 adjacent to the first source S1 within the first region Z1 can be doped into a conductor, ensuring that the first source S1 can connect to the conductor-enhanced region of the first semiconductor pattern 31.

[0165] In one example, as shown in Figures 8 and 10, the first source S1 covers a portion of the second region Z2, the third region Z3, and the first region Z1, and at least a portion of the first source S1 does not overlap with the first region Z1. This helps to increase the contact area between the first source S1 and the data signal line DL, and reduce the contact resistance between the first source S1 and the data signal line DL. Simultaneously, it avoids contact between the first source S1 and the first semiconductor pattern 31 at the edges and on the slope between the first region Z1 and the second region Z2, ensuring reliable connection between the first source S1 and the first semiconductor pattern 31.

[0166] As shown in Figure 10, in some embodiments, the first source S1 includes a fourth end (left end) that contacts the first semiconductor pattern 31 and a fifth end (right end) that does not contact the first semiconductor pattern 311; at least a portion of the surface of the fifth end near the first substrate 10 contacts the gate insulating layer GI. That is, at least a portion of the first source S1 is located outside the range of the first via V1. For example, in Figures 8 and 10, the fifth end of the first source S1 is located outside the first via V1, and the surface of the portion of the first source S1 outside the first via V1 near the first substrate 10 contacts the gate insulating layer GI. This increases the contact area between the first source S1 and the data signal line DL, and reduces the contact resistance between the first source S1 and the data signal line DL.

[0167] As shown in Figures 8 and 9, in some embodiments, the orthographic projection of the first via V1 on the first substrate 10 can be circular or elliptical, or the orthographic projection of the first via V1 on the first substrate 10 is approximately circular or approximately elliptical.

[0168] In some embodiments, referring to Figures 8 and 9, the first semiconductor pattern 31 includes a sawtooth structure at the edge of the second region Z2 near the first region Z1; in other words, the edge of the second region Z2 near the first region Z1 includes multiple irregular undulating structures, forming a sawtooth-like structure. The buffer layer BUF has an undulating structure at the boundary of the data signal line DL, thereby at least one of the films generally disposed in the second region Z2 near the first region Z1 includes a sawtooth structure 28. Exemplarily, the first semiconductor pattern 31 may be serrated at the edge of the second region Z2 near the first region Z1, and / or the first source S1 may be serrated at the edge of the second region Z2 near the first region Z1. It should be noted that Figure 13 is only used to illustrate the morphology of the sawtooth structure and does not specifically refer to any particular film layer. For example, the sawtooth structure may be located on the first semiconductor pattern 31 and / or the first source S1.

[0169] Referring to Figures 10 and 11, in the first region Z1, the array substrate 100 includes a buffer layer BUF, a first semiconductor pattern 31, and a first source S1 stacked together. In the second region Z2, the array substrate 100 includes a data signal line DL, a buffer layer BUF, the first semiconductor pattern 31, and a first source S1 stacked together. In the third region Z3, the array substrate 100 includes a data signal line DL and a first source S1 stacked together.

[0170] Based on the film layer relationship at the first via V1 shown in Figures 10 and 11, in the second region Z2, at least one of the buffer layer BUF, the first semiconductor pattern 31, and the first source S1 forms a protrusion structure 24. The protrusion structure 24 protrudes away from the first substrate 10 relative to the first region Z1 and / or the third region Z3. For example, as shown in Figure 10, in the second region Z2, the buffer layer BUF, the first semiconductor pattern 31, and the first source S1 all form a protrusion structure 24. The protrusion structure 24 protrudes upward. For example, in the second region Z2, the protrusion structure 24 formed by the buffer layer BUF protrudes upward relative to the first region Z1 and the third region Z3; the protrusion structure 24 formed by the first semiconductor pattern 31 protrudes upward relative to the first region Z1 and the third region Z3; and the protrusion structure 24 formed by the first source S1 protrudes upward relative to the first region Z1 and the third region Z3.

[0171] In some embodiments, referring to FIG10, a portion of the first semiconductor pattern 31 extends into the first source S1.

[0172] For example, during the formation of the first via V1 in the patterned gate insulating layer GI, a portion of the buffer layer BUF located on the side of the first semiconductor pattern 31 near the first substrate 10 is removed (forming an undercut structure), and a suspended structure is formed at the end of the first semiconductor pattern 31 away from the first drain D1. Then, during the fabrication of the first source S1, the first source S1 fills the aforementioned removed portion of the buffer layer BUF, and the first source S1 covers the suspended portion of the first semiconductor pattern 31, forming a structure as shown in FIG10, where a portion of the first semiconductor pattern 31 extends into the first source S1.

[0173] Referring to Figure 12, in some embodiments, the first semiconductor pattern 31 includes a first portion 32, a second portion 33, and a third portion 34 connected sequentially along a first direction X. The first portion 32 is located on the side of the second portion 33 near the first via V1, that is, in Figure 12, the first portion 32, the second portion 33, and the third portion 34 are connected sequentially from right to left. The ends (lower ends) of the first portion 32, the second portion 33, and the third portion 34 along the second direction Y near the gate line GL are approximately flush, and the ends (upper ends) of the first portion 32 and the third portion 34 along the second direction Y away from the gate line GL extend beyond the boundary of the first portion 32. In this way, the first semiconductor pattern 31 forms a U-shaped structure, so the first portion 32 and the third portion 34 are no longer limited to being arranged along the first direction X, and the arrangement space of the first portion 32 and the third portion 34 is more flexible, which is beneficial to improving the pixel density of the array substrate 100.

[0174] For example, at least a portion of the second portion 33 can be used to form the channel structure of the first transistor T1, and the first portion 32 and the third portion 34 can be used to form the source contact region and the drain contact region of the first transistor T1, respectively. That is, at least a portion of the second portion 32 can include undoped semiconductor material, and at least a portion of the first portion 32 and the third portion 34 can include doped semiconductor material.

[0175] Referring again to Figure 12, the upper boundary of the second portion 33 away from the gate line GL (the upper boundary of the second portion 33 in Figure 12) is approximately an arc when projected onto the first substrate 10, and the arc is concave towards the side (lower side) closer to the gate line GL. In other words, the upper boundary of the second portion 33 forms a downwardly concave arc, which avoids the formation of a sharp corner between the second portion 33, the first portion 32, and the fourth portion 34.

[0176] In some embodiments, the first part 32 and the third part 34 are arranged asymmetrically. The first part 32 and the third part 34 can be flexibly sized according to the size of their respective spaces, making the arrangement of the first part 32 and the third part 34 more flexible.

[0177] For example, as shown in FIG12, the maximum dimension D4 of the first portion 32 along the first direction X is smaller than the maximum dimension D5 of the third portion along the first direction, that is, D4 is smaller than D5. For the same sub-pixel, the first transistor T1 (gate G1) is located in two adjacent data signal lines, closer to the side of the data signal line DL connected to the first transistor T1. Therefore, the space between the first gate G1 and the data signal line DL is smaller. Based on this, setting the maximum dimension D4 of the first portion 32 along the first direction X to be smaller than the maximum dimension D5 of the third portion 34 along the first direction X is more conducive to the space setting of the first portion 32.

[0178] As shown in Figure 12, the maximum dimension D6 of the first part 32 along the second direction Y is either smaller or larger than the maximum dimension D7 of the third part D7 along the second direction Y. That is, the dimensions of the first part 32 and the third part 34 along the second direction Y are not equal. This means that the first part 32 and the third part 34 are not limited to having the same size, which is beneficial to improving the flexibility of the arrangement space of the first part 32 and the third part 34 and helps to increase the pixel density of the array substrate 100.

[0179] In some embodiments, as shown in Figures 12 and 13, the first conductive layer 20 further includes a plurality of first light-shielding patterns 21. The portion (39) where the orthographic projections of the first gate G1 and the first semiconductor pattern 31 on the first substrate 10 overlap is located within the range of the orthographic projection of the first light-shielding pattern 21 on the first substrate 10. The portion of the first semiconductor pattern 31 that overlaps with the orthographic projection of the first gate G1 on the first substrate 10 can be roughly considered as the region of the channel structure 39. In other words, the orthographic projection of the channel structure 39 of the first transistor T1 on the first substrate 10 is located within the range of the orthographic projection of the first light-shielding pattern 21 on the first substrate 10. In this way, the risk of light directly irradiating the channel structure 39 of the first semiconductor pattern 31 can be reduced, and the stability of the switching characteristics (on-state voltage) of the first transistor T1 in the light environment can be improved.

[0180] Exemplarily, the orthographic projection of the first light-shielding pattern 21 on the first substrate 10 completely covers the orthographic projection of the channel structure 39 on the first substrate 10, and at least a portion of the boundary of the orthographic projection of the first light-shielding pattern 21 on the first substrate 10 does not coincide with the boundary of the orthographic projection of the channel structure 39 on the first substrate 10. That is, the area of ​​the first light-shielding pattern 21 is larger than the area of ​​the channel structure 39, so that the first light-shielding pattern 21 can block as much light as possible from the channel structure 39. Exemplarily, the orthographic projection of the gate GI on the first substrate 10 is located within the range of the orthographic projection of the first light-shielding pattern 21 on the first substrate 10.

[0181] As shown in Figures 12 and 13, the orthographic projection of the second portion 33 of the first semiconductor pattern 31 onto the first substrate 10 is within the range of the orthographic projection of the first light-shielding pattern 21 onto the first substrate 10. At least a portion of the first portion 32 that is away from the second portion 33 and at least a portion of the third portion 34 that is away from the second portion 33 do not coincide with the orthographic projection of the first light-shielding pattern 21 onto the first substrate 10.

[0182] For example, as shown in FIG12, the orthographic projections of the two ends of the second portion 33 along the first direction X onto the first substrate 10 substantially coincide with the orthographic projections of the two ends of the first light-shielding pattern 21 along the first direction X onto the first substrate 10, that is, the two ends of the second portion 33 along the first direction X are substantially flush with the two ends of the first light-shielding pattern 21 along the first direction X. The orthographic projections of the two ends of the second portion 33 along the second direction Y onto the first substrate 10 are spaced apart from the orthographic projections of the two ends of the first light-shielding pattern 21 along the second direction Y onto the first substrate 10. In other words, the second portion 33 is located in the middle of the first light-shielding pattern 21 along the second direction Y.

[0183] Referring again to Figures 12 and 13, the portion (channel structure 39) where the orthographic projections of the first gate G1 and the first semiconductor pattern 31 on the first substrate 10 overlap is spaced apart from the two ends of the first light-shielding pattern 21 along the first direction X. This enhances the light-shielding effect of the first light-shielding pattern 21 on the channel structure 39 of the first transistor T1, reducing the risk of lateral light entering the channel structure 39.

[0184] As shown in Figure 12, within a sub-pixel, along the second direction Y and away from the gate line GL (from bottom to top in Figure 12), the first portion 32 includes a first end 321 away from the gate line, the third portion 34 includes a second end 341 away from the gate line GL, and the first light-shielding pattern 21 includes a third end 211 away from the gate line GL. At least one of the first end 321 and the second end 341 is at a greater distance from the gate line GL than the third end 211 is at a greater distance from the gate line GL. Specifically, the distance between the first end 321 and the gate line GL is D16, the distance between the second end 341 and the gate line GL is D16, and the distance between the third end 211 and the gate line GL is D18. That is, D16 is greater than D18, and / or, D17 is greater than D18.

[0185] As shown in Figures 12 and 13, the orthographic projection of the end of the first portion 32 of the first semiconductor pattern 31 away from the gate line GL (the third end 211) on the first substrate 10, along the second direction Y and away from the gate line GL (from bottom to top), extends beyond the boundary of the first light-shielding pattern 21 away from the gate line GL. In other words, the upper end of the first portion 32 extends beyond the upper boundary of the first light-shielding pattern 21 along the second direction Y. And / or, the orthographic projection of the end of the third portion 34 away from the gate line GL on the first substrate 10, along the second direction Y and away from the gate line GL, extends beyond the boundary of the first light-shielding pattern 21 away from the gate line GL. In other words, the upper end of the third portion 34 extends beyond the upper boundary of the first light-shielding pattern 21 along the second direction Y.

[0186] As shown in Figure 13, the orthographic projection of the first gate G1 onto the first substrate 10 is located within the range of the orthographic projection of the first light-shielding pattern 21 onto the first substrate 10, and the end of the first gate G1 away from the gate line GL is spaced apart from the boundary of the first light-shielding pattern 21 away from the gate line GL. In this way, the first gate G1 can also be completely blocked by the first light-shielding pattern 21, which can reduce the light directly incident on the first gate G1 from the backlight module, thereby reducing the risk of the first gate G1 reflecting light towards the channel structure 39 near the surface (lower surface) of the first substrate 10, and improving the characteristic stability of the first transistor T1.

[0187] Of course, as shown in Figure 5B, in some other embodiments, the first conductive layer 20 may not have the first light-shielding pattern 21. In this case, the semiconductor layer 30 can be formed using a material with stronger light stability. For example, the material of the semiconductor layer 30 may include a high-mobility metal oxide semiconductor material (HMOS). High-mobility metal oxide semiconductor materials also have good light stability, which is beneficial to improving the light stability of the first thin-film transistor T10. High-mobility metal oxide semiconductor materials include, but are not limited to, rare-earth element-doped IZO and IGZO, or oxide semiconductor materials with trace amounts of rare earth elements. For example, InXYO:Ln, where Ln includes lanthanide rare earth elements such as Pr and Tb. X and Y are metal elements, such as one or more of Ga, Sn, Zn, Ta, and W. The concentration of rare earth element doping can be between 0.1% and 2%.

[0188] Referring to FIG14, in some embodiments, the line connecting the first transistor T1, the first via V1 and the second via V2 on the first substrate 10 is arranged along the first direction X, or is approximately U-shaped. In this way, the size of the first transistor T1, the first via V1 and the second via V2 in the second direction Y can be reduced to the greatest extent, and the size of the non-aperture region 102 in the second direction Y can be reduced, which is beneficial to improving the aperture ratio of the array substrate 100.

[0189] Referring to Figure 14, the second conductive layer 40 further includes multiple gate lines GL extending along the first direction X and spaced apart along the second direction Y. Each gate line GL includes a third extension GL1 and a fourth extension GL2. The third extension GL1 and the second via V2 are disposed opposite each other along the second direction Y. The fourth extension GL2 is offset from the data signal line DL, the first via V1, and the first gate G1 in the first direction X. The fourth extension GL2 does not overlap with the data signal line DL, the first via V1, or the first gate G1 in the second direction Y. The linewidth D8 of the third extension GL1 is smaller than the linewidth D9 of the fourth extension GL2, i.e., D8 < D9. This increases the spacing between the second via V2 and the gate line GL, thereby reducing not only the parasitic capacitance between the gate line GL and the first drain D1 and the second electrode 53, but also the risk of a short circuit between the gate line GL and the first drain D1 and the second electrode 53. In addition, it is beneficial to increase the arrangement space of the second via V2. The second via V2 can be set on the side closer to the gate line GL, which is beneficial to increase the pixel density of the array substrate 100.

[0190] Referring to Figure 15, in some embodiments, the gate line GL further includes a fifth extension GL3. The orthographic projection of the fifth extension GL3 onto the first substrate 10 at least partially coincides with the orthographic projection of the data signal line DL onto the first substrate 10. The linewidth D10 of the fifth extension GL3 is equal to the linewidth D8 of the third extension GL1, or equal to the linewidth D9 of the fourth extension GL4, or greater than the linewidth D8 of the third extension GL3 and less than the linewidth D9 of the fourth extension GL4; that is, D8≤D10≤D9.

[0191] In some examples, as shown in Figure 14, the linewidth D10 of the fifth extension segment GL3 is equal to the linewidth D8 of the third extension segment GL1. This helps to reduce the parasitic capacitance between the fifth extension segment GL3 and the data signal line DL, thereby reducing the load on the fifth extension segment GL3 and the data signal line DL. Alternatively, in some examples, as shown in Figure 15, the linewidth D10 of the fifth extension segment GL3 is equal to the linewidth D9 of the fourth extension segment GL2. Thus, the fifth extension segment GL3 and the fourth extension segment GL2 are connected and have equal linewidths. This helps to reduce the resistance on the gate line GL and reduce the voltage drop when the gate line GL transmits the scan signal. Alternatively, in some examples, the linewidth D10 of the fifth extension segment GL3 can be between the linewidth D8 of the third extension segment GL1 and the linewidth D9 of the fourth extension segment GL2.

[0192] In some embodiments, as shown in Figures 14 and 15, the third extension segment GL1, the fourth extension segment GL2, and the fifth extension segment GL3 are flush with the side boundary away from the first gate G1, which is electrically connected to the gate line GL; that is, the lower boundaries of the third extension segment GL1, the fourth extension segment GL2, and the fifth extension segment GL3 are flush. Thus, a groove 41 is formed at the position of the third extension segment GL1 on the edge of the gate line GL near the gate G1. The groove 41 is at least partially opposite to the second via V2 to increase the spacing between the gate line GL and the second via V2.

[0193] Referring to Figures 16-18, the second via V2 includes a first sub-via V21 and a second sub-via V22. The first sub-via V21 penetrates the planarization layer PLN, and at least a portion of the second passivation layer PVX2 is located within the first sub-via V21 and contacts its sidewall. The second sub-via V22 penetrates the second passivation layer PVX2 and the first passivation layer PVX1, and the orthographic projection of the second sub-via V22 onto the first substrate 10 lies within the range of the orthographic projection of the first sub-via V21 onto the first substrate 10. Furthermore, the boundary of the second sub-via V22 does not at least partially coincide with the boundary of the first sub-via V21. Thus, the size of the portion of the second via V2 that simultaneously penetrates the second passivation layer PVX2, the planarization layer PLN, and the first passivation layer PVX1 is approximately equal to the size of the second sub-via V22. By reducing the size of the second sub-via V22, the overall size of the second via V2 can be reduced, thereby improving the pixel density of the array substrate 100.

[0194] In some embodiments, the center Q1 of the orthographic projection of the first sub-via V21 onto the first substrate 10 is spaced apart from the center Q2 of the orthographic projection of the second sub-via V22 onto the first substrate 10. That is, the first sub-via V21 and the second sub-via V21 are not centrally symmetrical. This helps to reduce the overall area of ​​the orthographic projection of the second via V2 onto the first substrate 10, and helps to reduce the area of ​​the black matrix on the color filter substrate (the orthographic projection of the black matrix on the array substrate needs to cover the second via to avoid light leakage), thereby improving the aperture ratio of the array substrate.

[0195] For example, the first sub-via V21 and the second sub-via V22 can be formed by two mask processes respectively. For instance, the method for fabricating the array substrate may include forming a full-layer first passivation layer PVX1 and a full-layer planarization layer PLN; then forming the first sub-via V21 on the planarization layer PLN by photolithography; then forming a first electrode layer and a second passivation layer PVX2 on the planarization layer PLN, wherein the second passivation layer PVX2 can cover the first sub-via V21; and then forming the second sub-via V22 through the second passivation layer PVX2 and the first passivation layer PVX1 by an etching process.

[0196] Referring again to Figures 16 to 18, in some embodiments, the second sub-hole V22 and the first drain D1 are partially overlapped by their orthogonal projections on the first substrate 10, and the portion of the orthogonal projection of the second sub-hole V22 on the first substrate 10 is located outside the range of the orthogonal projection of the first drain D1 on the first substrate 10. That is, the second sub-hole V22 exposes at least a portion of the area other than the first drain D1.

[0197] As shown in Figures 16 and 17, the array substrate 100 also includes a third via V3. The third via V3 penetrates the gate insulating layer GI and exposes a portion of the first semiconductor pattern 31. The first drain D1 is electrically connected to the first semiconductor pattern 31 through the third via V3. At least a portion of the first semiconductor pattern 31 within the third via V3 is not covered by the first drain D1. Thus, during the doping process of the semiconductor layer 30 using the second conductive layer 40 as a mask, the portion of the first semiconductor pattern 31 adjacent to the first drain D1 within the third via V3 can be doped into a conductor, thereby achieving the electrical connection between the first semiconductor pattern 31 and the first drain D1.

[0198] As shown in Figures 15 and 16, in some embodiments, the portion of the third via V3 located outside the range of the orthogonal projection of the first drain D1 onto the first substrate 10 is located on the side of the first drain D1 away from the first gate G1. In other words, the portion of the third via V3 that does not coincide with the orthogonal projection of the first drain D1 onto the first substrate 10 is located to the left of the first drain D1, i.e., the first drain D1 covers the left side of the third via V3. This reduces the spacing between the first drain D1 and the first gate G1, thereby facilitating a reduction in the size of the first transistor T1 in the first direction X, and improving the aperture ratio of the array substrate.

[0199] As shown in Figures 16 and 17, in some embodiments, the orthographic projection of the third via V3 on the first substrate 10 partially overlaps with the orthographic projection of the first sub-via V21 on the first substrate 10, and is partially located outside the orthographic projection of the second sub-via V21 on the first substrate 10. This helps to reduce the portion where the orthographic projections of the second via V2 and the third via V3 overlap on the first substrate 10, reduces the size of the black matrix on the color filter substrate used to block the areas where the second via V2 and the third via V3 are located, and helps to improve the aperture ratio of the array substrate.

[0200] In some embodiments, as shown in FIG16, the orthographic projection of the third via V3 on the first substrate 10 is either a circle or an ellipse.

[0201] Referring to Figure 15, in some embodiments, two adjacent data signal lines DL along the first direction X are respectively the first data signal line DL3 and the second data signal line DL4. In the first transistor T1 located between the two adjacent data signal lines DL, the first source S1 is electrically connected to the first data signal line DL3, and the first drain D1 is located between the first gate G1 and the second data signal line DL4. The gap D11 between the first drain D1 and the first gate G1 (also referred to as the second gap D11 in some embodiments below) is smaller than the gap D12 between the first drain D1 and the second data signal line DL4. This is beneficial to increase the gap D12 between the first drain D1 and the adjacent second data signal line DL4, thereby reducing the parasitic capacitance between the first drain D1 and the second data signal line DL4, and reducing the risk of short circuit between the first drain D1 and the second data signal line DL4.

[0202] Referring to Figure 18, in some embodiments, the sidewall of the second via V2 is in contact with the second passivation layer PVX2, the planarization layer PLN, and the first passivation layer PVX1, respectively. That is, the second via V2 is formed by a single etching process. This helps to reduce the fabrication steps of the array substrate 100, reducing the fabrication process of the array substrate 100 from 8 masks to 7 masks, which helps to reduce the fabrication cost of the array substrate 100.

[0203] In some embodiments, referring to FIG19, in the same first transistor T1, the distance between the first gate G1 and the first source S1 along the first direction X is a first distance D13, and the distance between the first gate G1 and the first drain D1 along the first direction is a second distance D11. The difference between the second distance D11 and the first distance D13 is greater than or equal to 4 μm. Exemplarily, the second distance D11 is greater than the first distance D13, and the second distance D11 is at least 2 μm larger than the first distance D13. Exemplarily, the second distance D11 is at least 4 μm, at least 5 μm, at least 6 μm, at least 7 μm, at least 8 μm, at least 9 μm, at least 10 μm, at least 11 μm, or at least 12 μm larger than the first distance D13.

[0204] In some embodiments, the second interval D11 is in the range of 5μm to 12μm, for example, the second interval D11 is 5μm to 6μm, 6μm to 7μm, 7μm to 8μm, 8μm to 9μm, 9μm to 10μm, 10μm to 11μm, or 11μm to 12μm.

[0205] In some embodiments, the first interval D13 is in the range of 3μm to 7μm, for example, the first interval D13 is 3μm to 4μm, 4μm to 5μm, 5μm to 6μm, or 6μm to 7μm.

[0206] The inventors of this disclosure have discovered that the first transistor T1 in the array substrate exhibits bulk accumulation; the electron accumulation layer extends to the entire depth of the semiconductor pattern. The first transistor T1 in the array substrate of this disclosure exhibits good negative bias photo-stress stability due to its high gate drive, resulting in a near-zero on-state voltage, regardless of the defect state density changes caused by negative bias photo-stress. This structure leads to excellent light / bias stress stability in the array substrate, which is particularly significant for large-area display panels.

[0207] By making the second interval D11 larger than the first interval D13, although the electric field in the first drain D1 offset region is reduced, resulting in a decrease in the electron concentration in the first drain D1 offset region, it is surprisingly observed that the electrical properties of the semiconductor pattern remain essentially unchanged due to the presence of the first light-shielding pattern 21.

[0208] Alternatively, in some embodiments, as shown in FIG15, in the same first transistor T1, the distance D13 between the first gate G1 and the first source S1 along the first direction X can be set to be greater than the distance D12 between the first gate G1 and the first drain D1 along the first direction; that is, the first distance D13 can be set to be greater than the second distance D11. In this case, it is more advantageous for the spatial arrangement of the first transistor T1 and for improving the pixel density of the array substrate.

[0209] Referring to FIG20, in some embodiments, the semiconductor layer 30 includes a first semiconductor layer 35 and a second semiconductor layer 36 stacked together. The second semiconductor layer 36 is disposed on the side of the first semiconductor layer 35 away from the first substrate 10, and the orthographic projection of the second semiconductor layer 36 on the first substrate 10 lies within the orthographic projection of the first semiconductor layer 35 on the first substrate 10. The first semiconductor pattern 31 includes a first pattern 351 located on the first semiconductor layer 35 and two second patterns 361 located on the second semiconductor layer 36. The two second patterns 361 are respectively located on both sides of the first gate G1 along the first direction X, and are electrically connected to the first source S1 and the first drain D1, respectively.

[0210] As shown in Figure 15, in some embodiments, a partial gate insulating layer GI is included between the first source S1 and the second pattern 361, and / or, a partial gate insulating layer GI is included between the first drain D1 and the second pattern 361.

[0211] Referring to Figures 18 and 20, in some embodiments, the area in the third via V3 not covered by the first drain D1 may also be located on the side of the first drain D1 close to the first gate G1.

[0212] As shown in Figure 21, in some embodiments, the second conductive layer 40 may not have a first drain D1. In this case, the second electrode 52 passes through the second via V2 and directly contacts the semiconductor pattern 31.

[0213] Referring to Figures 22 and 23, in some embodiments, the array substrate 100 further includes a second transistor T2 located in the peripheral region BB. The second transistor T2 includes a second semiconductor pattern 37 located in the semiconductor layer 30, a second gate G2, a second source S2, and a second drain D2 located in the second conductive layer 40. The second semiconductor pattern 37 includes a plurality of second sub-semiconductor patterns 371 spaced apart along the channel width direction M1 (the vertical direction in Figure 22) of the second transistor T2. The second gate G2, the second source S2, and the second drain D2 each form a second sub-transistor on one of the plurality of second sub-semiconductor patterns 371, and the plurality of second sub-transistors are connected in parallel.

[0214] For example, as shown in FIG3, the second transistor T2 can be a switching transistor (SW-TFT) disposed in the peripheral area BB and electrically connected to the data signal line DL.

[0215] Referring again to Figures 22 and 23, the first conductive layer 20 further includes a second light-shielding pattern 22 located in the peripheral region BB. The orthographic projection of the second semiconductor pattern 37 onto the first substrate 10 is located within the range of the orthographic projection of the second light-shielding pattern 22 onto the first substrate 10. In this way, the amount of light emitted from the backlight module that directly enters the second semiconductor pattern 37 can be greatly reduced, thereby improving the stability of the second transistor T2.

[0216] In some other embodiments, as shown in Figures 24 and 25, the first conductive layer 20 further includes a second light-shielding pattern 22 located in the peripheral region BB. The second light-shielding pattern 22 includes a plurality of openings 23. The orthographic projections of the second source S2 and the second drain D2 on the first substrate 10 respectively partially overlap with at least one opening 23 on the first substrate 10, and the orthographic projection of the second gate G2 on the first substrate 10 does not overlap with the opening 23 on the first substrate 10.

[0217] As shown in Figures 22 and 24, in some embodiments, the second light-shielding pattern 22 is electrically connected to the second gate G2. This helps to reduce the resistance on the second gate G2 and increase the on-state current of the second transistor T2. Exemplarily, the second light-shielding pattern 22 and the second gate G2 can be electrically connected via a fifth via V5.

[0218] In some embodiments, the spacing D14 between the second gate G2 and the second source S2 along the channel length direction M2 of the second transistor T2 is not equal to the spacing D15 between the second gate G2 and the second drain D2 along the channel length direction of the second transistor T2. For example, the spacing D14 between the second gate G2 and the second source S2 may be greater than or less than the spacing D15 between the second gate G2 and the second drain D2 along the channel length direction of the second transistor T2.

[0219] The inventors discovered that display panels using related technologies exhibit problems such as whitening and conductive properties of thin-film transistors (e.g., the first transistor T1) during the double-layer copper process used to form the gate. Research revealed that the root cause of these problems is a stress mismatch between the inorganic layer (first passivation layer) above the gate (first gate / second gate) G and the gate itself. This mismatch leads to separation of the metal material between the first passivation layer and the gate, allowing moisture to penetrate between them, ultimately resulting in conductive properties of the thin-film transistor.

[0220] Figure 26 shows a scanning electron microscope (SEM) image of an array substrate with the inorganic layer separated from the gate. Figure 27 shows a SEM image of an array substrate with the inorganic layer and gate intact. Referring to Figure 26, the array substrate includes a gate G, a silicon oxide (SiO) layer on the gate G, and a silicon nitride (SiN) layer on the side of the SiO layer away from the gate G. The separation of the SiO layer from the gate G is represented as Sep in Figure 1. Figure 27 shows an array substrate with the SiO layer from the gate G intact.

[0221] Referring to Figure 28, some embodiments of this disclosure provide an array substrate that can substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art.

[0222] The array substrate 100 includes a first substrate 10, a first conductive layer 20 on the first substrate 10, a buffer layer BUF on the side of the first conductive layer 20 away from the first substrate 10, a semiconductor layer 30 on the side of the buffer layer BUF away from the first substrate 10, a gate insulating layer GI on the side of the semiconductor layer 30 away from the first substrate 10, a second conductive layer 40 on the side of the gate insulating layer GI away from the first substrate 10, a first passivation layer PVX1 on the side of the second conductive layer 40 away from the first substrate 10, a planarization layer PLN on the side of the first passivation layer PVX1 away from the first substrate 10, a first electrode layer 51 on the side of the planarization layer PLN away from the first substrate 10, a second passivation layer PVX2 on the side of the first electrode layer 51 away from the first substrate 10, and a second electrode layer 52 on the side of the second passivation layer PVX2 away from the first substrate 10.

[0223] In some embodiments, the first conductive layer 20 includes a plurality of data signal lines DL, and a corresponding data signal line of the plurality of data signal lines DL is connected to the first source S1 of the first transistor T1 in the array substrate. In some embodiments, the first conductive layer 20 further includes a first light-shielding pattern 21. The orthographic projection of the first light-shielding pattern 21 on the first substrate 10 substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the channel structure of the first semiconductor pattern 31 of the first transistor T1 on the first substrate 10.

[0224] In some embodiments, the first source S1 includes a fourth end (the left end of the first source S1 in FIG. 28) that contacts the first semiconductor pattern 31 and a fifth end (the right end of the first source S1 in FIG. 28) that does not contact the first semiconductor pattern 31. Exemplarily, the orthographic projection of the fourth end on the first substrate 10 at least partially coincides with the orthographic projection of the first semiconductor pattern 31 on the first substrate 10, and the orthographic projection of the fourth end on the first substrate 10 does not coincide with the orthographic projection of the gate insulating layer GI on the first substrate 10. Exemplarily, the orthographic projection of the fifth end on the first substrate 10 at least partially coincides with the orthographic projection of the gate insulating layer GI on the first substrate 10, and the orthographic projection of the fifth end on the first substrate 10 does not coincide with the orthographic projection of the first semiconductor pattern 31 on the first substrate 10. In some embodiments, the side of the fifth end closest to the first substrate 10 contacts the gate insulating layer GI.

[0225] In some embodiments, the first passivation layer PVX1 includes a plurality of sublayers. Exemplarily, the first passivation layer PVX1 includes a first sublayer PVX11 located on the side of the second conductive layer 40 away from the first substrate 10, a second sublayer PVX12 located on the side of the first sublayer PVX11 away from the first substrate 10, and a third sublayer PVX13 located on the side of the second sublayer PVX12 away from the first substrate 10.

[0226] In some embodiments, the first sublayer PVX11 of the first passivation layer PVX1 comprises silicon oxide; the second sublayer PVX12 of the first passivation layer PVX1 comprises silicon nitride; and the third sublayer PVX13 of the first passivation layer PVX1 comprises silicon nitride.

[0227] In some embodiments, the stress of the first passivation layer PVX1 having a first sublayer PVX11, a second sublayer PVX12, and a third sublayer PVX13 is in the range of -4000 Pa to -1000 Pa, for example, -4000 Pa to -3500 Pa, -3500 Pa to -3000 Pa, -3000 Pa to -2500 Pa, -2500 Pa to -2000 Pa, -2000 Pa to -1500 Pa, or -1500 Pa to -1000 Pa.

[0228] In other embodiments, the first sublayer PVX11 of the first passivation layer PVX1 comprises silicon nitride; the second sublayer PVX12 of the first passivation layer PVX1 comprises silicon oxide; and the third sublayer PVX13 of the first passivation layer PVX1 comprises silicon nitride.

[0229] In some embodiments, the second sublayer PVX12 of the first passivation layer PVX1 comprises 0.3% to 2.0% (e.g., 0.3% to 0.5%, 0.5% to 0.7%, 0.7% to 0.9%, 0.9% to 1.1%, 1.1% to 1.3%, 1.3% to 1.5%, 1.5% to 1.7%, 1.7% to 1.9%, or 1.9% to 2.0%) w / w silicon-hydrogen (Si-H). In one example, the stress of silicon nitride with 1.0% w / w silicon-hydrogen is -1060. As used herein, the term “w / w” refers to weight / weight. For example, if the second sublayer PVX12 with a total mass of 100 grams contains 0.3 grams of silicon-hydrogen and 99.7 grams of silicon nitride, then the second sublayer PVX12 comprises 0.3% w / w silicon-hydrogen.

[0230] In some embodiments, the second sublayer PVX12 of the first passivation layer PVX1 comprises 1% to 10% silicon-hydrogen.

[0231] In some embodiments, the third sublayer PVX13 of the first passivation layer PVX1 comprises 8% to 15% (e.g., 8% to 9%, 9% to 10%, 10% to 11%, 11% to 12%, 12% to 13%, 13% to 14%, or 14% to 15%) w / w silicon-hydrogen. In one example, the silicon nitride with 9.7% w / w silicon-hydrogen has a stress of 89.3.

[0232] In some embodiments, the ratio of the thickness of the second sublayer PVX12 to the thickness of the third sublayer PVX13 is in the range of 1:4 to 1:1, for example, 1:4 to 1:3, 1:3 to 2:5, 2:5 to 1:2, 1:2 to 3:5, 3:5 to 2:3, 2:3 to 3:4, or 3:4 to 1:1.

[0233] In some embodiments, the total thickness of the second sublayer PVX12 and the third sublayer PVX13 of the first passivation layer PVX1 is in the range of 150 nm to 500 nm.

[0234] In some embodiments, the thickness of the first sublayer PVX11 of the first passivation layer PVX1 is in the range of 100 nm to 300 nm.

[0235] In a specific example, the thickness of the first sublayer PVX11 of the first passivation layer PVX1 is 200 nm, the thickness of the second sublayer PVX12 is 100 nm, and the thickness of the third sublayer PVX13 is 100 nm.

[0236] The inventors of this disclosure have discovered that the array substrate provided in the embodiments of this disclosure can improve the on-state current Ion of the first transistor T1 and reduce stress, ensuring that the first passivation layer PVX1 covers the first gate G1, thereby avoiding the problem of film separation between the first passivation layer PVX1 and the first gate G1. As shown in FIG29, in the array substrate provided in the embodiments of this disclosure, no film separation occurs between the first passivation layer PVX1 and the first gate G1.

[0237] Referring to Figure 30, in a transistor where film separation has occurred, the transistor characteristics are abnormal. Referring to Figure 31, in a first transistor in an array substrate according to some embodiments of the present disclosure, the first transistor exhibits normal device characteristics. In Figures 30 and 31, A represents the curve when the drain voltage is 0.1V, B represents the curve when the drain voltage is 5.1V, C represents the curve when the drain voltage is 10.1V, and D represents the curve when the drain voltage is 15.1V.

[0238] The embodiments of this disclosure also provide a method for fabricating an array substrate, the method comprising steps S110 to S190.

[0239] S110, a single layer or multiple layers of metal are deposited on a first substrate, and then the single layer or multiple layers are patterned (e.g., etched) to form a first conductive layer. The thickness of the first conductive layer can be... to Within the range.

[0240] S120, a buffer layer is formed by depositing (e.g., using a CVD process) a single layer of silicon oxide, a two-layer structure of silicon nitride / silicon dioxide, or a three-layer structure of silicon nitride / silicon oxynitride / silicon oxide on the first conductive layer. The thickness of the buffer layer can be... to Within a certain range. Silicon nitride can be a single layer or stacked into layers with a thickness ranging from... to Two or three layers. The thickness of silicon oxynitride is... to Within the range. Silica is located on the top layer, in contact with the subsequent layers, with a thickness of [missing information]. to

[0241] S130, a semiconductor material is deposited on the buffer layer (e.g., using a sputtering process) to form a semiconductor layer. This semiconductor material is described above and will not be repeated here. The semiconductor layer is formed to have a thickness of... to Within the range.

[0242] S140, a single layer of silicon oxide, a two-layer structure of silicon nitride / silicon dioxide, or a three-layer structure of silicon nitride / silicon oxynitride / silicon oxide is deposited on the semiconductor layer (e.g., using CVD or ALD processes) to form a gate insulating layer. The gate insulating layer is formed to a thickness of [insert thickness here]. to Within a certain range. Silicon oxide can be a single layer or stacked into two or three layers. The thickness of silicon oxynitride is within... to Within the range. Silica is located on the top layer, in contact with the subsequent active layer, with a thickness of [missing information]. to

[0243] S150, depositing one or more layers of metal on the gate insulating layer and patterning the single or multiple layers of metal to form a second conductive layer. The thickness of the second conductive layer can be... arrive Within the range.

[0244] S160, deposit silicon oxide to form a first sublayer of the first passivation layer, deposit low-hydrogen silicon nitride to form a second sublayer of the first passivation layer, and deposit low-stress silicon nitride to form a third sublayer of the first passivation layer. The first passivation layer is formed with a total thickness of... to Within a certain range. For example, the thickness of the first sublayer of the first passivation layer is in the range of 100 nm to 300 nm, and the combined thickness of the second and third sublayers is in the range of 150 nm to 500 nm. The ratio of the thickness of the second sublayer to the thickness of the third sublayer can be 1:1, 1:2, 1:3, 1:4, 2:3, 2:5, 3:4, or 3:5. The silicon-hydrogen content in the second sublayer is in the range of 0.3% to 2.0%, and the silicon-hydrogen content in the third sublayer is in the range of 8% to 15%.

[0245] S170, deposit positive photoresist to form a planarization layer. The first electrode layer is formed on the planarization layer.

[0246] S180, a dense, low-density silicon nitride is deposited to form a second passivation layer to block water vapor and hydrogen.

[0247] S190, deposit (e.g., by sputtering) a transparent conductive material with a thickness of 40nm to 135nm (including endpoint values) to form a second electrode layer, and pattern the second electrode layer to obtain the desired pattern.

[0248] Referring to FIG32, in some embodiments, the array substrate includes a first substrate 10, a first conductive layer 20 on the first substrate 10, a buffer layer BUF on the side of the first conductive layer 20 away from the first substrate 10, a semiconductor layer 30 on the side of the buffer layer BUF away from the first substrate 10, a gate insulating layer GI on the side of the semiconductor layer 30 away from the first substrate 10, a second conductive layer 40 on the side of the gate insulating layer GI away from the first substrate 10, a first passivation layer PVX1 on the side of the second conductive layer 40 away from the first substrate 10, a planarization layer PLN on the side of the first passivation layer PVX1 away from the first substrate 10, a first electrode layer 51 on the side of the planarization layer PLN away from the first substrate 10, a second passivation layer PVX2 on the side of the first electrode layer 51 away from the first substrate 10, and a second electrode layer 52 on the side of the second passivation layer PVX2 away from the first substrate 10.

[0249] In some embodiments, the first conductive layer 20 includes a plurality of data signal lines DL, and a corresponding data signal line of the plurality of data signal lines DL is connected to the first source S1 of the first transistor T1 in the array substrate. In some embodiments, the first conductive layer 20 further includes a first light-shielding pattern 21. The orthographic projection of the first light-shielding pattern 21 on the first substrate 10 substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the first semiconductor pattern 31 of the first transistor T1 on the first substrate 10.

[0250] In some embodiments, the first passivation layer PVX1 includes a plurality of sublayers. Exemplarily, the first passivation layer PVX1 includes a first sublayer PVX11 located on the side of the second conductive layer 40 away from the first substrate 10, and a second sublayer PVX12 located on the side of the first sublayer PVX11 away from the first substrate 10.

[0251] In some embodiments, the first sublayer PVX11 of the first passivation layer PVX1 comprises silicon oxide; the second sublayer PVX12 of the first passivation layer PVX1 comprises silicon nitride. In some embodiments, the stress of the first passivation layer PVX1 having the first sublayer PVX11 and the second sublayer PVX12 is in the range of -2000 Pa to -100 Pa, for example, -2000 Pa to -1500 Pa, or -1500 Pa to -1000 Pa, or -1000 Pa to -500 Pa, or -500 Pa to -100 Pa.

[0252] In some embodiments, the second sublayer PVX12 of the first passivation layer PVX1 comprises 0.3% to 2.0% (e.g., 0.3% to 0.5%, 0.5% to 0.7%, 0.7% to 0.9%, 0.9% to 1.1%, 1.1% to 1.3%, 1.3% to 1.5%, 1.5% to 1.7%, 1.7% to 1.9%, or 1.9% to 2.0%) w / w of silicon-hydrogen. In one example, the silicon nitride with 1.0% w / w silicon-hydrogen has a stress of -1060. In an alternative embodiment, the second sublayer PVX12 of the first passivation layer PVX1 comprises 8% to 15% (e.g., 8% to 9%, 9% to 10%, 10% to 11%, 11% to 12%, 12% to 13%, 13% to 14%, or 14% to 15%) w / w of silicon-hydrogen. In one example, the stress of silicon nitride with 9.7% w / w silicon-hydrogen is 89.3.

[0253] In some embodiments, the thickness of the first sublayer PVX11 of the first passivation layer PVX1 is in the range of 100 nm to 300 nm. In some embodiments, the thickness of the second sublayer PVX12 of the first passivation layer PVX1 is in the range of 150 nm to 500 nm.

[0254] In a specific example, the thickness of the first sublayer PVX11 of the first passivation layer PVX1 is 200 nm, and the thickness of the second sublayer PVX12 is 300 nm.

[0255] Referring to Figures 33 and 34, in the peripheral region, the array substrate includes a first substrate 10, a first conductive layer 20 located on the first substrate 10, a buffer layer BUF located on the side of the first conductive layer 20 away from the first substrate 10, a semiconductor layer 30 located on the side of the buffer layer BUF away from the first substrate 10, a gate insulating layer GI located on the side of the semiconductor layer 30 away from the first substrate 10, and a second conductive layer 40 located on the side of the gate insulating layer GI away from the first substrate 10.

[0256] The array substrate may also include a third transistor T3 located in the peripheral region. The third transistor T3 may include a third semiconductor pattern 38 located in the semiconductor layer 30, a third gate G3, a third source S3, and a third drain D3 located in the second conductive layer 40. Exemplarily, the third transistor T3 may be a transistor in a gate driving circuit.

[0257] In some embodiments, the first conductive layer 20 includes a third light-shielding pattern 25 in the peripheral region. The orthographic projection of the third light-shielding pattern 25 in the peripheral region onto the first substrate 10 substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) covers the orthographic projection of the third semiconductor pattern 38 of the third transistor T3 in the peripheral region onto the first substrate 10.

[0258] The third transistor T3, located in the peripheral region, operates in a positive bias environment. The inventors of this disclosure have discovered that the third transistor T3, located in the peripheral region of the array substrate of this disclosure, maintains positive bias temperature stress stability under positive bias conditions, which is crucial for its reliable operation in applications exposed to such environments.

[0259] In some embodiments, the array substrate includes a seventh via V7 and an eighth via V8 extending through the gate insulating layer GI, respectively. In some embodiments, the seventh via V7 exposes a portion of the third source S3, and the eighth via V8 exposes a portion of the third drain D3.

[0260] In some embodiments, the orthographic projection of the seventh via V7 on the first substrate 10 is spaced apart from the orthographic projection of the channel of the third semiconductor pattern 38 of the third transistor T3 on the first substrate 10 by a first distance D16. In some embodiments, the orthographic projection of the seventh via V7 on the first substrate 10 is spaced apart from the orthographic projection of the third light-shielding pattern 25 on the first substrate 10 by a second distance D17, and the orthographic projection of the third light-shielding pattern 25 on the first substrate 10 is spaced apart from the orthographic projection of the channel of the third semiconductor pattern 38 of the third transistor T3 on the first substrate 10 by a third distance D18. Exemplarily, the first distance D16 is equal to the sum of the second distance D17 and the third distance D18.

[0261] In some embodiments, the first distance D16 is greater than or equal to 2 μm. Exemplarily, the second distance D17 is greater than or equal to 1 μm, and the third distance D18 is greater than or equal to 1 μm. The inventors of this disclosure have discovered that when the first distance D16 is greater than or equal to 2 μm, there is no source-gate short circuit on the array substrate. Figure 35 illustrates the correlation between the gate voltage and drive current of a third transistor in the peripheral region of the array substrate according to some embodiments of this disclosure. Figure 35 corresponds to a third transistor with a second distance D17 of 10 μm. Figure 35 shows the results of a negative bias temperature stress (NBTS) test on the second transistor in the absence of light. The curves from right to left represent the transistor characteristics in the dark state, 100 seconds after the NBTS test, 500 seconds after the NBTS test, 1000 seconds after the NBTS test, 1800 seconds after the NBTS test, and 3600 seconds after the NBTS test. The curve corresponding to the dark state represents the baseline performance of the transistor without any applied stress. The characteristics corresponding to the dark state are stable and are used as a reference point.

[0262] Figure 36 illustrates the correlation between the gate voltage and drive current of a third transistor in the peripheral region of an array substrate according to some embodiments of the present disclosure. Figure 36 corresponds to the third transistor with a second distance D17 of 10 μm. Figure 36 shows the results of a negative bias temperature instability stress (NBTIS) test on the second transistor under 6000 nit illumination. The curves from right to left represent the transistor characteristics in the dark state, 100 seconds after the NBTIS test, 500 seconds after the NBTIS test, 1000 seconds after the NBTIS test, 1800 seconds after the NBTIS test, and 3600 seconds after the NBTIS test. The curve corresponding to the dark state represents the baseline performance of the transistor without any applied stress. The characteristics corresponding to the dark state are stable and are used as a reference point.

[0263] Referring to Figures 37 to 40, in some embodiments, the array substrate includes a first substrate 10, a first conductive layer 20 on the first substrate 10, a buffer layer BUF on the side of the first conductive layer 20 away from the first substrate 10, a semiconductor layer 30 on the side of the buffer layer BUF away from the first substrate 10, a gate insulating layer GI on the side of the semiconductor layer 30 away from the first substrate 10, a second conductive layer 40 on the side of the gate insulating layer GI away from the first substrate 10, a first passivation layer PVX1 on the side of the second conductive layer 40 away from the first substrate 10, a planarization layer PLN on the side of the first passivation layer PVX1 away from the first substrate 10, a first electrode layer 51 on the side of the planarization layer PLN away from the first substrate 10, a second passivation layer PVX2 on the side of the first electrode layer 51 away from the first substrate 10, and a second electrode layer 52 on the side of the second passivation layer PVX2 away from the first substrate 10.

[0264] Referring to Figures 37-40, in some embodiments, the array substrate further includes a plurality of touch signal lines 61, a plurality of touch electrodes 62, and a plurality of connection electrodes 63. In some embodiments, each connection electrode among the plurality of connection electrodes 63 connects the touch signal lines among the plurality of touch signal lines 61 to the touch electrodes among the plurality of touch electrodes 62.

[0265] In some embodiments, each connection electrode 63 is located in the second electrode layer 52, for example, each connection electrode 63 is located in the same layer as the second electrode layer 52.

[0266] In some embodiments, the touch electrode is located on the first electrode layer 51, for example, the touch electrode and the first electrode E1 are located on the same layer.

[0267] Referring to Figures 37 and 38, in some embodiments, the array substrate further includes a fourth via V4 through which each connection electrode is connected to the touch signal line and the touch electrode. In some embodiments, a portion of the touch electrode is inserted into the fourth via V4. In some embodiments, the orthographic projection of the touch electrode on the first substrate 10 coincides with the orthographic projection of the corresponding connection electrode on the first substrate 10. The touch electrode and the touch signal line are located in two different layers, and the corresponding connection electrode connects the touch signal line to the touch electrode.

[0268] In some embodiments, referring to FIG37, the touch signal line 61 is located in the first conductive layer 20, the touch electrode is located in the first electrode layer 51, and each connecting electrode is located in the second electrode layer 52. The array substrate may further include a transition electrode 64 located in the second conductive layer. The connecting electrode 63 is connected to the transition electrode 64 through a fourth via V4, and the transition electrode 64 is electrically connected to the touch signal line 61 through a sixth via V6. The transition electrode 64 can reduce the depth of the fourth via V4, reducing the difficulty for the connecting electrode 63 to climb the sidewall of the fourth via V4.

[0269] The inventors of this disclosure have discovered that an array substrate can be manufactured without an additional mask by setting the touch structure depicted in FIG37. By modifying the mask used for the first electrode layer 51, the electrodes in the first electrode layer 51 can be used as hard masks, and interleaved vias can be formed. The array substrate of this disclosure achieves the maximum possible aperture ratio.

[0270] In some embodiments, referring to FIG38, the array substrate further includes a third conductive layer 60, which is located on the side of at least one sublayer (e.g., the first sublayer PVX11) of the first passivation layer PVX1 away from the second conductive layer 40. In some embodiments, touch signal lines 61 are located in the third conductive layer 60, touch electrodes are located in the first electrode layer 51, and each connection electrode is located in the second electrode layer 52.

[0271] The inventors of this disclosure have discovered that two additional masks can be introduced by setting up the touch structure depicted in FIG38.

[0272] Referring to FIG39, in some embodiments, the array substrate further includes a third passivation layer PVX3 located on the side of the second electrode layer 52 away from the first substrate 10, and a touch electrode layer 70 located on the side of the third passivation layer PVX3 away from the first substrate 10. In some embodiments, touch signal lines 61 are located on the touch electrode layer 70, touch electrodes 62 are located on the first electrode layer 51, and respective connection electrodes 63 are located on the second electrode layer 52. In some embodiments, touch signal lines extend through a fourth via V4 penetrating the third passivation layer PVX3 to connect to a corresponding connection electrode, and the corresponding connection electrode extends through a via penetrating the second passivation layer PVX2 to connect to the touch electrode.

[0273] The inventors of this disclosure have discovered that by setting up the touch structure depicted in FIG39, the process risk of manufacturing the array substrate can be minimized, thereby reducing the risk associated with process variations.

[0274] Referring to FIG39, in some embodiments, the array substrate further includes a touch electrode layer 70 located on the side of the first electrode layer 51 away from the first substrate 10. In some embodiments, the touch signal line 61 is located on the touch electrode layer 70, and the touch electrode 62 is located on the first electrode layer 51, with the touch signal line 61 in direct contact with the touch electrode 62. In this case, the connection electrode 63 may not be provided.

[0275] Some embodiments of this disclosure also provide a method for fabricating an array substrate. The fabrication method may include steps S210 to S310.

[0276] S210, the transparent substrate is cleaned using a standard method.

[0277] S211, depositing (e.g., sputtering) one or more layers of metal material on a substrate, and then patterning the deposited one or more layers of metal material to obtain a thickness of... The first conductive layer.

[0278] The first conductive layer may include data signal lines and multiple light-shielding patterns (such as one or more of a first light-shielding pattern, a second light-shielding pattern, and a third light-shielding pattern).

[0279] The specific method for forming the first conductive layer may include a single layer of metal material on a substrate, such as one of titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys, or multiple layers of metal material, such as aluminum and aluminum alloy structures and their stacks with metal buffer layers, such as titanium-aluminum-titanium (Ti / Al / Ti) stacked structures, molybdenum-aluminum (Mo / Al) stacked structures, aluminum-molybdenum (Al / Mo) stacked structures, molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structures, molybdenum-aluminum alloy (Mo / Al alloy) stacked structures, aluminum alloy-molybdenum (Al alloy / Mo) stacked structures, and molybdenum-aluminum alloy-molybdenum (Mo / Al) stacked structures. Molybdenum alloy / Mo (Mo) stacked structures can include copper and copper alloys, as well as stacks with metal buffer layers, such as molybdenum-niobium-copper (MoNb / Cu) stacked structures, molybdenum-titanium-copper (MoTi / Cu) stacked structures, molybdenum-nickel-titanium-copper (MTD / Cu) stacked structures, etc.; such as molybdenum-niobium-copper-molybdenum-niobium (MoNb / Cu / MoNb) stacked structures, molybdenum-niobium-copper-molybdenum-nickel-titanium (MoNb / Cu / MTD) stacked structures, and molybdenum-nickel-titanium-copper-molybdenum-nickel-titanium (MTD / Cu / MTD) stacked structures. Molybdenum alloy-copper-molybdenum alloy structures include molybdenum-titanium-copper-molybdenum-nickel-titanium (MoTi / Cu / MTD) stacked structures, molybdenum-titanium-copper-molybdenum-titanium (MoTi / Cu / MoTi) stacked structures, etc.; it can include copper and copper alloys as well as their stacks with metal oxide buffer layers, such as indium tin oxide-copper-indium tin oxide (ITO / Cu / ITO), zinc tin oxide-copper-zinc tin oxide (IZO / Cu / IZO), indium oxide-copper-indium oxide (InOx / Cu / InOx), molybdenum alloy-copper-indium tin oxide (Mo Alloy / Cu / ITO), titanium-copper-indium tin oxide (Ti / Cu / ITO), copper alloy-indium tin oxide (CuTi alloy / ITO), etc., where ITO, IZO, and InOx can be interchanged, Mo alloys include but are not limited to MoNd, MTD, MoTi, etc., and Cu alloys include CuTi alloys, etc.Examples include molybdenum-niobium-titanium (MoNb / Ti) stacked structures, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) stacked structures, molybdenum-niobium-copper (MoNb / Cu) stacked structures, molybdenum-niobium-titanium-copper (MTD / Cu) stacked structures, molybdenum-niobium-copper-molybdenum-niobium-titanium (MoNb / Cu / MTD) stacked structures, molybdenum-niobium-titanium-copper-molybdenum-niobium-titanium (MTD / Cu / MTD) stacked structures, molybdenum-titanium-copper (MoTi / Cu) stacked structures, and molybdenum-titanium-copper-molybdenum-niobium-titanium stacked structures. The following are possible combinations of structures: (MoTi / Cu / MTD) stacked structures, molybdenum-titanium-copper-molybdenum-titanium (MoTi / Cu / MoTi) stacked structures, molybdenum-neodymium-copper stacked structures, MoNb-copper-MoNb stacked structures, AlNb-molybdenum-AlNd stacked structures, titanium-copper (Ti / Cu) stacked structures, copper-titanium (Cu / Ti) stacked structures, titanium-copper-titanium (Ti / Cu / Ti) stacked structures, and single or multiple layers of CuTi alloys.

[0280] S220, continue to deposit (e.g., by chemical vapor deposition) insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate to form a buffer layer with a thickness between 100 nm and 700 nm.

[0281] S230, a semiconductor material with a thickness of 10nm to 80nm is sputtered on a substrate, and the formed semiconductor material is patterned to obtain a semiconductor layer with a preset pattern.

[0282] The semiconductor materials mentioned above are described in the text above and will not be repeated here.

[0283] S240, using chemical vapor deposition or atomic layer deposition and silicon oxide and / or silicon nitride as insulating materials, forms a semiconductor layer with a thickness of [thickness value missing] on the side away from the substrate. The gate insulation layer.

[0284] S250, the gate insulating layer and buffer layer are patterned to form a via structure including a first via and a third via.

[0285] S250 involves depositing (e.g., magnetron sputtering) one or more layers of metal material on the surface of the gate insulating layer away from the substrate, and then patterning the deposited metal material (e.g., including photolithography and etching) to obtain a thickness of... The second conductive layer.

[0286] The second conductive layer may include the first gate, first source, and first drain of the first transistor.

[0287] S260, the gate insulating layer is patterned using the second conductive layer as a mask to remove the portion of the gate insulating layer not covered by the second conductive layer, so as to facilitate subsequent doping of the semiconductor layer.

[0288] S270, continue to deposit (e.g., by plasma-enhanced chemical vapor deposition) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the substrate to form a first passivation layer with a thickness between 200 nm and 400 nm.

[0289] S280, an organic insulating layer (such as a resin layer) with a thickness between 2 μm and 3 μm is coated on the first passivation layer, and the organic insulating layer is photolithographically processed to form a planarization layer with a first sub-hole.

[0290] S290, a transparent conductive material layer (such as indium gallium zinc oxide or indium zinc oxide) with a thickness between 40 nm and 100 nm is deposited on the resin layer, and the transparent conductive material layer is patterned to form a common electrode.

[0291] S300, deposit (e.g., by chemical vapor deposition) an insulating material (silicon oxide or silicon nitride / silicon oxide) on the common electrode to form a second passivation layer with a thickness between 100 nm and 300 nm, and pattern the second passivation layer to form a second sub-via, such as the second via in the aforementioned array substrate.

[0292] S310, deposit a transparent conductive material layer with a thickness between 40 nm and 135 nm on the second passivation layer, and pattern the transparent conductive material layer to form a pixel electrode.

[0293] Other embodiments of this disclosure also provide another method for fabricating an array substrate. Unlike the above-described fabrication method (S210-S211), after the second conductive layer is formed in step S250, the gate insulating layer is not patterned. That is, the fabrication method of the array substrate in this embodiment does not include the above-described step S260.

[0294] Alternatively, some embodiments of this disclosure also provide another method for fabricating the array substrate. Unlike the above-described fabrication method (S210-S211), step S280 is replaced by coating an organic insulating layer (e.g., a resin layer) with a thickness between 2 μm and 3 μm onto the first passivation layer to form a planarization layer with a generally flat surface. That is, the planarization layer is not photolithographically patterned; instead, it is patterned simultaneously with the second passivation layer during step S300. This saves one mask process, which helps reduce the fabrication cost of the array substrate.

[0295] Alternatively, some embodiments of this disclosure also provide another method for fabricating the array substrate. Unlike the methods described above (S210-S211), when forming the first conductive layer in step S220, a light-shielding pattern (e.g., a first light-shielding pattern) may not be formed within the first conductive layer. Meanwhile, the semiconductor material used in step 230 can be a high-mobility oxide semiconductor material. High-mobility oxide semiconductor materials are described above and will not be repeated here.

[0296] Alternatively, some embodiments of this disclosure also provide another method for fabricating the array substrate, which differs from the above-described fabrication method (S210-S211) in that corresponding film layers with different patterns can be formed in any step. For example, the second conductive layer formed in step S250 may not include the first drain electrode; of course, the embodiments of this disclosure are not limited to this, and it is also possible to form other array substrates with different film layer structures based on the above-described fabrication method.

[0297] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate having a display area and a peripheral area located on at least one side of the display area; the array substrate comprising: First substrate; A first conductive layer is located on one side of the first substrate. The first conductive layer includes multiple data signal lines, which are spaced apart along a first direction and extend generally along a second direction. The first direction and the second direction intersect each other. A buffer layer is located on the side of the first conductive layer away from the first substrate. A semiconductor layer is located on the side of the buffer layer away from the first substrate, and the semiconductor layer includes a first semiconductor pattern; A gate insulating layer is located on the side of the semiconductor layer away from the first substrate. The second conductive layer is located on the side of the gate insulating layer away from the first substrate, and the second conductive layer includes a first source, a first drain and a first gate. A first via penetrates the gate insulation layer and the buffer layer, and exposes at least a portion of the data signal line; The array substrate includes a plurality of first transistors located within the display area. Each first transistor includes a first semiconductor pattern, a first gate, a first source, and a first drain. A portion of the first source passes through the first via and is electrically connected to the data signal line.

2. The array substrate according to claim 1, wherein, The second conductive layer further includes a plurality of gate lines extending along the first direction and spaced apart along the second direction. The orthographic projections of the plurality of gate lines and the plurality of data signal lines on the first substrate intersect each other to form a grid structure. Each grid of the grid structure defines a sub-pixel, and the sub-pixel includes an opening region. The data signal line includes a first extension segment and a second extension segment alternately connected along the second direction, wherein the first extension segment and the opening area are disposed opposite to each other in the first direction. The first extension has the same linewidth at all points along the second direction; the second extension includes a first sub-segment and a second sub-segment, the first sub-segment being electrically connected to the first source electrode, and the linewidth of the first sub-segment being greater than the linewidth of the second sub-segment.

3. The array substrate according to claim 2, wherein, The line width of the first sub-segment is greater than the line width of the first extension segment; and / or, The line width of the second sub-segment is less than or equal to the line width of the first extension segment.

4. The array substrate according to claim 3, wherein, The linewidth of the first extension segment is 2μm to 4μm.

5. The array substrate according to claim 3, wherein, The linewidth of the first extension segment is 2μm to 2.5um.

6. The array substrate according to any one of claims 2 to 5, wherein, A first extension segment includes at least two third sub-segments; the extension direction of the third sub-segments has a first angle with the second direction, the first angle being 5° to 11°; Wherein, the two adjacent third segments along the second direction have opposite inclination directions to the second direction.

7. The array substrate according to claim 6, wherein, The first included angle is 8° to 11°.

8. The array substrate according to any one of claims 1 to 7, wherein, The orthographic projection of the first semiconductor pattern on the first substrate at least partially overlaps with the orthographic projection of the data signal line on the first substrate. The first via includes a first region, a second region, and a third region connected sequentially along a direction away from the first source electrode; the orthographic projection of the first region on the first substrate coincides with the orthographic projection of the first semiconductor pattern on the first substrate, but does not coincide with the orthographic projection of the data signal line on the first substrate. The orthographic projection of the second region onto the first substrate coincides with the orthographic projections of the first semiconductor pattern and the data signal line onto the first substrate, respectively. The orthographic projection of the third region on the first substrate does not coincide with the orthographic projection of the first semiconductor pattern on the first substrate, but coincides with the orthographic projection of the data signal line on the first substrate. The first source electrode covers at least a portion of the second region and at least a portion of the third region, and the first source electrode does not overlap with at least a portion of the first region.

9. The array substrate according to claim 8, wherein, The first source electrode covers the second region, the third region, and a portion of the first region, and at least a portion of the first source electrode does not overlap with the first region.

10. The array substrate according to claim 9, wherein, In the first region, the array substrate includes the buffer layer, the first semiconductor pattern, and the first source electrode stacked together; In the second region, the array substrate includes the data signal lines, the buffer layer, the first semiconductor pattern, and the first source electrode stacked together; In the third region, the array substrate includes the data signal lines and the first source electrode stacked together.

11. The array substrate according to claim 10, wherein, In the second region, at least one of the buffer layer, the first semiconductor pattern, and the first source electrode forms a protrusion structure that protrudes away from the first substrate relative to the first region and / or the third region.

12. The array substrate according to any one of claims 9 to 11, wherein, The first semiconductor pattern includes a serrated structure at the edge of the second region near the first region.

13. The array substrate according to any one of claims 1 to 12, wherein, The second conductive layer further includes a plurality of gate lines extending along the first direction and distributed along the second direction, wherein the first gate is electrically connected to the gate lines; The first semiconductor pattern includes a first portion, a second portion, and a third portion connected sequentially along the first direction. The first portion is located on the side of the second portion near the first via. The first portion, the second portion, and the third portion are substantially flush with each other at the end near the gate line along the second direction. The first portion and the third portion extend beyond the boundary of the second portion along the second direction at the end away from the gate line.

14. The array substrate according to claim 13, wherein, The orthographic projection of the second portion on the side of the gate line away from the gate line onto the first substrate is approximately an arc, and the arc is concave towards the side closer to the gate line.

15. The array substrate according to claim 13 or 14, wherein, The maximum dimension of the first part along the first direction is smaller than the maximum dimension of the third part along the first direction; And / or, The maximum dimension of the first part along the second direction is not equal to the maximum dimension of the third part along the second direction.

16. The array substrate according to any one of claims 13 to 15, wherein, The first conductive layer further includes a plurality of first light-shielding patterns, wherein the portion of the first gate and the first semiconductor pattern whose orthogonal projections on the first substrate overlap with each other is located within the range of the orthogonal projection of the first light-shielding pattern on the first substrate. The orthographic projection of the second portion onto the first substrate is within the range of the orthographic projection of the first light-shielding pattern onto the first substrate. The orthographic projection of at least a portion of the first portion away from the second portion and at least a portion of the third portion away from the second portion onto the first substrate does not coincide with the orthographic projection of the first light-shielding pattern onto the first substrate.

17. The array substrate according to claim 16, wherein, The orthographic projections of the two ends of the second part along the first direction onto the first substrate generally coincide with the orthographic projections of the two ends of the first light-shielding pattern along the first direction onto the first substrate. The orthographic projections of the two ends of the second portion along the second direction onto the first substrate are spaced apart from the orthographic projections of the two ends of the first light-shielding pattern along the second direction onto the first substrate.

18. The array substrate according to claim 16 or 17, wherein, The portions where the orthographic projections of the first gate and the first semiconductor pattern on the first substrate overlap are spaced apart from the two ends of the first light-shielding pattern along the first direction.

19. The array substrate according to any one of claims 16 to 18, wherein, In one of the sub-pixels, along the second direction and away from the gate line, the first portion includes a first end portion away from the gate line, the third portion includes a second end portion away from the gate line, the first light-shielding pattern includes a third end portion away from the gate line, and at least one of the first end portion and the second end portion is at a greater distance from the gate line than the distance between the third end portion and the gate line.

20. The array substrate according to any one of claims 16 to 19, wherein, The orthographic projection of the first gate on the first substrate is located within the range of the orthographic projection of the first light-shielding pattern on the first substrate, and the end of the first gate away from the gate line is spaced from the boundary of the first light-shielding pattern away from the gate line.

21. The array substrate according to any one of claims 1 to 20, further comprising: The first passivation layer is located on the side of the second conductive layer away from the first substrate. A planarization layer is located on the side of the first passivation layer away from the first substrate. The first electrode layer is located on the side of the planarization layer away from the first substrate. The second passivation layer is located on the side of the first electrode layer away from the first substrate. The second via penetrates the second passivation layer, the first electrode layer, and the first passivation layer, and exposes at least a portion of the first drain electrode; The second electrode layer is located on the side of the second passivation layer away from the first substrate, and includes a plurality of second electrodes, which are electrically connected to the first drain electrode through the second via. The lines connecting the first transistor, the first via, and the second via on the first substrate are arranged along the first direction or are generally U-shaped.

22. The array substrate according to claim 21, wherein, The second conductive layer further includes a plurality of gate lines extending along the first direction and spaced apart along the second direction; The gate line includes a third extension and a fourth extension. The third extension and the second via are disposed opposite to each other along the second direction. The fourth extension is respectively offset from the data signal line, the first via and the first gate in the first direction. The line width of the third extension segment is smaller than that of the fourth extension segment.

23. The array substrate according to claim 22, wherein, The gate line further includes a fifth extension, the orthographic projection of the fifth extension on the first substrate at least partially coincides with the orthographic projection of the data signal line on the first substrate; The line width of the fifth extension segment is equal to the line width of the third extension segment, or equal to the line width of the fourth extension segment, or greater than the line width of the third extension segment and less than the line width of the sixth extension segment.

24. The array substrate according to claim 23, wherein, The boundaries of the third, fourth, and fifth extensions are flush with the side of the first gate that is electrically connected to the gate line.

25. The array substrate according to any one of claims 21 to 24, wherein, The second via includes a first sub-via and a second sub-via; the first sub-via penetrates the planarization layer, at least a portion of the second passivation layer is located within the first sub-via and contacts the sidewall of the first sub-via; the second sub-via penetrates the second passivation layer and the first passivation layer, and the orthographic projection of the second sub-via on the first substrate is within the range of the orthographic projection of the first sub-via on the first substrate, and the boundary of the second sub-via does not at least partially coincide with the boundary of the first sub-via.

26. The array substrate according to claim 25, wherein, The center of the orthographic projection of the first sub-hole onto the first substrate is spaced apart from the center of the orthographic projection of the second sub-hole onto the first substrate.

27. The array substrate according to claim 25 or 26, wherein, The second sub-hole and the first drain electrode have their orthogonal projections on the first substrate overlapping, and the portion of the second sub-hole's orthogonal projection on the first substrate is outside the range of the first drain electrode's orthogonal projection on the first substrate.

28. The array substrate according to any one of claims 25 to 27, further comprising: The third via penetrates the gate insulating layer and exposes a portion of the first semiconductor pattern; The first drain is electrically connected to the first semiconductor pattern through the third via; Wherein, the orthographic projection of the third via and the first drain on the first substrate coincides, and the orthographic projection of the third via on the first substrate is located outside the range of the orthographic projection of the first drain on the first substrate.

29. The array substrate according to claim 28, wherein, The portion of the orthographic projection of the third via on the first substrate that does not coincide with the orthographic projection of the first drain on the first substrate is located on the side of the first drain away from the first gate.

30. The array substrate according to claim 28, wherein, The orthographic projection of the third via on the first substrate partially overlaps with the orthographic projection of the first sub-via on the first substrate, and is partially located outside the orthographic projection of the second sub-via on the first substrate.

31. The array substrate according to any one of claims 28 to 30, wherein, The orthographic projection of the first via on the first substrate is either a circle or an ellipse; and / or, the orthographic projection of the third via on the first substrate is either a circle or an ellipse.

32. The array substrate according to any one of claims 21 to 24, wherein, The sidewalls of the second via are in contact with the second passivation layer, the planarization layer, and the first passivation layer, respectively.

33. The array substrate according to any one of claims 21 to 32, wherein, Two adjacent data signal lines along the first direction are respectively a first data signal line and a second data signal line; in the first transistor located between the two adjacent data signal lines, the first source is electrically connected to the first data signal line, the first drain is located between the first gate and the second data signal line, and the spacing between the first drain and the first gate is smaller than the spacing between the first drain and the second data signal line; In the same first transistor, the distance between the first gate and the first source along the first direction is a first distance, the distance between the first gate and the first drain along the first direction is a second distance, and the difference between the second distance and the first distance is greater than or equal to 4 μm.

34. The array substrate according to any one of claims 1 to 32, wherein, In the same first transistor, the distance between the first gate and the first source along the first direction is greater than the distance between the first gate and the first drain along the first direction.

35. The array substrate according to any one of claims 1 to 34, wherein, The semiconductor layer includes a first semiconductor layer and a second semiconductor layer stacked together. The second semiconductor layer is disposed on the side of the first semiconductor layer away from the first substrate, and the orthographic projection of the second semiconductor layer on the first substrate is located within the orthographic projection of the first semiconductor layer on the first substrate. The first semiconductor pattern includes a first pattern located in the first semiconductor layer and two second patterns located in the second semiconductor layer. The two second patterns are respectively located on both sides of the first gate along the first direction and are electrically connected to the first source and the first drain, respectively.

36. The array substrate according to claim 35, wherein, A portion of the gate insulating layer is included between the first source and the second pattern; and / or, A portion of the gate insulating layer is included between the first drain and the second pattern.

37. The array substrate according to any one of claims 1 to 36, wherein, The first source includes a fourth end that contacts the first semiconductor pattern and a fifth end that does not contact the first semiconductor pattern; at least a portion of the surface of the fifth end near the first substrate contacts the gate insulating layer.

38. The array substrate according to any one of claims 1 to 37, wherein, The array substrate further includes a second transistor located in the peripheral region, the second transistor including a second semiconductor pattern located in the semiconductor layer, a second gate, a second source, and a second drain located in the second conductive layer; The second semiconductor pattern includes a plurality of second sub-semiconductor patterns spaced apart along the channel width direction of the second transistor; the second gate, the second source, and the second drain each form a second sub-transistor on the plurality of second sub-semiconductor patterns, and the plurality of second sub-transistors are connected in parallel.

39. The array substrate according to claim 38, wherein, The first conductive layer further includes a second light-shielding pattern located in the peripheral region, wherein the orthographic projection of the second semiconductor pattern on the first substrate is within the range of the orthographic projection of the second light-shielding pattern on the first substrate.

40. The array substrate according to claim 39, wherein, The first conductive layer further includes a second light-shielding pattern located in the peripheral region. The second light-shielding pattern includes a plurality of openings. The orthographic projections of the second source and the second drain on the first substrate respectively coincide with at least one of the openings on the first substrate, and the orthographic projection of the second gate on the first substrate does not coincide with the openings on the first substrate.

41. The array substrate according to claim 39 or 40, wherein, The second light-shielding pattern is electrically connected to the second gate.

42. The array substrate according to any one of claims 38 to 41, wherein, The spacing between the second gate and the second source along the channel length of the second transistor is not equal to the spacing between the second gate and the second drain along the channel length of the second transistor.

43. The array substrate according to any one of claims 1 to 42, wherein, The array substrate further includes a first passivation layer, which is located on the side of the second conductive layer away from the first substrate and is in contact with the first passivation layer. The first passivation layer comprises multiple sub-layers with different materials, and the stress of the first passivation layer is in the range of -4000Pa to -100Pa.

44. The array substrate according to claim 43, wherein, The first passivation layer includes a first sub-layer and a second sub-layer stacked together, wherein the second sub-layer is located on the side of the first sub-layer away from the first substrate. The material of one of the first sublayer and the second sublayer comprises a silicon oxide compound, and the material of the other comprises a silicon nitride compound.

45. The array substrate according to claim 44, wherein, The second sublayer comprises 0.3% to 2.0% w / w silicon-hydrogen; or, The second sublayer comprises 8% to 15% w / w silicon-hydrogen; or, The second sublayer comprises 1% to 10% w / w silicon-hydrogen.

46. ​​The array substrate according to claim 44 or 45, wherein, The thickness of the first sublayer is 100 nm to 300 nm; and / or, The thickness of the second sublayer is 150nm to 500nm.

47. The array substrate according to claim 46, wherein, The first passivation layer further includes a third sublayer located on the side of the second sublayer away from the first substrate, the material of the third sublayer being silicon nitride.

48. The array substrate according to claim 47, wherein, The second sublayer comprises 0.3% to 2.0% w / w silicon-hydrogen; and, The third sublayer comprises 8% to 15% w / w silicon-hydrogen.

49. The array substrate according to claim 47 or 48, wherein, The ratio of the thickness of the second sublayer to the thickness of the third sublayer is 1:4 to 1:1; The thickness of the first sublayer is 100nm to 300nm; The total thickness of the second sublayer and the third sublayer is 150nm to 500nm.

50. The array substrate according to any one of claims 1 to 49, wherein, The array substrate further includes a first passivation layer, a planarization layer, a second passivation layer, and a second electrode layer, which are sequentially disposed on the side of the second conductive layer away from the first substrate along a direction away from the first substrate. The array substrate also includes multiple touch signal lines, multiple touch electrodes located on the first electrode layer, and multiple connection electrodes located on the second electrode layer; The connecting electrodes are electrically connected to the corresponding touch signal lines and touch electrodes, respectively.

51. The array substrate according to claim 50, further comprising: The fourth via is used to electrically connect the connection electrode to the touch signal line and the touch electrode. The orthographic projection of the touch electrode on the first substrate partially coincides with the orthographic projection of the connection electrode on the first substrate. The touch signal line and the touch electrode are located on two different layers.

52. The array substrate according to claim 40, further comprising: The third passivation layer is located on the side of the second electrode layer away from the first substrate. The touch electrode layer is located on the side of the third passivation layer away from the first substrate. The plurality of touch signal lines are located in the touch electrode layer. The touch signal lines are connected to the connection electrode through a fifth via penetrating the third passivation layer. The connection electrode is electrically connected to the touch electrode through a sixth via penetrating the second passivation layer.

53. A display panel, comprising: The array substrate as described in any one of claims 1 to 52; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate.

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