Synchronization control method and apparatus, and electronic device and readable storage medium

Abstract

Provided in the embodiments of the present application are a synchronization control method and apparatus, and an electronic device and a readable storage medium. The method comprises: controlling a design under test to execute a test program, and determining the number of executed instructions of the said design; when said design satisfies a first trigger condition of an instruction submission event, on the basis of the number of executed instructions of said design, driving a reference model to execute the same number of instructions; when said design satisfies a second trigger condition of a synchronization event, interrupting the operation of said design, and acquiring first state information of said design; and on the basis of the first state information, updating second state information of the reference model, so as to perform state synchronization between said design and the reference model.

Description

A synchronization control method, apparatus, electronic device, and readable storage medium

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411441668.X, filed on October 15, 2024, entitled "A Synchronization Control Method, Apparatus, Electronic Device and Readable Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a synchronization control method, apparatus, electronic device, and readable storage medium. Background Technology

[0004] For frameworks that run processors on FPGAs and need to be compared with software reference models, a method is needed to synchronously control the processor and software reference model on the FPGA. Traditional processor verification DUTs and REFs are synchronized at the cycle level, and the drivers of the DUT and REF have sequential dependencies, which are not easy to decouple, resulting in slow verification system operation. Summary of the Invention

[0005] This application provides a synchronization control method, apparatus, electronic device, and readable storage medium, which can solve the problem in related technologies where the driving logic of the design under test and the reference model are dependent, resulting in slow operation of the verification system.

[0006] On one hand, this application discloses a synchronization control method applied to a verification system, the verification system including a hardware terminal and a software terminal, the hardware terminal including a design under test, and the software terminal including a reference model of the design under test; the method includes:

[0007] Control the design under test to execute the test program, and determine the number of execution instructions of the design under test;

[0008] If the design under test meets the first triggering condition of the instruction submission event, the reference model is driven to execute the same number of instructions according to the number of execution instructions of the design under test;

[0009] If the design under test meets the second triggering condition of the synchronization event, the operation of the design under test is interrupted, and the first state information of the design under test is obtained.

[0010] The second state information of the reference model is updated based on the first state information to synchronize the state of the design under test with that of the reference model.

[0011] Optionally, the second triggering condition for the synchronization event includes at least one of the following:

[0012] An abnormal event occurred in the design under test;

[0013] An external interruption event occurred in the design under test;

[0014] A self-trapping event occurred in the design under test;

[0015] The design under test executes atomic instructions;

[0016] The design under test accesses external devices on the hardware side.

[0017] Optionally, the hardware also includes a control module; the output of the first clock domain of the control module is connected to the input of the gated clock, and the output of the gated clock is connected to the input of the second clock domain of the design under test.

[0018] The interruption of the operation of the design under test includes:

[0019] The control module shuts down the gated clock to pause the clock in the second clock domain.

[0020] Optionally, the instruction submission event includes an instruction comparison event, and the first triggering condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

[0021] Optionally, the method further includes:

[0022] Write the first execution information of the design under test into the first queue;

[0023] Write the second execution information of the reference model into the second queue;

[0024] After detecting that data has been written to both the first queue and the second queue, read the first execution information recorded in the first queue and the second execution information recorded in the second queue;

[0025] The first execution information is compared with the second execution information;

[0026] If the first execution information and the second execution information do not match, it is determined that the design under test is malfunctioning, and the operation of the design under test and the reference model is interrupted.

[0027] Optionally, the instruction submission event includes a register comparison event, and the first triggering condition includes: the number of instructions executed by the design under test since the last register comparison event is greater than or equal to a second threshold.

[0028] Optionally, the hardware further includes a register data module; the method further includes:

[0029] Write the first value of each register in the design under test into the register data module;

[0030] Write the second value of each register in the reference model into the register data module;

[0031] If the design under test meets the first triggering condition of the register comparison event, the operation of the design under test is interrupted until the first value and the second value are both written to the register data module, and then the operation of the design under test is resumed to compare the first value and the second value.

[0032] On the other hand, embodiments of this application disclose a synchronization control device applied to a verification system. The verification system includes a hardware terminal and a software terminal. The hardware terminal includes a design under test (DUT), and the software terminal includes a reference model of the DUT. The device includes:

[0033] The first control module is used to control the design under test to execute the test program and determine the number of execution instructions of the design under test;

[0034] The second control module is used to drive the reference model to execute the same number of instructions according to the number of execution instructions of the design under test when the design under test meets the first triggering condition of the instruction submission event.

[0035] The interrupt module is used to interrupt the operation of the design under test and obtain the first state information of the design under test when the design under test meets the second triggering condition of the synchronization event.

[0036] The synchronization module is used to update the second state information of the reference model based on the first state information, so as to synchronize the state of the design under test and the reference model.

[0037] In another aspect, embodiments of this application also disclose an electronic device, which includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the aforementioned synchronization control method.

[0038] This application also discloses a readable storage medium, which, when the instructions in the readable storage medium are executed by the processor of an electronic device, enables the electronic device to perform the aforementioned synchronization control method.

[0039] The embodiments of this application have the following advantages:

[0040] This application provides a synchronization control method that abstracts the behavior of the design under test (DUT) into events. Synchronization control is then performed on the DUT and a reference model based on these events: When a first triggering condition for an instruction submission event is met, the reference model executes the same number of instructions as the DUT, synchronizing the execution information of the reference model and the DUT; when a second triggering condition for a synchronization event is met, the DUT's operation is interrupted, and the second state information of the reference model is synchronized based on the first state information of the DUT, achieving state synchronization between the DUT and the reference model. This application decouples the driving logic of the DUT and the reference model by separating instruction submission events and synchronization events, thereby improving the operating speed of the verification system. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 is a flowchart of the steps of an embodiment of the synchronization control method of this application;

[0043] Figure 2 is a structural block diagram of an embodiment of a synchronization control device according to this application;

[0044] Figure 3 is a structural block diagram of an electronic device for synchronous control provided in this application example. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0047] Method Implementation Examples

[0048] Referring to Figure 1, a flowchart of an embodiment of the synchronization control method of this application is shown. The method is applied to a verification system, which includes a hardware terminal and a software terminal. The hardware terminal includes a design under test, and the software terminal includes a reference model of the design under test. The method may specifically include the following steps:

[0049] Step 101: Control the design under test to execute the test program and determine the number of execution instructions for the design under test;

[0050] Step 102: If the design under test meets the first triggering condition of the instruction submission event, drive the reference model to execute the same number of instructions according to the number of execution instructions of the design under test;

[0051] Step 103: If the design under test meets the second triggering condition of the synchronization event, interrupt the operation of the design under test and obtain the first state information of the design under test;

[0052] Step 104: Update the second state information of the reference model according to the first state information to synchronize the state of the design under test and the reference model.

[0053] The verification method provided in this application can be applied to a verification system, which includes a hardware terminal and a software terminal. The hardware terminal and the software terminal are used for collaborative verification of the Design Under Test (DUT). The hardware terminal includes the DUT, and the software terminal includes a reference model of the DUT.

[0054] For example, the hardware in this application may be a Field Programmable Gate Array (FPGA), and the design under test is deployed in the Programmable Logic (PL) area of ​​the FPGA chip.

[0055] It's important to note that an FPGA is a reconfigurable integrated circuit chip with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured to adapt to different applications and functions according to user needs. An FPGA consists of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks typically consist of look-up tables (LUTs), registers, and other logic elements, capable of performing various logical functions. Programmable interconnect resources are used to connect the logic blocks to form the desired circuit structure. Using FPGAs, design engineers can describe the required circuit functions using hardware description languages ​​and translate them into a bitstream compatible with the FPGA chip using programming tools. The bitstream contains information for programming and configuring the FPGA's internal logic and interconnect resources. One of the main advantages of FPGAs is their programmability and flexibility. It allows design engineers to implement custom functions and algorithms at the hardware level without the need for traditional custom integrated circuit design and manufacturing processes. This makes FPGAs play a crucial role in prototyping and rapid design iteration.

[0056] Design Under Test (DUT) refers to the circuit design or implementation to be tested during prototype verification. For example, a DUT can be a Register Transfer Level (RTL) circuit or other hardware designs. It's important to note that RTL circuits are a common type of hardware description level circuit. RTL circuits describe the behavior and structure of digital circuits and are represented using the register transfer level abstraction. RTL circuit descriptions are typically written using Hardware Description Languages ​​(HDLs), such as VHDL (VHSIC Hardware Description Language), Verilog HDL, or System Verilog HDL. Designers can use RTL-level descriptions to define and implement the desired digital circuit functionality, and then use synthesis tools to translate the RTL-level description into a physical implementation in a Field-Programmable Gate Array (FPGA).

[0057] A reference model is used to implement the same functionality as the design under test (DUT). During the verification process of the DUT, the data generated when the reference model is invoked is assumed to be correct and is used as reference data for comparison with the data generated by the DUT. Understandably, different reference models are generated for different DUTs. As an example, before performing high-level synthesis on the DUT, a source design model of the DUT can be generated based on the DUT's C / C++ design code. This source design model has the same algorithmic functionality as the DUT and can serve as a reference model for the DUT.

[0058] Software and hardware need to communicate through a defined interaction structure, achieving decoupling between them through interfaces. For example, for a CPU, the interface between software and hardware is the Instruction Set Architecture (ISA). The processor below the ISA is the hardware, while the various programs, datasets, files, etc., above the instruction set are the software.

[0059] In this application embodiment, the software refers to the program on top of the instruction set. The software can be installed on a personal computer (PC) or on other electronic devices with an operating system that can run software. The electronic devices may include, but are not limited to, smart terminals, computers, personal digital assistants (PDAs), tablet computers, etc.

[0060] The hardware and software communicate through data interfaces, such as the Peripheral Component Interconnect Express (PCIE) interface, General Purpose Input Output (GPIO), and so on.

[0061] In the embodiments of this application, the behavior of the design under test can be abstracted as events, and the design under test and the reference model can be synchronized based on the events, thereby decoupling the design under test and the reference model.

[0062] For example, taking a processor prone to out-of-order execution as an example, processor behavior can be abstracted as: instruction comparison events (instruction execution result comparison events), register comparison events, comparison error events, exception events, external interrupt events, trap events, atomic instruction events, and peripheral access events. Instruction comparison events refer to comparing the instruction execution results between the design under test (DUT) and the reference model. Register comparison events refer to comparing the values ​​of various registers in the DUT and the reference model. Comparison error events include at least one of the following: an error in comparing the instruction execution results between the DUT and the reference model, or an error in comparing register values. Exception events refer to abnormal events that occur during the execution of the DUT, interrupting the normal instruction execution flow. In the field of chip design, exception events in the DUT typically include hardware execution exceptions or software faults. An exception received after the processor has executed an instruction triggers the processor to execute a dedicated exception handling procedure. External interrupt events refer to the interruption of the DUT's execution caused by input signals from outside the DUT. For example, an external interrupt event for the DUT could include an interrupt signal sent by the interrupt module in the hardware to the DUT when an error occurs, causing the DUT to be interrupted. After receiving an interrupt signal from external hardware, the processor needs to handle the input interrupt. A trap event is a pre-arranged exception, like a pre-set "trap." When the processor executes a trap instruction, it automatically handles it according to the different trap types and then returns to the next instruction after the trap instruction (if the trap instruction is a jump instruction, it returns to the jump target instruction). An atomic instruction event refers to the processor locking the accessed memory space to prevent other hardware from accessing it, ensuring that the processor's running program can access data synchronously across multiple threads. A peripheral access event refers to the design under test accessing external devices. These external devices are devices mounted on the FPGA chip that are neither part of the PL nor the PS side, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR) and other external storage devices.

[0063] In this embodiment, the design under test (DUT) and the reference model execute the same test program. When the DUT meets the first triggering condition of the instruction submission event, the reference model is driven to execute the same number of instructions based on the number of instructions executed by the DUT. For example, during the operation of the DUT, if the first triggering condition is met, a data packet is generated based on the first execution information of the DUT, containing the number of instructions executed by the DUT. The hardware sends this data packet to the software. The software drives the reference model to execute the same number of instructions based on the number of instructions executed in the data packet.

[0064] Furthermore, the software can update the data packet with the second execution information of the reference model and send the updated data packet to the hardware. The hardware parses the updated data packet from the software to obtain the second execution information of the reference model. Then, it compares the first execution information of the design under test with the second execution information of the reference model. If the first execution information and the second execution information do not match, it can be determined that the design under test is malfunctioning.

[0065] It is understandable that the test program executed by the design under test (DUT) and the reference model is the same, so the order of instructions executed by the two is the same. When the DUT and the reference model execute the same number of instructions each time, it can be ensured that the first execution information of the DUT and the second execution information of the reference model are synchronized. This achieves synchronous control of the DUT and the reference model, avoids inaccurate verification results due to asynchrony between the first and second execution information, and ensures the accuracy of the verification results.

[0066] Furthermore, if the design under test (DUT) meets the second triggering condition of the synchronization event, the operation of the DUT can be interrupted, the first state information of the DUT can be obtained, and the second state information of the reference model can be updated based on the first state information of the DUT, so that the DUT and the reference model can maintain state synchronization.

[0067] Optionally, the second triggering condition for the synchronization event includes at least one of the following:

[0068] An abnormal event occurred in the design under test;

[0069] An external interruption event occurred in the design under test;

[0070] A self-trapping event occurred in the design under test;

[0071] The design under test executes atomic instructions;

[0072] The design under test accesses external devices on the hardware side.

[0073] As an example, when the hardware detects an event requiring synchronization in the design under test (DUT) (such as an interrupt, exception, trap, peripheral access, atomic instruction event, etc.), it sends an interrupt signal to the DUT and enters a synchronization processing state. At this point, the relevant state of the DUT needs to be sent to the software, and the corresponding synchronization function in the software is started. Exemplarily, the hardware also includes a control module and a transmission module. The control module detects the synchronization event and outputs the corresponding synchronization event signal to the transmission module, while also outputting the number of instructions to be executed. The transmission module reads the corresponding synchronization information based on the synchronization event signal, assembles it into a data packet, sets the corresponding synchronization information bits, and then sends the data packet to the software. Upon receiving the data packet, the software parses it, first driving the reference model to execute the instructions according to the required number of instructions and writing the results into the data packet. Then, the software extracts the synchronization information from the data packet and passes it to the synchronization processing function to update the relevant state in the reference model. After processing, the data packet's end state is set, and the data packet is sent to the hardware's parsing module through the transmission module. The parsing module parses the data packet, generates a synchronization event end signal, sends this signal to the control module, and simultaneously writes the instruction execution results in the data packet into the FIFO queue corresponding to the reference model. After receiving the synchronization event end signal, the control module terminates the interrupt signal, resumes the operation of the design under test, and the synchronization event ends.

[0074] Optionally, the hardware further includes a control module; the output of the first clock domain of the control module is connected to the input of a gated clock, and the output of the gated clock is connected to the input of the second clock domain of the design under test. Interrupting the operation of the design under test includes:

[0075] The control module shuts down the gated clock to pause the clock in the second clock domain.

[0076] In this embodiment, the control module can pause the clock in the clock domain of the design under test by gating the clock.

[0077] It should be noted that when using a gated clock, the input clock can be output based on the clock enable condition. When the processor's clock stops updating, the processor's internal state remains unchanged, thus achieving a pause function. The gated clock enable comes from an external module input, such as when a synchronization event is triggered, or when the FIFO storing processor information (e.g., the PC) is nearly full, which will pause the processor's operation.

[0078] For hardware modules whose clocks are suspended, they should be considered as separate clock domains. In other words, when the clock of the design under test (DUT) is suspended, the second clock domain of the DUT is a separate clock domain, and all communication between the hardware within this clock domain and the outside world requires cross-clock domain processing.

[0079] For example, for bus signals, since it is bidirectional communication, the AXI-InterConnect IP is used for connection. Since the paused clock does not trigger an update, the AXI-InterConnect module can save the access state on the bus.

[0080] For unidirectional line-type signals, only the signal when the clock of the design under test is not paused is sampled, and the signal input when paused is ignored.

[0081] In this embodiment, the control module can use the original clock domain of the design under test (DUT) and control the DUT's operating state by controlling the gated clock. For the AXI bus originally used by the DUT to access peripherals, AXI-InterConnect is added to handle synchronization issues. Regarding the connection between the DUT and the control module, the control module only detects data when the DUT is not paused. When the control module sends communication to external modules, it uses AXI_interConnect to process the output request and uses an asynchronous FIFO to store the data returned by the external module.

[0082] Optionally, the instruction submission event includes an instruction comparison event, and the first triggering condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

[0083] Optionally, the method further includes:

[0084] Step S11: Write the first execution information of the design under test into the first queue;

[0085] Step S12: Write the second execution information of the reference model into the second queue;

[0086] Step S13: After detecting that data has been written to both the first queue and the second queue, read the first execution information recorded in the first queue and the second execution information recorded in the second queue;

[0087] Step S14: Compare the first execution information with the second execution information;

[0088] Step S15: If the first execution information and the second execution information do not match, determine that the design under test is running incorrectly, and interrupt the operation of the design under test and the reference model.

[0089] In this embodiment, a queue can be configured on the hardware side for writing execution information to the design under test (DUT) and the reference model, respectively. Specifically, the first execution information of the DUT is written to the first queue, and the second execution information of the reference model is written to the second queue. After detecting that data has been written to both the first and second queues, the execution information recorded in the two queues is read and compared. If the first execution information and the second execution information do not match, it can be determined that the DUT has encountered an error.

[0090] The content of the first and second execution information can be determined based on the data to be verified in the design under test. For example, the first and second execution information may include the values ​​of all General Purpose Registers (GPRs), the Control and Status Register (CSR), the Program Counter (PC), instruction execution results, and so on. In practical applications, the specific content of the first and second execution information can be specified according to the actual situation and specific verification requirements. Taking a RISC-V processor as an example, during comparison, the 32 GPR registers, 18 CSR registers, and PC values ​​can be compared.

[0091] The first execution information of the design under test is compared with the second execution information of the reference model. If the first execution information matches the second execution information, for example, the first execution information is the same as the second execution information, or the value of the parameter in the first execution information falls within the value range of the corresponding parameter in the second execution information, etc., it can be considered that the design under test has no error. At this time, the design under test can be controlled to continue to execute the next instruction.

[0092] If the first execution information and the second execution information do not match—for example, if they are not the same, or if the value of a parameter in the first execution information does not fall within the range of the corresponding parameter in the second execution information—then the design under test can be considered to be malfunctioning. In this case, a snapshot of the entire hardware can be taken to save its state information, and the saved data can be sent to the software for display. This allows verification engineers to use the saved state information to troubleshoot on-site.

[0093] In one possible application scenario of this application, snapshot information from the hardware can be imported into simulation software on the software side, and the simulation software can be used to perform fine-grained debugging of the design under test.

[0094] Optionally, the instruction submission event includes a register comparison event, and the first triggering condition includes: the number of instructions executed by the design under test since the last register comparison event is greater than or equal to a second threshold.

[0095] Optionally, the hardware further includes a register data module; the method further includes:

[0096] Write the first value of each register in the design under test into the register data module;

[0097] Write the second value of each register in the reference model into the register data module;

[0098] If the design under test meets the first triggering condition of the register comparison event, the operation of the design under test is interrupted until the first value and the second value are both written to the register data module, and then the operation of the design under test is resumed to compare the first value and the second value.

[0099] In this embodiment of the application, a register data module, such as the Diff_Tile for Reg data module, can be allocated in the hardware. When the triggering condition of the register comparison event is met, the first value of each register in the design under test and the second value of each register in the reference model are written into the register data module for comparison.

[0100] Optionally, the method further includes:

[0101] If the number of instructions executed by the design under test since the last register comparison event is greater than or equal to the second threshold, the operation of the design under test is interrupted until both the first value and the second value are written to the register data module, and then the operation of the design under test is resumed.

[0102] In this embodiment of the application, when the triggering condition of the register comparison event is met, the operation of the design under test can be interrupted first. After the first value of the register in the design under test and the second value of the register in the reference model are both written to the register data module, the operation of the design under test can be resumed. This is to prevent the design under test from continuing to execute instructions to update the value of the register, which would cause the register state of the design under test to be out of sync with the register state of the reference model.

[0103] In summary, this application provides a synchronization control method that abstracts the behavior of the design under test (DUT) into events. Based on these events, the DUT and a reference model are synchronized: when the first triggering condition of the instruction submission event is met, the reference model executes the same number of instructions as the number of instructions executed by the DUT, thus synchronizing the execution information of the reference model and the DUT; when the second triggering condition of the synchronization event is met, the operation of the DUT is interrupted, and the second state information of the reference model is synchronized based on the first state information of the DUT, thus synchronizing the states of the DUT and the reference model. This application decouples the driving logic of the DUT and the reference model by dividing the event into instruction submission events and synchronization events, thereby improving the operating speed of the verification system.

[0104] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily necessary for the embodiments of this application.

[0105] Device Examples

[0106] Referring to Figure 2, a structural block diagram of a synchronization control device according to this application is shown, applied to a verification system. The verification system includes a hardware terminal and a software terminal. The hardware terminal includes a design under test (DUT), and the software terminal includes a reference model of the DUT. Specifically, the device may include:

[0107] The first control module 201 is used to control the design under test to execute the test program and determine the number of execution instructions of the design under test;

[0108] The second control module 202 is used to drive the reference model to execute the same number of instructions according to the number of execution instructions of the design under test when the design under test meets the first triggering condition of the instruction submission event.

[0109] Interrupt module 203 is used to interrupt the operation of the design under test and obtain the first state information of the design under test when the design under test meets the second triggering condition of the synchronization event;

[0110] The synchronization module 204 is used to update the second state information of the reference model according to the first state information, so as to synchronize the state of the design under test and the reference model.

[0111] Optionally, the second triggering condition for the synchronization event includes at least one of the following:

[0112] An abnormal event occurred in the design under test;

[0113] An external interruption event occurred in the design under test;

[0114] A self-trapping event occurred in the design under test;

[0115] The design under test executes atomic instructions;

[0116] The design under test accesses external devices on the hardware side.

[0117] Optionally, the hardware also includes a control module; the output of the first clock domain of the control module is connected to the input of the gated clock, and the output of the gated clock is connected to the input of the second clock domain of the design under test.

[0118] The interrupt module includes:

[0119] A clock control submodule is used by the control module to turn off the gated clock to pause the clock in the second clock domain.

[0120] Optionally, the instruction submission event includes an instruction comparison event, and the first triggering condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

[0121] Optionally, the device further includes:

[0122] The first writing module is used to write the first execution information of the design under test into the first queue;

[0123] The second writing module is used to write the second execution information of the reference model into the second queue;

[0124] The reading module is used to read the first execution information recorded in the first queue and the second execution information recorded in the second queue after detecting that data has been written to both the first queue and the second queue.

[0125] The first comparison module is used to compare the first execution information with the second execution information;

[0126] The determination module is used to determine that the design under test is malfunctioning when the first execution information and the second execution information do not match, and to interrupt the operation of the design under test and the reference model.

[0127] Optionally, the instruction submission event includes a register comparison event, and the first triggering condition includes: the number of instructions executed by the design under test since the last register comparison event is greater than or equal to a second threshold.

[0128] Optionally, the hardware further includes a register data module; the device further includes:

[0129] The third write module is used to write the first value of each register in the design under test into the register data module.

[0130] The fourth write module is used to write the second values ​​of each register in the reference model into the register data module;

[0131] The second comparison module is used to interrupt the operation of the design under test when the design under test meets the first triggering condition of the register comparison event, and resume the operation of the design under test after both the first value and the second value are written to the register data module, and compare the first value and the second value.

[0132] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0133] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0134] Regarding the processor in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0135] Referring to Figure 3, it is a structural block diagram of an electronic device for synchronization control provided in an embodiment of this application. As shown in Figure 3, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the synchronization control method of the aforementioned embodiment.

[0136] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0137] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one line is used in Figure 3, but this does not indicate that there is only one bus or one type of bus.

[0138] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk, and optical data storage devices, etc.

[0139] This application also provides a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), enables the processor to execute the synchronization control method shown in FIG1.

[0140] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0141] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0142] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0143] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0144] These computer program instructions may also be loaded onto a computer or other programmable data processing terminal equipment to cause a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable terminal equipment, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0145] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0146] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0147] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0148] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0149] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0150] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0151] It is understood that the embodiments described in this disclosure can be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, modules, units, and subunits can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in this disclosure, or combinations thereof.

[0152] For software implementation, the techniques described in the embodiments of this disclosure can be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described in the embodiments of this disclosure. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or externally.

[0153] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0154] The above provides a detailed description of the synchronization control method, apparatus, electronic device, and readable storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A synchronous control method, wherein, The method is applied to a verification system, which includes hardware and software components. The hardware component includes a design under test (DUT), and the software component includes a reference model of the DUT. Control the design under test to execute the test program, and determine the number of execution instructions of the design under test; If the design under test meets the first triggering condition of the instruction submission event, the reference model is driven to execute the same number of instructions according to the number of execution instructions of the design under test; If the design under test meets the second triggering condition of the synchronization event, the operation of the design under test is interrupted, and the first state information of the design under test is obtained. The second state information of the reference model is updated based on the first state information to synchronize the state of the design under test with that of the reference model.

2. The method of claim 1, wherein, The second triggering condition for the synchronization event includes at least one of the following: An abnormal event occurred in the design under test; An external interruption event occurred in the design under test; A self-trapping event occurred in the design under test; The design under test executes atomic instructions; The design under test accesses external devices on the hardware side.

3. The method of claim 1, wherein, The hardware also includes a control module; the output of the first clock domain of the control module is connected to the input of the gated clock, and the output of the gated clock is connected to the input of the second clock domain of the design under test. The interruption of the operation of the design under test includes: The control module shuts down the gated clock to pause the clock in the second clock domain.

4. The method of claim 1, wherein, The instruction submission event includes an instruction comparison event. The first triggering condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

5. The method of claim 4, wherein, The method further includes: Write the first execution information of the design under test into the first queue; Write the second execution information of the reference model into the second queue; After detecting that data has been written to both the first queue and the second queue, read the first execution information recorded in the first queue and the second execution information recorded in the second queue; The first execution information is compared with the second execution information; If the first execution information and the second execution information do not match, it is determined that the design under test is malfunctioning, and the operation of the design under test and the reference model is interrupted.

6. The method of claim 1, wherein, The instruction submission event includes a register comparison event, and the first triggering condition includes: the number of instructions executed by the design under test since the last register comparison event is greater than or equal to a second threshold.

7. The method of claim 6, wherein, The hardware also includes a register data module; the method further includes: Write the first value of each register in the design under test into the register data module; Write the second value of each register in the reference model into the register data module; If the design under test meets the first triggering condition of the register comparison event, the operation of the design under test is interrupted until the first value and the second value are both written to the register data module, and then the operation of the design under test is resumed to compare the first value and the second value.

8. The method of claim 1, wherein, When the design under test meets the first triggering condition of the instruction submission event, driving the reference model to execute the same number of instructions according to the number of execution instructions of the design under test includes: When the design under test (DUT) meets the first triggering condition of the instruction submission event, the hardware generates a data packet based on the first execution information of the DUT and sends the data packet to the software. The data packet contains the number of execution instructions of the DUT. The DUT executes the same test program as the reference model. The software program drives the reference model to execute the same number of instructions based on the number of execution instructions in the data packet.

9. A synchronization control device, wherein, The device is applied to a verification system, which includes hardware and software components. The hardware component includes a design under test (DUT), and the software component includes a reference model of the DUT. The first control module is used to control the design under test to execute the test program and determine the number of execution instructions of the design under test; The second control module is used to drive the reference model to execute the same number of instructions according to the number of execution instructions of the design under test when the design under test meets the first triggering condition of the instruction submission event. The interrupt module is used to interrupt the operation of the design under test and obtain the first state information of the design under test when the design under test meets the second triggering condition of the synchronization event. The synchronization module is used to update the second state information of the reference model based on the first state information, so as to synchronize the state of the design under test and the reference model.

10. The apparatus of claim 9, wherein, The second triggering condition for the synchronization event includes at least one of the following: An abnormal event occurred in the design under test; An external interruption event occurred in the design under test; A self-trapping event occurred in the design under test; The design under test executes atomic instructions; The design under test accesses external devices on the hardware side.

11. The apparatus of claim 9, wherein, The hardware also includes a control module; the output of the first clock domain of the control module is connected to the input of the gated clock, and the output of the gated clock is connected to the input of the second clock domain of the design under test. The interrupt module includes: A clock control submodule is used by the control module to turn off the gated clock to pause the clock in the second clock domain.

12. The apparatus of claim 9, wherein, The instruction submission event includes an instruction comparison event. The first triggering condition includes: the number of instructions executed by the design under test is greater than or equal to a first threshold, and no synchronization event is detected.

13. The apparatus of claim 12, wherein, The device further includes: The first writing module is used to write the first execution information of the design under test into the first queue; The second writing module is used to write the second execution information of the reference model into the second queue; The reading module is used to read the first execution information recorded in the first queue and the second execution information recorded in the second queue after detecting that data has been written to both the first queue and the second queue. The first comparison module is used to compare the first execution information with the second execution information; The determination module is used to determine that the design under test is malfunctioning when the first execution information and the second execution information do not match, and to interrupt the operation of the design under test and the reference model.

14. The apparatus of claim 9, wherein, The instruction submission event includes a register comparison event, and the first triggering condition includes: the number of instructions executed by the design under test since the last register comparison event is greater than or equal to a second threshold.

15. The apparatus of claim 14, wherein, The hardware also includes a register data module; the device also includes: The third write module is used to write the first value of each register in the design under test into the register data module. The fourth write module is used to write the second values ​​of each register in the reference model into the register data module; The second comparison module is used to interrupt the operation of the design under test when the design under test meets the first triggering condition of the register comparison event, and resume the operation of the design under test after both the first value and the second value are written to the register data module, and compare the first value and the second value.

16. The apparatus of claim 9, wherein, The second control module includes: When the design under test (DUT) meets the first triggering condition of the instruction submission event, the hardware generates a data packet based on the first execution information of the DUT and sends the data packet to the software. The data packet contains the number of execution instructions of the DUT. The DUT executes the same test program as the reference model. The software program drives the reference model to execute the same number of instructions based on the number of execution instructions in the data packet.

17. An electronic device, comprising: The electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store executable instructions, which cause the processor to execute the synchronization control method as described in any one of claims 1 to 8.

18. A readable storage medium, wherein, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor is enabled to perform the synchronization control method as described in any one of claims 1 to 8.

19. A chip comprising a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to run a program or instructions to implement the synchronization control method as described in any one of claims 1-8.

20. A synchronization control device / apparatus, comprising said device / apparatus (configured to) perform the synchronization control method as claimed in any one of claims 1 to 8. The embodiment of the application provides a synchronization control method and device, electronic equipment and a readable storage medium, and the method comprises the following steps: Control the design under test to execute the test program, and determine the number of execution instructions of the design under test; If the design under test meets the first triggering condition of the instruction submission event, the reference model is driven to execute the same number of instructions according to the number of execution instructions of the design under test; If the design under test meets the second triggering condition of the synchronization event, the operation of the design under test is interrupted, and the first state information of the design under test is obtained. updating second state information of the reference model according to the first state information, so as to synchronize the to-be-tested design and the reference model in state.

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