Communication method and apparatus, and storage medium

Abstract

Provided in the present application are a communication method and apparatus, and a storage medium, which can increase the success rate of downlink synchronization for a terminal device in a deep fading environment, increase the probability of the terminal device receiving downlink paging, and can be applied to satellite communication systems, such as an NTN. The method comprises: a network device generating a first sequence, and sending the first sequence to a terminal device, wherein the first sequence comprises q gold sequences that are connected in series, and each of the q gold sequences is obtained on the basis of an initial sequence and a scrambling code sequence, the initial sequence being an m-sequence generated on the basis of one of q information bits, and the scrambling code sequence being an m-sequence generated on the basis of all or part of information bits from among first information bits having a length of z, which first information bits comprise the q information bits, and are used for indicating time-frequency resource configurations of subsequent sequences or information, and the number of repetitions, z and q being integers greater than 1, and q being less than or equal to z.

Description

Communication methods, devices and storage media

[0001] This application claims priority to Chinese Patent Application No. 202411466384.6, filed on October 18, 2024, entitled "Communication Method, Apparatus and Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a communication method, apparatus and storage medium. Background Technology

[0003] In wireless communication scenarios, some terminal devices (e.g., those placed in a bag or in remote mountainous areas) may miss or fail to receive downlink paging in a timely manner due to poor signal-to-noise ratio (SNR). The 3rd Generation Partnership Project (3GPP) radio access network (RAN) 1 plan introduces an alert channel to enhance paging, notifying terminal devices to move to a location with better coverage before receiving downlink paging.

[0004] For a terminal device to receive downlink paging, it must obtain downlink synchronization. However, existing synchronization sequences often fail to enable terminal devices in deep fading environments to achieve good downlink synchronization. Therefore, it is urgent to design a new synchronization sequence that enables terminal devices in deep fading environments to obtain downlink synchronization and thus receive downlink paging. Summary of the Invention

[0005] This application provides a communication method, apparatus, and storage medium to improve the success rate of downlink synchronization in terminal devices.

[0006] Firstly, this application provides a communication method that can be applied to the terminal side, such as a terminal or a communication module within a terminal, or a circuit or chip (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip or system-in-package (SIP) chip containing a modem core) responsible for communication functions within the terminal. The method is described below using a terminal as an example.

[0007] For example, the method includes: receiving a first sequence comprising q concatenated gold sequences, each of the q gold sequences being obtained based on an initial sequence and a scrambling sequence; and performing downlink synchronization based on the first sequence.

[0008] The initial sequence is an m-sequence generated from one information bit in a block of q information bits, and the scrambling sequence is an m-sequence generated from all or part of the information bits in the first information bit of length z, where z and q are integers greater than 1, and q is less than or equal to z.

[0009] The first information bit contains q blocks of information bits, or in other words, q blocks of information bits constitute the first information bit. This first information bit is used to indicate the time-frequency resource configuration and repetition number of subsequent sequences or information. The subsequent sequence may be, for example, a sequence of synchronization signal 1 (SS1) and / or synchronization signal 2 (SS2), and the subsequent information may be the information that needs to be sent in actual communication.

[0010] Based on this technical solution, the first sequence received by the terminal device is obtained by concatenating q gold sequences. Each of these q gold sequences is based on an initial sequence and a scrambling sequence. The initial sequence is generated based on q blocks of information bits contained in the first information bits, and the scrambling sequence is used to scramble the initial sequence to change the cross-correlation peak value among the q initial sequences. Therefore, this method of adding a scrambling sequence to the initial sequence can effectively reduce the probability of spurious peaks when the terminal device detects the first sequence, thereby increasing the probability of the terminal device correctly detecting the first sequence and thus effectively improving the success rate of downlink synchronization.

[0011] It can be understood that the q gold sequences are obtained from q initial sequences and q scrambling sequences, respectively. The q scrambling sequences are generated from q blocks of information bits, and these q blocks may contain identical information bit blocks; therefore, the q initial sequences may include the same m-sequence. The q scrambling sequences are generated from all or part of the bits in the first information bit set; therefore, these q scrambling sequences may be the same m-sequence or different m-sequences.

[0012] Secondly, this application provides a communication method that can be applied to the network side, such as access network equipment, modules (e.g., circuits, chips, or chip systems) within the access network equipment, or logical nodes, logical modules, or software capable of implementing all or part of the functions of the access network equipment. The method is described below using a network device as an example.

[0013] For example, the method includes: generating a first sequence comprising q concatenated gold sequences, each of the q gold sequences being obtained based on an initial sequence and a scrambling sequence; and transmitting the first sequence.

[0014] The initial sequence is an m-sequence generated from one information bit in a block of q information bits, and the scrambling sequence is an m-sequence generated from all or part of the information bits in the first information bit of length z, where z and q are integers greater than 1, and q is less than or equal to z.

[0015] The first information bit contains q blocks of information bits, or in other words, q blocks of information bits constitute the first information bit. This first information bit is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information.

[0016] Based on this technical solution, the first sequence sent by the network device to the terminal device is obtained by concatenating q gold sequences. Each of these q gold sequences is based on an initial sequence and a scrambling sequence. The initial sequence is generated based on q blocks of information bits contained in the first information bits, and the scrambling sequence is used to scramble the initial sequence to change the cross-correlation peak value among the q initial sequences. Therefore, this method of adding a scrambling sequence to the initial sequence can effectively reduce the probability of spurious peaks when the terminal device detects the first sequence, thereby increasing the probability of the terminal device correctly detecting the first sequence and thus effectively improving the downlink synchronization success rate.

[0017] In conjunction with the first and second aspects, in certain implementations of the first and second aspects, the scrambling sequence is an m-sequence generated based on all or part of the information bits in a first information bit of length z, including: the scrambling sequence is an m-sequence generated based on a second information bit.

[0018] One possible implementation is that the second information bit is obtained by summing and moduloing the p information bits in the q-block information bits, where p is an integer greater than 1 and less than or equal to q.

[0019] Here, p blocks of information bits can be any p blocks of information bits from q blocks of information bits. The selection of these p blocks of information bits is related to the information bit blocks used to generate the scrambling sequence. For example, the first gold sequence among q gold sequences is obtained based on a first initial sequence and a first scrambling sequence. The first initial sequence is generated based on the first block of information bits in the q blocks of information bits, so the second information bit can be obtained by summing and moduloing the remaining information bit blocks in the q blocks of information bits excluding the first block of information bits.

[0020] Another possible implementation is that the second information bit is another block of information bits within the q-block information bits. That is, in each gold sequence, the information bit block used to generate the initial sequence and the information bit block used to generate the scrambling sequence are located in different positions within the first information bits.

[0021] Optionally, when the second information bit is another information bit in a block of q information bits, the information bit used to generate the initial sequence is adjacent to the second information bit in the first information bit. Alternatively, when the second information bit is another information bit in a block of q information bits, the aforementioned information bit used to generate the initial sequence and the second information bit are consecutive information bits in the first information bit.

[0022] This method of generating scrambling sequences can increase the distance between adjacent sequences in the initial sequence to which the scrambling sequence is added, thereby reducing false peaks.

[0023] In conjunction with the first and second aspects, in some implementations of the first and second aspects, the q blocks of information bits are of equal length. That is, the first information bit is divided into q blocks of information bits, or q blocks of information bits of equal length constitute the first information bit.

[0024] This ensures that each information bit block contains the same number of bits, and the number of possible sequences corresponding to the same number of bits is also the same.

[0025] In conjunction with the first and second aspects, in certain implementations of the first and second aspects, the scrambling sequence is an m-sequence generated based on all or part of the information bits in a first information bit of length z, including: the scrambling sequence is generated based on a third information bit.

[0026] One possible implementation is that the third information bit is obtained by summing and moduloing the y-block information bits in the x-block information bits contained in the fourth information bit of length z.

[0027] The fourth information bit is obtained by interleaving the first information bit, where y is a positive integer less than or equal to x, and x is an integer greater than 1 and less than or equal to z.

[0028] The y-block information bits can be any y-block information bits from the x-block information bits. The y-block information bits corresponding to the scrambling sequences of the q gold sequences can be the same or different. If they are the same, then different gold sequences correspond to the same scrambling sequence; if they are different, then different gold sequences correspond to multiple scrambling sequences.

[0029] Another possible implementation is that the third information bit is one of the information bits in x blocks of information bits. It can be understood that the scrambling sequences corresponding to different gold sequences among the q gold sequences may correspond to the same or different blocks of information bits.

[0030] This method, which involves interleaving the first information bits and using the resulting fourth information bits to generate a scrambling sequence, can eliminate the problem of high false detection probability for fixed patterns.

[0031] In conjunction with the first and second aspects, in some implementations of the first and second aspects, the x blocks of information bits are of equal length. That is, the fourth information bit is divided into x blocks of information bits, or x blocks of information bits of equal length constitute the fourth information bit.

[0032] In conjunction with the first and second aspects, in some implementations of the first and second aspects, the first sequence further includes r gold sequences concatenated with q gold sequences, the r gold sequences being obtained by repeating all or part of the q gold sequences.

[0033] This increases the probability that the terminal device can correctly detect the first sequence, thereby effectively improving the success rate of downlink synchronization.

[0034] Thirdly, this application provides a communication method that can be applied to the terminal side, such as a terminal or a communication module in a terminal, or a circuit or chip in a terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core). The following describes the method using a terminal as an example.

[0035] For example, the method includes: receiving a first sequence comprising n concatenated m sequences, the n m sequences being generated based on all or part of the bits in a coded bit of length b; and performing downlink synchronization based on the first sequence.

[0036] The encoded bits of length b are obtained by encoding the first information bits of length z.

[0037] The first information bit is used to indicate the time-frequency resource configuration of subsequent sequences or information, the number of repetitions, b is an integer greater than or equal to n, and n and z are integers greater than 1.

[0038] Based on this technical solution, the first sequence received by the terminal device is obtained by concatenating n m sequences. These n m sequences are generated based on all or part of the bits in a coded bit of length b, and the coded bit of length b is obtained by encoding the first information bit. This method of generating m sequences based on coded bits minimizes the probability of sending the same sequence at the same position among multiple m sequences carrying different information bits in the first sequence. This effectively reduces the probability of false peaks appearing when the terminal device detects the first sequence, thereby effectively improving the probability of the terminal device correctly detecting the first sequence and thus effectively improving the success rate of downlink synchronization.

[0039] Similar to the first aspect, the first information bit of length z can be composed of q blocks of information bits. Optionally, the encoded bit of length b can be obtained by encoding each information bit in the q blocks of information bits as an information bit; or, the encoded bit of length b can be obtained by encoding the q blocks of information bits as information bits.

[0040] Fourthly, this application provides a communication method that can be applied to the network side, such as access network equipment, modules (e.g., circuits, chips, or chip systems) within the access network equipment, or logical nodes, logical modules, or software capable of implementing all or part of the functions of the access network equipment. The method is described below using a network device as an example.

[0041] For example, the method includes: receiving a first sequence comprising n concatenated m sequences, the n m sequences being generated based on all or some bits of an encoded bit of length b; and transmitting the first sequence.

[0042] The encoded bits of length b are obtained by encoding the first information bits of length z.

[0043] The first information bit is used to indicate the time-frequency resource configuration of subsequent sequences or information, the number of repetitions, b is an integer greater than or equal to n, and n and z are integers greater than 1.

[0044] Based on this technical solution, the network device sends a first sequence obtained by concatenating n m sequences to the terminal device. These n m sequences are generated based on all or part of the bits in a coded bit set of length b, where the coded bit set of length b is obtained by encoding the first information bit. This method of generating m sequences based on coded bits minimizes the probability of sending the same sequence at the same position among multiple m sequences carrying different information bits in the first sequence. This effectively reduces the probability of false peaks appearing when the terminal device detects the first sequence, thereby significantly increasing the probability of the terminal device correctly detecting the first sequence and thus effectively improving the success rate of downlink synchronization.

[0045] Similar to the first aspect, the first information bit of length z can be composed of q blocks of information bits. Optionally, the encoded bit of length b can be obtained by encoding each information bit in the q blocks of information bits as an information bit; or, the encoded bit of length b can be obtained by encoding the q blocks of information bits as information bits.

[0046] In conjunction with the third and fourth aspects, in some implementations of the third and fourth aspects, n m sequences are generated based on all or part of the coded bits in a coded bit of length b, including: each m sequence in the n m sequences is generated based on one bit in a d block of bits included in the coded bits, where d is an integer greater than or equal to n.

[0047] This allows the first information bit of length z to be distributed across different sequences.

[0048] Optionally, the d blocks of bits are of equal length. That is, the encoded bits are divided into d blocks of bits, or d blocks of bits of equal length constitute the first information bits.

[0049] In conjunction with the third and fourth aspects, in some implementations of the third and fourth aspects, the first sequence also includes s m sequences concatenated with the n m sequences, where the s m sequences are obtained by repeating all or part of the n m sequences.

[0050] Optionally, when the n m sequences are generated based on a portion of the coded bits of length b, the s m sequences may also include m sequences generated based on the remaining bits of the coded bits excluding the portion of the bits.

[0051] This increases the probability that the terminal device can correctly detect the first sequence, thereby effectively improving the success rate of downlink synchronization.

[0052] Fifthly, this application provides a communication device, including modules or units for implementing the methods of any of the above aspects and any possible implementations of any of the above aspects. It should be understood that each module or unit can implement its corresponding function by executing a computer program.

[0053] Sixthly, this application provides a communication device including a processor, the processor being configured to perform the methods described in any of the foregoing aspects and any possible implementations of any of the foregoing aspects.

[0054] The apparatus may further include a memory for storing instructions and data. The memory is coupled to the processor, which, when executing the instructions stored in the memory, can implement the methods described in the foregoing aspects.

[0055] The device may also include a communication interface for communicating with other devices. For example, the communication interface may be a transceiver, circuit, bus, module or other type of communication interface.

[0056] In a seventh aspect, this application provides a chip system including at least one processor for supporting the implementation of the functions involved in any of the above aspects and any possible implementations of any of the above aspects, such as receiving or processing data and / or information involved in the above methods.

[0057] In one possible design, the chip system also includes a memory for storing program instructions and data, which may be located within or outside the processor.

[0058] The chip system can consist of chips or include chips and other discrete components.

[0059] Eighthly, this application provides a computer-readable storage medium including a computer program that, when run on a computer, causes the computer to implement the methods in any of the foregoing aspects and any possible implementations of any of the foregoing aspects.

[0060] Ninthly, this application provides a computer program product comprising: a computer program (also referred to as code or instructions) that, when run, causes a computer to perform the methods of any of the above aspects and any possible implementations of any of the above aspects.

[0061] In a tenth aspect, this application provides a communication system including the aforementioned terminal device and network device. The terminal device is configured to execute the methods described in the first aspect and any possible implementation thereof, and the network device is configured to instruct the methods described in the second aspect and any possible implementation thereof. Alternatively, the terminal device is configured to instruct the methods described in the third aspect and any possible implementation thereof; and the network device is configured to instruct the methods described in the fourth aspect and any possible implementation thereof.

[0062] It should be understood that the fifth to tenth aspects of this application correspond to the technical solutions of the first to fourth aspects of this application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0063] Figure 1 is a schematic diagram of the architecture of a communication system applicable to the method provided in the embodiments of this application;

[0064] Figure 2 is a schematic diagram of an application scenario of a satellite network provided in an embodiment of this application;

[0065] Figure 3 is a schematic diagram of the NPSS and NSSS transmission subframe positions;

[0066] Figure 4 is a schematic flowchart of the communication method provided in an embodiment of this application;

[0067] Figure 5 is a schematic flowchart of a network device generating a first sequence according to an embodiment of this application;

[0068] Figure 6 is a schematic diagram of generating an initial sequence provided in an embodiment of this application;

[0069] Figure 7 is a schematic diagram of the generated scrambling sequence provided in an embodiment of this application;

[0070] Figure 8 is another schematic diagram of the generated scrambling sequence provided in an embodiment of this application;

[0071] Figure 9 is a schematic diagram of generating a gold sequence according to an embodiment of this application;

[0072] Figure 10 is another schematic diagram of generating a gold sequence provided in an embodiment of this application;

[0073] Figure 11 is another schematic diagram of generating a gold sequence provided in an embodiment of this application;

[0074] Figure 12 is another schematic flowchart of the communication method provided in an embodiment of this application;

[0075] Figure 13 is a schematic diagram of the encoded bits provided in an embodiment of this application;

[0076] Figure 14 is another schematic flowchart of the network device generating the first sequence provided in an embodiment of this application;

[0077] Figure 15 is another schematic diagram of the encoded bits provided in an embodiment of this application;

[0078] Figure 16 is a schematic diagram of generating m sequences provided in an embodiment of this application;

[0079] Figure 17 is a schematic block diagram of the device provided in an embodiment of this application;

[0080] Figure 18 is another schematic block diagram of the device provided in the embodiments of this application. Detailed Implementation

[0081] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0082] To facilitate understanding of the embodiments of this application, the following points are explained first:

[0083] First, in the embodiments of this application, the use of prefixes such as "first" and "second" is merely for the purpose of distinguishing and describing different things belonging to the same name category, and does not constrain the order, size, or quantity of things. For example, "first information bit" and "second information bit" are simply different information bits, and there is no temporal sequence, size, or priority relationship between them.

[0084] Second, in the embodiments of this application, "send" and "receive" indicate the direction of signal transmission. For example, "send the first sequence to the terminal device" can be understood as the destination of the information being the terminal device, which may include direct transmission via the air interface or indirect transmission via the air interface by other units or modules. "Receive the first sequence from the network device" can be understood as the source of the configuration information being the network device, which may include direct reception from the network device via the air interface or indirect reception from the network device via the air interface by other units or modules. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface.

[0085] In other words, sending and receiving can occur between devices, such as between terminal devices and network devices; or they can occur within a device, such as between components, modules, chips, software modules, or hardware modules within a device via a bus, wiring, or interface.

[0086] It is understandable that information may undergo necessary processing, such as encoding and modulation, before being sent from the source to the destination. Similarly, the destination, upon receiving information from the source, can also perform corresponding processing, such as decoding and demodulation, to interpret the valid information from the source. Similar expressions in this application can be understood in a similar way and will not be elaborated further.

[0087] Third, in the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the preceding and following related objects, but it does not exclude the possibility of indicating an "and" relationship. The specific meaning can be understood in conjunction with the context. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c; a and b; a and c; b and c; or a and b and c. Here, a, b, and c can be single or multiple.

[0088] Fourth, in the embodiments of this application, descriptions such as "when," "under the circumstances," "if," and "if" all refer to the fact that the device (e.g., network device or terminal device) will make corresponding processing under certain objective circumstances. They are not time limits, nor do they require the device (e.g., network device or terminal device) to make a judgment action when implementing it, nor do they imply any other limitations.

[0089] Fifth, the predefined terms in this application can be understood as: definition, pre-defined, storage, pre-storage, pre-negotiation, pre-configuration, solidification, or pre-firing.

[0090] Sixth, the term "storage" in this application can refer to storage in one or more memory devices. These memory devices can be separate installations or integrated into an encoder, decoder, processor, or communication device. Alternatively, some memory devices can be separately installed, while others can be integrated into the decoder, processor, or communication device. The type of memory can be any form of storage medium, and this application does not limit this.

[0091] The technical solutions provided in this application can be applied to various communication systems, such as: Long Term Evolution (LTE) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, sidelink (SL) communication systems, 5th generation (5G) mobile communication systems or new radio access technology (NR), satellite communication systems, etc. Among them, 5G mobile communication systems can include non-standalone (NSA) and / or standalone (SA) networking. The technical solutions provided in this application can also be applied to future communication networks. The satellite communication system can be a satellite communication system integrated with 5G communication systems or future communication systems, such as a non-terrestrial network (NTN).

[0092] The network device in this application can be a radio access network (RAN) device with wireless transceiver capabilities. RAN devices can provide wireless communication services, allowing terminals to access the wireless network. RAN devices can be nodes within the radio access network, referred to as RAN nodes.

[0093] In one possible scenario, a RAN node can be a base station (BS), an evolved NodeB (eNodeB), a transmission reception point (TRP), a home evolved NodeB (or home Node B, HNB), an access point (AP) for wireless fidelity (Wi-Fi), a mobile switching center, or a base station in a future mobile communication system. A RAN node can also be a device that performs base station functions in device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, machine-to-machine (M2M) communication systems, and internet-to-things (IoT) communication systems. A RAN node can also be a RAN node in a non-terrestrial network (NTN), meaning that a RAN node can be deployed on a high-altitude platform or satellite, or a satellite with base station functions, or a high / low-altitude device with base station functions. RAN nodes can be macro base stations, micro base stations, indoor stations, relay nodes, donor nodes, etc., or radio controllers in cloud radio access network (CRAN) scenarios, or nodes in open radio access network (O-RAN or ORAN) scenarios. Optionally, RAN nodes can also be servers, wearable devices, vehicles, or in-vehicle equipment. For example, in V2X technology, RAN nodes can be roadside units (RSUs). Of course, RAN nodes can also be nodes in the core network. In satellite communication scenarios, RAN nodes can be satellites, or equipment deployed on high-altitude platforms or within satellites that performs base station functions.

[0094] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0095] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU may also be called an open CU (O-CU), DU may also be called an open DU (O-DU), CU-CP may also be called an open CU-CP (O-CU-CP), CU-UP may also be called an open CU-UP (O-CU-UP), and RU may also be called an open RU (O-RU).

[0096] Any one of the CU (or CU-CP, CU-UP), DU, and RU units can be implemented through software modules, hardware modules, or a combination of software and hardware modules. That is, the wireless access network device in this application can be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. The general-purpose hardware can be a server, such as a cloud server.

[0097] The terminal equipment in this application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device.

[0098] Terminal devices can be devices that provide voice / data connectivity to users, such as handheld devices with wireless connectivity, in-vehicle devices, etc. Currently, examples of terminal devices include: mobile phones, tablets, computers with wireless transceiver capabilities (such as laptops and PDAs), mobile internet devices (MIDs), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving vehicles, drones, wireless terminals in remote medical care, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in 5G networks, or future evolution of public terrestrial mobile communication networks (PPPoE). Terminal equipment in a land mobile network (PLMN), etc.

[0099] Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices; they achieve powerful functions through software support, data interaction, and cloud interaction. Broadly defined, wearable smart devices include those with comprehensive functions, large sizes, and the ability to perform complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses. They also include devices focused on a specific application function that require the use of other devices, such as smart bracelets and smart jewelry for vital sign monitoring.

[0100] Furthermore, terminal devices can also be terminal devices within an IoT system. IoT is a crucial component of future information technology development, its main technological characteristic being the connection of objects to networks via communication technologies, thereby achieving intelligent networks that enable human-machine and machine-to-machine interconnection. IoT technology, for example, can achieve massive connectivity, deep coverage, and low power consumption at the terminal level through narrowband (NB) technology.

[0101] In addition, terminal devices may also include sensors such as smart printers, train detectors, and gas stations. Their main functions include collecting data (for some terminal devices), receiving control information and downlink data from network devices, and sending electromagnetic waves to transmit uplink data to network devices.

[0102] The terminal device in this application can be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. The general-purpose hardware can be a server, such as a cloud server.

[0103] In addition, the terminal equipment can also be a terminal equipment in a satellite communication system, such as NTN.

[0104] It should be understood that this application does not limit the specific form of wireless access network equipment and terminal equipment.

[0105] Figure 1 is a schematic diagram of the architecture of a communication system 100 applicable to the method provided in the embodiments of this application. As shown in Figure 1, the communication system 100 includes a wireless access network 10 and a core network 20. Optionally, the communication system 100 may also include an Internet 30. The wireless access network 10 may include at least one wireless access network device (110a and 110b in Figure 1) and at least one terminal device (120a-120j in Figure 1).

[0106] Terminal devices can connect to radio access network (RAN) devices wirelessly, and RAN devices can connect to the core network wirelessly or via wired connections. Core network devices and RAN devices can be independent, separate physical devices, or they can integrate the functions of core network devices and the logical functions of RAN devices onto a single physical device. Alternatively, a single physical device can integrate some core network device functions and some RAN device functions. Terminals and RAN devices can connect to each other via wired or wireless connections.

[0107] Communication between wireless access network devices and terminal devices, between wireless access network devices, and between terminal devices can all be conducted using licensed spectrum, unlicensed spectrum, or a combination of both. Communication can be conducted using spectrum below 6 GHz, spectrum above 6 GHz, or a combination of both. The embodiments of this application do not limit the spectrum resources used for wireless communication.

[0108] Among them, the wireless access network equipment can be a base station deployed in the air, such as a satellite base station 110a; or it can be a base station deployed indoors, such as a micro base station or an indoor station 110b.

[0109] The terminal equipment can be terminal equipment deployed in the air, such as the helicopter or drone 120i in Figure 1; or it can be terminal equipment deployed on the ground, such as mobile phones 120a, 120e, 120f and 120j, vehicle 120b, computer 110b, printer 120h, etc. in Figure 1.

[0110] Wireless access network equipment and terminals can be fixed or mobile. For example, wireless access network equipment and terminal equipment can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and satellites.

[0111] The roles of wireless access network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile base station. For those 120j accessing the wireless access network 10 via 120i, 120i is a base station; but for 110a, 120i is a terminal, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via an interface protocol between wireless access network devices. In this case, relative to 110a, 120i is also a base station. Therefore, both wireless access network devices and terminal devices can be collectively referred to as communication devices. 110a, 110b, and 120a-120j in Figure 1 can be called communication devices with their respective corresponding functions, such as communication devices with base station functions or communication devices with terminal device functions.

[0112] It should be understood that Figure 1 is only a schematic diagram. The communication system may also include other devices, such as wireless relay devices and wireless backhaul devices, which are not shown in Figure 1.

[0113] Figure 2 is a schematic diagram of an application scenario of a satellite network provided in an embodiment of this application. As shown in Figure 2, ground terminal equipment accesses the network through the 5G New Radio interface. 5G base stations are deployed on satellites and connected to ground stations via wireless links (NG interfaces), thereby connecting to the ground core network. Simultaneously, wireless links (Xn interfaces) exist between satellites to complete signaling interaction and user data transmission between base stations.

[0114] The ground station is responsible for forwarding signaling and service data between the satellite base station and the core network. The air interface is the wireless link between the terminal and the base station. The Xn interface is the interface between base stations, mainly used for signaling exchange such as handover. The NG interface is the interface between the base station and the core network, mainly exchanging core network NAS and other signaling, as well as user service data.

[0115] In wireless communication systems, such as scenarios where terminal devices are directly connected to satellites, the terminal devices may be obstructed due to factors like being placed in a bag or in remote mountainous areas. This can lead to these terminal devices missing or failing to receive downlink paging messages due to poor signal-to-noise ratio (SNR). RAN1 plans to introduce an alert channel to enhance paging, notifying terminal devices to move to a location with better coverage before receiving downlink paging. However, terminal devices need to complete downlink synchronization before receiving downlink paging.

[0116] Existing methods for obtaining downlink synchronization involve using the primary synchronization signals (PSS) and secondary synchronization signals (SSS) within the synchronization signal block (SSB). The PSS and SSS are single-symbol m-sequences or gold sequences that carry only the cell identifier (ID) and are not repeated. Therefore, terminal devices in deep fading environments have difficulty obtaining good downlink synchronization.

[0117] For NB-IoT systems, the narrow-band PSS (NPSS) consists of 11 repeated transmissions of a Zadoff-Chu (ZC) sequence of length 11, transmitted in a fixed subframe within each radio frame. The sequence generation does not carry any information. The NSSS is a ZC sequence of length 12*11=132, transmitted in the 9th subframe of even-numbered frames. The sequence generation carries the physical cell identifier (PCI) (9 bits) and temporal location information (2 bits). Terminal devices typically collect multiple PSSs to obtain downlink synchronization.

[0118] Figure 3 is a schematic diagram of the subframe positions for NPSS and NSSS transmission. As shown in Figure 3, NPSS is transmitted on the 5th subframe (i.e., subframe 5) of each radio frame (including radio frames with system frame number (SNF) mod 2 = 0 and SNF mod 2 = 1); NPSS is transmitted on the 9th subframe (i.e., subframe 9) in even-numbered frames (i.e., SFN mod 2 = 0).

[0119] Terminal devices operating in deep fading scenarios struggle to achieve downlink synchronization based on existing downlink synchronization sequences. Therefore, to ensure good downlink synchronization in such scenarios, the downlink synchronization sequence needs more repetitions and carries more bits of information. However, carrying such a large amount of information in a single sequence is often difficult. Distributing it across multiple sequences can increase the probability of the terminal device detecting spurious peaks due to the cross-correlation properties between sequences, leading to the terminal device's inability to correctly detect the downlink synchronization signal and ultimately preventing downlink synchronization from being completed.

[0120] In view of this, embodiments of this application provide a communication method, apparatus, and storage medium. In this method, multiple sequences carrying information bits are scrambled or encoded to reduce the cross-correlation peak between sequences, thereby reducing the probability of false peaks during detection, increasing the probability of the terminal device correctly detecting the sequence, and thus improving the success rate of downlink synchronization.

[0121] The communication method and apparatus provided in the embodiments of this application are described in detail below with reference to the accompanying drawings. The method provided in this application can be applied to the communication systems shown in Figures 1 and 2, but the embodiments of this application are not limited thereto.

[0122] Figure 4 is a schematic flowchart of the communication method 400 provided in an embodiment of this application. The flowchart in Figure 4 illustrates the method from the perspective of interaction between the terminal device and the network device, but this application does not limit the subject executing the method. For example, the terminal device in Figure 4 can replace the terminal or the communication module within the terminal, or the circuit or chip responsible for communication functions in the terminal (such as a modem chip, also known as a baseband chip, or a system-on-a-chip (SoC) chip containing a modem core, or a system-in-package (SIP) chip). The network device in Figure 4 can be replaced by a network device, a module within the network device (e.g., a circuit, chip, or chip system), or a logical node, logical module, or software capable of implementing all or part of the network device's functions.

[0123] As shown in Figure 4, method 400 may include steps S401 to S403. The steps in method 400 are described in detail below.

[0124] S401, the network device generates a first sequence, which includes q concatenated gold sequences, each of which is obtained based on an initial sequence and a scrambling sequence.

[0125] For example, each gold sequence can be obtained by adding the initial sequence and the scrambling sequence.

[0126] The initial sequence described above is an m-sequence generated from one information bit in a block of q information bits. The scrambling sequence is an m-sequence generated from all or part of the information bits in the first information bit of length z, where z and q are integers greater than 1, and q is less than or equal to z. The values ​​of z and q can be predefined.

[0127] The first information bit contains q blocks of information bits, or in other words, q blocks of information bits constitute the first information bit. This first information bit is used to indicate specific information such as the time-frequency resource configuration, repetition count, etc., of the subsequent sequence or information. The subsequent sequence can be, for example, a sequence of SS1 and / or SS2, and the subsequent information can be the information that needs to be sent in actual communication.

[0128] It can be understood that the q gold sequences in this application are obtained from q initial sequences and the same scrambling sequence. Alternatively, the q gold sequences in this application are obtained from q initial sequences and q scrambling sequences. The q initial sequences can each be generated from q blocks of information bits, and the q blocks of information bits may contain the same information bit blocks.

[0129] When the scrambling sequence is an m-sequence generated from all information bits in a first information bit of length z, the aforementioned q gold sequences can be obtained from different initial sequences and the same scrambling sequence. When the scrambling sequence is an m-sequence generated from a portion of the information bits in a first information bit of length z, the aforementioned q gold sequences can be obtained from different initial sequences and different scrambling sequences.

[0130] It is understandable that the q blocks of information bits can be of equal length. That is, the first information includes q blocks of information bits of equal length, or q blocks of information bits of equal length constitute the first information bits.

[0131] Optionally, the initial sequence and scrambling sequence used to obtain each gold sequence can be a preferred pair.

[0132] S402, the network device sends a first sequence to the terminal device. Correspondingly, the terminal device receives the first sequence from the network device.

[0133] S403, the terminal device performs downlink synchronization based on the first sequence.

[0134] In this embodiment, the first sequence sent by the network device to the terminal device is obtained by concatenating q gold sequences. Each of these q gold sequences is based on an initial sequence and a scrambling sequence. The initial sequence is generated based on q blocks of information bits contained in the first information bits, and the scrambling sequence is used to scramble the initial sequence to change the cross-correlation peak value among the q initial sequences. Therefore, this method of adding a scrambling sequence to the initial sequence can effectively reduce the probability of false peaks when the terminal device detects the first sequence, thereby increasing the probability of the terminal device correctly detecting the first sequence and thus effectively improving the downlink synchronization success rate.

[0135] Optionally, the scrambling sequence is an m-sequence generated based on all or part of the information bits in the first information bits of length z, including: the scrambling sequence is an m-sequence generated based on the second information bits.

[0136] Design 1: The second information bit can be obtained by summing and moduloing the p information bits in the q information bit block, where p is an integer greater than 1 and less than or equal to q.

[0137] Among them, the p-block information bits can be any p-block information bits from the q-block information bits.

[0138] When p = q, the scrambling sequence can be considered as an m-sequence generated based on all the information bits in the first information bit.

[0139] When p = q-1, the p-block information bits may not include a block of information bits used to generate the initial sequence. Specifically, the first glob sequence is obtained based on the first initial sequence and the first scrambling sequence. The first initial sequence is an m-sequence generated based on the first block of information bits in the q-block information bits, and the first scrambling sequence can be an m-sequence generated based on the remaining information bit block in the q-block information bits excluding the first block of information bits.

[0140] In design two, the second information bit can be another block of information bits within the q-block information bits. That is, the first initial sequence and the first scrambling sequence used to obtain the first gold sequence are m sequences generated based on different information bit blocks in the first information bits.

[0141] In this application, different information bit blocks (or different information bit blocks in q blocks of information bits) refer to two blocks of information bits located at different positions within the first information bit. For example, if the first information bit is 011101, the first block of information bits is 01, the second block of information bits is 11, and the third block of information bits is 01, since the first and third blocks of information bits are located at different positions within the first information bit, this application considers the first and third blocks of information bits to be different information bit blocks.

[0142] The first gold sequence in Design 1 and Design 2 is any one of the q gold sequences.

[0143] Optionally, if the second information bit is another block of information bits within a q-block of information bits, the aforementioned block of information bits used to generate the initial sequence is adjacent to the second information bit in the first information bit block. That is, the block of information bits used to generate the initial sequence and the second information bit are consecutive information bits in the first information bit block.

[0144] Optionally, the scrambling sequence is an m-sequence generated based on all or part of the information bits in the first information bits of length z, including: the scrambling sequence is generated based on the third information bits.

[0145] The third information bit is obtained by summing and moduloing the information bits of the y blocks in the x blocks of information bits; or, the third information bit is one information bit in the x blocks of information bits, where y is a positive integer less than or equal to x, and x is an integer greater than 1 and less than or equal to z.

[0146] Here, x blocks of information bits constitute a fourth information bit of length z. Alternatively, the fourth information bit of length z contains x blocks of information bits. This fourth information bit is obtained by interleaving the first information bit. Therefore, the fourth information bit and the first information bit have the same length and contain the same number of information bits, but the order of the information bits is different.

[0147] The value of x can be q, i.e., x = q.

[0148] Optionally, x blocks of information bits can be of equal or unequal length.

[0149] Optionally, the first sequence also includes r gold sequences concatenated with the q gold sequences, wherein the r gold sequences are obtained by repeating all or part of the q gold sequences.

[0150] If r is less than q, the r gold sequences are obtained by repeating a portion of the q gold sequences. This portion can be any r gold sequences from the q gold sequences.

[0151] If r is greater than q, the r gold sequences can be obtained by repeating all sequences from the q gold sequences. Some sequences may be repeated multiple times, while others may be repeated only once.

[0152] Alternatively, the r gold sequences can be mapped using different information bits corresponding to different frequency hopping patterns. This can reduce spurious peaks.

[0153] The process of generating the first sequence by the network device is described in detail below with reference to Figure 5. The process shown in Figure 5 can be implemented through steps 1 to 6.

[0154] Step 1: Divide the first information bit of length z into q blocks to obtain q blocks of information bits, with each block having a length of z / q.

[0155] For example, the first information bit 011011, which is 6 bits long, is divided into 3 blocks, resulting in the first block of information bits 01, the second block of information bits 10, and the third block of information bits 11. The length of each block of information bits is 2.

[0156] Step 2: Map each information bit in the q blocks of information bits to an m-sequence (i.e., the initial sequence mentioned above), resulting in q m-sequences.

[0157] Different m-sequences are obtained by cyclically shifting m-sequences. For example, 01 is mapped to m-sequence m1, 10 to m-sequence m2, 11 to m-sequence m3, and 00 to m-sequence m4. Here, m4 can be obtained by cyclically shifting m3, m3 can be obtained by cyclically shifting m2, and m2 can be obtained by cyclically shifting m1.

[0158] Figure 6 is a schematic diagram of generating an initial sequence provided in an embodiment of this application. Referring to the example in step 1 above, as shown in Figure 6, the first block of information bits 01 is mapped to an m-sequence m1, the second block of information bits 10 is mapped to an m-sequence m2, and the third block of information bits 11 is mapped to an m-sequence m3. Here, m1, m2, and m3 are the initial sequences described above.

[0159] Step 3: Generate at least one scrambling sequence based on the first information bits. The number of scrambling sequences can be 1 or q.

[0160] One possible implementation is to generate at least one scrambling sequence based on the first information bits, including: generating a scrambling sequence based on each block of information bits in the q blocks of information bits.

[0161] That is, q blocks of information bits can yield q scrambling sequences. Referring to the example in Figure 6, m1, m2, and m3 can also be the scrambling sequences described above.

[0162] A second possible implementation involves generating at least one scrambling sequence based on the first information bits, including generating one scrambling sequence based on each p block of information bits in the q-block information bits.

[0163] That is, the information bits of block q can be obtained A scrambling sequence.

[0164] Figure 7 is a schematic diagram of the generated scrambling sequence provided in an embodiment of this application. Referring to the example in step 1 above, and with p = 2, as shown in Figure 7, the sum of 01 and 10, modulo 11, maps to an m-sequence m3; the sum of 10 and 11, modulo 01, maps to an m-sequence m1; and the sum of 01 and 11, modulo 10, maps to an m-sequence m2. These m3, m1, and m2 are the scrambling sequences described above.

[0165] Figure 8 is another schematic diagram of the generation of scrambling sequence provided in the embodiment of this application. Combining with the example in step 1 above, and p = 3. As shown in Figure 8, the addition and modulo operation of the three information bits 01, 10 and 11 to obtain 00 is mapped to an m sequence m4, which is the scrambling sequence described above.

[0166] A third possible implementation involves generating at least one scrambling sequence based on the first information, including: interleaving the first information bits to obtain a fourth information bit of length z; and generating at least one scrambling sequence based on the fourth information bit.

[0167] Referring to the example in step 1, the first information bit 101011, after being processed by a 3×2 interleaver, yields the fourth information bit: 011101. Similarly, the fourth information bit is divided into three blocks: the first block contains information bit 01, the second block contains information bit 11, and the third block contains information bit 01. Therefore, the description of generating at least one scrambling sequence for the fourth information bit can be found in the first and second possible implementations described above, and will not be repeated here.

[0168] Step 4: Add a scrambling sequence to each of the q initial sequences to obtain q gold sequences. Alternatively, add a scrambling sequence to each of the q initial sequences to obtain q gold sequences.

[0169] When the number of scrambling sequences is 1, the same scrambling sequence is added to each of the q initial sequences; when the number of scrambling sequences is q, different scrambling sequences are added to each of the q initial sequences.

[0170] Figure 9 is a schematic diagram of generating a gold sequence according to an embodiment of this application. As shown in Figure 9, the initial sequence is m1, m2, m3 as shown in Figure 6, and the scrambling sequence is m1, m2, m3 as shown in Figure 6. Adding m1 and m2 yields the gold sequence g1, adding m2 and m3 yields the gold sequence g2, and adding m3 and m1 yields the gold sequence g3. That is, the information bit block used to generate the scrambling sequence is the next information bit block after the information bit block used to generate the initial sequence.

[0171] Figure 10 is another schematic diagram of generating a gold sequence according to an embodiment of this application. As shown in Figure 10, the initial sequence is m1, m2, and m3 as shown in Figure 6; the scrambling sequence is m1, m2, and m3 as shown in Figure 7. Adding m1 to m1 yields the gold sequence g1, adding m2 to m2 yields the gold sequence g2, and adding m3 to m3 yields the gold sequence g3. That is, the information bit block used to generate the scrambling sequence is the sum of the remaining information bit blocks in the q-block information bits, excluding the information bit block used to generate the initial sequence.

[0172] Figure 11 is another schematic diagram of generating a gold sequence provided in an embodiment of this application. As shown in Figure 11, the initial sequence is m1, m2, and m3 as shown in Figure 6; the scrambling sequence is m4 as shown in Figure 8. Adding m1 and m4 yields the gold sequence g1, adding m2 and m4 yields the gold sequence g2, and adding m3 and m4 yields the gold sequence g3. That is, the information bit block used to generate the scrambling sequence is the sum of q blocks of information bits.

[0173] Step 5: Repeat all or part of the q gold sequences to obtain r gold sequences.

[0174] Step 6: Concatenate the q gold sequences and the r gold sequences to obtain the first sequence. This first sequence can occupy (q+r) symbols in the time domain.

[0175] It is understandable that step 5 above can be omitted. If step 5 is omitted, step 6 can be replaced by concatenating the q gold sequences to obtain the first sequence.

[0176] Optionally, if it is necessary to repeatedly send the first information bits (i.e., to perform step 5), the network device may also generate the first sequence by performing the following steps:

[0177] Step 1: Divide the first information bit of length z into q blocks to obtain q blocks of information bits, with each block having a length of z / q.

[0178] Step 2: Map each information bit in the q blocks of information bits to an m-sequence (i.e., the initial sequence mentioned above), resulting in q m-sequences.

[0179] Step 3: Interleave the first information bit to obtain the fourth information bit of length z.

[0180] Step 4: Divide the fourth information bit of length z into q blocks to obtain q blocks of information bits, with each block having a length of z / q.

[0181] Step 5: Map the q blocks of information bits obtained in Step 4 to q m sequences (i.e., the scrambling sequences mentioned above).

[0182] Step 6: Add a scrambling sequence to each of the q initial sequences to obtain q gold sequences. Alternatively, add a scrambling sequence to each of the q initial sequences to obtain q gold sequences.

[0183] Optionally, after step 6, steps 3 to 6 can be repeated N times (N is a positive integer) to obtain (N×q) gold sequences again. It should be noted that when repeating steps 3 to 6, the interleaving method in step 3 needs to be continuously changed. That is, the interleaving method used each time step 3 is repeated is different.

[0184] Step 7: Concatenate all the gold sequences obtained in the above steps to obtain the first sequence.

[0185] Figure 12 is another schematic flowchart of the communication method 1200 provided in an embodiment of this application. The flowchart in Figure 12 illustrates the method from the perspective of interaction between the terminal device and the network device, but this application does not limit the subject executing the method. For example, the terminal device in Figure 12 can replace the terminal or the communication module in the terminal, or the circuit or chip in the terminal responsible for communication functions (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core); the network device in Figure 12 can be replaced by a network device, a module in the network device (e.g., a circuit, chip, or chip system), or a logical node, logical module, or software capable of implementing all or part of the network device functions.

[0186] As shown in Figure 12, method 1200 may include steps S1201 to S1203. The steps in method 1200 are described in detail below.

[0187] S1201, the network device generates a first sequence, which includes n concatenated m sequences, the n m sequences being generated based on all or part of the bits in a coded bit of length b.

[0188] The encoded bits of length b are obtained by encoding the first information bits of length z. The first information bits are used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information, where b is an integer greater than or equal to n, and n and z are integers greater than 1.

[0189] Similar to method 400, the first information bit of length z contains q blocks of information bits, or in other words, q blocks of information bits constitute the first information bit. Therefore, the encoded bit of length b can be obtained by encoding each information bit in the q blocks of information bits as an information bit (hereinafter referred to as method one); or the encoded bit of length b can be obtained by encoding the q blocks of information bits as information bits (hereinafter referred to as method two).

[0190] Figure 13 is a schematic diagram of the encoded bits provided in an embodiment of this application. As shown in Figure 13(a), in method one, the encoded bit of length b can be composed of q blocks of encoded bits, where each block can be obtained by encoding one information bit from the q blocks of information bits. That is, each block of encoded bits includes an information bit and a parity bit, and the parity bit in each block is obtained by encoding the information bit in that block. As shown in Figure 13(b), in method two, the encoded bit of length b is composed of a first information bit and a first parity bit.

[0191] Optionally, the above-mentioned encoding type can be maximum distance separable (MDS) encoding, including Reed-Solomon (RS) encoding, Bose–Chaudhuri–Hocquenghem (BCH) encoding, etc.

[0192] S1202, the network device sends a first sequence to the terminal device. Correspondingly, the terminal device receives the first sequence from the network device.

[0193] S1203, the terminal device performs downlink synchronization based on the first sequence.

[0194] In this embodiment, the first sequence sent by the network device to the terminal device is obtained by concatenating n m sequences. These n m sequences are generated based on all or part of the bits in a coded bit of length b, which is obtained by encoding the first information bit. Therefore, the n m sequences include m sequences generated based on the check bits in the coded bits. This method of generating the first sequence minimizes the probability of the same sequence being sent at the same position between sequences carrying different information in the paging notification sequence, i.e., maximizes the distance between them. This reduces the probability of false peaks appearing during blind detection, increases the probability of the terminal device correctly detecting the first sequence, and thus improves the success rate of downlink synchronization.

[0195] Optionally, the n m-sequences are generated based on all or part of the coded bits in a coded bit array of length b, including: each m-sequence in the n m-sequences is generated based on a single bit in a d-block bit array. Alternatively, a single bit in a d-block bit array is mapped to an m-sequence, and the n m-sequences belong to the d m-sequences. d is an integer greater than or equal to n.

[0196] Here, d blocks of bits constitute a coded bit of length b. Or, a coded bit of length b contains d blocks of bits.

[0197] Combining the descriptions of Method 1 and Method 2 above, a coded bit of length b includes information bits and parity bits. Therefore, after dividing a coded bit of length b into blocks, some bit blocks may contain information bits but not parity bits; or contain parity bits but not information bits; or contain both information bits and parity bits. That is, a bit block in a d-block of bits may not contain information bits, or may not contain parity bits, or may contain both information bits and parity bits.

[0198] Based on the description of Method 1 above, d blocks of bits can be composed of q blocks of information bits and q blocks of parity bits. That is, each of the q sequences out of the n m sequences is generated based on one information bit from the q blocks of information bits, and each of the other q sequences out of the n m sequences is generated based on one parity bit from the q blocks of parity bits.

[0199] It can be understood that when n equals d, n m sequences are generated based on all the coded bits in a coded bit of length b; when n is less than d, n m sequences are generated based on a portion of the coded bits in a coded bit of length b.

[0200] Optionally, the d-block bits can be of equal or unequal length.

[0201] Optionally, the first sequence also includes s m sequences concatenated with the n m sequences, wherein the s m sequences are obtained by repeating all or part of the n m sequences.

[0202] The following section uses Method 1 as an example and describes in detail the process of the network device generating the first sequence in conjunction with Figure 14. The process shown in Figure 14 can be implemented through the following steps 1 to 4.

[0203] Step 1: Divide the first information bit of length z into q blocks to obtain q blocks of information bits, with each block having a length of z / q.

[0204] For example, the first information bit 011011, which is 6 bits long, is divided into 3 blocks, resulting in the first block of information bits 01, the second block of information bits 10, and the third block of information bits 11. The length of each block of information bits is 2.

[0205] Step 2: Use each block of information bits as an information bit and generate a parity bit (or check bit) using MDS encoding.

[0206] Figure 15 is another schematic diagram of the encoded bits provided in an embodiment of this application. As shown in Figure 15, in conjunction with the example in step 1, the first block of information bits is encoded to obtain the check bit 00; the second block of information bits is encoded to obtain the check bit 11; and the third block of information bits is encoded to obtain the check bit 01. The check bit obtained by encoding each block of information bits belongs to the d blocks of bits mentioned above.

[0207] Step 3: Map each information bit and each check bit to an m-sequence (or gold sequence) to obtain 2q m-sequences.

[0208] Different m-sequences are obtained by cyclically shifting m-sequences. For example, 01 is mapped to m-sequence m1, 10 to m-sequence m2, 11 to m-sequence m3, and 00 to m-sequence m4. Here, m4 can be obtained by cyclically shifting m3, m3 can be obtained by cyclically shifting m2, and m2 can be obtained by cyclically shifting m1.

[0209] Figure 16 is a schematic diagram of generating m-sequences according to an embodiment of this application. Referring to the example shown in Figure 15, as shown in Figure 16, information bit 01 is mapped to an m-sequence m1, information bit 10 is mapped to an m-sequence m2, and information bit 11 is mapped to an m-sequence m3. Check bit 00 is mapped to m4, and check bit 01 is mapped to m1.

[0210] Step 4: Concatenate the 2q m sequences to obtain the first sequence.

[0211] It is understandable that step 4 can be replaced by concatenating some of the m sequences from the 2q m sequences to obtain the first sequence. Alternatively, it can be replaced by copying all or some of the m sequences from the 2q m sequences to obtain s m sequences; concatenating the 2q m sequences and the s m sequences to obtain the first sequence.

[0212] The method provided by the embodiments of this application has been described in detail above with reference to Figures 1 to 16. The apparatus provided by the implementation of this application will be described in detail below with reference to Figures 17 and 18.

[0213] Figures 17 and 18 are schematic diagrams of possible apparatuses provided in embodiments of this application. These apparatuses can be used to implement the functions of terminal devices or network devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0214] Figure 17 is a schematic block diagram of the device provided in an embodiment of this application. As shown in Figure 17, the device 1700 includes a transceiver module 1710 and a processing module 1720.

[0215] One possible design is that the device 1700 is used to implement the functions of the terminal device in the method embodiments shown in Figures 4 and 12 above.

[0216] For example, the transceiver module 1710 is configured to: receive a first sequence, the first sequence comprising q concatenated gold sequences, each of the q gold sequences being obtained based on an initial sequence and a scrambling sequence, the initial sequence being an m-sequence generated based on one information bit from q blocks of information bits, and the scrambling sequence being an m-sequence generated based on all or part of the information bits from a first information bit of length z; wherein the first information bit contains the q blocks of information bits, the first information bit being used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information, z and q being integers greater than 1, and q being less than or equal to z; the processing module 1720 is configured to: perform downlink synchronization based on the first sequence.

[0217] For example, processing module 1720 is configured to: generate a first sequence comprising q concatenated gold sequences, each of the q gold sequences being obtained based on an initial sequence and a scrambling sequence, the initial sequence being an m-sequence generated based on one information bit from q blocks of information bits, and the scrambling sequence being an m-sequence generated based on all or part of the information bits from a first information bit of length z; wherein the first information bit contains the q blocks of information bits, the first information bit being used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information, z and q being integers greater than 1, and q being less than or equal to z; and transceiver module 1710 is configured to: transmit the first sequence.

[0218] A more detailed description of the transceiver module 1710 and the processing module 1720 can be obtained directly from the relevant descriptions in the embodiments shown in Figure 4 or Figure 12, and will not be repeated here.

[0219] Another possible design is that the device 1700 is used to implement the functions of the network device in the method embodiments shown in Figures 4 and 12 above.

[0220] For example, the transceiver module 1710 is configured to: receive a first sequence, the first sequence comprising n concatenated m sequences, the n m sequences being generated based on all or part of the bits in a coded bit of length b, the coded bit of length b being obtained by encoding a first information bit of length z; wherein, the first information bit is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information, b being an integer greater than or equal to n, and n and z being integers greater than 1; the processing module 1720 is configured to: perform downlink synchronization based on the first sequence.

[0221] For example, the processing module 1720 is configured to: generate a first sequence, the first sequence comprising n concatenated m sequences, the n m sequences being generated based on all or part of the bits in an encoding bit of length b, the encoding bit of length b being obtained by encoding a first information bit of length z; wherein, the first information bit is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information, b being an integer greater than or equal to n, and n and z being integers greater than 1; the transceiver module 1710 is configured to: transmit the first sequence.

[0222] A more detailed description of the transceiver module 1710 and the processing module 1720 can be obtained directly from the relevant descriptions in the embodiments shown in Figures 4 and 12, and will not be repeated here.

[0223] It should be noted that device 1700 may include a transmitting module but not a receiving module. Alternatively, device 1700 may include a receiving module but not a transmitting module. Specifically, it depends on whether the above-described scheme executed by device 1700 includes both transmitting and receiving actions. It is understood that because device 1700 has communication capabilities, it can also be called a communication device.

[0224] Figure 18 is another schematic block diagram of the device provided in an embodiment of this application. As shown in Figure 18, the device 1800 includes one or more processors 1810. The processor 1810 may be a general-purpose processor or a special-purpose processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor can be used to process communication protocols and communication data, and the central processing unit can be used to control the device (e.g., terminal device, network device, or chip, etc.), execute software programs, and process data of the software programs.

[0225] Alternatively, in one design, processor 1810 may include a program (also referred to as code or instructions) that can be executed on processor 1810, causing device 1800 to perform the methods executed by the terminal device or network device in the above method embodiments. In yet another possible design, device 1800 includes circuitry (not shown in FIG18) for implementing the functions of the terminal device or network device in the above method embodiments.

[0226] For example, processor 1810 can be used to execute computer programs or instructions in memory to implement the steps performed by the terminal device or network device in the method embodiments shown in any of the embodiments shown in FIG4 and FIG12.

[0227] Optionally, the device 1800 may include one or more memories 1820 storing programs (sometimes referred to as code or instructions) that can be run on the processor 1810, causing the device 1800 to perform the methods executed by the terminal device or network device in the above embodiments.

[0228] Optionally, the processor 1810 and / or memory 1820 may also store data. The processor and memory may be configured separately or integrated together.

[0229] Optionally, the device 1800 may further include a communication interface 1830. The processor 1810, sometimes referred to as a processing unit, controls the device (e.g., a terminal device or a network device). The communication interface 1830, sometimes referred to as a transceiver unit, transceiver, transceiver circuit, or transceiver, is used to implement the device's transceiver functions.

[0230] Optionally, the device 1800 also includes a communication interface 1830. The processor 1810 and the communication interface 1830 are coupled to each other. It is understood that the communication interface 1830 can be a transceiver or an input / output interface.

[0231] It is understandable that since device 1800 has communication capabilities, it can also be called a communication device.

[0232] When device 1800 is used to implement the methods of Figures 4 and 12, processor 1810 is used to execute the functions of the aforementioned processing unit, and communication interface 1830 is used to execute the functions of the aforementioned transceiver module. Whether communication interface 1830 is used for sending or receiving depends on whether the scheme executed by device 1800 is used to perform a sending or receiving action.

[0233] When the aforementioned device 1800 is a chip applied to a terminal device, the chip implements the functions of the terminal device in the above method embodiments. The chip of the terminal device receives signals from other modules (such as radio frequency modules or antennas) in the terminal device, and these signals may be sent to the terminal device by the network device; or, the chip of the terminal device sends signals to other modules (such as radio frequency modules or antennas) in the terminal device, and these signals may be sent to the network device by the terminal device.

[0234] When the aforementioned device 1800 is a chip applied to a network device, the chip implements the functions of the network device in the above method embodiments. The chip of the network device receives signals from other modules (such as radio frequency modules or antennas) in the network device, and these signals may be sent to the network device by the terminal device; or, the chip of the network device sends signals to other modules (such as radio frequency modules or antennas) in the network device, and these signals may be sent to the terminal device by the network device.

[0235] It is understood that when the device 1800 is a terminal device or a network device, the communication interface 1830 can be a transceiver, specifically including a transmitter and a receiver, with the transmitter used to send signals and the receiver used to receive signals. When the device 1800 is a chip applied to a terminal device or a network device, the communication interface 1830 can be an input / output circuit, wherein the input circuit can be used for receiving and the output interface can be used for sending.

[0236] It should be noted that the above method embodiments can be applied to a processor, or implemented by a processor. A processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed through integrated logic circuits in the processor's hardware or through software instructions.

[0237] The aforementioned processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0238] The steps of the method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in mature storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0239] The memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0240] The methods provided in the above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, in the form of a computer program product. The computer program product may include one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic disk), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0241] This application also provides a computer program product that, when run on a processor, can implement the methods shown in the above method embodiments.

[0242] This application also provides a computer-readable storage medium containing computer instructions that, when executed on a processor, can implement the methods shown in the above-described method embodiments.

[0243] This application also provides a chip, including a processor, for reading instructions stored in a memory. When the processor executes the stored instructions, the chip can implement the method shown in the above method embodiments.

[0244] This application also provides a communication system, including the aforementioned terminal device and network device.

[0245] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0246] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0247] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0248] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0249] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0250] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0251] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A communication method, characterized in that, include: A first sequence is received, comprising q concatenated gold sequences. Each of the q gold sequences is obtained based on an initial sequence and a scrambling sequence. The initial sequence is an m-sequence generated based on one information bit from q blocks of information bits. The scrambling sequence is an m-sequence generated based on all or part of the information bits from a first information bit of length z. The first information bit contains the q blocks of information bits and is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information. z and q are integers greater than 1, and q is less than or equal to z. Downlink synchronization is performed based on the first sequence.

2. A communication method, characterized in that, include: A first sequence is generated, comprising q concatenated gold sequences. Each of the q gold sequences is obtained based on an initial sequence and a scrambling sequence. The initial sequence is an m-sequence generated based on one information bit from q blocks of information bits. The scrambling sequence is an m-sequence generated based on all or part of the information bits from a first information bit of length z. The first information bit contains the q blocks of information bits and is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information. z and q are integers greater than 1, and q is less than or equal to z. Send the first sequence.

3. The method according to claim 1 or 2, characterized in that, The scrambling sequence is an m-sequence generated based on all or part of the information bits in a first information bit of length z, including: The scrambling sequence is an m-sequence generated based on the second information bits; The second information bit is obtained by summing and moduloing the p blocks of information bits in the q blocks of information bits; or, The second information bit is another block of information bits in the q-block information bits; Where p is an integer greater than 1 and less than or equal to q.

4. The method according to claim 3, characterized in that, The second information bit is another block of information bits in the q-block information bits; the block of information bits used to generate the initial sequence is adjacent to the second information bit in the first information bits.

5. The method according to any one of claims 1 to 4, characterized in that, The q-block information bits are of equal length.

6. The method according to claim 1 or 2, characterized in that, The scrambling sequence is an m-sequence generated based on all or part of the information bits in a first information bit of length z, including: The scrambling sequence is generated based on the third information bit; The third information bit is obtained by summing and moduloing the y-block information bits within the x-block information bits contained in the fourth information bit of length z; or, The third information bit is one of the information bits in the x blocks of information bits; The fourth information bit is obtained by interleaving the first information bit, where y is a positive integer less than or equal to x, and x is an integer greater than 1 and less than or equal to z.

7. The method according to claim 6, characterized in that, The x blocks of information bits are of equal length.

8. The method according to any one of claims 1 to 7, characterized in that, The first sequence also includes r gold sequences concatenated with the q gold sequences, wherein the r gold sequences are obtained by repeating all or part of the q gold sequences.

9. A communication method, characterized in that, include: A first sequence is received, the first sequence comprising n concatenated m sequences, the n m sequences being generated based on all or part of the bits in a coded bit of length b, the coded bit of length b being obtained by encoding a first information bit of length z; wherein, the first information bit is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information, b is an integer greater than or equal to n, and n and z are integers greater than 1; Downlink synchronization is performed based on the first sequence.

10. A communication method, characterized in that, include: A first sequence is generated, comprising n concatenated m sequences, wherein the n m sequences are generated based on all or part of the bits in an encoding bit of length b, wherein the encoding bit of length b is obtained by encoding a first information bit of length z; wherein the first information bit is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information, b is an integer greater than or equal to n, and n and z are integers greater than 1. Send the first sequence.

11. The method according to claim 9 or 10, characterized in that, The n m sequences are generated based on all or part of the coded bits of length b, including: Each of the n m sequences is generated based on a block of d bits included in the coded bits, where d is an integer greater than or equal to n.

12. The method according to claim 11, characterized in that, The d-block bits are of equal length.

13. The method according to any one of claims 9 to 12, characterized in that, The first sequence also includes s m sequences concatenated with the n m sequences, wherein the s m sequences are obtained by repeating all or part of the n m sequences.

14. A communication device, characterized in that, include: A transceiver module is used to receive a first sequence, which includes q concatenated gold sequences. Each of the q gold sequences is obtained based on an initial sequence and a scrambling sequence. The initial sequence is an m-sequence generated based on one information bit from q blocks of information bits. The scrambling sequence is an m-sequence generated based on all or part of the information bits from a first information bit of length z. The first information bit contains the q blocks of information bits and is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information. z and q are integers greater than 1, and q is less than or equal to z. The processing module is used to perform downlink synchronization based on the first sequence.

15. A communication device, characterized in that, include: A processing module is configured to generate a first sequence comprising q concatenated gold sequences. Each of the q gold sequences is obtained based on an initial sequence and a scrambling sequence. The initial sequence is an m-sequence generated based on one information bit from a block of q information bits. The scrambling sequence is an m-sequence generated based on all or part of the information bits from a first information bit of length z. The first information bit contains the q blocks of information bits and is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information. z and q are integers greater than 1, and q is less than or equal to z. The transceiver module is used to send the first sequence.

16. The apparatus according to claim 14 or 15, characterized in that, The scrambling sequence is an m-sequence generated based on all or part of the information bits in a first information bit of length z, including: The scrambling sequence is an m-sequence generated based on the second information bits; The second information bit is obtained by summing and moduloing the p blocks of information bits in the q blocks of information bits; or, The second information bit is another block of information bits in the q-block information bits; Where p is an integer greater than 1 and less than or equal to q.

17. The apparatus according to claim 16, characterized in that, The second information bit is another block of information bits in the q-block information bits; the block of information bits used to generate the initial sequence is adjacent to the second information bit in the first information bits.

18. The apparatus according to any one of claims 14 to 17, characterized in that, The q-block information bits are of equal length.

19. The apparatus according to claim 14 or 15, characterized in that, The scrambling sequence is an m-sequence generated based on all or part of the information bits in a first information bit of length z, including: The scrambling sequence is generated based on the third information bit; The third information bit is obtained by summing and moduloing the y-block information bits within the x-block information bits contained in the fourth information bit of length z; or, The third information bit is one of the information bits in the x blocks of information bits; The fourth information bit is obtained by interleaving the first information bit, where y is a positive integer less than or equal to x, and x is an integer greater than 1 and less than or equal to z.

20. The apparatus according to claim 19, characterized in that, The x blocks of information bits are of equal length.

21. The apparatus according to any one of claims 14 to 20, characterized in that, The first sequence also includes r gold sequences concatenated with the q gold sequences, wherein the r gold sequences are obtained by repeating all or part of the q gold sequences.

22. A communication device, characterized in that, include: A transceiver module is used to receive a first sequence, the first sequence comprising n concatenated m sequences, the n m sequences being generated based on all or part of the bits in an encoding bit of length b, the encoding bit of length b being obtained by encoding a first information bit of length z; wherein, the first information bit is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information, b being an integer greater than or equal to n, and n and z being integers greater than 1; The processing module is used to perform downlink synchronization based on the first sequence.

23. A communication device, characterized in that, include: A processing module is used to generate a first sequence, which includes n concatenated m sequences. The n m sequences are generated based on all or part of the bits in a coding bit of length b. The coding bit of length b is obtained by encoding a first information bit of length z. The first information bit is used to indicate the time-frequency resource configuration and repetition count of subsequent sequences or information. b is an integer greater than or equal to n, and n and z are integers greater than 1. The transceiver module is used to send the first sequence.

24. The apparatus according to claim 22 or 23, characterized in that, The n m sequences are generated based on all or part of the coded bits of length b, including: Each of the n m sequences is generated based on a block of coded bits from the d blocks of coded bits, where p is an integer greater than or equal to n.

25. The apparatus according to claim 24, characterized in that, The d-block bits are of equal length.

26. The apparatus according to any one of claims 22 to 25, characterized in that, The first sequence also includes s m sequences concatenated with the n m sequences, wherein the s m sequences are obtained by repeating all or part of the n m sequences.

27. A communication device, characterized in that, It includes at least one processor for causing the communication device to implement the method as described in any one of claims 1 to 13 by executing a computer program and / or by logic circuitry.

28. A computer-readable storage medium storing a computer program thereon, characterized in that, When the computer program is executed by a processor, the method of any one of claims 1 to 13 is performed.

29. A computer program product, characterized in that, Includes a computer program, and when the computer program is run, the method of any one of claims 1 to 13 is performed.

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