Single-inverter oscillator

Abstract

In some examples, provided is an apparatus comprising an oscillator comprising a pair of cross-coupled logic gates and a single inverter arranged to generate an output signal, wherein the output signal of the inverter is connected to the pair of cross-coupled logic gates, a first latch, arranged to capture the output of the oscillator on a first phase of a clock, and a second latch, arranged to capture the output of the oscillator on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock, a logic gate comprising a first input and a second input, wherein the first input comprises the output signal of the first latch, wherein the second input comprises an output of the second latch, wherein the logic gate is arranged to output a high signal only in response to the first input being the same as the second input.

Description

[0001] SING LE IN VERTER OSCILLATOR

[0002] TECHNICAL FIELD

[0003] The present disclosure relates, in general, to a single-inverter oscillator. Aspects of the disclosure relate to modelling physical phenomena using the single-inverter oscillator.

[0004] BACKGROUND

[0005] Oscillators are essential components in various electronic systems, generating periodic signals used in timing, signal processing, and frequency synthesis. In many applications, oscillators are also used to model physical phenomena, such as transistor leakage, which can provide valuable insights into the performance and characteristics of semiconductor devices. However, conventional oscillator designs, particularly those used for such measurements, sometimes face challenges related to area efficiency and operational reliability.

[0006] In conventional solutions, the typical approach is to use five or more large inverters to construct the required oscillator. This design, involving a minimum of 10 large transistors, ensures that the output signal is stable and can be used in subsequent stages for counting cycles or measuring leakage accurately. However, while this solution addresses the need for reliable oscillation, it introduces significant drawbacks in terms of area usage and power consumption.

[0007] The primary disadvantage of existing oscillator designs is the substantial area cost associated with the use of multiple large inverting stages. As the number of stages increases, so too does the number of transistors, leading to a design that consumes a significant amount of chip area. This is especially problematic in cases where it is required to perform a measurement in multiple locations, inevitably using many replicas of the measuring RO. The additional stages, although necessary for stable oscillation, contribute little to the measurement while dramatically increasing the size of the design.

[0008] Furthermore, these conventional oscillators may not guarantee the appropriate pulse width required for reliable signal capture by downstream flip-flops or counters, particularly when unbalanced waveforms are involved. As a result, existing solutions may require additional design considerations to prevent signal loss or failures in cycle counting. These limitations hinder the practical application of traditional oscillators in modem semiconductor designs where efficiency, accuracy, and reliability are paramount.

[0009] SUMMARY

[0010] An objective of the present disclosure is to provide a safe oscillator using a single transistor.

[0011] The foregoing and other objectives are achieved by the features of the independent claims.

[0012] Further implementation forms are apparent from the dependent claims, the description and the Figures.

[0013] A first aspect of the present disclosure provides an apparatus comprising an oscillator comprising a pair of cross-coupled logic gates and a single inverter arranged to generate an output signal, wherein the output signal of the inverter is connected to the pair of cross-coupled logic gates, a first latch, arranged to capture the output of the oscillator on a first phase of a clock, and a second latch, arranged to capture the output of the oscillator on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock, a logic gate comprising a first input and a second input, wherein the first input comprises the output signal of the first latch, wherein the second input comprises an output of the second latch, wherein the logic gate is arranged to output a high signal only in response to the first input being the same as the second input. Accordingly, a safe oscillator can be provided by employing a single large transistor, which helps mitigate pulse width races while ensuring the pulse width is wide enough for flip-flop functionality. This design choice enables the use of only a single large inverter stage instead of multiple, thereby significantly reducing the area required for the circuit. Additionally, the implementation of cross-coupled logic gates results in solid rail-level signals, contributing to a more robust overall design. Advantageously, the circuit ensures that the generation race remains functional, enhancing reliability and performance in the oscillator's operation.

[0014] The oscillator may comprise a ring oscillator.

[0015] The pair of cross-coupled logic gates may comprise a pair of NOR gates.

[0016] The first phase of the clock may comprise a low-to-high transition, wherein the second phase of the clock may comprise a high- to-low transition.

[0017] The second phase opposite to the first phase of the clock may comprise a phase shifted by 180 degrees from the first phase of the clock.

[0018] The first latch may comprise a master latch, wherein the second latch may comprise a slave latch.

[0019] The logic gate may comprise an exclusive NOR (XNOR) gate.

[0020] The oscillator may comprise multiple stages, wherein the multiple stages may comprise an inverter stage, wherein a speed of the inverter stage may be slower than a speed of remaining stages of the multiple stages, wherein the inverter stage may be arranged to measure a leakage current.

[0021] The oscillator may be associated with a delay, wherein the inverter stage of the multiple stages may account for a significant portion of the delay, and the remaining stages may account for a smaller portion of the delay than the inverter stage.

[0022] The other stages of the ring oscillator may be faster than the inverter stage by a factor of at least 100, wherein the inverter stage may contribute to at least 99% of the total delay of the oscillator signal.

[0023] The oscillator may be configured to have an unbalanced waveform, such that the high phase of the output signal may be shorter than the low phase.

[0024] The cross-coupled logic gates may be arranged to serve as a level shifter to accommodate the unbalanced waveform generated by the oscillator.

[0025] A second aspect of the present disclosure provides a method of fabricating an oscillator, the method comprising providing an oscillator comprising a pair of cross-coupled logic gates and a single inverter arranged to generate an output signal, wherein the output signal of the inverter is connected to the pair of cross-coupled logic gates, connecting an output of the oscillator to: a first latch, arranged to capture the output of the oscillator on a first phase of a clock, and a second latch, arranged to capture the output of the oscillator on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock, providing a logic gate comprising a first input and a second input, wherein the first input comprises the output signal of the first latch, wherein the second input comprises an output of the second latch, wherein the logic gate is arranged to output a high signal only in response to the first input being the same as the second input. The oscillator may comprise a ring oscillator.

[0026] A third aspect of the present disclosure provides a method of modelling a physical phenomenon using an apparatus comprising an oscillator comprising a pair of cross-coupled logic gates and a single inverter arranged to generate an output signal, wherein the output signal of the inverter is connected to the pair of cross-coupled logic gates, a first latch, arranged to capture the output of the oscillator on a first phase of a clock, and a second latch, arranged to capture the output of the oscillator on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock, a logic gate comprising a first input and a second input, wherein the first input comprises the output signal of the first latch, wherein the second input comprises an output of the second latch, wherein the logic gate is arranged to output a high signal only in response to the first input being the same as the second input, the method comprising using the output signal of the oscillator, captured by the first and second latches, to model the physical phenomenon by correlating the timing and duration of the output signal with the characteristics of the phenomenon being measured.

[0027] These and other aspects of the invention will be apparent from the embodiment(s) described below.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0030] Figure 1 is a schematic representation of an oscillator circuit according to an example;

[0031] Figure 2 is a schematic representation of an apparatus according to an example;

[0032] Figure 3 is a flow chart of a method for manufacturing the apparatus according to an example; and

[0033] Figure 4 is a flow chart of a method for modelling a physical phenomenon according to an example.

[0034] DETAILED DESCRIPTION

[0035] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0036] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0037] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and ‘The” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof. Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0038] A common approach in the design of oscillators is to use multiple stages, typically comprising inverting logic gates, to ensure reliable oscillation. For instance, an oscillator may require at least five stages to generate a stable output signal. When modelling physical phenomena, such as transistor leakage, the transistors used in the oscillator stages may need to be quite large to capture the desired behaviour accurately. As a result, the traditional five-stage oscillator design could involve as many as 10 large transistors, significantly increasing the area and complexity of the circuit.

[0039] The problem becomes even more pronounced when the oscillator is used in environments where space and power efficiency are critical. For example, in semiconductor testing or sensor applications, the area overhead of these large transistors can limit the applicability of the design. Moreover, the resulting waveform produced by the oscillator must be suitable for capturing by flip-flops (FFs) or other clocked components, requiring adequate high and low times. If the pulse widths generated by the oscillator are too short, the signal may fail to be captured reliably, further reducing the efficacy of the solution.

[0040] According to an example, there is provided a mechanism to reduce the area and improve the reliability of oscillators used to model physical phenomena, such as leakage, in semiconductor devices. More specifically, aspects of the invention relate to the use of a single large inverter stage instead of multiple stages, in combination with cross-coupled NOR gates functioning as a Schmitt trigger and level shifter. For example, this mechanism provides solid rail-level signals, ensuring robust operation of the oscillator. In addition, a master-slave flip-flop with an XNOR safety gate is leveraged to address pulse-width race issues, ensuring that the signal generated is wide enough to be reliably captured by a flip-flop. This approach advantageously reduces the overall area by minimising the number of large transistors required, while maintaining the functionality and safety of the oscillator. Thus, in an example, instead of using multiple large devices, the invention utilises a single large transistor to model physical phenomena, providing a safe, functional circuit with minimised area cost.

[0041] Examples in the present disclosure can be provided as methods, systems or machine-readable instructions, such as any combination of software, hardware, firmware or the like. Such machine-readable instructions may be included on a computer readable storage medium (including but not limited to disc storage, CD-ROM, optical storage, etc.) having computer readable program codes therein or thereon.

[0042] The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary and / or additional blocks may be added. It shall be understood that each flow and / or block in the flow charts and / or block diagrams, as well as combinations of the flows and / or diagrams in the flow charts and / or block diagrams can be realized by machine readable instructions.

[0043] Figure 1 is a schematic representation of an oscillator circuit 100 according to an example. The oscillator circuit may comprise an inverter 101, a pair of cross-coupled logic gates 102 (for example, NOR gates), and multiple transistors 103, 104, and 105. In this design, the slow inverter 101 may be utilised to model a physical property, such as leakage. By employing just a single slow inverter, the circuit may effectively capture the rising output signal without the need for multiple inverting stages typically found in conventional ring oscillators (ROs). This single inverter may account for approximately 99% of the delay, while the remaining components contribute only 1%. This approach may significantly reduce both area and power consumption, as the circuit can achieve its objectives with minimal large leaky devices. The slow inverter 101 is a critical element in this design, as it is responsible for modelling the physical property to be measured by generating a delayed output signal. This signal, representing the property, may be captured and stabilised using the pair of cross-coupled logic gates 102. These cross-coupled NOR gates may be arranged to form a Schmitt trigger, which introduces hysteresis into the signal transition, ensuring that the output levels are stable and reducing susceptibility to noise. Additionally, the cross-coupled NOR gates may function as level shifters, which are important for ensuring that the output signal transitions are solid and reliable.

[0044] In operation, the rising edge of the output signal from the slow inverter 101 may be captured by the cross-coupled NOR gates within circuit 100. However, using only these three gates — a single slow inverter 101 and two fast NOR gates 102 — may result in a non-safe RO due to the possibility of generating a pulse that is too short to be reliably captured by a traditional flip-flop.

[0045] To address this problem, the implementation shown in Figure 2 may be used. Figure 2 is a schematic representation of an apparatus 200 according to an example. The apparatus 200 comprises the complete oscillator circuit, including the measuring inverter and level shifter, shown as element 100 in Figure 1, which may function as a ring oscillator. The oscillator circuit 100 may be responsible for generating the clock signal that drives the rest of the apparatus.

[0046] The apparatus further includes a first latch 201 and a second latch 202, both of which are arranged to capture the output of the measuring inverter 100. These latches may be clocked by the output of the oscillator circuit 100, with each latch’s data input connected to itself (inverted). As a result, every time the clock (i.e., the output of the measuring inverter and the level shifter (oscillator circuit 100)) rises, the latches 201 and 202 may flip their state, alternating between high and low phases.

[0047] The critical function of this arrangement lies in the interaction with the exclusive-NOR (XNOR) gate 204. The XNOR gate 204 may be designed to respond to the clock signal generated by the oscillator circuit 100. Specifically, the output of the XNOR 204 may rise when the clock signal from the measuring inverter 100 rises and falls after the latches 201 and 202 have been properly clocked. This ensures that the oscillator circuit captures and processes the signal correctly, with the latches switching state in response to the clock while the XNOR provides an additional timing control that governs the oscillator’s operation.

[0048] The first latch 201 may function as a master latch, while the second latch 202 may act as a slave latch. This division helps mitigate issues associated with using a single slow inverter 101 and two fast NOR gates 102. By splitting the flip-flop stage into a master latch 201 and a slave latch 202, the system may effectively handle potentially short pulses that may otherwise be lost. Specifically, the slave latch 202 may receive a pulse that is too short for conventional data capture.

[0049] The first latch 201 may remain open for most of the clock cycle, specifically when the clock signal is low. During this time, the input from the master latch 201 may be passed transparently to the second latch 202, which remains closed. Upon the clock signal rising, the first latch 201 may close, and the second latch 202 may open. When the second latch 202 opens, it may output the data present at its input, which causes the XNOR gate 204 to rise. This rise in the XNOR output may allow the clock signal to fall again, at which point the second latch 202 may close, and the first latch 201 may reopen, passing the newly inverted output back to the input of the second latch.

[0050] This configuration may effectively widen the clock pulse to the duration required for the flip-flop to operate correctly. The two latches, combined, 201+ 202, may serve as the first stage of a counter circuit, providing a stable 50% duty cycle signal at its output. This signal may be ideal for driving any counter circuit required for subsequent operations, ensuring consistent timing and reliable signal capture. The apparatus 200 further comprises a feedback circuit 204, which may include a logic gate with a first input and a second input. The first input may comprise the output signal of the first latch 201, while the second input may represent the output of the second latch 202. This logic gate is arranged to output a high signal only when the first input is the same as the second input. The logic gate may comprise an exclusive NOR (XNOR) gate, which ensures that the output signal is one only when the inputs to the XNOR gate are equal.

[0051] Through the presence of the feedback circuit 204 (and the XNOR gate therein), a hazardous "generation race" may be transformed into a self-limited race. This guarantees that the high pulse, once it has performed its task, is no longer needed and can be safely discarded. The XNOR gate effectively ensures that the signal is propagated only when the pulse has accomplished its intended function, thereby preventing potential errors and ensuring the robustness of the oscillator's operation.

[0052] In the embodiment shown in Figure 2, the apparatus 200 may also comprise a further logic gate 203 (for example, an AND gate). The AND gate 203 may take one or more inputs to produce a high (logic 1 ) output only when all its inputs are high. This gate may serve as part of the control mechanism for the oscillator circuit 100, ensuring that specific conditions are met before allowing the output to proceed.

[0053] Advantageously, the output signal of the oscillator 100, captured by the first and second latches, to model the physical phenomenon by correlating the timing and duration of the output signal with the characteristics of the phenomenon being measured. This correlation may allow for the assessment of the physical phenomenon based on variations in the output signal's properties, such as pulse width and frequency, thus enabling accurate modelling of the phenomenon in question.

[0054] Figure 3 is a method of fabricating an apparatus comprising an oscillator. The method comprises, in block 301, providing the oscillator comprising a pair of cross-coupled logic gates and a single inverter arranged to generate an output signal, wherein the output signal of the inverter is connected to the pair of cross-coupled logic gates. In block 302, the method comprises connecting an output of the oscillator to: a first latch, arranged to capture the output of the oscillator on a first phase of a clock, and a second latch, arranged to capture the output of the oscillator on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock. In block 303, the method comprises providing a logic gate comprising a first input and a second input, wherein the first input comprises the output signal of the first latch, wherein the second input comprises an output of the second latch, wherein the logic gate is arranged to output a high signal only in response to the first input being the same as the second input. The resulting apparatus may correspond to the apparatus 200 described above in relation to Figures 1 and 2.

[0055] Figure 4 is a flow chart of a method for modelling a physical phenomenon according to an example. The method comprises modelling a physical phenomenon (such as current leakage) using an apparatus comprising an oscillator comprising a pair of cross-coupled logic gates and a single inverter arranged to generate an output signal, wherein the output signal of the inverter is connected to the pair of cross-coupled logic gates, a first latch, arranged to capture the output of the oscillator on a first phase of a clock, and a second latch, arranged to capture the output of the oscillator on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock, a logic gate comprising a first input and a second input, wherein the first input comprises the output signal of the first latch, wherein the second input comprises an output of the second latch, wherein the logic gate is arranged to output a high signal only in response to the first input being the same as the second input. That is, the method may comprise using the apparatus described above in relation to Figures 1 and 2.

[0056] The method comprises, in block 401 , using the output signal of the oscillator, captured by the first and second latches, to model the physical phenomenon by correlating the timing and duration of the output signal with the characteristics of the phenomenon being measured. The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure. The embodiments disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Claims

CLAIMS1. An apparatus (200) comprising: an oscillator (100) comprising a pair of cross-coupled logic gates (102) and a single inverter (101) arranged to generate an output signal, wherein the output signal of the inverter (101) is connected to the pair of cross-coupled logic gates (102); a first latch (201), arranged to capture the output of the oscillator (100) on a first phase of a clock, and a second latch (202), arranged to capture the output of the oscillator (100) on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock; a logic gate (203) comprising a first input and a second input, wherein the first input comprises the output signal of the first latch (201), wherein the second input comprises an output of the second latch (202), wherein the logic gate (203) is arranged to output a high signal only in response to the first input being the same as the second input.

2. The apparatus (200) of claim 1, wherein the oscillator (100) comprises a ring oscillator.

3. The apparatus (200) of claim 2 or 3, wherein the pair of cross-coupled logic gates (102) comprises a pair of NOR gates.

4. The apparatus (200) of claim 1, 2 or 3, wherein the first phase of the clock comprises a low-to-high transition, wherein the second phase of the clock comprises a high-to-low transition.

5. The apparatus (200) of any one of claims 1 to 4, wherein the second phase opposite to the first phase of the clock comprises a phase shifted by 180 degrees from the first phase of the clock.

6. The apparatus (200) of any one of claims 1 to 5, wherein the first latch (201) comprises a master latch, wherein the second latch (202) comprises a slave latch.

7. The apparatus (200) of any one of claims 1 to 6, wherein the logic gate (203) comprises an exclusive NOR, XNOR, gate.

8. The apparatus (200) of any one of claims 1 to 7, wherein the oscillator (100) comprises multiple stages, wherein the multiple stages comprise an inverter stage, wherein a speed of the inverter stage is slower than a speed of remaining stages of the multiple stages, wherein the inverter stage is arranged to measure a leakage current.

9. The apparatus (200) of claim 8, wherein the oscillator (100) is associated with a delay, wherein the inverter stage of the multiple stages accounts for a significant portion of the delay, and the remaining stages account for a smaller portion of the delay than the inverter stage.

10. The apparatus (200) of claim 9, wherein the other stages of the oscillator (100) are faster than the inverter stage by a factor of at least 100, wherein the inverter stage contributes to at least 99% of the total delay of the oscillator signal.

811. The apparatus (200) of any one of claims 1 to 10, wherein the oscillator (100) is configured to have an unbalanced waveform, such that the high phase of the output signal is shorter than the low phase.

12. The apparatus (200) of any one of claims 1 to 10, wherein the cross-coupled logic gates (102) are arranged to serve as a level shifter to accommodate the unbalanced waveform generated by the oscillator (100).

13. A method of fabricating an oscillator, the method comprising: providing an oscillator comprising a pair of cross-coupled logic gates and a single inverter arranged to generate an output signal, wherein the output signal of the inverter is connected to the pair of cross-coupled logic gates (301) connecting an output of the oscillator to: a first latch, arranged to capture the output of the oscillator on a first phase of a clock, and a second latch, arranged to capture the output of the oscillator on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock 1'302 ): providing a logic gate comprising a first input and a second input, wherein the first input comprises the output signal of the first latch, wherein the second input comprises an output of the second latch, wherein the logic gate is arranged to output a high signal only in response to the first input being the same as the second input (303).

14. The method of claim 13, wherein the oscillator comprises a ring oscillator.

15. A method of modelling a physical phenomenon using an apparatus comprising an oscillator comprising a pair of crosscoupled logic gates and a single inverter arranged to generate an output signal, wherein the output signal of the inverter is connected to the pair of cross-coupled logic gates; a first latch, arranged to capture the output of the oscillator on a first phase of a clock, and a second latch, arranged to capture the output of the oscillator on a second phase of the clock, wherein the second phase of the clock comprises a phase opposite to the first phase of the clock; a logic gate comprising a first input and a second input, wherein the first input comprises the output signal of the first latch, wherein the second input comprises an output of the second latch, wherein the logic gate is arranged to output a high signal only in response to the first input being the same as the second input, the method comprising: using the output signal of the oscillator, captured by the first and second latches, to model the physical phenomenon by correlating the timing and duration of the output signal with the characteristics of the phenomenon being measured (401).

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