Imaging element and imaging device

Abstract

An imaging element includes a plurality of pixels and a capacitive element. A pixel is formed on a semiconductor substrate and includes: a photoelectric conversion unit that performs photoelectric conversion of incident light to generate charge; and a signal generating unit that generates a pixel signal that is a signal based on the generated charge. The capacitive element includes: a lower electrode disposed for each of the pixels, the lower electrode disposed adjacent to an inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film formed in a shape to cover the lower electrode; an upper electrode formed in a shape to face the lower electrode via the insulating film in the opening; and a lower electrode protection portion disposed adjacent to an upper end of the lower electrode to protect the lower electrode.

Description

IMAGING ELEMENT AND IMAGING DEVICE

[0001] The present disclosure relates to an imaging element and an imaging device.

[0002] Among imaging elements that generate an image signal on the basis of light from a subject, a complementary metal oxide semiconductor (CMOS)-type imaging element includes a plurality of pixels arranged in a two-dimensional matrix shape. In these pixels, a photoelectric conversion unit that performs photoelectric conversion of incident light, a charge retaining unit that retains a charge generated by the photoelectric conversion unit, and a signal generating unit that generates a signal corresponding to the charge retained in the charge retaining unit are arranged. The photoelectric conversion unit performs photoelectric conversion during an exposure period to accumulate charges. These charges are transferred to and retained in the charge retaining unit after the exposure period. Then, the signal generating unit generates a signal on the basis of the charge retained in the charge retaining unit and outputs the signal as an image signal.

[0003] A floating diffusion (FD) region which is a semiconductor region formed in a semiconductor substrate is used for the charge retaining unit. In the case where the charge retaining capacitance in the FD is insufficient or in a case of an application for switching the charge retaining capacitance, an auxiliary charge retaining unit is added to a pixel. A photodetection element (imaging element) using a metal insulator metal (MIM) capacitive element as such an additional charge retaining unit has been proposed (see, for example, PTL 1.). The MIM capacitive element is disposed in an insulating layer in a wiring region adjacent to the semiconductor substrate and includes a lower electrode, an insulating film, and an upper electrode arranged on a side wall of a trench formed in the insulating layer. The lower electrode is formed in a film shape covering the side wall of the trench and is disposed only inside the trench. In addition, the insulating film is formed in a shape covering a surface including the upper end of the lower electrode. The upper electrode facing the lower electrode is disposed across the insulating film.

[0004] WO 2024 / 053372 A

[0005] However, in the above-described related art, since the upper end of the lower electrode formed inside the trench is exposed in the manufacturing process of the imaging element, there is a disadvantage that the upper end of the lower electrode is damaged in subsequent steps. Therefore, there is a disadvantage that the performance of the capacitive element is deteriorated.

[0006] Therefore, the present disclosure proposes an imaging element and an imaging device that reduce damages to a capacitive element arranged in a pixel.

[0007] An imaging element according to the present disclosure includes: a plurality of pixels formed on a semiconductor substrate, the plurality of pixels comprising: a photoelectric conversion unit that performs photoelectric conversion of incident light to generate charge; and a signal generating unit that generates a pixel signal that is a signal based on the generated charge; and a capacitive element comprising: a lower electrode disposed for each of the pixels, the lower electrode disposed adjacent to an inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film formed in a shape to cover the lower electrode; an upper electrode formed in a shape to face the lower electrode via the insulating film in the opening; and a lower electrode protection portion disposed adjacent to an upper end of the lower electrode to protect the lower electrode.

[0008] Fig. 1 is a diagram illustrating a configuration example of an imaging element according to an embodiment of the present disclosure.Fig. 2 is a diagram illustrating a configuration example of a pixel according to the embodiment of the disclosure.Fig. 3 is a cross-sectional view illustrating a structure example of a pixel according to a first embodiment of the disclosure.Fig. 4 is a diagram illustrating a structure example of a second charge retaining unit according to the first embodiment of the disclosure.Fig. 5 is a diagram illustrating a structure example of a pixel according to the first embodiment of the disclosure.Fig. 6A is a diagram illustrating an exemplary manufacturing method of an imaging element according to the first embodiment of the disclosure.Fig. 6B is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 6C is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 6D is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 6E is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 6F is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 6G is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 6H is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 6I is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 6J is a diagram illustrating the exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure.Fig. 7A is a diagram for explaining an effect of a lower electrode protection portion according to the first embodiment of the disclosure.Fig. 7B is a diagram for explaining the effect of the lower electrode protection portion according to the first embodiment of the disclosure.Fig. 8 is a diagram illustrating a structure example of a pixel according to a second embodiment of the disclosure.Fig. 9 is a diagram illustrating a structure example of a second charge retaining unit according to the second embodiment of the disclosure.Fig. 10A is a diagram illustrating an exemplary manufacturing method of an imaging element according to the second embodiment of the disclosure.Fig. 10B is a diagram illustrating an exemplary manufacturing method of the imaging element according to the second embodiment of the disclosure.Fig. 10C is a diagram illustrating the exemplary manufacturing method of the imaging element according to the second embodiment of the disclosure.Fig. 10D is a diagram illustrating the exemplary manufacturing method of the imaging element according to the second embodiment of the disclosure.Fig. 10E is a diagram illustrating the exemplary manufacturing method of the imaging element according to the second embodiment of the disclosure.Fig. 10F is a diagram illustrating the exemplary manufacturing method of the imaging element according to the second embodiment of the disclosure.Fig. 10G is a diagram illustrating the exemplary manufacturing method of the imaging element according to the second embodiment of the disclosure.Fig. 10H is a diagram illustrating the exemplary manufacturing method of the imaging element according to the second embodiment of the disclosure.Fig. 11 is a diagram illustrating another structure example of a second charge retaining unit according to the second embodiment of the disclosure.Fig. 12 is a diagram illustrating a structure example of a capacitive element according to a third embodiment of the disclosure.Fig. 13 is a diagram illustrating another structure example of the capacitive element according to the third embodiment of the disclosure.Fig. 14 is a diagram illustrating another structure example of the capacitive element according to the third embodiment of the disclosure.Fig. 15 is a diagram illustrating another structure example of the capacitive element according to the third embodiment of the disclosure.Fig. 16 is a diagram illustrating another structure example of the capacitive element according to the third embodiment of the disclosure.Fig. 17 is a diagram illustrating a structure example of an imaging element according to the third embodiment of the disclosure.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail on the basis of the drawings. Description will be given in the following order. Note that in each of the following embodiments, the same parts are denoted by the same symbols, and redundant description will be omitted. 1. First Embodiment 2. Second Embodiment 3. Third Embodiment

[0010] (1. First Embodiment) <Configuration of Imaging Element> Fig. 1 is a diagram illustrating a structure example of an imaging element according to an embodiment of the present disclosure. The drawing is a block diagram illustrating a configuration example of an imaging element 1. The imaging element 1 is a semiconductor element that generates image data of a subject. The imaging element 1 includes a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 30, and a control unit 40.

[0011] The pixel array unit 10 includes a plurality of pixels 100 arranged therein. In the pixel array unit 10, a plurality of pixels 100 is arranged in the shape of a two-dimensional matrix. In this example, a pixel 100 includes a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge retaining unit (first charge retaining unit 105 to be described later) that retains a charge generated by the photoelectric conversion. For example, a photodiode can be used for the photoelectric conversion unit. Furthermore, a signal generating unit (signal generating unit 110 described later) is disposed in each of the pixels 100. The signal generating unit 110 generates an image signal on the basis of a charge retained in a first charge retaining unit 105 of the pixel 100.

[0012] Signal lines 11 are wired to each of the pixels 100. The pixel 100 is controlled by a control signal transmitted by the signal lines 11. Furthermore, a signal line 12 is wired to the pixel 100. An image signal from the signal generating unit 110 is output to the signal line 12. Note that a signal line 11 is disposed for each of the rows shaping the two-dimensional matrix and is wired in a shared manner to a plurality of pixels 100 arranged in one row. A signal line 12 is disposed for each of the columns shaping the two-dimensional matrix and is wired in a shared manner to a plurality of pixels 100 arranged in one column.

[0013] The vertical drive unit 20 generates control signals for the pixels 100 described above. The vertical drive unit 20 in the drawing generates a control signal for each of the rows of the two-dimensional matrix of the pixel array unit 10 and sequentially outputs the control signals via a signal line 11.

[0014] The column signal processing unit 30 processes an image signal generated by a pixel 100. The column signal processing unit 30 in the drawing simultaneously processes image signals from a plurality of pixels 100 arranged in one row of the pixel array unit 10 transmitted via a signal line 12. As this processing, for example, analog-digital conversion for converting an analog image signal generated by a pixel 100 into a digital image signal or correlated double sampling (CDS) for removing an offset error of the image signal can be performed. The processed image signal is output to a circuit or the like outside the imaging element 1.

[0015] The control unit 40 controls the vertical drive unit 20 and the column signal processing unit 30. The control unit 40 in the drawing outputs control signals via each of a signal lines 41 and 42 to control the vertical drive unit 20 and the column signal processing unit 30.

[0016] Note that the imaging element 1 is an example of the "imaging device" of the present disclosure. In addition, the column signal processing unit 30 is an example of the "processing circuit" of the present disclosure.

[0017] <Configuration of Pixel> Fig. 2 is a diagram illustrating a configuration example of a pixel according to the embodiment of the disclosure. The drawing is a circuit diagram illustrating a configuration example of a pixel 100.

[0018] The pixel 100 includes a photoelectric conversion unit 101, a charge transfer unit 102, a first charge retaining unit 105, a reset unit 104, a coupling transistor 103, a second charge retaining unit 106, and the signal generating unit 110. The signal generating unit 110 further includes an amplification transistor 111 and a selection transistor 112.

[0019] The charge transfer unit 102, the coupling transistor 103, the reset unit 104, the amplification transistor 111, and the selection transistor 112 can include an n-channel MOS transistor. Meanwhile, the first charge retaining unit 105 can include a semiconductor region similar to the FD described above.

[0020] As described above, the signal lines 11 and 12 are wired to the pixel 100. The signal lines 11 in the drawing include a signal line TG, a signal line FDG, a signal line RST, and a signal line SEL. Meanwhile, the signal line 12 includes a signal line VSL. In addition, power supply lines VDD and MIMVDD are wired to the pixel 100. The MIMVDD is a wire that supplies a voltage applied to the second charge retaining unit 106.

[0021] The anode of the photoelectric conversion unit 101 is connected to a common grounding wire, and the cathode is connected to the source of the charge transfer unit 102. The drain of the charge transfer unit 102 is connected to the gate of the amplification transistor 111, the drain of the coupling transistor 103, and one end of the first charge retaining unit 105. The other end of the first charge retaining unit 105 is connected to the common grounding wire. The drain of the reset unit 104 and the drain of the amplification transistor 111 are connected to the power supply lines VDD. The drain of the coupling transistor 103 and one end of the second charge retaining unit 106 are connected to the source of the reset unit 104. Another end of the second charge retaining unit 106 is connected to the MIMVDD. The source of the amplification transistor 111 is connected to the drain of the selection transistor 112, and the source of the selection transistor 112 is connected to the signal line VSL.

[0022] The gate of the charge transfer unit 102 is connected to the signal line TG. The gate of the reset unit 104 is connected to the signal line RST. The gate of the coupling transistor 103 is connected to the signal line FDG. The gate of the selection transistor 112 is connected to the signal line SEL.

[0023] The reset unit 104 resets the first charge retaining unit 105 and the second charge retaining unit 106. This reset can be performed by discharging charges of the first charge retaining unit 105 and others to the power supply lines VDD. A control signal for the reset unit 104 is transmitted by the signal line RST.

[0024] The amplification transistor 111 amplifies the voltage of the first charge retaining unit 105. The gate of the amplification transistor 111 is connected to the first charge retaining unit 105. Therefore, an image signal having a voltage corresponding to the charge retained in the first charge retaining unit 105 is generated at the source of the amplification transistor 111. Furthermore, the image signal can be output to the signal line VSL by making the selection transistor 112 conductive. A control signal for the selection transistor 112 is transmitted by the signal line SEL.

[0025] The second charge retaining unit 106 is a capacitor coupled to the first charge retaining unit 105. By coupling the second charge retaining unit 106 to the first charge retaining unit 105, the charge retaining capacitance of the pixel 100 can be adjusted. That is, by coupling the second charge retaining unit 106 to the first charge retaining unit 105, the charge retaining capacitance of the pixel 100 can be increased. As a result, the sensitivity of the pixel 100 can be adjusted. In a case where the second charge retaining unit 106 is not coupled to the first charge retaining unit 105, a high sensitivity mode is set. Contrarily, in a case where the second charge retaining unit 106 is coupled to the first charge retaining unit 105, a low sensitivity mode is set.

[0026] The coupling transistor 103 couples the second charge retaining unit 106 to the first charge retaining unit 105.

[0027] <Structure of Cross-Section of Pixel> Fig. 3 is a cross-sectional view illustrating a structure example of a pixel according to the first embodiment of the disclosure. The drawing is a cross section illustrating a structure example of a pixel 100. The pixel 100 includes a semiconductor substrate 120, a wiring region 140, a color filter 192, and an on-chip lens 193.

[0028] The semiconductor substrate 120 is a semiconductor substrate in which a diffusion layer of a semiconductor element of the pixel 100 is disposed. The semiconductor substrate 120 can be made of silicon (Si), for example. The semiconductor element and others are arranged in a well region formed in the semiconductor substrate 120. For convenience, it is based on the premise that the semiconductor substrate 120 in the drawing includes a p-type well region. A semiconductor element can be formed by disposing an n-type or p-type semiconductor region in the p-type well region. An insulating film 139 is disposed on a surface on the front side of the semiconductor substrate 120. The insulating film 139 can be made of, for example, silicon oxide (SiO2) or silicon nitride (SiN).

[0029] The photoelectric conversion unit 101, the first charge retaining unit 105, the charge transfer unit 102, and the amplification transistor 111 are illustrated in the semiconductor substrate 120 in the drawing. The photoelectric conversion unit 101 includes an n-type semiconductor region 121. Specifically, a photodiode including a p-n junction at an interface between the n-type semiconductor region 121 and a surrounding p-type well region corresponds to the photoelectric conversion unit 101. Note that the semiconductor region 121 has a shape in which a part protrudes to the vicinity of the surface on the front side of the semiconductor substrate 120.

[0030] The first charge retaining unit 105 includes a semiconductor region 122. The semiconductor region 122 is an n-type semiconductor region having a relatively high impurity concentration. The semiconductor region 122 corresponds to the FD described above.

[0031] The charge transfer unit 102 includes a MOS transistor including the semiconductor regions 121 and 122 and a gate electrode 131. The semiconductor region 121 corresponds to the source region, and the semiconductor region 122 corresponds to the drain region. Note that the insulating film 139 immediately below the gate electrode 131 corresponds to the gate insulating film.

[0032] Note that only the gate electrode of the amplification transistor 111 is illustrated. The gate electrode is connected with the semiconductor region 122 of the first charge retaining unit 105 by wiring 151 and a contact plug 153 described later. An isolator 129 for isolation from other elements is disposed on the semiconductor substrate 120 in the vicinity of the amplification transistor 111. The isolator 129 can be configured by shallow trench isolation (STI).

[0033] The wiring region 140 is a region disposed on the surface on the front side of the semiconductor substrate 120 and in which wiring of an element is formed. The wiring region 140 includes the wiring 151, a via plug 152, a contact plug 153, and an insulating layer 141. The wiring 151 is a conductor that transmits a signal to an element or the like in the semiconductor substrate 120. The wiring 151 can be made of metal such as copper (Cu) or tungsten (W). The insulating layer 141 insulates the wiring 151 and others. The insulating layer 141 can be made of, for example, SiO2. As illustrated in the drawing, the wiring can be formed in multiple layers. In this case, multiple layers of insulating films are also formed. An insulating layer disposed between layers is also referred to as an interlayer insulating film. The via plug 152 connects pieces of wiring 151 arranged in different layers. The via plug 152 can be made of a metal having a columnar shape, for example. The contact plug 153 connects an element and others in the semiconductor substrate 120 and the wiring 151.

[0034] An isolator 138 is further disposed in the semiconductor substrate 120. This isolator 138 is disposed at a boundary of the pixel 100 in the semiconductor substrate 120 to electrically and optically isolate the pixel 100. The isolator 138 can be formed of an insulator embedded in the semiconductor substrate 120. The isolator 138 can be formed, for example, by disposing an insulator such as SiO2in a groove penetrating the semiconductor substrate 120 formed at the boundary of the pixel 100.

[0035] In addition, a protective film 191 is disposed on a surface on the back side of the semiconductor substrate 120. The protective film 191 protects the back side of the semiconductor substrate 120. The protective film 191 can be made of an insulator such as SiO2.

[0036] The color filter 192 is an optical filter that transmits incident light having a predetermined wavelength among incident light. As the color filter 192, color filters that transmit red light, green light, or blue light can be used. In this case, one color filter 192 corresponding to any of red light, green light, or blue light is disposed in the pixel 100. The pixel 100 generates an image signal of incident light having a wavelength supported by the color filter 192.

[0037] The on-chip lens 193 has a hemispherical cross section and condenses incident light on the photoelectric conversion unit 101. The on-chip lens 193 can be made of an organic material such as an acrylic resin or an inorganic material such as SiN.

[0038] The second charge retaining unit 106 is disposed in the wiring region 140 in the drawing. Unlike the above-described first charge retaining unit 105, the second charge retaining unit 106 includes a capacitive element 160. Details of the structure of the second charge retaining unit 106 will be described with reference to Fig. 4.

[0039] <Structure of Second Charge Retaining Unit> Fig. 4 is a diagram illustrating a structure example of the second charge retaining unit according to the first embodiment of the disclosure. The drawing is a schematic cross-sectional view illustrating a structure example of the second charge retaining unit 106. The wiring region 140 in the drawing includes a stack of a plurality of insulating layers. In the drawing, insulating layers 141 to 143 are illustrated. Wiring is formed between these insulating layers. An insulating film 149 is disposed between the insulating layers 141 and 142. The insulating film 149 is referred to as a block film and can be made of SiN or silicon carbide nitride (SiCN).An insulating film 148 is disposed between the insulating layers 142 and 143. The insulating film 148 can be made of, for example, SiN or SiCN.

[0040] As described above, the second charge retaining unit 106 includes the capacitive element 160. The capacitive element 160 in the drawing is formed in the insulating layer 142. The capacitive element 160 includes a lower electrode 162, an insulating film 163, and an upper electrode 164.

[0041] The lower electrode 162 is disposed adjacent to an inner wall of an opening 161 formed in the insulating layer 142. The lower electrode 162 can be made of, for example, a metal or a metal compound. For example, the lower electrode 162 can be made of a metal (for example, Ti, Ta, W, Mo, Al, Cu, Co, Ni, or Ru) or a compound containing any of the above metals (for example, TiN, TaN, WN, or MoN). Note that the lower electrode 162 is preferably formed of a member having a lower selection ratio in etching than that of the insulating layer 142.

[0042] The insulating film 163 is formed in a shape covering the lower electrode 162. The insulating film 163 can be made of an oxide or a nitride. Moreover, a member having a high relative permittivity called high-k, such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), or hafnium oxide (HfO2), can also be applied to the insulating film 163. Furthermore, the insulating film 163 can also be formed by stacking these members.

[0043] The upper electrode 164 is formed in a shape facing the lower electrode 162 via the insulating film 163 in the opening 161. The upper electrode 164 can be formed of a similar member to that of the lower electrode 162. Note that the second charge retaining unit 106 can include a plurality of capacitive elements 160. The upper electrode 164 can be formed in a shape having a plurality of protrusions arranged in openings 161 of respective capacitive elements 160. Note the upper electrode 164 can also be regarded as an electrode portion disposed in the opening 161. In this case, the second charge retaining unit 106 in the drawing can be regarded as having an electrode structure in which a plurality of upper electrodes 164 arranged in respective openings 161 is coupled by a common electrode.

[0044] The lower electrode 162 is connected to lower layer wiring 155 which is disposed in a lower layer of the wiring region 140. The upper electrode 164 is connected to upper layer wiring 156 which is disposed in an upper layer of the wiring region 140. The upper layer wiring 156 in the drawing is connected with the upper electrode 164 via a via plug 157. In addition, the upper layer wiring 156 is connected to wiring 154 disposed in the insulating layer 141 via a via plug 158.

[0045] Note that the second charge retaining unit 106 can also be configured by one capacitive element 160.

[0046] As illustrated in the drawing, the lower electrode 162 is disposed only inside the opening 161. In addition, since an end of the lower electrode 162 is covered with the insulating film 163, the lower electrode has a shape separated from an end of the upper electrode 164. As a result, the electric resistance between the lower electrode 162 and the upper electrode 164 can be improved, and the leakage current can be reduced.

[0047] As described above, the insulating film 148 is disposed above the insulating layer 142. The insulating film 148 is made of a member having a lower selection ratio in etching than that of the insulating layer 142. Specifically, in a case where SiO2is applied to the insulating layer 142, SiN can be applied to the insulating film 148. In addition, the insulating film 148 in the vicinity of the capacitive element 160 is formed in a shape in which an end protrudes onto the lower electrode 162. That is, the end of the insulating film 148 is disposed adjacent to the upper end of the lower electrode 162. The region of the insulating film 148 which is disposed adjacent to the upper end of the lower electrode 162 is referred to as a lower electrode protection portion 165. The lower electrode protection portion 165 protects the lower electrode 162. Note that the insulating film 148 is an example of the "second insulating film" of the present disclosure.

[0048] <Structure of Pixel and Second Charge Retaining Unit> Fig. 5 is a diagram illustrating a structure example of a pixel according to the first embodiment of the disclosure. The drawing is a plan view illustrating a structure example of a pixel 100. As described above, a second charge retaining unit 106 is disposed in the pixel 100. A capacitive element 160 is disposed in the second charge retaining unit 106. A broken-line circle in the drawing represents an opening 161 of the capacitive element 160. The second charge retaining unit 106 in the drawing represents an exemplary case where the second charge retaining unit 106 includes sixteen capacitive elements 160 in four rows and four columns. By arranging a plurality of capacitive elements 160, the capacitance of the second charge retaining unit 106 can be increased. In addition, the lower layer wiring 155, the upper electrode 164, the upper layer wiring 156, and the via plugs 157 and 158 are illustrated in the drawing. Circles indicated by alternate long and short dash lines in the drawing represent the via plugs 157 and 158. The upper layer wiring 156 is connected to, for example, the MIMVDD in Fig. 2. Furthermore, the lower layer wiring 155 is connected to, for example, the reset unit 104 in Fig. 2.

[0049] <Manufacturing Method of Imaging Element> Figs. 6A to 6J are diagrams illustrating an exemplary manufacturing method of the imaging element according to the first embodiment of the disclosure. The drawings illustrate exemplary manufacturing steps of the capacitive element 160 part in the imaging element 1.

[0050] First, the insulating layer 141 of the wiring region 140 is formed on the semiconductor substrate 120, and the lower layer wiring 155 and the wiring 154 are arranged. Next, the insulating film 149, the insulating layer 142, and the insulating film 148 are stacked (Fig. 6A). The insulating layer 141, the insulating film 149, and the insulating layer 142 can be formed by, for example, chemical vapor deposition (CVD).

[0051] Next, an opening 400 is formed at a position where the insulating film 148 and the capacitive element 160 in the insulating layer 142 are arranged. The opening 400 has a lower end in contact with the lower layer wiring 155 (Fig. 6B). The opening 400 can be formed by, for example, dry etching.

[0052] Next, the insulating layer 142 in the opening 400 is etched to form the opening 161. At this point, the side surface of the insulating layer 142 in the opening 400 is ground, and a region in which the insulating film 148 protrudes toward the opening 400 is formed. This region forms the lower electrode protection portion 165 (Fig. 6C). The insulating layer 142 can be etched by, for example, atomic layer etching (ALE).

[0053] Next, a material film 401 of the lower electrode 162 is disposed on the surface of the insulating film 148 including the opening 161 (Fig. 6D). The material film 401 can be formed by sputtering, CVD, ALD, or plating.

[0054] Next, the material film 401 on the upper surface and the side surface of the insulating film 148 is removed to form the lower electrode 162 (Fig. 6E). The material film 401 can be removed by dry etching.

[0055] Next, the insulating film 163 is disposed on the upper surface of the insulating film 148 and the side surface of the lower electrode 162 (Fig. 6F). The insulating film 163 can be formed by, for example, CVD.

[0056] Next, the upper electrode 164 is formed (Fig. 6G). This can be performed, for example, by disposing a material film of the upper electrode 164 on the surface of the insulating film 163 including the opening 161 and removing an unnecessary portion. At this point, unnecessary portions are also removed in the insulating film 163. As a result, the capacitive element 160 can be formed.

[0057] Next, the insulating layer 143 is disposed on the upper electrode 164 (Fig. 6H). Next, the via plug 158 is formed (Fig. 6I). Next, an insulating layer is stacked to form the via plug 157 and the upper layer wiring 156 (Fig. 6J).

[0058] <Effects> Figs. 7A and 7B are diagrams illustrating the effect of the lower electrode protection portion according to the first embodiment of the present disclosure. Fig. 7A illustrates the capacitive element 160 in a case where the lower electrode protection portion 165 is not disposed, which is illustrated as a comparative example. As illustrated in the drawing, the lower electrode 162 has a shape in which the upper end is exposed inside the opening 161. Therefore, the upper end of the lower electrode 162 is damaged by the plasma of CVD at the time of forming the upper electrode 164. The arrows in the figure represent the plasma locus. There are also cases where a corner portion is scraped off in an etching step at the time of forming the lower electrode 162 itself, whereby a protrusion is formed. A hollow arrow in the drawing represents this protrusion. An electric field concentrates on such a protrusion, which causes damage.

[0059] Fig. 7B illustrates the capacitive element 160 having the lower electrode protection portion 165. The upper end of the lower electrode 162 is covered and protected by the lower electrode protection portion 165.

[0060] As described above, in the imaging element 1 according to the first embodiment of the present disclosure, the lower electrode protection portion 165 is disposed in the capacitive element 160. This makes it possible to prevent damages to the upper end of the lower electrode 162 in the manufacturing steps of the capacitive element 160.

[0061] (2. Second Embodiment) In the imaging element 1 of the first embodiment described above, the insulating film 163 and the upper electrode 164 are arranged inside the lower electrode 162. Meanwhile, an imaging element 1 according to a second embodiment of the present disclosure is different from the above-described first embodiment in that an insulating film 163 and an upper electrode 164 having a shape sandwiching a lower electrode 162 is included.

[0062] <Configuration of Imaging Device> Fig. 8 is a diagram illustrating a structure example of a pixel according to the second embodiment of the disclosure. The drawing is a plan view illustrating a structure example of a pixel 100 similarly to Fig. 5. The second charge retaining unit 106 in the drawing represents an exemplary case where the second charge retaining unit 106 includes sixteen capacitive elements 160 in four rows and four columns. Note that, in the drawing, illustration of the upper layer wiring 156 and the via plugs 157 and 158 is omitted. The capacitive element 160 in the drawing is disposed in a capacitive element region 170. In addition, a capacitive element region isolator 171 is disposed at the boundary of the capacitive element region 170. The region indicated by an alternate long and short dash line in the drawing represents the capacitive element region isolator 171. As illustrated in the drawing, the capacitive element 160 is disposed inside the capacitive element region isolator 171.

[0063] <Structure of Second Charge Retaining Unit> Fig. 9 is a diagram illustrating a structure example of the second charge retaining unit according to the second embodiment of the disclosure. The drawing is a schematic cross-sectional view illustrating a structure example of the second charge retaining unit 106 similarly to Fig. 4. The capacitive element 160 in the drawing includes an insulating film 163 disposed on both sides of a lower electrode 162 and an upper electrode 164 having a shape sandwiching the lower electrode 162 via the insulating film 163.

[0064] Meanwhile, the capacitive element 160 is disposed in the capacitive element region 170. The capacitive element region isolator 171 is disposed at the boundary of the capacitive element region 170. The capacitive element region isolator 171 isolates an insulating layer 142 inside the capacitive element region 170. The capacitive element region isolator 171 in the drawing illustrates an example in which the capacitive element region isolator 171 is configured by an annular capacitive element. Specifically, the capacitive element region isolator 171 includes a lower electrode (lower electrode 173), an insulating film, and an upper electrode arranged in an opening 172 formed in an annular groove shape in the insulating layer 142. Note that the lower electrode 173 of the capacitive element region isolator 171 is formed in a shape not in contact with lower layer wiring 155.

[0065] In the capacitive element 160 in the drawing, since the upper electrode 164 is disposed on both sides of the lower electrode 162, the electrostatic capacitance of the capacitive element 160 can be improved. Since a lower electrode protection portion 165 is disposed also in the capacitive element 160 in the drawing, damages to the upper end of the lower electrode 162 in the manufacturing steps can be prevented.

[0066] <Manufacturing Method of Imaging Element> Figs. 10A to 10H are diagrams illustrating an exemplary manufacturing method of the imaging element according to the second embodiment of the disclosure. The drawings illustrate exemplary manufacturing steps of the capacitive element 160 part in the imaging element 1.

[0067] First, as in Fig. 6A, an insulating layer 141 of a wiring region 140 is formed on a semiconductor substrate 120, and the lower layer wiring 155 is disposed. Next, an insulating film 149, an insulating layer 142, and an insulating film 148 are stacked (Fig. 10A).

[0068] Next, an opening 400 is formed at a position where the insulating film 148 and the capacitive element 160 in the insulating layer 142 are arranged. In addition, an opening 402 is formed at a position where the insulating film 148 and the capacitive element region isolator 171 in the insulating layer 142 are arranged. The opening 402 is formed to a depth at which the bottom is in contact with the insulating film 149 (Fig. 10B).

[0069] Next, the insulating layer 142 in the opening 400 is etched to form the opening 161. Furthermore, the insulating layer 142 in the opening 402 is etched to form the opening 172. At this point, a lower electrode protection portion 165 is formed (Fig. 10C).

[0070] Next, the lower electrode 162 is disposed in the opening 161. The lower electrode 173 is also disposed in the opening 172 (Fig. 10D).

[0071] Next, an opening 403 is formed in the insulating film 148 and the insulating layer 142 between capacitive elements 160 in the capacitive element region 170 (Fig. 10E).

[0072] Next, the insulating layer 142 is etched through the opening 403. The region to be etched is limited to the inside of the capacitive element region 170 by the action of the lower electrode 173 of the capacitive element region isolator 171 (Fig. 10F).

[0073] Next, the insulating film 163 is disposed on both sides of the lower electrode 162 (Fig. 10G).

[0074] Then, the upper electrode 164 is formed in the capacitive element 160 and the capacitive element region isolator 171 (Fig. 10H). With the above steps, the capacitive element 160 can be manufactured.

[0075] <Another Configuration of Second Charge Retaining Unit> Fig. 11 is a diagram illustrating another structure example of the second charge retaining unit according to the second embodiment of the disclosure. The drawing is a schematic cross-sectional view illustrating a structure example of the second charge retaining unit 106 similarly to Fig. 9. The second charge retaining unit 106 in the drawing is different from the second charge retaining unit 106 in Fig. 9 in that a capacitive element region isolator 179 is disposed instead of the capacitive element region isolator 171.

[0076] The capacitive element region isolator 179 is made of an insulating member or metal embedded in the insulating layer 142. Specifically, the capacitive element region isolator 179 can be made of an insulating member or metal disposed in the opening 172 of the insulating layer 142.

[0077] The structure of the imaging element 1 other than that described above is similar to that of the imaging element 1 in the first embodiment of the present disclosure, and thus description thereof is omitted.

[0078] As described above, the imaging element 1 according to the second embodiment of the disclosure includes the capacitive element 160 having the upper electrode 164 having a shape sandwiching the lower electrode 173. As a result, the electrostatic capacitance of the capacitive element 160 can be improved.

[0079] (3. Third Embodiment) Next, a variation of the imaging element 1 of the first embodiment described above will be described.

[0080] Fig. 12 is a diagram illustrating a structure example of a capacitive element according to a third embodiment of the disclosure. The drawing is a schematic cross-sectional view illustrating the structure example of a capacitive element 160. The capacitive element 160 in the drawing illustrates an example in which the capacitive element 160 is formed across a plurality of stacked insulating layers. Specifically, the capacitive element 160 in the drawing is formed in an insulating layer 142, an insulating film 147, and an insulating layer 146 stacked in order. The insulating film 147 can be made of the same member as that of the insulating film 148. Furthermore, the insulating layer 146 can be made of the same member as that of the insulating layer 142. By forming the capacitive element 160 in a shape penetrating the plurality of insulating layers, the electrostatic capacitance of the capacitive element 160 can be improved.

[0081] Fig. 13 is a diagram illustrating another structure example of a capacitive element according to the third embodiment of the disclosure. The drawing is a schematic cross-sectional view illustrating the structure example of a capacitive element 160. Note that only an upper portion of the capacitive element 160 is illustrated in the drawing. An insulating film 148 adjacent to the capacitive element 160 in the drawing has an arc-shaped cross section at the corner. As a result, an insulating film 163 and an upper electrode 164 can be easily embedded in an opening 161.

[0082] Fig. 14 is a diagram illustrating another structure example of a capacitive element according to the third embodiment of the disclosure. The drawing is a schematic cross-sectional view illustrating the structure example of a capacitive element 160. Note that only an upper portion of the capacitive element 160 is illustrated in the drawing. A lower electrode 162 of the capacitive element 160 in the drawing is formed to have a side surface with irregularities. Therefore, irregularities are also formed in an upper electrode 164 facing the lower electrode 162. As a result, the electrostatic capacitance of the capacitive element 160 can be improved.

[0083] Fig. 15 is a diagram illustrating another structure example of a capacitive element according to the third embodiment of the disclosure. This drawing illustrates an example in which a capacitive element 160 and a capacitive element region isolator 171 similar to those in Fig. 9 are included. The capacitive element region isolator 171 in the drawing is different from the capacitive element region isolator 171 in Fig. 9 in that a lower electrode 173 is connected to lower layer wiring 155. By using the capacitive element region isolator 171 as a capacitive element, the capacitance of a second charge retaining unit 106 including the capacitive element can be improved.

[0084] Fig. 16 is a diagram illustrating another structure example of a capacitive element according to the third embodiment of the disclosure. The drawing illustrates an example in which a capacitive element 160 similar to that in Fig. 4 is included. A via plug 158 in the drawing Illustrates an example in which the via plug 158 has substantially the same height as the upper electrode 164. The via plug 158 in the drawing is further connected with upper layer wiring 156 via a via plug 159.

[0085] Fig. 17 is a diagram illustrating a structure example of an imaging element according to the third embodiment of the present disclosure. The drawing is a cross-sectional view illustrating another configuration example of the imaging element 1. An imaging element 1 in the drawing is different from the imaging element 1 in Fig. 2 in that a pixel array unit 10 is disposed on two stacked semiconductor substrates 120 and 220 in a divided manner.

[0086] The imaging element 1 in the drawing is configured by joining a wiring region 140 of the semiconductor substrate 120 and a wiring region 240 of the semiconductor substrate 220. A so-called Cu-Cu connection is applied to join the wiring region 140 and the wiring region 240. A second charge retaining unit 106 is disposed in the wiring region 240. Note that a semiconductor region 222 and a gate 231 of the MOS transistor constituting the element of the pixel 100 are described on the semiconductor substrate 220 in the drawing. Note that a light shielding film 195 is disposed instead of the color filter 192 in a region outside the pixel array unit 10 of the semiconductor substrate 120. An opening 196 for wire bonding is disposed at an end of the semiconductor substrate 120. The opening 196 is formed in a shape extending from the back side of the semiconductor substrate 120 to the wiring region 140. A pad 197 for wire bonding is disposed at the bottom of the opening 196.

[0087] The structure of the imaging element 1 other than that described above is similar to that of the imaging element 1 in the first embodiment of the present disclosure, and thus description thereof is omitted.

[0088] Note that the effects described herein are merely examples and are not limited, and other effects may also be achieved.

[0089] Note that the present technology can also have the following configurations. (1) 　An imaging element comprising: 　a plurality of pixels formed on a semiconductor substrate, the plurality of pixels comprising: a photoelectric conversion unit that performs photoelectric conversion of incident light to generate charge; and a signal generating unit that generates a pixel signal that is a signal based on the generated charge; and 　a capacitive element comprising: a lower electrode disposed for each of the pixels, the lower electrode disposed adjacent to an inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film formed in a shape to cover the lower electrode; an upper electrode formed in a shape to face the lower electrode via the insulating film in the opening; and a lower electrode protection portion disposed adjacent to an upper end of the lower electrode to protect the lower electrode. (2) 　The imaging element according to the above (1), wherein a plurality of the capacitive elements is arranged for each of the pixels. (3) 　The imaging element according to the above (1), wherein the lower electrode protection portion includes a region in which a second insulating film stacked on the insulating layer protrudes toward the opening. (4) 　The imaging element according to the above (3), wherein the second insulating film is made of a member different from a member of the insulating layer. (5) 　The imaging element according to the above (4), 　wherein the insulating layer is made of silicon oxide, and 　the second insulating film is made of silicon nitride. (6) 　The imaging element according to any one of the above (1) to (5), wherein the capacitive element includes: the lower electrode; the insulating film disposed on both sides of the lower electrode; the upper electrode formed in a shape to sandwich the lower electrode via the insulating film; and the lower electrode protection portion. (7) 　The imaging element according to the above (6), further comprising a capacitive element region isolator disposed at a boundary of a capacitive element region, the capacitive element region being a region where the capacitive element is disposed in the insulating layer. (8) 　The imaging element according to the above (7), wherein the capacitive element region isolator includes the capacitive element having an annular shape, the capacitive element formed at the boundary of the capacitive element region. (9) 　The imaging element according to the above (7), wherein the capacitive element region isolator includes an insulating member embedded in the insulating layer. (10) 　The imaging element according to the above (7), wherein the capacitive element region isolator is made of metal embedded in the insulating layer. (11) 　The imaging element according to the above (7), wherein a plurality of the capacitive elements is arranged in the capacitive element region. (12) 　The imaging element according to any one of the above (1) to (11), 　wherein the capacitive element is formed by: 　a step of forming the insulating layer in the wiring region of the semiconductor substrate; 　a step of stacking a second insulating film on the insulating layer; 　a step of forming an opening in the second insulating film and the insulating layer; 　a step of forming the lower electrode protection portion in the second insulating film in the opening; 　a step of forming a material film of the lower electrode on surfaces of the insulating layer and the second insulating film including the opening; 　a step of grinding the material film of the lower electrode in a vicinity of the surface of the second insulating film to form the lower electrode; 　a step of forming the insulating film; and 　a step of forming the upper electrode. (13) 　The imaging element according to the above (12), wherein the step of forming the lower electrode protection portion is a step of grinding a side surface of the insulating layer in the opening to form a region in which the second insulating film protrudes toward the opening. (14) 　An imaging device comprising: 　a plurality of pixels formed on a semiconductor substrate, the plurality of pixels comprising: a photoelectric conversion unit that performs photoelectric conversion of incident light to generate charge; and a signal generating unit that generates a pixel signal that is a signal based on the generated charge; 　a capacitive element comprising: a lower electrode disposed for each of the pixels, the lower electrode disposed adjacent to an inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film formed in a shape to cover the lower electrode; an upper electrode formed in a shape to face the lower electrode via the insulating film in the opening; and a lower electrode protection portion disposed adjacent to an upper end of the lower electrode to protect the lower electrode; and 　a processing circuit that processes the pixel signal.

[0090] 1 Imaging element 10 Pixel array unit 30 Column signal processing unit 100 Pixel 101 Photoelectric conversion unit 105 First charge retaining unit 106 Second charge retaining unit 110 Signal generating unit 120, 220 Semiconductor substrate 140, 240 Wiring region 141 to 143, 146 Insulating layer 147 to 149, 163 Insulating film 160 Capacitive element 161, 172 Opening 162 Lower electrode 164 Upper electrode 165 Lower electrode protection portion 170 Capacitive element region 171, 179 Capacitive element region isolator

Claims

1. An imaging element comprising: 　a plurality of pixels formed on a semiconductor substrate, the plurality of pixels comprising: a photoelectric conversion unit that performs photoelectric conversion of incident light to generate charge; and a signal generating unit that generates a pixel signal that is a signal based on the generated charge; and 　a capacitive element comprising: a lower electrode disposed for each of the pixels, the lower electrode disposed adjacent to an inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film formed in a shape to cover the lower electrode; an upper electrode formed in a shape to face the lower electrode via the insulating film in the opening; and a lower electrode protection portion disposed adjacent to an upper end of the lower electrode to protect the lower electrode.

2. The imaging element according to claim 1, wherein a plurality of the capacitive elements is arranged for each of the pixels.

3. The imaging element according to claim 1, wherein the lower electrode protection portion includes a region in which a second insulating film stacked on the insulating layer protrudes toward the opening.

4. The imaging element according to claim 3, wherein the second insulating film is made of a member different from a member of the insulating layer.

5. The imaging element according to claim 4, 　wherein the insulating layer is made of silicon oxide, and 　the second insulating film is made of silicon nitride.

6. The imaging element according to claim 1, wherein the capacitive element includes: the lower electrode; the insulating film disposed on both sides of the lower electrode; the upper electrode formed in a shape to sandwich the lower electrode via the insulating film; and the lower electrode protection portion.

7. The imaging element according to claim 6, further comprising a capacitive element region isolator disposed at a boundary of a capacitive element region, the capacitive element region being a region where the capacitive element is disposed in the insulating layer.

8. The imaging element according to claim 7, wherein the capacitive element region isolator includes the capacitive element having an annular shape, the capacitive element formed at the boundary of the capacitive element region.

9. The imaging element according to claim 7, wherein the capacitive element region isolator includes an insulating member embedded in the insulating layer.

10. The imaging element according to claim 7, wherein the capacitive element region isolator is made of metal embedded in the insulating layer.

11. The imaging element according to claim 7, wherein a plurality of the capacitive elements is arranged in the capacitive element region.

12. The imaging element according to claim 1, 　wherein the capacitive element is formed by: 　a step of forming the insulating layer in the wiring region of the semiconductor substrate; 　a step of stacking a second insulating film on the insulating layer; 　a step of forming an opening in the second insulating film and the insulating layer; 　a step of forming the lower electrode protection portion in the second insulating film in the opening; 　a step of forming a material film of the lower electrode on surfaces of the insulating layer and the second insulating film including the opening; 　a step of grinding the material film of the lower electrode in a vicinity of the surface of the second insulating film to form the lower electrode; 　a step of forming the insulating film; and 　a step of forming the upper electrode.

13. The imaging element according to claim 12, wherein the step of forming the lower electrode protection portion is a step of grinding a side surface of the insulating layer in the opening to form a region in which the second insulating film protrudes toward the opening.

14. An imaging device comprising: 　a plurality of pixels formed on a semiconductor substrate, the plurality of pixels comprising: a photoelectric conversion unit that performs photoelectric conversion of incident light to generate charge; and a signal generating unit that generates a pixel signal that is a signal based on the generated charge; 　a capacitive element comprising: a lower electrode disposed for each of the pixels, the lower electrode disposed adjacent to an inner wall of an opening formed in an insulating layer included in a wiring region adjacent to the semiconductor substrate; an insulating film formed in a shape to cover the lower electrode; an upper electrode formed in a shape to face the lower electrode via the insulating film in the opening; and a lower electrode protection portion disposed adjacent to an upper end of the lower electrode to protect the lower electrode; and 　a processing circuit that processes the pixel signal.

Images