Communication device and method for compensating for nonlinearity of power amplifier in wireless communication system

Abstract

A communication device comprises: a digital predistortion (DPD) circuit; a digital-to-analog converter (DAC) configured to convert output signals of the DPD circuit into analog signals; a power amplifier configured to amplify the analog signals; and an antenna configured to transmit the amplified analog signals, wherein the DPD circuit may be configured to: generate first predistortion signals by performing a convolution operation on digital signals of a reference time unit over a time interval including a first set of time units before the reference time unit and a second set of time units after the reference time unit; generate second predistortion signals by performing predistortion on the digital signals; and generate the output signals of the DPD circuit on the basis of the first predistortion signals and the second predistortion signals.

Description

Communication device and method for compensating for nonlinearity of a power amplifier in a wireless communication system

[0001] The following descriptions relate to a communication device and method for compensating for the nonlinearity of a power amplifier (PA) in a wireless communication system.

[0002] In wireless communication systems, signals can be amplified through a power amplifier (PA). High linearity characteristics of the power amplifier are required for the distortion-free transmission of the signal. Digital predistortion (DPD) is utilized to provide high linearity to the power amplifier.

[0003] The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure.

[0004] A communication device is provided. The communication device may include a digital predistortion (DPD) circuit. The communication device may include a digital-to-analog converter (DAC) configured to convert output signals of the DPD circuit into analog signals. The communication device may include a power amplifier configured to amplify the analog signals. The communication device may include an antenna configured to transmit the amplified analog signals. The DPD circuit may be configured to generate first predistortion signals by performing a convolution operation on the digital signals of the reference time unit over a time interval including a first set of time units prior to the reference time unit and a second set of time units prior to the reference time unit. The DPD circuit may be configured to generate second predistortion signals by performing predistortion on the digital signals. The above DPD circuit may be configured to generate the output signals of the DPD circuit based on the first pre-distortion signals and the second pre-distortion signals.

[0005] A method is provided to be performed by a communication device. The method may include an operation of generating first pre-distortion signals by performing a convolution operation on digital signals of a reference time unit over a time interval including a first set of time units prior to a reference time unit and a second set of time units prior to the reference time unit. The method may include an operation of generating second pre-distortion signals by performing pre-distortion on the digital signals. The method may include an operation of generating output signals of a digital predistortion (DPD) circuit based on the first pre-distortion signals and the second pre-distortion signals.

[0006] In relation to the description of the drawings, the same or similar reference numerals may be used for identical or similar components.

[0007] Figure 1 illustrates an example of a wireless communication system.

[0008] Figure 2 illustrates the interface between an upper network node and a lower network node.

[0009] Figure 3a is a simplified block diagram of an upper network node.

[0010] Figure 3b is a simplified block diagram of a sub-network node.

[0011] FIG. 4a illustrates the components of a communication device for compensating for the nonlinearity of a power amplifier.

[0012] FIG. 4b illustrates the components of a communication device for compensating for the nonlinearity of a power amplifier.

[0013] Figure 4c illustrates the components of the actuator of the DPD circuit.

[0014] Figure 5 illustrates the components of a communication device for compensating for the nonlinearity of a power amplifier.

[0015] Figure 6 illustrates the components of the actuator of the DPD circuit.

[0016] Figure 7 illustrates the time units in which convolution operations are performed.

[0017] FIG. 8 illustrates the operations of a communication device to compensate for the nonlinearity of a power amplifier.

[0018] The terms used in this disclosure are used merely to describe specific embodiments and are not intended to limit the scope of other embodiments. A singular expression may include a plural expression unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as generally understood by those skilled in the art described in this disclosure. Terms used in this disclosure that are defined in a general dictionary may be interpreted as having the same or similar meaning as they have in the context of the relevant technology, and are not to be interpreted in an ideal or overly formal sense unless explicitly defined in this disclosure. In some cases, even terms defined in this disclosure are not to be interpreted to exclude the embodiments of this disclosure.

[0019] In the various embodiments of the present disclosure described below, a hardware-based approach is described as an example. However, since the various embodiments of the present disclosure include techniques using both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0020] Terms used in the following description to refer to signals (e.g., signal, signal flow, composite signal, digital signal, analog signal, modulated signal, distorted signal), terms referring to resources (e.g., time, time unit, symbol, slot, subframe, radio frame, subcarrier, RE (resource element), RB (resource block), BWP (bandwidth part), occasion)), terms for operation states (e.g., step, operation, procedure)), terms referring to channels, terms referring to network entities, terms referring to device components, etc., are examples provided for the convenience of explanation. Accordingly, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used.

[0021] Terms used in the following description to refer to parts of an electronic device (e.g., module, antenna, antenna element, circuit, processor, chip, component, device), terms referring to circuits (e.g., composite circuit, combined circuit, separation circuit, distribution circuit, PIMC circuit, harmonic elimination circuit), terms referring to the shape of a part (e.g., structure, structure, support, contact, protrusion), and terms referring to circuits (e.g., PCB, FPCB, signal line, feeding line, data line, RF signal line, antenna line, RF path, RF module, RF circuit, splitter, divider, coupler, combiner), etc., are provided as examples for convenience of explanation. Accordingly, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used. Furthermore, terms such as '...part', '...device', '...object', '...body', etc. used below may refer to at least one shape structure or a unit that processes a function.

[0022] Additionally, in this disclosure, expressions of "greater than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled; however, this is merely for the purpose of expressing an example and does not exclude descriptions of "greater than" or "less than." Conditions described as "greater than" may be replaced with "greater than," conditions described as "less than" may be replaced with "less than," and conditions described as "greater than and less than" may be replaced with "greater than and less than." Furthermore, "A" to "B" below refer to at least one of the elements from A (including A) to B (including B).

[0023] Figure 1 illustrates an example of a wireless communication system.

[0024] Referring to FIG. 1, FIG. 1 illustrates a base station (110) and a terminal (120) as part of nodes using a wireless channel in a wireless communication system. FIG. 1 illustrates only one base station, but the wireless communication system may include other base stations identical or similar to the base station (110).

[0025] A base station (110) is a network infrastructure that provides wireless access to a terminal (120). The base station (110) has coverage defined based on the distance over which it can transmit signals. In addition to being a base station, the base station (110) may be referred to as an 'access point (AP)', 'eNodeB (eNB)', '5G node (5th generation node)', 'next generation nodeB (gNB)', 'wireless point', 'transmission / reception point (TRP)', or other terms having an equivalent technical meaning.

[0026] A terminal (120) is a device used by a user and communicates with a base station (110) via a wireless channel. The link from the base station (110) to the terminal (120) is referred to as a downlink (DL), and the link from the terminal (120) to the base station (110) is referred to as an uplink (UL). Additionally, although not shown in FIG. 1, the terminal (120) and another terminal can communicate with each other via a wireless channel. In this case, the link between the terminal (120) and another terminal (device-to-device link, D2D) is referred to as a sidelink, and the sidelink may be used interchangeably with the PC5 interface. In some other embodiments, the terminal (120) may be operated without user involvement. For example, the terminal (120) may be a device that performs machine type communication (MTC) and may not be carried by the user. In addition, for example, the terminal (120) may be a narrowband (NB) IoT (internet of things) device.

[0027] The terminal (120) may be referred to as 'user equipment (UE)', 'customer premises equipment (CPE)', 'mobile station', 'subscriber station', 'remote terminal', 'wireless terminal', 'electronic device', or 'user device' or other terms having an equivalent technical meaning.

[0028] The base station (110) can perform beamforming with the terminal (120). The base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively low frequency band (e.g., FR 1 (frequency range 1) of NR). Additionally, the base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively high frequency band (e.g., FR 2 (or FR 2-1, FR 2-2, FR 2-3), FR 3) of NR) and a millimeter wave (mmWave) band (e.g., 28 GHz, 30 GHz, 38 GHz, 60 GHz)). To improve channel gain, the base station (110) and the terminal (120) can perform beamforming. Here, beamforming may include transmit beamforming and receive beamforming. The base station (110) and the terminal (120) can impart directivity to the transmitted signal or the received signal. To this end, the base station (110) and the terminal (120) can select serving beams through a beam search or beam management procedure. After the serving beams are selected, subsequent communication can be performed through a resource that has a QCL relationship with the resource that transmitted the serving beams.

[0029] If large-scale characteristics of the channel that transmitted the symbol on the first antenna port can be inferred from the channel that transmitted the symbol on the second antenna port, the first antenna port and the second antenna port can be evaluated as being in a QCL relationship. For example, the large-scale characteristics may include at least one of a delay spread, a Doppler spread, a Doppler shift, an average gain, an average delay, and a spatial receiver parameter.

[0030] In FIG. 1, it is described that both the base station (110) and the terminal (120) perform beamforming, but the embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the terminal may or may not perform beamforming. Also, the base station may or may not perform beamforming. That is, either the base station or the terminal may perform beamforming, or neither the base station nor the terminal may perform beamforming.

[0031] In the present disclosure, a beam refers to a spatial flow of a signal in a wireless channel, formed by one or more antennas (or antenna elements), and this formation process may be referred to as beamforming. Beamforming may include at least one of analog beamforming or digital beamforming (e.g., precoding). A reference signal transmitted based on beamforming may include, for example, a demodulation-reference signal (DM-RS), a channel state information-reference signal (CSI-RS), a synchronization signal / physical broadcast channel (SS / PBCH), or a sounding reference signal (SRS). Additionally, an IE such as a CSI-RS resource or an SRS-resource may be used as a configuration for each reference signal, and such a configuration may include information associated with the beam. Information associated with a beam may refer to whether the configuration (e.g., CSI-RS resource) uses the same spatial domain filter as other configurations (e.g., other CSI-RS resources within the same CSI-RS resource set) or a different spatial domain filter, or which reference signal it is quasi-colocated with, and if so, what type (e.g., QCL type A, B, C, D).

[0032] Conventionally, in communication systems with a relatively large cell radius of base stations, each base station was installed to include the functions of a digital processing unit (or DU (distributed unit)) and an RF (radio frequency) processing unit (RF processing unit, or RU (radio unit)). However, as high frequency bands are used in 4G (4th generation) and / or subsequent communication systems (e.g., 5G) and the cell coverage of base stations decreases, the number of base stations required to cover a specific area has increased. Consequently, the burden of installation costs for operators to install base stations has also increased. To minimize base station installation costs, a structure has been proposed in which the DU and RU of a base station are separated, with one or more RUs connected to a single DU via a wired network, and one or more geographically distributed RUs deployed to cover a specific area. Below, with reference to FIG. 2, deployment structures and extension examples of base stations according to various embodiments of the present disclosure are described.

[0033] Figure 2 illustrates the interface between an upper network node and a lower network node.

[0034] The interface between the upper network node (210) and the lower network node (220) may include a fronthaul interface. The term fronthaul (215) refers to the space between entities between a wireless LAN and a base station, unlike the backhaul between a base station and a core network. FIG. 2 illustrates an example of a fronthaul structure between an upper network node (210) and one lower network node (220), but this is merely for convenience of explanation and the present disclosure is not limited thereto. In other words, the embodiment of the present disclosure may also be applied to a fronthaul structure between one upper network node (210) and a plurality of lower network nodes. For example, the embodiment of the present disclosure may be applied to a fronthaul structure between one upper network node (210) and two lower network nodes. Additionally, the embodiment of the present disclosure may also be applied to a fronthaul structure between one upper network node (210) and three lower network nodes.

[0035] For example, the upper network node (210) may include a digital unit / distributed unit (DU). The upper network node (210) may be referred to as a DU. The lower network node (220) may include a radio unit (RU) or a massive MIMO unit (MMU). The lower network node (220) may be referred to as a RU or an MMU.

[0036] Referring to FIG. 2, the base station (110) may include an upper network node (210) and a lower network node (220). The fronthole (215) between the upper network node (210) and the lower network node (220) may be operated via an Fx interface. For the operation of the fronthole (215), an interface such as eCPRI (enhanced common public radio interface) or ROE (radio over ethernet) may be used.

[0037] As communication technology develops, mobile data traffic increases, and consequently, the bandwidth requirements for the fronthaul between the digital unit and the wireless unit have increased significantly. In a deployment such as a C-RAN (centralized / cloud radio access network), the upper network node (210) performs functions for PDCP (packet data convergence protocol), RLC (radio link control), MAC (media access control), and PHY (physical), and the lower network node (220) can be implemented to perform functions for the PHY layer in addition to RF (radio frequency) functions.

[0038] The upper network node (210) may be responsible for upper layer functions of the wireless network. For example, the upper network node (210) may perform functions of the MAC layer and parts of the PHY layer. Here, parts of the PHY layer are functions of the PHY layer that are performed at a higher level, and may include, for example, channel encoding (or channel decoding), scrambling (or descrambling), modulation (or demodulation), and layer mapping (or layer demapping). According to one embodiment, if the upper network node (210) conforms to the O-RAN standard, it may be referred to as an O-DU (O-RAN DU) (or DU). The upper network node (210) may be replaced and represented as a first network entity or DU for a base station (e.g., gNB) in the embodiments of the present disclosure as necessary.

[0039] The lower network node (220) can perform lower layer functions of the wireless network. For example, the lower network node (220) can perform RF functions, which are part of the PHY layer. Here, part of the PHY layer refers to functions of the PHY layer that are performed at a relatively lower level than the upper network node (210), and may include, for example, iFFT transformation (or FFT transformation), CP (cyclic prefix) insertion (CP removal), and digital beamforming. The lower network node (220) may be referred to as an 'access unit (AU)', 'access point (AP)', 'transmission / reception point (TRP)', 'remote radio head (RRH)', 'radio unit (RU)', or other terms having an equivalent technical meaning. According to one embodiment, if the sub-network node (220) conforms to the O-RAN standard, it may be referred to as an O-RU (O-RAN RU) (or RU). The sub-network node (220) may be replaced with a second network entity or RU for a base station (e.g., gNB) in the embodiments of the present disclosure as needed.

[0040] In the above example, it is described that the upper network node (210) includes a DU and the lower network node (220) includes an RU, but the embodiments of the present disclosure are not limited thereto. A base station according to the embodiments may be implemented in a distributed deployment according to a centralized unit (CU) configured to perform the functions of the upper layers of the access network (e.g., packet data convergence protocol (PDCP), radio resource control (RRC)) and a distributed unit (DU) configured to perform the functions of the lower layers. In this case, the distributed unit (DU) may include a digital unit (DU) and a radio unit (RU). Between a core network (e.g., 5G core or next generation core (NGC)) and a radio network (RAN), the base station may be implemented in a structure in which the CU, DU, and RU are arranged in that order. The interface between the CU and the distributed unit (DU) may be referred to as the F1 interface.

[0041] For example, a centralized unit (CU) can be connected to one or more DUs and perform functions at a higher layer than the DUs. For instance, the CU can perform functions at the radio resource control (RRC) and packet data convergence protocol (PDCP) layers, while the DU and RU can perform functions at lower layers. The DU can perform radio link control (RLC), media access control (MAC), and some functions of the physical (PHY) layer (high PHY), while the RU can perform the remaining functions of the PHY layer (low PHY). Additionally, as an example, a digital unit (DU) can be included in a distributed unit (DU) depending on the distributed deployment implementation of the base station. The following description describes the operations of DU and RU unless otherwise defined, but various embodiments of the present disclosure may be applied to both base station deployments including CU and deployments where DU is directly connected to the core network (i.e., implemented by integrating CU and DU into a single entity base station (e.g., NG-RAN node)).

[0042] Figure 3a is a simplified block diagram of an upper network node.

[0043] The configuration exemplified in FIG. 3a can be understood as part of a base station and as the configuration of an upper network node (e.g., a distributed unit (DU)) of FIG. 2a. Terms such as '...part', '...unit' used below refer to a unit that processes at least one function or operation, and this can be implemented in hardware or software, or a combination of hardware and software.

[0044] Referring to FIG. 3a, the upper network node (210) may include a transceiver (310), memory (320), and a processor (330).

[0045] The transceiver (310) can perform functions for transmitting and receiving signals in a wired communication environment. The transceiver (310) may include a wired interface for controlling a direct connection between a device and another device through a transmission medium (e.g., copper wire, optical fiber, etc.). For example, the transceiver (310) can transmit an electrical signal to another device through a copper wire or perform conversion between an electrical signal and an optical signal. An upper network node (210) can communicate with a lower network node (220) through the transceiver (310). The upper network node (210) can be connected to a core network or a centralized unit (CU) of a distributed arrangement through the transceiver (310).

[0046] The transceiver (310) can perform functions for transmitting and receiving signals in a wireless communication environment. For example, the transceiver (310) can perform conversion functions between baseband signals and bit sequences according to the physical layer specifications of the system. For example, when transmitting data, the transceiver (310) can generate complex symbols by encoding and modulating the transmitted bit sequence. For example, when receiving data, the transceiver (310) can restore the received bit sequence through decoding the baseband signal. For example, the transceiver (310) may include a plurality of transmission and reception paths. For example, the transceiver (310) may be connected to a core network or to other nodes (e.g., an integrated access backhaul (IAB)).

[0047] The transceiver (310) can transmit and receive signals. For example, the transceiver (310) can transmit a management plane (M-plane) message. For example, the transceiver (310) can receive a synchronization plane (S-plane) message. For example, the transceiver (310) can transmit a control plane (C-plane) message. For example, the transceiver (310) can transmit a user plane (U-plane) message. For example, the transceiver (310) can receive a user plane message. FIG. 3a shows only the transceiver (310), but according to other implementation examples, the upper network node (210) may include two or more transceivers.

[0048] The transceiver (310) can transmit and receive signals as described above. Accordingly, all or part of the transceiver (310) may be referred to as a 'communication unit', 'transmitter unit', 'receiver unit', or 'transmitter / receiver unit'. Furthermore, in the following description, transmission and reception performed via a wireless channel may be used to mean that processing as described above is performed by the transceiver (310).

[0049] Although not illustrated in FIG. 3a, the transceiver (310) may further include a backhaul transceiver for connecting to a core network or another base station. For example, the backhaul transceiver may provide an interface for communicating with other nodes within the network. For example, the backhaul transceiver may convert a bit sequence transmitted from a base station to another node, e.g., another access node, another base station, an upper node, a core network, etc., into a physical signal, and convert a physical signal received from another node into a bit sequence.

[0050] The memory (320) can store data such as basic programs, applications, and configuration information for the operation of the upper network node (210). For example, the memory (320) may be referred to as a storage unit. For example, the memory (320) may be composed of volatile memory, non-volatile memory, or a combination of volatile memory and non-volatile memory. For example, the memory (320) may provide stored data upon the request of the processor (330).

[0051] The processor (330) can control the overall operations of the upper network node (210). For example, the processor (330) may be referred to as a control unit. For example, the processor (330) can transmit and receive signals through the transceiver (310) (or through the backhaul communication unit). For example, the processor (330) can write and read data to and from memory (320). For example, the processor (330) can perform the functions of a protocol stack required by the communication standard. FIG. 3a shows only the processor (330), but according to other implementation examples, the upper network node (210) may include two or more processors.

[0052] The configuration of the upper network node (210) shown in FIG. 3a is merely an example, and the examples of upper network nodes performing embodiments of the present disclosure are not limited to the configuration shown in FIG. 3a. In some embodiments, some configurations may be added, deleted, or changed.

[0053] Figure 3b is a simplified block diagram of a sub-network node.

[0054] The configuration exemplified in FIG. 3b can be understood as a configuration of a sub-network node (e.g., RU (radio unit)) of FIG. 2b as part of a base station. Terms such as '...part', '...unit' used below refer to a unit that processes at least one function or operation, which may be implemented in hardware or software, or a combination of hardware and software.

[0055] Referring to FIG. 3b, the sub-network node (220) may include an RF (radio frequency) transceiver (360), a fronthole transceiver (365), a memory (370), and a processor (380).

[0056] The RF transceiver (360) can perform functions for transmitting and receiving signals through a wireless channel. For example, the RF transceiver (360) can up-convert a baseband signal into an RF band signal and transmit it through an antenna, and down-convert an RF band signal received through an antenna into a baseband signal. For example, the RF transceiver (360) may include a transmit filter, a receive filter, an amplifier, a mixer, an oscillator, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), etc.

[0057] The RF transceiver (360) may include a plurality of transmission and reception paths. For example, the RF transceiver (360) may include an antenna section. For example, the RF transceiver (360) may include at least one antenna array composed of a plurality of antenna elements. For example, in terms of hardware, the RF transceiver (360) may be composed of a digital circuit and an analog circuit (e.g., a radio frequency integrated circuit (RFIC)). For example, the digital circuit and the analog circuit may be implemented in a single package. For example, the RF transceiver (360) may include a plurality of RF chains. For example, the RF transceiver (360) may perform beamforming. For example, the RF transceiver (360) may apply a beamforming weight to a signal to give directionality according to the settings of the processor (380) to the signal to be transmitted and received. For example, the RF transceiver (360) may include an RF block (or RF section).

[0058] For example, the RF transceiver (360) can transmit and receive signals over a radio access network. For example, the RF transceiver (360) can transmit downlink signals. For example, the downlink signal may include a synchronization signal (SS), a reference signal (RS) (e.g., CRS (cell-specific reference signal), DM (demodulation)-RS), system information (e.g., MIB, SIB, RMSI (remaining system information), OSI (other system information)), a configuration message, control information, or downlink data. For example, the RF transceiver (360) can receive uplink signals. For example, the uplink signal may include random access-related signals (e.g., random access preamble (RAP) (or Msg1 (message 1)), Msg3 (message 3)), reference signals (e.g., SRS (sounding reference signal), DM-RS), or power headroom reports (PHR), etc. FIG. 3b shows only an RF transceiver (360), but according to other embodiments, the sub-network node (220) may include two or more RF transceivers.

[0059] The fronthall transceiver (365) can transmit and receive signals. For example, the fronthall transceiver (365) can transmit and receive signals on the fronthall interface. For example, the fronthall transceiver (365) can receive management plane (M-plane) messages. For example, the fronthall transceiver (365) can receive synchronization plane (S-plane) messages. For example, the fronthall transceiver (365) can receive control plane (C-plane) messages. For example, the fronthall transceiver (365) can transmit user plane (U-plane) messages. For example, the fronthall transceiver (365) can receive user plane messages. FIG. 3b shows only a fronthole transceiver (365), but according to other implementation examples, the lower network node (220) may include two or more fronthole transceivers.

[0060] The RF transceiver (360) and the fronthall transceiver (365) can transmit and receive signals as described above. Accordingly, all or part of the RF transceiver (360) and the fronthall transceiver (365) may be referred to as a 'communication unit', 'transmitter unit', 'receiver unit', or 'transmitter unit'. In the following description, transmission and reception performed via a wireless channel may be used to mean that processing as described above is performed by the RF transceiver (360).

[0061] The memory (370) can store data such as basic programs, applications, and configuration information for the operation of the sub-network node (220). For example, the memory (370) may be referred to as a storage unit. For example, the memory (370) may be composed of volatile memory, non-volatile memory, or a combination of volatile and non-volatile memory. For example, the memory (370) provides stored data upon the request of the processor (380). For example, the memory (370) may include memory for conditions, commands, or configuration values ​​related to the SRS transmission method.

[0062] The processor (380) can control the overall operations of the sub-network node (220). For example, the processor (380) may be referred to as a control unit. For example, the processor (380) can transmit and receive signals through the RF transceiver (360) or the fronthall transceiver (365). For example, the processor (380) can write and read data to and from memory (370). For example, the processor (380) can perform the functions of the protocol stack required by the communication standard. FIG. 3b shows only the processor (380), but according to other implementation examples, the sub-network node (220) may include two or more processors. For example, the processor (380) may be a set of instructions or code stored in memory (370), at least temporarily resided in the processor (380), or a storage space storing instructions / code, or part of a circuitry constituting the processor (380). For example, the processor (380) may include various modules for performing communication. For example, the processor (380) may control a sub-network node (220) to perform operations according to the embodiments described below.

[0063] The configuration of the sub-network node (220) shown in FIG. 3b is merely an example, and the examples of sub-network nodes performing embodiments of the present disclosure are not limited to the configuration shown in FIG. 3b. In some embodiments, some configurations may be added, deleted, or changed.

[0064] FIG. 4a illustrates components of a communication device for compensating for the nonlinearity of a power amplifier. The communication device (400) of FIG. 4a may correspond to a base station (110) of FIG. 1 or a sub-network node (220) (e.g., a radio unit (RU)) of FIG. 2 and FIG. 3b.

[0065] Referring to FIG. 4a, the communication device (400) may include a digital predistortion (DPD) circuit (410) and a power amplifier (PA) (450).

[0066] Graph (405) of FIG. 4a illustrates a waveform representing the relationship between the magnitude of the input signal (402) of the power amplifier (450) and the magnitude of the output signal (403) of the power amplifier (450). As shown in graph (405), the power amplifier (450) may have non-linear characteristics due to a memory effect. A memory effect may mean that a past signal causes nonlinearity in the current output signal of the power amplifier (450).

[0067] For example, a memory effect may be caused by an impedance mismatch between the power amplifier (450) and the antenna (or load). Due to the impedance mismatch between the power amplifier (450) and the antenna (or load), the output signal of the power amplifier (450) is reflected, thereby distorting the current output signal of the power amplifier (450) according to the current input signal. As the current output signal is distorted, non-linear characteristics of the power amplifier (450) may be caused. The memory effect caused by the impedance mismatch may occur over a relatively short time interval. In the following embodiments, the memory effect occurring over a relatively short time interval may be referred to as a short-term memory effect.

[0068] For example, a memory effect may be caused by a change in the properties or physical properties of the transistors of the power amplifier (450). The properties or physical properties of the transistors of the power amplifier (450) may be changed by heat, charge accumulation, etc., generated while processing past signals. The output signal of the power amplifier (450) according to the current input signal may be distorted by the changed properties or physical properties of the transistors. The memory effect caused by the change in the properties or physical properties of the transistors may occur over a relatively long time interval. In the following embodiments, the memory effect occurring over a relatively long time interval may be referred to as a long-term memory effect or a slow-rate memory effect. To improve the nonlinearity of the power amplifier (450) due to the memory effect described above, a DPD circuit (410) may be used.

[0069] Referring to FIG. 4a, in one embodiment, the DPD circuit (410) can perform pre-distortion of the digital signal through digital signal processing. For example, the DPD circuit (410) can generate an output signal (402) by performing predistortion on the input signal (401). The output signal (402) of the DPD circuit (410) can be associated with the inverse function of the non-linear characteristics of the power amplifier (450). For example, the relationship between the magnitude of the input signal (401) of the DPD circuit (410) and the magnitude of the output signal (402) of the DPD circuit (410) is illustrated in graph (404). The output signal (402) of the DPD circuit (410) can be converted into an analog signal by a digital-to-analog converter (DAC) and then provided as an input to the power amplifier (450). The power amplifier (450) can amplify the analog signal. For example, the relationship between the magnitude of the input signal of the power amplifier (450) and the magnitude of the output signal (403) of the power amplifier (450) is illustrated in graph (405). Since pre-distortion is performed by the DPD circuit (410) to compensate for the non-linear characteristics of the power amplifier (450), the relationship between the magnitude of the input signal (401) of the DPD circuit (410) and the magnitude of the output signal (403) of the power amplifier (450) may be linear. For example, the relationship between the magnitude of the input signal (401) of the DPD circuit (410) and the magnitude of the output signal (403) of the power amplifier (450) is illustrated in graph (406).

[0070] FIG. 4b illustrates components of a communication device for compensating for the nonlinearity of a power amplifier. The communication device (400) of FIG. 4b may correspond to a base station (110) of FIG. 1 or a sub-network node (220) (e.g., a radio unit (RU)) of FIG. 2 and FIG. 3b.

[0071] Referring to FIG. 4b, a communication device (400) according to one embodiment may include a digital predistortion (DPD) circuit (410), a digital-to-analog converter (DAC) (440), an analog-to-digital converter (ADC) (445), a power amplifier (PA) (450), a coupler (455), an isolator (460), a filter (465), and an antenna (470). The hardware components illustrated in FIG. 4b are illustrated based on different blocks, but the present disclosure is not limited thereto. For example, at least some of the hardware components shown in FIG. 4b (e.g., at least some of the DPD circuit (410), DAC (440), ADC (445), power amplifier (450), coupler (455), isolator (460), filter (465), and antenna (470)) may be included in a single integrated circuit such as a system on chip (SoC) or a system in package (SIP). The type and number of hardware components included in the communication device (400) are not limited to those shown in FIG. 4b. For example, the communication device (400) may include only some of the hardware components shown in FIG. 4b.

[0072] In one embodiment, the communication device (400) may include a DPD circuit (410). The DPD circuit (410) may be a circuit for performing distortion of a digital signal through digital signal processing to improve the nonlinearity of the power amplifier (450). For example, the DPD circuit (410) may be referred to as a digital predistorter, a DPD module, or other terms having an equivalent technical meaning in addition to the DPD circuit. For example, the DPD circuit (410) may include an actuator (430) and a coefficient estimator (435).

[0073] In one embodiment, the actuator (430) can perform pre-distortion on the input signal of the DPD circuit (410) based on coefficients provided by the coefficient meter (435). The actuator (430) can provide the output signal of the DPD circuit (410), generated by performing pre-distortion on the input signal of the DPD circuit (410), to the coefficient meter (435) and the DAC (440). The process of performing pre-distortion is described in FIG. 4c. Since pre-distortion is performed by the actuator (430), non-linearity due to the memory effect of the power amplifier (450) can be compensated in advance.

[0074] In one embodiment, the counter meter (435) is the output signal (X) of the actuator (430). OUTInverse function coefficients (or LUT (look-up table) coefficients) for the non-linear characteristics of the power amplifier (450) can be determined by using inverse function modeling based on at least a portion of the output signal (y[n]) of the power amplifier (450) obtained from [n]) and the feedback path. For example, the inverse function coefficients may include coefficients determined for each order term of the input signal. In one example, the inverse function coefficients may include a coefficient determined for the first-order term of the input signal, a coefficient determined for the second-order term of the input signal, a coefficient determined for the third-order term of the input signal, and a coefficient determined for the fourth-order term of the input signal. However, this is merely an example and the present disclosure is not limited thereto. The inverse function coefficients may include only some of the above coefficients. The inverse function coefficients can be stored in the buffer of the actuator (430) in the form of a look-up table (LUT).

[0075] In one embodiment, the communication device (400) may include a DAC (440). The DAC (440) may convert the output signal of the DPD circuit (410) from a digital signal into an analog signal. The DAC (440) may provide the analog signal converted from the digital signal to a power amplifier (450).

[0076] In one embodiment, the communication device (400) may include an ADC (445). The ADC (445) may convert a feedback signal provided from a coupler (455) through a feedback path into a digital signal. The ADC (445) may provide the digital signal converted from the analog signal to a counter meter (435) of the DPD circuit (410).

[0077] In one embodiment, the communication device (400) may include a power amplifier (450). The power amplifier (450) may amplify an analog signal converted from a digital signal by a DAC (440). For example, since the power amplifier (450) has non-linear characteristics, the magnitude of the input signal of the power amplifier (450) and the magnitude of the output signal of the power amplifier (450) may be non-linear. The power amplifier (450) may provide the amplified analog signal to a coupler (455).

[0078] In one embodiment, the communication device (400) may include a coupler (455). The coupler (455) may be a directional coupler. For example, the coupler (455) may provide the output signal of the power amplifier (450) to the ADC (445) through a feedback path. The output signal of the power amplifier (450) provided to the ADC (445) through the feedback path may be referred to as a feedback signal. For example, the coupler (455) may provide the output signal of the power amplifier (450) to the isolator (460).

[0079] In one embodiment, the communication device (400) may include an isolator (460). The isolator (460) may include a passive element for providing an analog signal amplified by a power amplifier (450) to a filter (465) and an antenna (470). The isolator (460) may be used to fix the flow of the analog signal amplified by the power amplifier (450) in one direction. The isolator (460) may control the flow of a signal from the filter (465) and the antenna (470) to the power amplifier (450) (or coupler (455)). In an example that is not limited to this, the isolator (460) may be replaced with a circulator capable of providing a flow of the signal in various directions.

[0080] In one embodiment, the communication device (400) may include a filter (465). The filter (465) may perform filtering on the output signal of the power amplifier (450) provided from the isolator (460). In one example, the filter (465) may include at least one of a band pass filter (BPF), a low pass filter (LPF), a high pass filter (HPF), or a notch filter. However, the present disclosure is not limited thereto.

[0081] In one embodiment, the communication device (400) may include an antenna (470). The antenna (470) may radiate a signal filtered by a filter (465). For example, the antenna (470) may be configured to transmit the filtered signal to another device (e.g., the terminal (120) of FIG. 1).

[0082] FIG. 4c illustrates the components of an actuator of a DPD circuit. The actuator (430) illustrated in FIG. 4c may correspond to the actuator (430) of FIG. 4b.

[0083] Referring to FIG. 4c, the actuator (430) of the DPD circuit (410) may include a level detection circuit (431-1), a look-up table (LUT) circuit (431-2), a delay circuit (432-1), a look-up table (LUT) circuit (432-2), a delay circuit (433-1), a look-up table (LUT) circuit (433-2), a delay circuit (434-1), a look-up table (LUT) circuit (434-2), an adder (436), and a multiplier (437). The hardware components illustrated in FIG. 4c are illustrated based on different blocks, but the present disclosure is not limited thereto. For example, at least some of the hardware components shown in FIG. 4c (e.g., level detection circuit (431-1), LUT circuit (431-2), delay circuit (432-1), LUT circuit (432-2), delay circuit (433-1), LUT circuit (433-2), delay circuit (434-1), LUT circuit (434-2), adder (436), and multiplier (437)) may be included in a single integrated circuit such as a system on chip (SoC) or a system in package (SIP). The number of hardware components included in the actuator (430) is not limited to that shown in FIG. 4c. For example, the actuator (430) may include only some of the hardware components shown in FIG. 4c.

[0084] In one embodiment, the actuator (430) may include a level detection circuit (431-1) and a LUT circuit (431-2). The level detection circuit (431-1) is an input signal (x) of the DPD circuit (410). IN It can be configured to identify the amplitude (or level of the input signal) of [n]). For example, the input signal (x IN[n]) may be a discrete signal. n may be referred to as an index of the discrete signal. For example, the level detection circuit (431-1) may be referred to as a signal strength detection circuit or other terms having an equivalent technical meaning. For example, the level detection circuit (431-1) may provide information about the magnitude of the input signal to the LUT circuit (431-2). The LUT circuit (431-2) may generate an output value (a1[n]) of the LUT circuit (431-2) based on the magnitude of the input signal and first coefficients. The first coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450) determined for the LUT circuit (431-2). In one example, the first coefficients may include a coefficient determined for the first-order term of the input signal, a coefficient determined for the second-order term of the input signal, and a coefficient determined for the third-order term of the input signal. The coefficient determined for the first-order term of the input signal may represent a coefficient applied to the magnitude of the input signal. The coefficient determined for the second-order term of the input signal may represent a coefficient applied to the square of the input signal. The coefficient determined for the third-order term of the input signal may represent a coefficient applied to the cube of the input signal. However, this is merely an example and the present disclosure is not limited thereto. For example, the first coefficients may include only some of the above coefficients.

[0085] In one embodiment, the actuator (430) may include a delay circuit (432-1) and a second LUT circuit (432-2). The delay circuit (432-1) may be configured to delay the input signal of the DPD circuit (410). For example, the input signal may be delayed by one time unit. The delay circuit (432-1) delays the input signal (e.g., x INInformation regarding the magnitude of [n-1]) can be provided to the LUT circuit (432-2). The LUT circuit (432-2) can generate an output value (a2[n]) of the LUT circuit (432-2) based on the magnitude of the delayed input signal and the second coefficients. The second coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450) determined for the LUT circuit (432-2). In one example, the second coefficients may include a coefficient determined for the first term of the delayed input signal, a coefficient determined for the second term of the input signal, and a coefficient determined for the third term of the input signal. However, this is merely an example and the present disclosure is not limited thereto. For example, the second coefficients may include only some of the above coefficients.

[0086] In one embodiment, the actuator (430) may include a delay circuit (433-1) and a LUT circuit (433-2). The delay circuit (433-1) may be configured to delay the input signal of the DPD circuit (410). For example, the input signal may be delayed by two time units. The delay circuit (433-1) delays the input signal (e.g., x IN Information regarding the magnitude of [n-2]) can be provided to the LUT circuit (433-2). The LUT circuit (433-2) can generate an output value (a3[n]) of the LUT circuit (433-2) based on the magnitude of the delayed input signal and third coefficients. The third coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450) determined for the LUT circuit (433-2). In one example, the third coefficients may include a coefficient determined for the first term of the delayed input signal, a coefficient determined for the second term of the input signal, and a coefficient determined for the third term of the input signal. However, this is merely an example and the present disclosure is not limited thereto. For example, the third coefficients may include only some of the above coefficients.

[0087] In one embodiment, the actuator (430) may include a delay circuit (434-1) and a LUT circuit (434-2). The delay circuit (434-1) may be configured to delay the input signal of the DPD circuit (410). For example, the input signal may be delayed by M time units. The delay circuit (434-1) delays the input signal (e.g., x IN Information regarding the magnitude of [nM-1]) can be provided to the LUT circuit (434-2). The LUT circuit (434-2) can provide the output value (a) of the LUT circuit (434-2) based on the magnitude of the delayed input signal and the fourth coefficients. M [n]) can be generated. The fourth coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450) determined for the LUT circuit (434-2). In one example, the fourth coefficients may include a coefficient determined for the first term of the delayed input signal, a coefficient determined for the second term of the input signal, and a coefficient determined for the third term of the input signal. However, this is merely an example and the present disclosure is not limited thereto. For example, the fourth coefficients may include only some of the above coefficients.

[0088] The output value of the LUT circuit described above can be generated according to [Equation 1] below.

[0089]

[0090] a m [n] represents the output value of the m-th LUT circuit for an input signal of time unit n. P represents the highest-order term used in inverse function modeling to compensate for the nonlinearity of the power amplifier (450). c 0,m,p represents the coefficient for the p-th order term in the m-th LUT circuit. x IN[Equation 1] represents an input signal of time unit n. The above [Equation 1] is merely an example to aid understanding, and the present disclosure is not limited thereto. [Equation 1] may be modified, applied, or extended in accordance with the contents described in the present disclosure.

[0091] In one embodiment, the actuator (430) may include an adder (436). The adder (436) may be configured to perform summation of the output values ​​of LUT circuits (431-2) to LUT circuits (434-2). For example, the adder (436) may be configured to perform summation of the output values ​​of one or more LUT circuits included in the actuator (430). The adder (436) may provide the summed value to a multiplier (437).

[0092] In one embodiment, the actuator (430) may include a multiplier (437). The multiplier (437) performs multiplication of the value summed by the adder (436) and the input signal, thereby producing an output signal (y) of the DPD circuit (410). o It can be configured to generate [n]).

[0093] As described above, the output of each LUT circuit may be based on the instantaneous (or discrete) sample level of the input signal. A method based on the instantaneous sample level of the input signal may be effective in compensating for memory effects occurring over relatively short time intervals. For example, a method based on the instantaneous sample level of the input signal may be effective in compensating for memory effects caused by impedance mismatch between the power amplifier (450) and the antenna (or load). However, a method based on the instantaneous sample level of the input signal has limitations in compensating for long-term memory effects and / or slow-rate memory effects occurring over relatively long time intervals.

[0094] In the following, a communication device (400) and a method performed by the communication device (400) for increasing the linearity of a power amplifier (450) by compensating for not only short-term memory effects but also long-term memory effects and low-speed memory effects are described.

[0095] FIG. 5 illustrates components of a communication device for compensating for the nonlinearity of a power amplifier. The communication device (400) of FIG. 5 may correspond to a base station (110) of FIG. 1 or a sub-network node (220) (e.g., RU (radio unit)) of FIG. 2 and FIG. 3b.

[0096] Referring to FIG. 5, a communication device (400) according to one embodiment may include a digital predistortion (DPD) circuit (410), a digital-to-analog converter (DAC) (440), an analog-to-digital converter (ADC) (445), a power amplifier (PA) (450), a coupler (455), an isolator (460), a filter (465), and an antenna (470). The hardware components illustrated in FIG. 5 are illustrated based on different blocks, but the present disclosure is not limited thereto. For example, at least some of the hardware components shown in FIG. 5 (e.g., at least some of the DPD circuit (410), DAC (440), ADC (445), power amplifier (450), coupler (455), isolator (460), filter (465), and antenna (470)) may be included in a single integrated circuit such as a system on chip (SoC) or a system in package (SIP). The type and number of hardware components included in the communication device (400) are not limited to those shown in FIG. 5. For example, the communication device (400) may include only some of the hardware components shown in FIG. 5.

[0097] In one embodiment, the communication device (400) may include a DPD circuit (410). The DPD circuit (410) may be a circuit for performing distortion of a digital signal through digital signal processing to improve the nonlinearity of the power amplifier (450). For example, the DPD circuit (410) may be referred to as a digital predistorter, a DPD module, or other terms having an equivalent technical meaning in addition to the DPD circuit. For example, the DPD circuit (410) may generate an output signal of the DPD circuit (410) to compensate for the memory effect of the power amplifier (450) based on a first predistorter signal (output signal of the first actuator (420)) and a second predistorter signal (output signal of the second actuator (430)).

[0098] In one embodiment, the DPD circuit (410) can generate a first pre-distortion signal. For the process of generating the first pre-distortion signal, the description of FIG. 6 may be referenced.

[0099] For example, the DPD circuit (410) can perform a convolution operation over a time interval. For example, the DPD circuit (410) can perform a convolution operation over a time interval on the input signal of the DPD circuit (410). In another example, the DPD circuit (410) can perform a convolution operation over a time interval on a scaled input signal. In another example, the DPD circuit (410) can perform a convolution operation over a time interval on the higher-order term of the input signal. In another example, the DPD circuit (410) can perform a convolution operation over a time interval on the higher-order term of the scaled input signal. The convolution operation may correspond to discrete convolution. For example, the convolution operation may be referred to as a dilated convolution operation.

[0100] For example, the time interval in which convolution is performed may include a first set of time units preceding a reference time unit (e.g., n) and a second set of time units following the reference time unit. The first set of time units may be identified based on the number of time units included in the first set and the interval between the time units included in the first set. The second set of time units may be identified based on the number of time units included in the second set and the interval between the time units included in the second set. For example, the number of time units in the first set, the interval between the time units in the first set, the number of time units in the second set, and the interval between the time units in the second set may be adjusted. Since the convolution operation is performed in the time interval identified based on the number of time units and the interval between the time units, the overall search interval is increased, and efficient operation is performed.

[0101] For example, sample signals for performing a convolution operation in a first set of time units and a second set of time units may have different weights (or coefficients). In one example, a sample signal of the first time unit among the first set of time units (e.g., x IN The weights applied to [n-2]) are the sample signals of the second time unit among the first set of time units (e.g., x IN The weights applied to [n-4]) may differ. In one example, the sample signal of the second time unit among the second set of time units (e.g., x IN The weight applied to [n+3]) is the fourth time unit among the second set of time units (e.g., x IN The weights applied to [n+6]) may differ. However, this is merely an example, and the present disclosure is not limited thereto.

[0102] For example, the DPD circuit (410) can generate a first pre-distortion signal based on the convolution output from the convolution operation and the coefficients of the LUT (look-up table). For example, the DPD circuit (410) can generate an output value based on the convolution output and the LUT coefficients. The LUT coefficients may refer to coefficients associated with the inverse function of the non-linear characteristics of the power amplifier (450). Meanwhile, FIG. 5 describes an example of generating an output value based on one convolution operation and one LUT, but this is for illustrative purposes only and the present disclosure is not limited thereto. For example, the DPD circuit (410) can generate output values ​​based on multiple convolution operations and multiple LUTs. For generating output values ​​based on multiple convolution operations and multiple LUTs, the description of FIG. 6 may be referenced. For example, the DPD circuit (410) can perform summation of output values. The DPD circuit (410) can generate a first pre-distortion signal by performing multiplication of the summed value and the input signal of the DPD circuit (410). For example, the first pre-distortion signal may be a signal for compensating for a long-term memory effect and / or a slow-rate memory effect occurring over a relatively long time interval.

[0103] In one embodiment, the DPD circuit (410) can generate a second pre-distortion signal. For the process of generating the second pre-distortion signal, the description of FIG. 4c may be referenced.

[0104] For example, the DPD circuit (410) can generate a first output value based on an input signal and first coefficients. The first coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450). The first coefficients may refer to coefficients set in the first LUT (e.g., LUT circuit (431-2)) of the actuator (420). For example, the DPD circuit (410) can generate a second output value based on a delayed input signal and second coefficients. The delayed input signal may be delayed by one time unit. The second coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450). The second coefficients may refer to coefficients set in the second LUT (e.g., LUT circuit (432-2)) of the actuator (420). For example, the DPD circuit (410) can generate a third output value based on a delayed input signal and third coefficients. The delayed input signal may be delayed by two time units. The third coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450). The third coefficients may refer to coefficients set in the third LUT of the actuator (420) (e.g., LUT circuit (433-2)). Generating the output value may be based on [Equation 1]. In FIG. 5, examples of generating the first through third output values ​​are described, but the present disclosure is not limited thereto. For example, the DPD circuit (410) may generate only some of the output values.

[0105] For example, the DPD circuit (410) can perform summation of the generated output values. For example, the DPD circuit (410) can generate a second pre-distortion signal by performing multiplication of the summed value and the input signal. However, this is merely an example and the present disclosure is not limited thereto.

[0106] In one embodiment, the DPD circuit (410) may include a first actuator (420), a second actuator (430), a processing delay compensator (425), and a coefficient estimator (435). For example, the first actuator (420) may be configured to generate a first pre-distortion signal based on interval level tracking (ILT). The description of the first actuator (420) may be substantially the same as the description of the actuator (420) in FIG. 6. For example, the second actuator (430) may be configured to generate a second pre-distortion signal based on the delay of the input signal. The description of the second actuator (430) may be substantially the same as the description of the actuator (430) in FIG. 4c. For example, the processing delay compensator (425) can compensate for a processing delay resulting from the difference between the processing time of the first actuator (420) and the processing time of the second actuator (430). After compensating for the processing delay, the processing delay compensator (425) can generate an output signal of the DPD circuit (410) based on the first pre-distortion signal and the second pre-distortion signal. For example, the processing delay compensator (425) can generate an output signal of the DPD circuit (410) by performing summation of the first pre-distortion signal and the second pre-distortion signal.

[0107] In one embodiment, the communication device (400) may include a DAC (440). The DAC (440) may convert the output signal of the DPD circuit (410) from a digital signal into an analog signal. The DAC (440) may provide the analog signal converted from the digital signal to a power amplifier (450).

[0108] In one embodiment, the communication device (400) may include an ADC (445). The ADC (445) may convert a feedback signal provided from a coupler (455) through a feedback path into a digital signal. The ADC (445) may provide the digital signal converted from the analog signal to a counter meter (435) of the DPD circuit (410).

[0109] In one embodiment, the communication device (400) may include a power amplifier (450). The power amplifier (450) may amplify an analog signal converted from a digital signal by a DAC (440). For example, since the power amplifier (450) has non-linear characteristics, the input and output of the power amplifier (450) may have non-linear characteristics. For example, the magnitude of the input signal of the power amplifier (450) and the magnitude of the output signal of the power amplifier (450) may be non-linear. Since compensation for the non-linear characteristics of the power amplifier (450) is performed by the DPD circuit (410), the relationship between the magnitude of the input signal of the DPD circuit (410) and the magnitude of the output signal of the power amplifier (450) may be linear. The power amplifier (450) may provide the amplified analog signal to a coupler (455).

[0110] In one embodiment, the communication device (400) may include a coupler (455). The coupler (455) may be a directional coupler. For example, the coupler (455) may provide the output signal of the power amplifier (450) to the ADC (445) through a feedback path. The output signal of the power amplifier (450) provided to the ADC (445) through the feedback path may be referred to as a feedback signal. For example, the coupler (455) may provide the output signal of the power amplifier (450) to the isolator (460).

[0111] In one embodiment, the communication device (400) may include an isolator (460). The isolator (460) may include a passive element for providing an analog signal amplified by a power amplifier (450) to a filter (465) and an antenna (470). The isolator (460) may be used to fix the flow of the analog signal amplified by the power amplifier (450) in one direction. The isolator (460) may control the flow of a signal from the filter (465) and the antenna (470) to the power amplifier (450) (or coupler (455)). In an example that is not limited to this, the isolator (460) may be replaced with a circulator capable of providing a flow of the signal in various directions.

[0112] In one embodiment, the communication device (400) may include a filter (465). The filter (465) may perform filtering on the output signal of the power amplifier (450) provided from the isolator (460). In one example, the filter (465) may include at least one of a band pass filter (BPF), a low pass filter (LPF), a high pass filter (HPF), or a notch filter. However, the present disclosure is not limited thereto.

[0113] In one embodiment, the communication device (400) may include an antenna (470). The antenna (470) may radiate a signal filtered by a filter (465). For example, the antenna (470) may be configured to transmit the filtered signal to another device (e.g., the terminal (120) of FIG. 1).

[0114] FIG. 6 illustrates the components of an actuator of a DPD circuit. The actuator (420) shown in FIG. 6 may correspond to the actuator (420) of FIG. 5. For example, the actuator (420) may be referred to as an ILT (interval level tracking) actuator.

[0115] Referring to FIG. 6, the actuator (420) of the digital predistortion (DPD) circuit (410) may include a level detection circuit (601), an operation circuit (602), a multiplier (603), a convolution circuit (604-1), a look-up table (LUT) circuit (604-2), a convolution circuit (605-1), a LUT circuit (605-2), a convolution circuit (606-1), a LUT circuit (606-2), a convolution circuit (607-1), a LUT circuit (607-2), an adder (608), and a multiplier (609). The hardware components illustrated in FIG. 6 are illustrated based on different blocks, but the present disclosure is not limited thereto. For example, at least some of the hardware components shown in FIG. 6 (e.g., level detection circuit (601), operation circuit (602), multiplier (603), convolution circuit (604-1), LUT circuit (604-2), convolution circuit (605-1), LUT circuit (605-2), convolution circuit (606-1), LUT circuit (606-2), convolution circuit (607-1), LUT circuit (607-2), adder (608), and multiplier (609)) may be included in a single integrated circuit such as a system on chip (SoC) or a system in package (SIP). The number of hardware components included in the actuator (420) is not limited to that shown in FIG. 6. For example, the actuator (420) may include one or more convolution circuits and one or more LUT circuits. For example, the actuator (420) may include only some of the hardware components shown in FIG. 6.

[0116] In one embodiment, the actuator (420) may include a level detection circuit (601). The level detection circuit (601) is an input signal (x) of the DPD circuit (410). INIt can be configured to identify the magnitude (or level of the input signal) of [n]). For example, the input signal (x IN [n]) may be a discrete signal. n may be referred to as an index of the discrete signal. For example, the level detection circuit (601) may be referred to as a signal strength detection circuit or other terms having an equivalent technical meaning. For example, the level detection circuit (601) may provide information about the magnitude of the input signal to the calculation circuit (602).

[0117] In one embodiment, the actuator (420) may include an operation circuit (602). The operation circuit (602) may be configured to identify a higher-order term value determined based on the magnitude of the input signal. In one example, the operation circuit (602) may be configured to identify a value corresponding to the square of the magnitude of the input signal. In another example, the operation circuit (602) may be configured to identify a value corresponding to the cube of the magnitude of the input signal. However, this is merely an example and the present disclosure is not limited thereto. For example, the operation circuit (602) may be configured to identify a value corresponding to the nth-order term with respect to the magnitude of the input signal. For example, the operation circuit (602) may provide a higher-order term value with respect to the magnitude of the input signal to the multiplier (603). For example, the operation circuit (602) may include a path to bypass the circuit for identifying the higher-order term value. By bypassing the circuit, a magnitude value corresponding to the first term of the input signal can be provided to the multiplier (603).

[0118] In one embodiment, the actuator (420) may include a multiplier (603). The multiplier (603) may scale the magnitude of an input signal (or a higher-order term value for the magnitude of the input signal) based on a predetermined value (e.g., G). For example, the multiplier (603) may scale the magnitude of the input signal (or a higher-order term value for the magnitude of the input signal) by performing multiplication between the predetermined value and the magnitude of the input signal (or a higher-order term value for the magnitude of the input signal). The first multiplier (603) may provide the scaled value to convolution circuits.

[0119] In one embodiment, the actuator (420) may include a convolution circuit (604-1) and a LUT circuit (604-2). For example, the convolution circuit (604-1) is an input signal (x) of the DPD circuit (410). IN Convolution operations can be performed over a time interval for [n]). In another example, the convolution circuit (604-1) is an input signal (G*x) scaled by the multiplier (603). IN Convolution operations can be performed over a time interval for [n]). In another example, the convolution circuit (604-1) is such that the input signal (x IN Convolution operations can be performed over time intervals for higher-order terms of [n]). In another example, the first convolution circuit (604-1) is scaled input signal (x IN Convolution operations can be performed over time intervals for higher-order terms of [n]). The convolution operation can correspond to a discrete convolution operation. For example, the convolution operation can be referred to as a dilated convolution operation.

[0120] For example, a time interval may include a first set of time units (e.g., time units (702) of FIG. 7) preceding a reference time unit (e.g., reference time unit (701) of FIG. 7) (e.g., n)) and a second set of time units (e.g., time units (703) of FIG. 7) following the reference time unit. The first set of time units may be identified based on the number of time units included in the first set and the interval between the time units included in the first set. The second set of time units may be identified based on the number of time units included in the second set and the interval between the time units included in the second set. For example, the number of time units included in the first set, the interval between the time units included in the first set, the number of time units included in the second set, and the interval between the time units included in the second set may be adjusted (or changed). Number of time units and time Since convolution operations are performed in time intervals identified based on the spacing between units, the total search interval is increased, and efficient computation can be achieved.

[0121] For example, sample signals for performing a convolution operation in a first set of time units and a second set of time units may have different weights (or coefficients). In one example, the sample signal of the first time unit among the first set of time units (e.g., x IN The weights applied to [n-2]) are the sample signals of the second time unit among the first set of time units (e.g., x IN The weights applied to [n-4]) may differ. In one example, the sample signal of the second time unit among the second set of time units (e.g., x IN The weight applied to [n+3]) is the fourth time unit among the second set of time units (e.g., x INThe weights applied to [n+6]) may differ. However, this is merely an example, and the present disclosure is not limited thereto.

[0122] For example, the LUT circuit (604-2) can generate the output value (β1[n]) of the LUT circuit (604-2) based on the output value (L1[n]) of the convolution circuit (604-1) and the first coefficients. The first coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450) determined for the LUT circuit (604-2). In one example, the first coefficients may include a coefficient determined for the first term of the output value of the convolution circuit (604-1), a coefficient determined for the second term of the output value of the convolution circuit (604-1), and a coefficient determined for the third term of the output value of the convolution circuit (604-1). The coefficient determined for the first term may represent a coefficient applied to the output value of the convolution circuit (604-1). The coefficient determined for the second term may represent a coefficient applied to the square of the output value of the convolution circuit (604-1). The coefficient determined for the third term may represent a coefficient applied to the cube of the output value of the convolution circuit (604-1). However, this is merely an example and the present disclosure is not limited thereto. For example, the first coefficients may include only some of the above coefficients.

[0123] In one embodiment, the actuator (420) may include a convolution circuit (605-1) and a LUT circuit (605-2). For example, the convolution circuit (605-1) is an input signal (x) of the DPD circuit (410). IN Convolution operations can be performed over a time interval for [n]). In another example, the convolution circuit (605-1) is an input signal (G*x) scaled by the multiplier (603). IN Convolution operations can be performed over a time interval for [n]). In another example, the convolution circuit (605-1) is such that the input signal (xIN Convolution operations can be performed over time intervals for higher-order terms of [n]). In another example, the convolution circuit (605-1) can perform convolution operations over time intervals for higher-order terms of the scaled input signal. The convolution operation can correspond to a discrete convolution operation.

[0124] For example, the time interval may include a third set of time units prior to the reference time unit and a fourth set of time units prior to the reference time unit. The third set of time units is the number of time units (N) included in the third set. d ) and can be identified based on the interval between the time units included in the third set. The time units of the fourth set can be identified based on the number of time units included in the fourth set and the interval between the time units included in the fourth set. For example, the number of time units included in the third set, the interval between the time units included in the third set, the number of time units included in the fourth set, and the interval between the time units included in the fourth set can be adjusted (or changed).

[0125] For example, sample signals for performing convolution operations in the third set of time units and the fourth set of time units may have different weights (or coefficients).

[0126] For example, the LUT circuit (605-2) can generate an output value (β2[n]) of the LUT circuit (605-2) based on the output value (L1[n]) of the convolution circuit (605-1) and second coefficients. The second coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450) determined for the LUT circuit (605-2).

[0127] In one embodiment, the actuator (420) may include a convolution circuit (606-1) and a LUT circuit (606-2). For example, the convolution circuit (606-1) is an input signal (x) of the DPD circuit (410). IN Convolution operations can be performed over a time interval for [n]). In another example, the convolution circuit (606-1) is an input signal (G*x) scaled by the multiplier (603). IN Convolution operations can be performed over a time interval for [n]). In another example, the convolution circuit (606-1) can perform an input signal (x IN Convolution operations can be performed over time intervals for higher-order terms of [n]). In another example, the convolution circuit (606-1) can perform convolution operations over time intervals for higher-order terms of the scaled input signal. The convolution operation can correspond to a discrete convolution operation.

[0128] For example, the time interval may include a fifth set of time units prior to a reference time unit and a sixth set of time units prior to the reference time unit. The fifth set of time units may be identified based on the number of time units included in the fifth set and the interval between the time units included in the fifth set. The sixth set of time units may be identified based on the number of time units included in the sixth set and the interval between the time units included in the sixth set. For example, the number of time units included in the fifth set, the interval between the time units included in the fifth set, the number of time units included in the sixth set, and the interval between the time units included in the sixth set may be adjusted (or changed).

[0129] For example, sample signals for performing convolution operations in the fifth set of time units and the sixth set of time units may have different weights (or coefficients).

[0130] For example, the LUT circuit (606-2) can generate an output value (β3[n]) of the LUT circuit (606-2) based on the output value (L3[n]) of the convolution circuit (606-1) and third coefficients. The third coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450) determined for the LUT circuit (606-2).

[0131] In one embodiment, the actuator (420) may include a convolution circuit (607-1) and a LUT circuit (607-2). For example, the convolution circuit (607-1) is an input signal (x) of the DPD circuit (410). IN Convolution operations can be performed over a time interval for [n]). In another example, the convolution circuit (607-1) is an input signal (G*x) scaled by the multiplier (603). IN Convolution operations can be performed over a time interval for [n]). In another example, the convolution circuit (607-1) is, input signal ((x IN Convolution operations can be performed over time intervals for higher-order terms of [n]). In another example, the convolution circuit (606-1) can perform convolution operations over time intervals for higher-order terms of the scaled input signal. The convolution operation can correspond to a discrete convolution operation.

[0132] For example, the time interval may include a seventh set of time units prior to a reference time unit and a seventh set of time units prior to a reference time unit. The seventh set of time units may be identified based on the number of time units included in the seventh set and the interval between the time units included in the seventh set. The eighth set of time units may be identified based on the number of time units included in the eighth set and the interval between the time units included in the eighth set. For example, the number of time units included in the seventh set, the interval between the time units included in the seventh set, the number of time units included in the eighth set, and the interval between the time units included in the eighth set may be adjusted (or changed).

[0133] For example, sample signals for performing convolution operations in the 7th set of time units and the 8th set of time units may have different weights (or coefficients).

[0134] For example, the LUT circuit (607-2) is the output value (L) of the convolution circuit (607-1). K Based on [n]) and the fourth coefficients, the output value (β) of the LUT circuit (607-2) K [n]) can be generated. The fourth coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450) determined for the LUT circuit (607-2).

[0135] The output value of the convolution circuit described above can be generated according to [Equation 2] below.

[0136]

[0137] L k [n] represents the output value of the k-th convolutional circuit. x[n] represents the input signal of the DPD circuit (410) at time unit n. T k represents the sample signals of the k-th convolutional circuit. Na represents the number of time units following the reference time unit. D a represents the interval between time units following the reference time unit. N d represents the number of time units prior to the reference time unit. D d ... refers to the interval between time units prior to the reference time unit. The above [Equation 2] is merely an example to aid understanding, and the present disclosure is not limited thereto. [Equation 2] may be modified, applied, or extended in accordance with the contents described in the present disclosure.

[0138] In one embodiment, the parameters of the convolution circuits (the number and interval of time units prior to the reference time, and the number and interval of time units after the reference time) may be set differently in each convolution circuit.

[0139] The output value of the LUT circuit described above can be generated according to [Equation 3] below.

[0140]

[0141] represents the output value of the k-th LUT circuit. P represents the highest-order term used in the inverse function modeling to compensate for the nonlinearity of the power amplifier (450). c ILT,k,p represents the coefficient for the p-th order term in the k-th LUT circuit. L k [n] represents the output value of the k-th convolutional circuit. The above [Equation 3] is merely an example to aid understanding, and the present disclosure is not limited thereto. [Equation 3] may be modified, applied, or extended in accordance with the contents described in the present disclosure.

[0142] In one embodiment, the actuator (420) may include an adder (608). For example, the adder (608) may be configured to perform summation of the output values ​​of LUT circuits (604-2) to LUT circuits (607-2). For example, the adder (608) may be configured to perform summation of the output values ​​of a plurality of LUT circuits included in the actuator (430). The adder (608) may provide the summed value to the multiplier (609).

[0143] In one embodiment, the actuator (420) may include a multiplier (609). The multiplier (609) can generate an output signal of the actuator (420) by performing multiplication of the value summed by the adder (608) and the input signal. For example, the output signal of the actuator (420) may be referred to as a pre-distorted signal.

[0144] The output signal of the actuator (420) as described above can be generated according to [Equation 4] below.

[0145]

[0146] y ILT [n] represents the output signal of the actuator (420). x IN [n] represents the input signal of the DPD circuit (410) at time unit n. K represents the number of LUT circuits. represents the output value of the k-th LUT circuit. The above [Equation 4] is merely an example to aid understanding, and the present disclosure is not limited thereto. [Equation 4] may be modified, applied, or extended in accordance with the contents described in the present disclosure.

[0147] FIG. 7 illustrates the time units in which convolution operations are performed. In FIG. 7, the time units in which convolution operations are performed are described.

[0148] Referring to FIG. 7, a convolution operation can be performed in a first set of time units (702) preceding a reference time unit (701) and in a second set of time units (703) following the reference time unit (701). The convolution operation can correspond to a discrete convolution operation.

[0149] For example, a first set of time units (702) can be identified based on the number of the first set of time units (702) and the interval between the first set of time units (702). In the example illustrated in FIG. 7, the number of the first set of time units may be 4, and the interval between the first set of time units may be 2. The first set of time units (702) may include a first time unit (702-1), a second time unit (702-2), a third time unit (702-3), and a fourth time unit (702-4). However, this is merely an example for illustrative purposes and the present disclosure is not limited thereto.

[0150] For example, a second set of time units (703) can be identified based on the number of the second set of time units (703) and the interval between the second set of time units (703). In the example illustrated in FIG. 7, the number of the second set of time units (703) may be 3, and the interval between the second set of time units (703) may be 3. The second set of time units (703) may include a fifth time unit (703-1), a sixth time unit (703-2), and a seventh time unit (703-3). However, this is merely an example for illustrative purposes and the present disclosure is not limited thereto.

[0151] For example, the DPD circuit (410) can perform a convolution operation over a time interval for an input signal. The time interval may include a first set of time intervals (702) and a second set of time intervals (703). By performing a convolution operation over the aforementioned time intervals, the DPD circuit (410) can extend the overall search interval. Additionally, the DPD circuit (410) can minimize (or reduce) the increase in complexity for the convolution operation by specifying the interval between sample signals.

[0152] FIG. 8 illustrates the operations of a communication device for compensating for the nonlinearity of a power amplifier. The operations of FIG. 8 may be performed by the terminal (120) of FIG. 1 or by the sub-network node (220) of FIG. 2 and FIG. 3b (e.g., a radio unit (RU)). For example, at least some of the operations may be performed by components of the communication device (400). In the following, each operation may be performed sequentially, but is not necessarily performed sequentially. For example, the order of each operation may be changed. For example, at least two operations (e.g., operation 801 and operation 802) may be performed in parallel.

[0153] Referring to FIG. 8, in operation 801, a communication device (400) according to one embodiment can generate a first pre-distorted signal by performing a convolution operation over a time interval on a digital signal of a reference time unit.

[0154] In one embodiment, the communication device (400) can perform a convolution operation over a time interval. For example, the communication device (400) can perform a convolution operation over a time interval on the input signal of the digital predistortion (DPD) circuit (410). In another example, the communication device (400) can perform a convolution operation over a time interval on a scaled input signal. In another example, the communication device (400) can perform a convolution operation over a time interval on the higher-order term of the input signal. In another example, the communication device (400) can perform a convolution operation over a time interval on the higher-order term of the scaled input signal. For example, the convolution operation may correspond to a discrete convolution operation. For example, the convolution operation may be referred to as a dilated convolution operation.

[0155] In one embodiment, the time interval in which convolution is performed may include a first set of time units preceding a reference time unit (e.g., n) and a second set of time units following the reference time unit. For example, the first set of time units may be identified based on the number of time units included in the first set and the interval between the time units included in the first set. The second set of time units may be identified based on the number of time units included in the second set and the interval between the time units included in the second set. For example, the number of time units in the first set, the interval between the time units in the first set, the number of time units in the second set, and the interval between the time units in the second set may be adjusted.

[0156] In one embodiment, sample signals for performing a convolution operation in a first set of time units and a second set of time units may have different weights (or coefficients). In one example, a sample signal of the first time unit among the first set of time units (e.g., x IN The weights applied to [n-2]) are the sample signals of the second time unit among the first set of time units (e.g., x IN The weights applied to [n-4]) may differ. In one example, the sample signal of the second time unit among the second set of time units (e.g., x IN The weight applied to [n+3]) is the fourth time unit among the second set of time units (e.g., x IN The weights applied to [n+6]) may differ. However, this is merely an example, and the present disclosure is not limited thereto.

[0157] In one embodiment, the communication device (400) can generate a first pre-distortion signal based on a plurality of convolution outputs and a plurality of LUTs (look-up tables) resulting from a plurality of convolution operations. For example, the communication device (400) can generate output values ​​based on convolution outputs and LUT coefficients. LUT coefficients may refer to coefficients associated with the inverse function of the non-linear characteristics of the power amplifier (450). For example, LUT coefficients may be set for each LUT corresponding to an individual convolution output. For example, the communication device (400) can generate output values ​​based on respective convolution outputs and LUT coefficients. For example, the communication device (400) can perform summation on the output values. The communication device (400) can generate a first pre-distortion signal by performing multiplication on the summed value and the input signal of the DPD circuit (410). For example, the first pre-distortion signal may be a signal to compensate for a long-term memory effect and / or a slot-rate memory effect occurring over a relatively long time interval.

[0158] In operation 802, a communication device (400) according to one embodiment can generate a second pre-distorted signal by performing pre-distortion on a digital signal.

[0159] In one embodiment, the communication device (400) can generate a first output value based on the input signal of the DPD circuit (410) and first coefficients. The first coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristic of the power amplifier (450). The first coefficients may refer to coefficients set in the first LUT of the actuator (420). For example, the communication device (400) can generate a second output value based on a delayed input signal and second coefficients. The delayed input signal may be delayed by one time unit. The second coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristic of the power amplifier (450). The second coefficients may refer to coefficients set in the second LUT of the actuator (420). For example, the communication device (400) can generate a third output value based on a delayed input signal and third coefficients. The delayed input signal may be delayed by two time units. The third coefficients may refer to coefficients associated with the inverse function of the nonlinear characteristics of the power amplifier (450). The third coefficients may refer to coefficients set in the third LUT of the actuator (420). Generating output values ​​may be based on [Equation 1]. In FIG. 8, examples of generating first to third output values ​​are described, but the present disclosure is not limited thereto. For example, the DPD circuit (410) may generate only some of the output values.

[0160] In one embodiment, the communication device (400) may perform summation of the generated output values. For example, the communication device (400) may generate a second pre-distortion signal by performing multiplication of the summed value and the input signal. For example, the second pre-distortion signal may be a signal for compensating for a short-term memory effect occurring in a relatively short time interval.

[0161] In operation 803, a communication device (400) according to one embodiment can generate an output signal of a DPD circuit (410) based on a first pre-distortion signal and a second pre-distortion signal.

[0162] For example, the communication device (400) can compensate for the difference between the processing time of the first actuator (420) configured to generate the first pre-distortion signal and the processing time of the second actuator (430) configured to generate the second pre-distortion signal. After compensating for the processing delay, the communication device (400) can generate an output signal of the DPD circuit (410) by performing summation of the first pre-distortion signal and the second pre-distortion signal. For example, the communication device (400) can convert the output signal of the DPD circuit (410) from a digital signal to an analog signal using a digital-to-analog converter (DAC) (440). For example, the communication device (400) can amplify the converted analog signal using a power amplifier (450). The communication device (400) can radiate the amplified signal into the air using an antenna (470).

[0163] The communication device (400) and the method performed by the communication device (400) according to the present disclosure can achieve linearity of the power amplifier (450) by compensating for memory effects occurring in a relatively short time interval and memory effects occurring in a relatively long time interval. The communication device (400) and the method performed by the communication device (400) according to the present disclosure can achieve linearity of the power amplifier (450) by compensating for not only short-term memory effects but also long-term memory effects and slow-rate memory effects. The communication device (400) and the method performed by the communication device (400) according to the present disclosure can increase the search interval for sample signals. The communication device (400) and the method performed by the communication device (400) according to the present disclosure can minimize (or reduce) the increase in computational complexity by performing a convolution operation based on sample signals of at least some of the time units.

[0164] The technical problems to be solved in this disclosure are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which this disclosure pertains.

[0165] The communication device (400) described above may include a digital predistortion (DPD) circuit (410). The communication device (400) may include a digital-to-analog converter (DAC) (440) configured to convert the output signals of the DPD circuit (410) into analog signals. The communication device may include a power amplifier (450) configured to amplify the analog signals. The communication device may include an antenna (470) configured to transmit the amplified analog signals. The DPD circuit (410) may be configured to generate first predistortion signals by performing a convolution operation on the digital signals of the reference time unit over a time interval including a first set of time units prior to the reference time unit and a second set of time units prior to the reference time unit. The above DPD circuit (410) may be configured to generate second pre-distorted signals by performing pre-distorted distortion on the digital signals. The above DPD circuit (410) may be configured to generate the output signals of the DPD circuit based on the first pre-distorted signals and the second pre-distorted signals.

[0166] For example, the communication device may include a first actuator configured to generate the first pre-distortion signals. The communication device may include a second actuator configured to generate the second pre-distortion signals. The communication device may include a compensation circuit configured to generate the output signals by compensating for a processing delay between the first actuator and the second actuator.

[0167] For example, the communication device may include a coupler configured to obtain feedback signals from the output of the power amplifier. The communication device may include a DPD coefficient estimator configured to generate coefficients for the first actuator and coefficients for the second actuator based on the feedback signals. The coefficients for the first actuator and the coefficients for the second actuator may be associated with an inverse function of the non-linear characteristics of the power amplifier.

[0168] For example, the time units of the first set may be identified based on the number of time units included in the first set and the intervals between the time units included in the first set. The time units of the second set may be identified based on the number of time units included in the second set and the intervals between the time units included in the second set.

[0169] For example, each sample signal for performing the convolution operation in the first set of time units and the second set of time units may have different weights.

[0170] For example, the DPD circuit may be configured to identify a first value based on coefficients identified from a first convolution output and a first LUT (look-up table) generated by performing a convolution operation on the digital signals of the reference time unit over a time interval including a first set of time units prior to the reference time unit and a second set of time units prior to the reference time unit. The DPD circuit may be configured to identify a second value based on coefficients identified from a second convolution output and a second LUT generated by performing a convolution operation on the digital signals of the reference time unit over a time interval including a third set of time units prior to the reference time unit and a fourth set of time units prior to the reference time unit. The DPD circuit may be configured to generate the first pre-distortion signals based on the first value, the second value, and the digital signals.

[0171] For example, the time units of the first set prior to the reference time unit may differ from the time units of the third set prior to the reference time unit. The time units of the second set after the reference time unit may differ from the time units of the fourth set after the reference time unit.

[0172] For example, the communication device may include a first actuator configured to generate the first pre-distortion signals. The first actuator may include a first multiplier for scaling the amplitude of the digital signals of the reference time unit.

[0173] For example, the first actuator may include a first convolution circuit configured to perform a convolution operation on the scaled digital signals over a time interval including a first set of time units prior to the reference time unit and a second set of time units prior to the reference time unit. The first actuator may include a first LUT circuit configured to identify a first value based on the output of the first convolution circuit and coefficients identified from the first LUT. The first actuator may include a second convolution circuit configured to perform a convolution operation on the scaled digital signals over a time interval including a third set of time units prior to the reference time unit and a fourth set of time units prior to the reference time unit. The first actuator may include a second LUT circuit configured to identify a second value based on the output of the second convolution circuit and coefficients identified from the second LUT.

[0174] For example, the first actuator may include an adder configured to perform summation of the first value and the second value. The first actuator may include a second multiplier configured to generate the first pre-distortion signals based on the output of the adder and the digital signals of the reference time unit.

[0175] A method performed by a communication device (400) as described above may include an operation of generating first pre-distortion signals by performing a convolution operation on digital signals of a reference time unit over a time interval including a first set of time units prior to a reference time unit and a second set of time units prior to the reference time unit. The method may include an operation of generating second pre-distortion signals by performing pre-distortion on the digital signals. The method may include an operation of generating output signals of a digital predistortion (DPD) circuit based on the first pre-distortion signals and the second pre-distortion signals.

[0176] For example, the operation of generating the output signals may include the operation of generating the output signals of the DPD circuit by compensating for a processing delay between a first actuator configured to generate the first pre-distortion signals and a second actuator configured to generate the second pre-distortion signals.

[0177] For example, the method may include the operation of obtaining feedback signals from the output of a power amplifier configured to amplify analog signals converted based on the output signals. The method may further include the operation of generating coefficients for the first actuator and coefficients for the second actuator based on the feedback signals. The coefficients for the first actuator and the coefficients for the second actuator may be associated with an inverse function of the non-linear characteristics of the power amplifier.

[0178] For example, the time units of the first set may be identified based on the number of time units included in the first set and the intervals between the time units included in the first set. The time units of the second set may be identified based on the number of time units included in the second set and the intervals between the time units included in the second set.

[0179] For example, each sample signal for performing a convolution operation in the first set of time units and the second set of time units may have different weights.

[0180] For example, the method may include an operation of identifying a first value based on coefficients identified from a first convolution output and a first LUT (look-up table) generated by performing a convolution operation on the digital signals of the reference time unit over a time interval including a first set of time units prior to the reference time unit and a second set of time units prior to the reference time unit. The method may include an operation of identifying a second value based on coefficients identified from a second convolution output and a second LUT generated by performing a convolution operation on the digital signals of the reference time unit over a time interval including a third set of time units prior to the reference time unit and a fourth set of time units prior to the reference time unit. The method may include an operation of generating first pre-distorted signals based on the first value, the second value, and the digital signals.

[0181] For example, the time units of the first set prior to the reference time unit may differ from the time units of the third set prior to the reference time unit. The time units of the second set after the reference time unit may differ from the time units of the fourth set after the reference time unit.

[0182] For example, the operation of generating the first pre-distortion signals may include the operation of scaling the amplitude of the digital signals of the reference time unit.

[0183] For example, the operation of generating the first pre-distortion signals may include an operation of performing a convolution operation on the scaled digital signals over a time interval including the first set of time units prior to the reference time unit and the second set of time units prior to the reference time unit. The operation of generating the first pre-distortion signals may include an operation of identifying a first value based on coefficients identified from the output of a first convolution circuit configured to perform the convolution operation over the time interval including the first set of time units and the second set of time units, and from a first LUT. The operation of generating the first pre-distortion signals may include an operation of performing a convolution operation on the scaled digital signals over a time interval including the third set of time units prior to the reference time unit and the fourth set of time units prior to the reference time unit. The operation of generating the first pre-distortion signals may include an operation of identifying a second value based on coefficients identified from the output of a second convolution circuit and a second LUT, which is configured to perform the convolution operation over the time interval including the third set of time units and the fourth set of time units.

[0184] For example, the operation of generating the first pre-distortion signals may include an operation of performing summation on the first value and the second value. The operation of generating the first pre-distortion signals may include an operation of generating the first pre-distortion signals by performing multiplication on the digital signals of the reference time unit and the output of an adder configured to perform summation.

[0185] The effects obtainable from the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present disclosure belongs.

[0186] Any of the embodiments described above may be combined with any other embodiment (or combination of embodiments) unless otherwise explicitly stated. The foregoing description of one or more embodiments is for illustrative and explanatory purposes only, and is not intended to limit or exhaust the scope of the embodiments in the exact form disclosed. Modifications and variations are possible in light of the foregoing teachings or may be obtained from the practice of various embodiments.

[0187] Methods according to the claims or embodiments described in the specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0188] When implemented in software, a computer-readable storage medium (e.g., a non-transient computer-readable storage medium) storing one or more programs (software modules) may be provided. One or more programs stored in the computer-readable storage medium are configured for execution by one or more processors within an electronic device. One or more programs include instructions that cause the electronic device to execute methods according to the claims or embodiments described in the specification of this disclosure. The one or more programs may be provided as a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0189] Such programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic disc storage devices, compact disc-ROM (CD-ROM), digital versatile discs (DVDs), or other forms of optical storage devices, magnetic cassettes. Alternatively, they may be stored in memory composed of some or all of these. Additionally, each constituent memory may include multiple units.

[0190] Additionally, the program may be stored on an attachable storage device that can be accessed via a communication network such as the Internet, Intranet, LAN (local area network), WAN (wide area network), or SAN (storage area network), or a combination thereof. Such a storage device may be connected to a device performing an embodiment of the present disclosure through an external port. Additionally, a separate storage device on a communication network may be connected to a device performing an embodiment of the present disclosure.

[0191] In the specific embodiments of the present disclosure described above, the components included in the disclosure are expressed in a singular or plural form according to the specific embodiments presented. However, the singular or plural expression is selected to suit the situation presented for convenience of explanation, and the present disclosure is not limited to singular or plural components; even if a component is expressed in the plural form, it may be composed of a singular form, and even if a component is expressed in the singular form, it may be composed of a plural form.

[0192] According to the embodiments, one or more of the aforementioned components or operations may be omitted, or one or more other components or operations may be added. Generally or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the plurality of components in the same or similar manner as those performed by the corresponding component among the plurality of components prior to the integration. According to the embodiments, operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0193] Meanwhile, although specific embodiments have been described in the detailed description of the present disclosure, it is understood that various modifications are possible within the scope of the present disclosure.

Claims

1. In a communication device, DPD (digital predistortion) circuit; A digital-to-analog converter (DAC) configured to convert the output signals of the above DPD circuit into analog signals; A power amplifier configured to amplify the above analog signals; and It includes an antenna configured to transmit the amplified analog signals, and The above DPD circuit is: First pre-distorted signals are generated by performing a convolution operation on the digital signals of the reference time unit over a time interval including a first set of time units prior to the reference time unit and a second set of time units prior to the reference time unit. By performing pre-distortion on the above digital signals, second pre-distortion signals are generated, and Configured to generate the output signals of the DPD circuit based on the first pre-distortion signals and the second pre-distortion signals. Communication device.

2. In Paragraph 1, A first actuator configured to generate the above-mentioned first pre-distortion signals; and A second actuator configured to generate the above second pre-distortion signals; and A compensation circuit further comprising a compensation circuit configured to generate the output signals by compensating for the processing delay between the first actuator and the second actuator. Communication device.

3. In Paragraph 2, A coupler configured to acquire feedback signals from the output of the power amplifier; It further includes a DPD coefficient estimator configured to generate coefficients for the first actuator and coefficients for the second actuator based on the feedback signals, and The coefficients for the first actuator and the coefficients for the second actuator are associated with an inverse function of the non-linear characteristics of the power amplifier. Communication device.

4. In Paragraph 1, The time units of the first set are identified based on the number of time units included in the first set and the intervals between the time units included in the first set, and The time units of the second set are identified based on the number of time units included in the second set and the intervals between the time units included in the second set. Communication device.

5. In Paragraph 1, Each sample signal for performing the convolution operation in the first set of time units and the second set of time units has a different weight, Communication device.

6. In Paragraph 1, The above DPD circuit is, A first value is identified based on coefficients identified from a first convolution output and a first LUT (look up table) generated by performing a convolution operation on the digital signals of the reference time unit over the time interval including the first set of time units prior to the reference time unit and the second set of time units prior to the reference time unit. A second value is identified based on coefficients identified from a second convolution output and a second LUT generated by performing a convolution operation on the digital signals of the reference time unit over a time interval including a third set of time units prior to the reference time unit and a fourth set of time units prior to the reference time unit, and Configured to generate the first pre-distortion signals based on the first value, the second value, and the digital signals, Communication device.

7. In Paragraph 6, The time units of the first set prior to the reference time unit are different from the time units of the third set prior to the reference time unit, and The second set of time units following the reference time unit are different from the fourth set of time units following the reference time unit. Communication device.

8. In Paragraph 1, It further includes a first actuator configured to generate the first pre-distortion signals, and The first actuator comprises a first multiplier for scaling the amplitude of the digital signals of the reference time unit. Communication device.

9. In Paragraph 8, The first actuator above is: A first convolution circuit configured to perform a convolution operation on the scaled digital signals over the time interval including the first set of time units prior to the reference time unit and the second set of time units prior to the reference time unit; A first LUT circuit configured to identify a first value based on the output of the first convolution circuit and coefficients identified from the first LUT; A second convolution circuit configured to perform a convolution operation on the scaled digital signals over a time interval including a third set of time units prior to the reference time unit and a fourth set of time units prior to the reference time unit; and A second LUT circuit configured to identify a second value based on the output of the second convolution circuit and coefficients identified from the second LUT, comprising Communication device.

10. In Paragraph 9, The first actuator above is: An adder configured to perform summation of the first value and the second value; and A second multiplier configured to generate the first pre-distortion signals based on the output of the adder and the digital signals of the reference time unit, Communication device.

11. In a method performed by a communication device, An operation to generate first pre-distorted signals by performing a convolution operation on the digital signals of the reference time unit over a time interval including a first set of time units prior to the reference time unit and a second set of time units prior to the reference time unit; The operation of generating second pre-distorted signals by performing pre-distortion on the above digital signals; and The operation of generating output signals of a digital predistortion (DPD) circuit based on the first predistortion signals and the second predistortion signals, method.

12. In paragraph 11, the operation of generating the output signals is, The operation of generating the output signals of the DPD circuit by compensating for the processing delay between the first actuator configured to generate the first pre-distortion signals and the second actuator configured to generate the second pre-distortion signals, method.

13. In Paragraph 12, An operation of obtaining feedback signals from the output of a power amplifier configured to amplify analog signals converted based on the above output signals; Based on the feedback signals, the method further includes the operation of generating coefficients for the first actuator and coefficients for the second actuator. The coefficients for the first actuator and the coefficients for the second actuator are associated with an inverse function of the non-linear characteristics of the power amplifier. method.

14. In Paragraph 11, The time units of the first set are identified based on the number of time units included in the first set and the intervals between the time units included in the first set, and The time units of the second set are identified based on the number of time units included in the second set and the intervals between the time units included in the second set. method.

15. In Paragraph 11, Each sample signal for performing a convolution operation in the first set of time units and the second set of time units has a different weight, method.

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