Flexible and scalable thermal test vehicle design for electronics cooling solutions

Abstract

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

Description

FLEXIBLE AND SCALABLE THERMAL TEST VEHICLE DESIGN FOR ELECTRONICS COOLING SOLUTIONSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to, and the benefit of, U.S. provisional patent application serial number 63 / 708,279 filed on October 17, 2024, incorporated herein by reference in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] Not ApplicableNOTICE OF MATERIAL SUBJECT TO COPYRIGHT PROTECTION

[0003] A portion of the material in this patent document may be subject to copyright protection under the copyright laws of the United States and of other countries. The owner of the copyright rights has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the United States Patent and Trademark Office publicly available file or records, but otherwise reserves all copyright rights whatsoever. The copyright owner does not hereby waive any of its rights to have this patent document maintained in secrecy, including without limitation its rights pursuant to 37 C. F. R. § 1 .14.BACKGROUND

[0004] 1. Technical Field

[0005] The technology of this disclosure pertains generally to thermal testing, and more particularly to a Thermal Test Vehicle (TTV) for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

[0006] 2. Background Discussion

[0007] In numerous electronic circuits and devices, one of the primary concerns has become thermal challenges. For example, consider the densityBK-2024-156-2-PCT -1-and power consumption of modern Graphics Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs). Removing heat from these devices is challenging and costly. The complexity of the problem is increased in view of the fact that it is difficult to maintain operating states of these devices to test the cooling system. Developing custom heat testing platforms for each specific device is often too costly in view of the limited data which would generally be provided.

[0008] Accordingly, a need arises for characterizing and validating cooling behavior on integrated circuits and devices which dissipate significant heat. The present disclosure fulfills that need with a scalable Thermal Test Vehicle (TTV) design which provides user heating across a heating array, along with integrated temperature and power sensing.BRIEF SUMMARY

[0009] A Thermal Test Vehicle (TTV) is typically a thermal twin of an electronic circuit package (e.g., CPU, GPU or NPU) to allow investigating thermal characteristics of these packages and / or their associated cooling systems.

[0010] The disclosed TTV uses an array of power transistors to generate desired levels of heat energy at each location in the array, in response to receiving gate drive signals through a multiplexer to each of the transistors in the array, based on user selected patterns for temperature, and / or power dissipation, across the array of transistors. The apparatus collects measurements, through a multiplexer, of drain-source current (IDS) for each row of transistors, as well as drain voltage (VD) and source voltage (Vs) measurements across each specific transistor array. In at least one embodiment, the system determines VDS (from VD - Vs), power dissipation, on- resistance, thermal impedance, and temperature for each transistor in the array. In at least one embodiment, user control inputs allow the user to select operational parameters and sequencing, with information and inputs displayed through a graphical user interface (GUI).

[0011] Further aspects of the technology described herein will be brought out in the following portions of the specification, wherein the detailed descriptionBK-2024-156-2-PCT -2-is for the purpose of fully disclosing preferred embodiments of the technology without placing limitations thereon.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The technology described herein will be more fully understood by reference to the following drawings which are for illustrative purposes only:

[0013] FIG. 1 is a block diagram of thermal test vehicle apparatus according to at least one embodiment of the present disclosure.

[0014] FIG. 2 is a schematic of the transistor array of the thermal test vehicle apparatus according to at least one embodiment of the present disclosure.

[0015] FIG. 3 is a block diagram of measurement and gate control circuitry of the thermal test vehicle apparatus according to at least one embodiment of the present disclosure.

[0016] FIG. 4 is a block diagram of the onboard computer of the thermal test vehicle apparatus according to at least one embodiment of the present disclosure.

[0017] FIG. 5 is a plot of measured device resistance according to at least one embodiment of the present disclosure.

[0018] FIG. 6 is a screen representation of a simple Graphical User Interface (GUI) enabling the selection of different thermal test profiles according to at least one embodiment of the present disclosure.

[0019] FIG. 7 is an image rendition of a fabricated thermal test vehicle apparatus according to at least one embodiment of the present disclosure.

[0020] FIG. 8A through FIG. 8D are image renditions of the transistor array and custom heat profile results created therefrom, according to at least one embodiment of the present disclosure.DETAILED DESCRIPTION

[0021] 1. Introduction

[0022] The advent of machine learning, artificial intelligence, and the internet- of-things has led to dramatic growth in Internet Technology (IT) infrastructure. While data centers already represent two percent of global energy usage, forecasts predict that their consumption may double in the next two years. ABK-2024-156-2-PCT -3-significant portion of this energy is expended as unwanted heat by the computing electronics; as a result, thermal challenges have become a primary concern. The density and power consumption of modern Graphics Processing Units (GPUs), Central Processing Units (CPUs) and Network Processing Units (NPUs) is growing rapidly. Removing heat from these devices can be extremely challenging, given their small size, electrical activity, and mechanical constraints. This necessitates the design of advanced liquid cooling systems for next-generation computing. Existing solutions for characterizing and validating these coolers are unable to meet targets for cost, scalability, and configurability.

[0023] The present disclosure provides a novel approach to Thermal Test Vehicle (TTV) design, based on an array of power transistors, measurement / control circuitry, and onboard control circuitry (e.g., computer).

[0024] 2. Thermal Testing

[0025] A. Thermal Test Vehicle Requirements

[0026] The purpose of a TTV is to mimic the thermal operating conditions of an electronic circuit (e.g., GPU, CPU, NPU or other IC, or packaged circuit such as containing a combination of ICs (server blade, etc.,)) while providing an accessible testing environment to assess performance of the cooling solution. There are three main components to this:

[0027] (1 ) Heat Generation: In at least one embodiment, the system must be capable of generating very large amounts of heat (e.g., in the multi-kilowatt range for modem and emerging computing platforms) in a small surface area (e.g., less than 100 cm2) with a controllable spatial and temporal profile.

[0028] (2) Temperature Sensing: Accurate temperature measurements should be recorded at the surface of the heater with sufficient spatial fidelity to allow assessing thermal performance characteristics.

[0029] (3) User Interface: Users should be able to quickly and easily specify operating conditions for tests, such as power levels, hotspots, and duration; while data collection and transmission should be amenable to integration within existing testing platforms.

[0030] B. Existing Commercial Solutions

[0031] It is possible to test cooling systems with the end-use electronicsBK-2024-156-2-PCT -4-themselves, such as an actual data center server blade; but high-performance commercial servers are extremely expensive and inflexible. There are also strict limitations on the amount of heat that can be generated before the server shuts down, and there is typically meager control, or no control, of how the heat is localized spatially along the surface.

[0032] An alternative approach is to use an array of mechanical heaters, such as copper pads, and to conduct current through them to dissipate power.Each heater is usually fairly large, however, so the heat cannot be localized accurately. Moreover, a complex mechanical assembly is required to extract operating temperature measurements. If each heater in the array is individually addressable, it will require its own temperature sensor and power supply, which drastically increases both complexity and cost. Another option involves designing Application Specific Integrated Circuits (ASICs) to simultaneously perform heat generation and temperature sensing. This technology is very expensive to develop and difficult to scale to a sufficiently large size and achievable power level. Additional circuitry would be required to communicate between ICs, which would further complicate the electrical design.

[0033] 3. Design Approach

[0034] FIG. 1 illustrates an example embodiment 10 for the disclosed Thermal Test Vehicle (TTV) design, highlighting three main aspects of an array of power transistors, measurement / control circuitry, and onboard computer.

[0035] The TTV is shown in the figure having an array 18 of transistors 36 for generating a thermal test pattern. Power and ground are provided from Power Supply Unit (PSU) 20 to conduct current through the array of power transistors, thus generating heat due to conduction losses. For the sake of simplicity of illustration this figure only shows one transistor 36, whereas the disclosure is configured for controlling transistor arrays of any practical size and geometric arrangement.

[0036] A measurement and control unit 16 is configured for controlling the activation of each transistor 36 in array 18 and measuring drain-source (VD - Vs) voltage and current (IDS) through each transistor. In at least one embodiment, the measurement and control unit utilizes multiplexing 35BK-2024-156-2-PCT -5-(multiplexed inputs and / or outputs), to reduce the amount of circuitry required.

[0037] A gate drive unit control 32 of measurement and control circuit 16 is used to control a Digital-to-Analog converter, or similar, here shown as a Gate Drive (GD) unit 32c which outputs a differential signal through 34c, 34d, through a portion of multiplexer 35 to drive the Gate-to-Source potential of transistor 36, and other transistors as the multiplexer is switched. It should be appreciated that in at least one embodiment directed to larger array sizes, that multiple gate drive control outputs can provided, with each directed through a different multiplexer.

[0038] An optional gate pulse stretching circuit 38, exemplified as a capacitor, is shown for extending the pulses which drive each transistor of the array to a desired level of drain-source resistance. If utilized, one gate pulse stretching circuit would be connected to the gate of each transistor 36, to extend the active time of the transistor, to thus compensate for the short active signals being output from the multiplexer and any gate leakage currents.

[0039] The figure shows the IDS line coming from the current sensing loop 37 into a portion of multiplexer 35 in the measurement and control circuit 16 through connection 34a to an Analog-to-Digital Converter (ADC) 32a. The VD and Vs lines read the differential voltage across a transistor 36 (from drain to source) into a portion of multiplexor 35 through connections 34b, 34c to an Analog-to-Digital Converter (ADC) 32b. It should be appreciated that in at least one embodiment directed to larger array sizes, multiple multiplexers and associated ADCs can be utilized, to reduce multiplexing depth.

[0040] The above measurements from the transistor array are then used in onboard computer 14, with the measured IDS and VDS utilized 26 to determine both power (PT) and thermal resistance (RT). Calibration parameters (data) 28 and temperature estimation 30 are utilized in determining heat flow (PT) versus changes in temperature AT (PT I AT) 24, with the information being passed to section 22 handling test conditions and calibration parameters and for controlling GUI 12. These aspects being described in greater detail in regard to FIG. 4. It should be appreciated that in at least one embodiment directed to multiple TTVs in a single system, a local microcontroller or other digital logic could send the pertinent information to a dedicated computerBK-2024-156-2-PCT -6-which processes, records, and displays data from multiple TTVs.

[0041] A. Transistor Array

[0042] FIG. 2 illustrates an example embodiment 50 of a small transistor array, showing three rows 52, 54, 56, with three transistors each 58a, 58b, and 58c. Each transistor is seen with its gate (G), drain (D) and source (S) connection. It should be appreciated that the array may be extended in both the number of rows and / or number of transistors per row, or the size of the transistors, to provide significant implementation flexibility to suit the specific application. The TTV array is scalable, allowing the array size and shape (geometric arrangement of transistors) to be readily modified to match the dimensions and shape of a desired application, for instance for commercial Graphics Processing Units (GPUs) or Central Processing Units (CPUs).

[0043] The array can also be fabricated to support any desired number of rows and / or columns, any desired size of transistors (thus changing the resolution of the thermal pattern control), changing spacing of transistors (from tight spacing on through to sparse array spacing), altering geometric arrangement (e.g., row-column geometry, interspersed array (somewhat sparse array with sequential rows offset by a specific fraction of transistor to transistor spacing (e.g., spacing, spacing, and so forth)), radial array, and any other geometry to which the transistors may be arranged. It should also be appreciated that the present disclosure can also be extended from a 2D TTV to a 3D TTV if warranted by the thermal geometry of a specific application.

[0044] The total power generated by the array as a whole may be adjusted by controlling the output current of the Power Supply Unit (PSU). Each transistor acts in the circuit as a variable resistor, so there is individual control of the power dissipated in every device. This enables the generation of custom heat maps, hot spots, and pulsed power profiles which can mimic a desired testing scenario. For each device, the drain-to-source current (IDS), drain voltage (VD), source voltage (Vs), and gate voltage (VG), are connected to the analog multiplexers of the measurement / control circuitry. It should be appreciated that in at least one embodiment the current-controlling PSU could be integrated as part of the TTV system.BK-2024-156-2-PCT -7-

[0045] B. Measurement / Control Circuitry

[0046] FIG. 3 illustrates an example embodiment 110 of Measurement and Control Circuitry. The transistor signals are connected through analog multiplexers 112a through 112d, which are connected as seen in FIG. 2 so they can be controlled and / or sampled individually. Multiplexer control signals 113 are seen connecting to control the states of each multiplexer.

[0047] In at least one embodiment, a bus 114 is utilized (e.g., Serial Peripheral Interface (SPI)) for communicating from the controller to various input and output elements. In the example Analog-to-digital converters (ADCs) 122, 120 are shown which are used to measure IDS and VDS, respectively. A Digital-to-Analog Converter (DAC) 116 is utilized in combination with a gate driver 118 to generate VGS 124.

[0048] FIG. 4 illustrates a block diagram of an example processing 150 being performed on a computer processor in the TTV. Based on test conditions and parameters 158 provided to the Graphical User Interface (GUI) 152, appropriate control signals are generated for the power supply, SPI bus communication, and analog multiplexers. Measured results are used to estimate thermal performance, which is reported in the GUI, and may be also provided to external devices (not shown) as desired.

[0049] In at least one embodiment, the TTV incorporates a processor, such as a small, onboard embedded processor executing firmware for controlling the TTV to perform all of the necessary low-level control, store calibration data, and to provide an accessible interface. It can be connected directly to a computer monitor where a graphical user interface (GUI) 152 will enable users to specify testing profiles and heat maps. This enables live data collection and visualization. The (GUI) 152 allows the user to setup and control the Test Conditions and Calibration Parameters 158 of the TTV.

[0050] Signals are shown coming in and out on the left side of this figure, depicting Power Supply Unit (PSU) Control 164, SPI communications 166 for reading back VDS and IDS, and Multiplexer Control 168 for switching the Analog Multiplexors 112a through 112d as seen in FIG. 3. It should be seen that multiplexors 112a and 112b in FIG. 3 are for receiving analog inputs for VD and Vs, while Analog Multiplexer 112d in FIG. 3 is for receiving an IDSBK-2024-156-2-PCT -8-signal from each of the rows of transistors. Analog multiplexer 112c in FIG. 3 is configured for outputting the gate drive signal to each of the transistors.

[0051] In at least on embodiment, the gate signal from the analog multiplexer is extended to hold the gate at a desired voltage state for a desired duration. In at least one embodiment, a gate pulse stretching circuit 38 in FIG. 1 , exemplified as a capacitor, is coupled between the gate and source of each transistor in the array to retain the charge from the gate pulse signal and thus stretch the duration of the specific resistance state of the transistor controlled by the gate signal. It should be appreciated that in some instances the intrinsic capacitance of the gate could be sufficient, depending on a number of factors including multiplexer refresh rate. In addition, other mechanisms can be utilized for retaining the gate drive.

[0052] The figure depicts the VDS and IDS signals coming back from the SPI bus 166 into block 162 which determines the power dissipated by the transistor (PT) by multiplying the voltage differential VDS and transistor current IDS, while on-resistance (RT) is determined by dividing voltage differential VDS by the IDS current level.PT = VDS X IDS (1 )RT = VDS I IDS (2)

[0053] The on-resistance of a transistor is temperature-dependent, so the junction temperature of each device (TT) may be extracted 160 as a function of the measured on-resistance and applied gate-to-source voltage (VGS). It can be seen in the figure that temperature estimation 154 is performed based on RT, and using calibration data 156 which are inputs to the PT I AT determination 160.TT= f(RT, VGS) (3)All of this information is preferably made available through GUI 152.

[0054] FIG. 5 illustrates an example results 210 of measured device resistance as a function of temperature for different applied gate-to-source voltages. This trend enables temperature estimation and accurate control of power dissipation in every transistor. Through calibration under known temperatures, the TTV system can then obtain a correlation between measured transistor resistance and temperature. The figure demonstratesBK-2024-156-2-PCT -9-that there is a clear relationship between the on-resistance of a transistor (y- axis) and the junction temperature of that transistor (x-axis); and that this relationship is used to perform estimation of transistor junction temperatures based on the measured on-resistance values. This figure also shows that on- resistance depends on the applied gate-to-source voltage (VGS). Therefore VGS is adjusted by the system according to the power dissipation (and heat generation) specified by the user for each transistor. Overall, these relationships between temperature, VGS, and on-resistance enable the temperature estimation and flexible heat generation provided by this design.

[0055] In at least one embodiment, the system only requires a single power supply, one gate driver, and two high-precision ADCs, which can significantly reduce complexity, component count, and cost. The use of standard, commercially available components also leads to a significant reduction in cost compared to existing solutions.

[0056] FIG. 6 illustrates an example embodiment 230 of a simple graphical user interface enabling the selection of different thermal test profiles and live visualization of measured characteristics.

[0057] In this simple example, a user can select from different heat maps, exemplified here as three different map types: Uniform, Pattern, and Letter shapes. Each dash in the Grid of dashes represents a desired heat dissipation for the transistor, such as in milliwatts (mW). It should also be appreciated that alternate and / or additional information may be displayed, such the resistance of the transistor, temperature, or other measured and / or derivable information. In at least one embodiment, a combined power consumption (Watts) is shown for the selected combination of power (e.g., mW or W) setting for each transistor. The measured resistance of each transistor (RT) is used to estimate its temperature, along with stored calibration data.

[0058] In the configuration shown in FIG. 3, control / data is passed to the hardware elements through a bus exemplified as a Serial Peripheral Interface (SPI) bus which communicates from the processor to the measurement circuitry, while digital control signals from the processor control the selection of analog multiplexer inputs / outputs. It should be appreciated that theBK-2024-156-2-PCT -10-controller circuit may directly or indirectly input / output both analog and digital signals, by means of other than a bus structure.

[0059] 4. Hardware Validation

[0060] FIG. 7 illustrates an example embodiment 250 of a fabricated TTV hardware prototype having an array of transistors 258. By way of example and not limitation, this specific array depicts 154 transistors spanning an area of 75 mm x 75 mm. The figure also depicts external signal connectors 252, an onboard processor 254 and the measurement circuitry 256, as well as power connections 258 and other circuitry 260 as desired.

[0061] In order to validate the proposed approach, this 1 kWTTV hardware prototype was built. The 154 transistors of the array are shown arranged into multiple rows and columns, which in this example were divided to provide 14 rows and 11 columns withing a 75 mm x 75 mm grid to match the footprint of a large commercial server Central Processing Unit (CPU). In at least one preferred embodiment, the transistors are housed in metal packages which offer low thermal impedance, thus facilitating high power operation.

[0062] FIG. 8A through FIG. 8D illustrates a demonstration of custom heat profiles for the disclosed TTV hardware prototype. FIG. 8A shows the transistor array itself 310. FIG. 8B shows Uniform heating 320 across the array. FIG. 8C shows heating a square ring pattern 330 (outer heating). FIG. 8D shows heating to create a letter H pattern 340 in the transistor array. It should be appreciated that other patterns may be created as desired, such as any geometric patterns, or patterns which mimic expected hot spot areas of the intended device being simulated, and other desired patterns without limitation.

[0063] 5. Conclusions

[0064] Thermal challenges in data centers have been growing rapidly. To address these concerns, high-performance cooling solutions must be developed and tested. The present disclosure describes an affordable, highly flexible, and scalable TTV design using an array of power transistors, associated measurement circuitry, and onboard computer. The approach is validated through a hardware prototype demonstrating individual control of device power dissipation and temperature as well as a convenient userBK-2024-156-2-PCT -11-interface to specify testing conditions.

[0065] 6. General Scope of Embodiments

[0066] Embodiments of the technology of this disclosure may be described herein with reference to flowchart illustrations of methods and systems according to embodiments of the technology. Embodiments of the technology of this disclosure may also be described with reference to procedures, algorithms, steps, operations, formulae, or other computational depictions, which may be included within the flowchart illustrations or otherwise described herein. It will be appreciated that any of the foregoing may also be implemented as computer program instructions. In this regard, each block or step of a flowchart, and combinations of blocks (and / or steps) in a flowchart, as well as any procedure, algorithm, step, operation, formula, or computational depiction can be implemented by various means, such as hardware, firmware, and / or software including one or more computer program instructions embodied in computer-readable program code. As will be appreciated, any such computer program instructions may be executed by one or more computer processors, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer processor(s) or other programmable processing apparatus create means for implementing the function(s) specified.

[0067] Accordingly, blocks of the flowcharts, and procedures, algorithms, steps, operations, formulae, or computational depictions described herein support combinations of means for performing the specified function(s), combinations of steps for performing the specified function(s), and computer program instructions, such as embodied in computer-readable program code logic means, for performing the specified function(s). It will also be understood that each block of the flowchart illustrations, as well as any procedures, algorithms, steps, operations, formulae, or computational depictions and combinations thereof described herein, can be implemented by special purpose hardware-based computer systems which perform the specified function(s) or step(s), or combinations of special purpose hardwareBK-2024-156-2-PCT -12-and computer-readable program code.

[0068] Furthermore, these computer program instructions, such as embodied in computer-readable program code, may also be stored in one or more computer-readable memory or memory devices that can direct a computer processor or other programmable processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory or memory devices produce an article of manufacture including instruction means which implement the function specified in the block(s) of the flowchart(s). The computer program instructions may also be executed by a computer processor or other programmable processing apparatus to cause a series of operational steps to be performed on the computer processor or other programmable processing apparatus to produce a computer- implemented process such that the instructions which execute on the computer processor or other programmable processing apparatus provide steps for implementing the functions specified in the block(s) of the flowchart(s), procedure (s) algorithm(s), step(s), operation(s), formula(e), or computational depiction(s).

[0069] It will further be appreciated that the terms "programming" or "program executable" as used herein refer to one or more instructions that can be executed by one or more computer processors to perform one or more functions as described herein. The instructions can be embodied in software, in firmware, or in a combination of software and firmware. The instructions can be stored locally to the device in non-transitory media, or can be stored remotely such as on a server, or all or a portion of the instructions can be stored locally and remotely. Instructions stored remotely can be downloaded (pushed) to the device by user initiation, or automatically based on one or more factors.

[0070] It will further be appreciated that as used herein, the terms controller, microcontroller, processor, microprocessor, hardware processor, computer processor, central processing unit (CPU), and computer are used synonymously to denote a device capable of executing the instructions and communicating with input / output interfaces and / or peripheral devices, and that the terms controller, microcontroller, processor, microprocessor, hardwareBK-2024-156-2-PCT -13-processor, computer processor, CPU, and computer are intended to encompass single or multiple devices, single core and multicore devices, and variations thereof.

[0071] From the description herein, it will be appreciated that the present disclosure encompasses multiple implementations of the technology which include, but are not limited to, the following:

[0072] A thermal test vehicle (TTV) apparatus, comprising: (a) an array of power transistors arranged as a number of serial connected power transistors in each row, and a number of rows adjacent one another; (b) wherein each row of transistors is configured to receive power and ground from a power supply unit; (c) analog multiplexers which receive a signal for drain-source current (IDS) for one row of transistors, and receive drain voltage (VD) and source voltage (Vs) across a specific transistor in one row of transistors; (d) analog-to-digital converters (ADC) configured for receiving and converting said IDS and VDS = VD - VS signals into digital signals; (e) a gate driver circuit comprising a digital-to-analog converter (DAC) which is configured for converting a selected gate drive value from a gate drive signal into an analog gate drive signal; (f) an analog multiplexer configured for receiving said analog gate drive signal and directing it from across the gate and source contacts of a particular transistor in said array of transistors; (g) executing instructions from a non-transitory memory storing instructions executable by a processor of the TTV for generating thermal test patterns, comprising: (g)(i) receiving user input on a user interface configured for allowing a user to set selected operational values; (g)(ii) controlling output of gate drive values for the transistors in the array of transistors based on user selected operational values for temperature, and / or power dissipation, for each transistor in the array; (g)(iii) determining both power dissipation PT = VDS X IDS, and on- resistance RT = VDS I IDS from IDS and VDS measurements for each transistor in the array; (g)(iv) extracting a temperature estimation of each transistor as transistor junction temperature as a function of measured on-resistance and applied gate-to-source voltage (VDS); (g)(v) determining thermal impedance (PT I AT) based on power dissipation, estimated temperature, and associated calibration information; (g)(vi) extracting a temperature estimation of eachBK-2024-156-2-PCT -14-transistor as a transistor junction temperature which is a function of measured on-resistance and the applied gate-to-source voltage (VDS); and (g)(vii) outputting information, for controlling an external display, on transistor operation selected from a group of determinations including power dissipation, on-resistance, thermal impedance, drain-to-source voltage, and source current.

[0073] A thermal test vehicle (TTV) apparatus, comprising: (a) an array of power transistors configured to receive power and ground from a power supply unit; (b) analog multiplexers which receive a signal for controlling drain-source current (IDS) through a gate driver or drivers, for each of the transistors in the array, and receive drain voltage (VD), source voltage (Vs), and drain-source current (IDS) measurements on the transistors in the array; (c) a control circuit configured for controlling the operation of the analog multiplexers, gate driver, and generation of thermal test patterns, comprising: (c)(i) controlling the output of gate drive values for the transistors in the array of transistors based on user selected operational values for temperature, and / or power dissipation, for each transistor in the array; (c)(ii) determining both power dissipation PT = VDS X IDS, and on-resistance RT = VDS I IDS from IDS and VDS measurements for each transistor in the array; (c)(iii) extracting a temperature estimation of each transistor as transistor junction temperature as a function of the measure on-resistance and the applied gate-to-source voltage (VDS); (c)(iv) determining thermal impedance (PT / AT) based on the power dissipation and estimated temperature as well as calibration information; (c)(v) extracting a temperature estimation of each transistor as a transistor junction temperature which is a function of the measure on- resistance and the applied gate-to-source voltage (VDS); and (c)(vi) outputting information on transistor operation selected from the group of determinations including power dissipation, on-resistance, thermal impedance, drain-to- source voltage, and source current.

[0074] A method of providing a thermal test vehicle (TTV), comprising: (a) directing power to an array of power transistors; (b) outputting a gate drive signal through an analog multiplexer based on user selected operational values for temperature, and / or power dissipation, with the output from theBK-2024-156-2-PCT -15-multiplexor controlling the gates of each transistor in the array; (c) outputting control signals for controlling analog multiplexers which receive drain voltage (VD), source voltage (Vs), and drain-source current (IDS) measurements on the transistors in the array; (d) determining power dissipation PT = VDS X IDS, and on-resistance RT = VDS I IDS from IDS and VDS measurements for each transistor in the array; (e) extracting a temperature estimation of each transistor as transistor junction temperature as a function of the measure on- resistance and the applied gate-to-source voltage (VDS); (f) determining thermal impedance (PT I AT) based on the power dissipation, estimated temperature, and calibration information; (g) extracting a temperature estimation of each transistor as a transistor junction temperature as a function of the measure on-resistance and the applied gate-to-source voltage (VDS); and (h) outputting information on transistor operation selected from the group of determinations consisting of power dissipation, on-resistance, thermal impedance, drain-to-source voltage, and source current.

[0075] A thermal test vehicle (TTV) apparatus, comprising: (a) an array of power transistors arranged as a number of serial connected power transistors in each row, and a number of rows adjacent one another; (b) wherein each row of transistors is configured to receive power and ground from a power supply unit; (c) analog multiplexers which receive a signal for the drain-source current (IDS) for one row of transistors, and receive drain voltage (VD) and source voltage (Vs) across a specific transistor in the one row of transistors;(d) analog-to-digital converters (ADC) configured for receiving and converting said IDS and VDS = VD - VS signals into digital signals; (e) a gate driver circuit including a digital-to-analog converter (DAC) which is configured for converting a selected gate drive value from a gate drive signal into an analog gate drive signal; (f) an analog multiplexer configured for receiving said analog gate drive signal and directing it from across the gate and source contacts of a particular transistor in said array of transistors; (g) executing instructions from a non-transitory memory storing instructions executable by a processor of the TTV for generating thermal test patterns, comprising: (g)(i) controlling the output of gate drive values for the transistors in the array of transistors based on user selected values for temperature, and / or powerBK-2024-156-2-PCT -16-dissipation, for each transistor in the array; (g)(ii) determining both power dissipation PT = VDS X IDS, and on-resistance RT = VDS I IDS from IDS and VDS measurements for each transistor in the array; (g)(iii) extracting a temperature estimation of each transistor as a transistor junction temperature as a function of the measure on-resistance and the applied gate-to-source voltage (VDS); (g)(iv) determining thermal impedance (PT I AT) based on the power dissipation and estimated temperature as well as associated calibration information; (g)(v) displaying information on transistor operation selected from the group of determinations including power dissipation, on-resistance, thermal impedance, drain-to-source voltage, and source current; and (g)(vi) extracting a temperature estimation of each transistor as a transistor junction temperature which is a function of the measure on-resistance and the applied gate-to-source voltage (VDS).

[0076] The apparatus or method of any preceding implementation, wherein said TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

[0077] The apparatus or method of any preceding implementation, wherein TTV test conditions and calibration parameters are stored for viewing and adjustment by the user through said user interface.

[0078] The apparatus or method of any preceding implementation, wherein said user interface comprises a graphical user interface.

[0079] The apparatus or method of any preceding implementation, wherein said user interface is configured to allow the user to select from different types of heat maps.

[0080] The apparatus or method of any preceding implementation, wherein said different types of heat maps are selected from the group of heat maps consisting of uniform, pattern, and letter shapes.

[0081] The apparatus or method of any preceding implementation, wherein each transistor acts in the circuit as a variable resistor, toward allowing individual control of power dissipation at each transistor in the array.

[0082] The apparatus or method of any preceding implementation, wherein said transistor operation is shown for the array of transistors in the form of a graphical heat map.BK-2024-156-2-PCT -17-

[0083] The apparatus or method of any preceding implementation, wherein said array of power transistors is a 2D array.

[0084] The apparatus or method of any preceding implementation, wherein total power generated by the array as a whole can be adjusted by controlling the output current of the power supply unit.

[0085] The apparatus or method of any preceding implementation, further comprising a gate pulse stretching circuit on a gate of each transistor in the array of transistors, to extend active time of signals being output from the multiplexer as driven from the gate drive signal.

[0086] As used herein, the term "implementation" is intended to include, without limitation, embodiments, examples, or other forms of practicing the technology described herein.

[0087] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. Reference to an object in the singular is not intended to mean "one and only one" unless explicitly so stated, but rather "one or more."

[0088] Phrasing constructs, such as “A, B and / or C”, within the present disclosure describe where either A, B, or C can be present, or any combination of items A, B and C. Phrasing constructs indicating, such as “at least one of” followed by listing a group of elements, indicates that at least one of these groups of elements is present, which includes any possible combination of the listed elements as applicable.

[0089] References in this disclosure referring to “an embodiment”, “at least one embodiment” or similar embodiment wording indicates that a particular feature, structure, or characteristic described in connection with a described embodiment is included in at least one embodiment of the present disclosure. Thus, these various embodiment phrases are not necessarily all referring to the same embodiment, or to a specific embodiment which differs from all the other embodiments being described. The embodiment phrasing should be construed to mean that the particular features, structures, or characteristics of a given embodiment may be combined in any suitable manner in one or more embodiments of the disclosed apparatus, system, or method.BK-2024-156-2-PCT -18-

[0090] As used herein, the term "set" refers to a collection of one or more objects. Thus, for example, a set of objects can include a single object or multiple objects.

[0091] Relational terms such as first and second, top and bottom, upper and lower, left and right, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0092] The terms "comprises," "comprising," "has", "having," "includes", "including," "contains", "containing" or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, apparatus, or system, that comprises, has, includes, or contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, apparatus, or system. An element proceeded by "comprises . . . a", "has . . . a", "includes . . . a", "contains . . . a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, apparatus, or system, that comprises, has, includes, contains the element.

[0093] As used herein, the terms "approximately", "approximate", "substantially", "substantial", "essentially", and "about", or any other version thereof, are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. When used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ± 10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1 %, less than or equal to ±0.5%, less than or equal to ±0.1 %, or less than or equal to ±0.05%. For example, "substantially" aligned can refer to a range of angular variation of less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1 °, less than or equal to ±0.5°, less than or equal to ±0.1 °, or lessBK-2024-156-2-PCT -19-than or equal to ±0.05°.

[0094] Additionally, amounts, ratios, and other numerical values may sometimes be presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. For example, a ratio in the range of about 1 to about 200 should be understood to include the explicitly recited limits of about 1 and about 200, but also to include individual ratios such as about 2, about 3, and about 4, and sub-ranges such as about 10 to about 50, about 20 to about 100, and so forth.

[0095] The term "coupled" as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is "configured" in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

[0096] Benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of the technology described herein or any or all the claims.

[0097] In addition, in the foregoing disclosure various features may be grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Inventive subject matter can lie in less than all features of a single disclosed embodiment.

[0098] The abstract of the disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

[0099] It will be appreciated that the practice of some jurisdictions may require deletion of one or more portions of the disclosure after the application is filed. Accordingly, the reader should consult the application as filed for the originalBK-2024-156-2-PCT -20-content of the disclosure. Any deletion of content of the disclosure should not be construed as a disclaimer, forfeiture, or dedication to the public of any subject matter of the application as originally filed.

[0100] All text in a drawing figure is hereby incorporated into the disclosure and is to be treated as part of the written description of the drawing figure.

[0101] The following claims are hereby incorporated into the disclosure, with each claim standing on its own as a separately claimed subject matter.

[0102] Although the description herein contains many details, these should not be construed as limiting the scope of the disclosure, but as merely providing illustrations of some of the presently preferred embodiments. Therefore, it will be appreciated that the scope of the disclosure fully encompasses other embodiments which may become obvious to those skilled in the art.

[0103] All structural and functional equivalents to the elements of the disclosed embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed as a "means plus function" element unless the element is expressly recited using the phrase "means for". No claim element herein is to be construed as a "step plus function" element unless the element is expressly recited using the phrase "step for".BK-2024-156-2-PCT -21-

Claims

CLAIMSWhat is claimed is:1 . A thermal test vehicle (TTV) apparatus, comprising:(a) an array of power transistors arranged as a number of serial connected power transistors in each row, and a number of rows adjacent one another;(b) wherein each row of transistors is configured to receive power and ground from a power supply unit;(c) analog multiplexers which receive a signal for drain-source current (IDS) for one row of transistors, and receive drain voltage (VD) and source voltage (Vs) across a specific transistor in one row of transistors;(d) analog-to-digital converters (ADC) configured for receiving and converting said IDS and VDS = VD - VS signals into digital signals;(e) a gate driver circuit comprising a digital-to-analog converter (DAC) which is configured for converting a selected gate drive value from a gate drive signal into an analog gate drive signal;(f) an analog multiplexer configured for receiving said analog gate drive signal and directing it from across the gate and source contacts of a particular transistor in said array of transistors;(g) executing instructions from a non-transitory memory storing instructions executable by a processor of the TTV for generating thermal test patterns, comprising:(i) receiving user input on a user interface configured for allowing a user to set selected operational values;(ii) controlling output of gate drive values for the transistors in the array of transistors based on user selected operational values for temperature, and / or power dissipation, for each transistor in the array;(iii) determining both power dissipation PT = VDS X IDS, and on- resistance RT = VDS I IDS from IDS and VDS measurements for each transistor in the array;(iv) extracting a temperature estimation of each transistor as transistor junction temperature as a function of measured on-resistance andBK-2024-156-2-PCT -22-applied gate-to-source voltage (VDS);(v) determining thermal impedance (PT I AT) based on power dissipation, estimated temperature, and associated calibration information;(vi) extracting a temperature estimation of each transistor as a transistor junction temperature which is a function of measured on-resistance and the applied gate-to-source voltage (VDS); and(vii) outputting information, for controlling an external display, on transistor operation selected from a group of determinations including power dissipation, on-resistance, thermal impedance, drain-to-source voltage, and source current.

2. The apparatus of claim 1 , wherein said TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

3. The apparatus of claim 1 , wherein TTV test conditions and calibration parameters are stored for viewing and adjustment by the user through said user interface.

4. The apparatus of claim 3, wherein said user interface comprises a graphical user interface.

5. The apparatus of claim 3, wherein said user interface is configured to allow the user to select from different types of heat maps.

6. The apparatus of claim 5, wherein said different types of heat maps are selected from the group of heat maps consisting of uniform, pattern, and letter shapes.

7. The apparatus of claim 1 , wherein each transistor acts in the circuit as a variable resistor, toward allowing individual control of power dissipation at each transistor in the array.BK-2024-156-2-PCT -23-8. The apparatus of claim 1 , wherein said transistor operation is shown for the array of transistors in the form of a graphical heat map.

9. The apparatus of claim 1 , wherein said array of power transistors is a 2D array.

10. The apparatus of claim 1 , wherein total power generated by the array as a whole, can be adjusted by controlling the output current of the power supply unit.11 . The apparatus of claim 1 , further comprising a gate pulse stretching circuit on a gate of each transistor in the array of transistors, to extend active time of signals being output from the multiplexer as driven from the gate drive signal.

12. A thermal test vehicle (TTV) apparatus, comprising:(a) an array of power transistors configured to receive power and ground from a power supply unit;(b) analog multiplexers which receive a signal for controlling drain-source current (IDS) through a gate driver or drivers, for each of the transistors in the array, and receive drain voltage (VD), source voltage (Vs), and drain-source current (IDS) measurements on the transistors in the array;(c) a control circuit configured for controlling the operation of the analog multiplexers, gate driver, and generation of thermal test patterns, comprising:(i) controlling the output of gate drive values for the transistors in the array of transistors based on user selected operational values for temperature, and / or power dissipation, for each transistor in the array;(ii) determining both power dissipation PT = VDS X IDS, and on- resistance RT = VDS I IDS from IDS and VDS measurements for each transistor in the array;(iii) extracting a temperature estimation of each transistor as transistor junction temperature as a function of the measure on-resistance and the applied gate-to-source voltage (VDS);BK-2024-156-2-PCT -24-(iv) determining thermal impedance (PT I AT) based on the power dissipation and estimated temperature as well as calibration information;(v) extracting a temperature estimation of each transistor as a transistor junction temperature which is a function of the measure on- resistance and the applied gate-to-source voltage (VDS); and(vi) outputting information on transistor operation selected from the group of determinations including power dissipation, on-resistance, thermal impedance, drain-to-source voltage, and source current.

13. The apparatus of claim 12, wherein TTV test conditions and calibration parameters are stored for viewing and adjustment by the user through said user interface.

14. The apparatus of claim 13, wherein said user interface is configured to allow the user to select from different types of heat maps.

15. The apparatus of claim 14, wherein said different types of heat maps comprise uniform, pattern, and letter shapes.

16. The apparatus of claim 12, wherein each transistor acts in the circuit as a variable resistor, toward allowing individual control of power dissipation at each transistor in the array.

17. The apparatus of claim 12, wherein said transistor operation is shown for the array of transistors in the form of a graphical heat map.

18. The apparatus of claim 12, wherein total power generated by the array as a whole can be adjusted by controlling the output current of the power supply unit.

19. The apparatus of claim 12, further comprising a gate pulse stretching circuit on the gate of each transistor in the array of transistors, to extend active time of signals being output from the multiplexer as driven from the gate drive signal.BK-2024-156-2-PCT -25-20. A method of providing a thermal test vehicle (TTV), comprising:(a) directing power to an array of power transistors;(b) outputting a gate drive signal through an analog multiplexer based on user selected operational values for temperature, and / or power dissipation, with the output from the multiplexor controlling the gates of each transistor in the array;(c) outputting control signals for controlling analog multiplexers which receive drain voltage (VD), source voltage (Vs), and drain-source current (IDS) measurements on the transistors in the array;(d) determining power dissipation PT = VDS X IDS, and on-resistance RT = VDS I IDS from IDS and VDS measurements for each transistor in the array;(e) extracting a temperature estimation of each transistor as transistor junction temperature as a function of the measure on-resistance and the applied gate-to-source voltage (VDS);(f) determining thermal impedance (PT I AT) based on the power dissipation, estimated temperature, and calibration information;(g) extracting a temperature estimation of each transistor as a transistor junction temperature as a function of the measure on-resistance and the applied gate-to-source voltage (VDS); and(h) outputting information on transistor operation selected from the group of determinations consisting of power dissipation, on-resistance, thermal impedance, drain-to-source voltage, and source current.BK-2024-156-2-PCT -26-

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