Constructing reduced quantum logic circuits for processing in a quantum computing system

Abstract

In a general aspect, reduced quantum logic circuits are constructed for processing in a quantum computing system. In some cases, a method includes obtaining a quantum logic circuit defined over a plurality of qubits; determining a light cone for a respective qubit; and constructing a reduced quantum logic circuit for an observable based on the light cone. Determining the light cone includes defining a graph including the respective qubit, a first subset of the qubits between which and the respective qubit a first subset of multi-qubit quantum logic gates are applied, and a second subset of the qubits between at least one of which and at least one of the first subset of the qubits a second subset of multi-qubit quantum logic gates do not commute with at least one prior quantum logic gate are applied.

Description

Constructing Reduced Quantum Logic Circuits for Processing in a Quantum Computing SystemCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Application No. 63 / 631,643 filed on April 9, 2024, and entitled "Constructing Reduced Quantum Logic Circuits for Processing in a Quantum Computing System." The above-referenced priority application is hereby incorporated by reference.TECHNICAL FIELD

[0002] The following description relates generally to constructing reduced quantum logic circuits for processing in a quantum computing system.BACKGROUND

[0003] Quantum computers can perform computational tasks by storing and processing information within quantum states of quantum systems. For example, qubits (i.e., quantum bits) can be stored in, and represented by, an effective two-level sub-manifold of a quantum coherent physical system. A variety of physical systems have been proposed for quantum computing applications. Examples include superconducting circuits, trapped ions, spin systems, and others.GOVERNMENT SUPPORT

[0004] These inventions were made with Government support under agreement No. HR00112090058, awarded by DARPA. The Government has certain rights in the inventions.BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a block diagram of an example computing environment.

[0006] FIG. 2 is a flow chart showing aspects of an example computing process.

[0007] FIG. 3 is a flow chart showing aspects of an example process.

[0008] FIGS. 4A-4E include schematic diagrams of an example process performed on an example quantum logic circuit to determine a light cone and a reduced quantum logic circuit for a respective qubit.

[0009] FIGS. 5A-5B are schematic diagrams showing aspects of processes to construct a reduced quantum logic circuit for a respective observable involving multiple qubits.

[0010] FIG. 6 is a log-log plot showing the number of reduced quantum logic circuits for compute all pairs of a single observable <ZiZj> as a function of the size of a problem (e.g., number of variables in the problem) for solving a quantum relax-and-round algorithm with p circuit layers.DETAILED DESCRIPTION

[0011] In some aspects of what is described here, a computing process is used to construct reduced quantum logic circuit based on an initial quantum logic circuit and a set of observables associated with the initial quantum logic circuit. At least one reduced quantum logic circuit can be determined for each observable. In some instances, a reduced quantum logic circuit can be determined based on light cones of respective qubits involved in the observable. In some implementations, a light cone of a qubit q is defined as a set of qubits on which a reduced quantum logical circuit is applied. The reduced quantum logic circuit, when executed, can output any one-body observable on the qubit q. In some instances, a light cone of a target qubit can be determined according to the initial quantum logic circuit and a set of criteria. In some instances, instead of executing the initial quantum logic circuits to determine values of the respective observables, the reduced quantum logic circuits defined over a subset of the qubits can be executed to determine the values of the respective observables.

[0012] In some implementations, a light cone for a qubit can be determined by building a graph based on the initial quantum logic circuit. Qubits may be added to the graph based on analyzing the quantum logic gates in the quantum logic circuit. When all quantum logic gates in the quantum logic circuit have been processed, the light cone can be represented by the graph. In some cases, the light cone for a selected qubit in a quantum logic circuitcan be considered a connectivity map, indicating which qubits become entangled with the selected qubit when the quantum logic circuit is applied. For instance, the graph may include nodes that represent qubits and edges that represent connectivity between pairs of qubits (e.g., an edge may represent an entangling operation). The graph may be used to construct a reduced quantum logic circuit that can be used to determine the values of certain observables. For instance, the reduced quantum logic circuit may be executed by a quantum processor unit.

[0013] In some implementations, the methods and techniques presented here offer several advantages, including more efficient utilization of hardware resources, improved error mitigation, enhanced scalability, and increased modularity and reusability of quantum algorithms. By breaking down complex quantum logic circuits into smaller, more manageable parts, the methods and techniques presented here allow for the allocation of qubits and gates in a resource-efficient manner, reducing the overall resource requirements for executing quantum algorithms. In certain instances, the methods and techniques presented here can facilitate the application of error mitigation strategies to each sub-circuit independently, leading to lower error rates and improved reliability. In some instances, the methods and techniques presented here can address the challenges of solving complex quantum algorithms on current and near-term quantum hardware. In some cases, a combination of these and potentially other advantages and improvements may be obtained.

[0014] FIG. 1 is a block diagram of an example computing environment 100, according to an example embodiment. The example computing environment 100 shown in FIG. 1 includes a computing system 101 and user devices 110A, 110B, 110C. A computing environment may include additional or different features, and the components of a computing environment may operate as described with respect to FIG. 1 or in another manner.

[0015] The example computing system 101 includes classical and quantum computing resources and exposes their functionality to the user devices 110A, HOB, HOC (referred to collectively as “user devices 110"). The computing system 101 shown in FIG. 1 includes one or more servers 108, quantum computing systems 103A, 103B, a local network 109, andother resources 107. The computing system 101 may also include one or more user devices (e.g., the user device 110A) as well as other features and components. A computing system may include additional or different features, and the components of a computing system may operate as described with respect to FIG. 1 or in another manner.

[0016] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115, the local network 109, or otherwise).

[0017] The user devices 110 shown in FIG. 1 may include one or more classical processors, memory, user interfaces, communication interfaces, and other components. For instance, the user devices 110 may be implemented as laptop computers, desktop computers, smartphones, tablets, or other types of computer devices. In the example shown in FIG. 1, to access computing resources of the computing system 101, the user devices 110 send information (e.g., programs, instructions, commands, requests, input data, etc.) to the servers 108; and in response, the user devices 110 receive information (e.g., application data, output data, prompts, alerts, notifications, results, etc.) from the servers 108. The user devices 110 may access services of the computing system 101 in another manner, and the computing system 101 may expose computing resources in another manner.

[0018] In the example shown in FIG. 1, the local user device 110A operates in a local environment with the servers 108 and other elements of the computing system 101. For instance, the user device 110A may be co-located with (e.g., located within 0.5 to 1 km of) the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, the user device 110A communicates with the servers 108 through a local data connection.

[0019] The local data connection in FIG. 1 is provided by the local network 109. For example, some or all of the servers 108, the user device 110A, the quantum computing systems 103A, 103B, and the other resources 107 may communicate with each other through the local network 109. In some implementations, the local network 109 operates as a communication channel that provides one or more low-latency communication pathways from the server 108 to the quantum computing systems 103A, 103B (or to one or more of the elements of the quantum computing systems 103A, 103B). The local network 109 can be implemented, for instance, as a wired or wireless Local Area Network, an Ethernet connection, or another type of wired or wireless connection. The local network 109 may include one or more wired or wireless routers, wireless access points (WAPs), wireless mesh nodes, switches, high-speed cables, or a combination of these and other types of local network hardware elements. In some cases, the local network 109 includes a software-defined network that provides communication among virtual resources, for example, among an array of virtual machines operating on the server 108 and possibly elsewhere.

[0020] In the example shown in FIG. 1, the remote user devices HOB, HOC operate remotely from the servers 108 and other elements of the computing system 101. For instance, the user devices 110B, 110C may be located at a remote distance (e.g., more than 1 km, 10 km, 100 km, 1,000 km, 10,000 km, or farther) from the servers 108 and possibly other elements of the computing system 101. As shown in FIG. 1, each of the user devices HOB, HOC communicates with the servers 108 through a remote data connection.

[0021] The remote data connection in FIG. 1 is provided by a wide area network 115, which may include, for example, the Internet or another type of wide area communication network. In some cases, remote user devices use another type of remote data connection (e.g., satellite-based connections, a cellular network, a virtual private network, etc.) to access the servers 108. The wide area network 115 may include one or more internet servers, firewalls, service hubs, base stations, or a combination of these and other types of remote networking elements. Generally, the computing environment 100 can be accessible to any number of remote user devices.

[0022] The example servers 108 shown in FIG. 1 can manage interaction with the user devices 110 and utilization of the quantum and classical computing resources in the computing system 101. For example, based on information from the user devices 110, the servers 108 may delegate computational tasks to the quantum computing systems 103A, 103B and the other resources 107; the servers 108 can then send information to the user devices 110 based on output data from the computational tasks performed by the quantum computing systems 103A, 103B, and the other resources 107.

[0023] As shown in FIG. 1, the servers 108 are classical computing resources that include classical processors 111 and memory 112. The servers 108 may also include one or more communication interfaces that allow the servers to communicate via the local network 109, the wide area network 115, and possibly other channels. In some implementations, the servers 108 may include a host server, an application server, a virtual server, or a combination of these and other types of servers. The servers 108 may include additional or different features and may operate as described with respect to FIG. 1 or in another manner.

[0024] The classical processors 111 can include various kinds of apparatus, devices, and machines for processing data, including, by way of example, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or combinations of these. The memory 112 can include, for example, a random-access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storage medium. The memory 112 can include various forms of volatile or non-volatile memory, media, and memory devices, etc.

[0025] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum simulators, or both) as well as classical (non-quantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry(e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.

[0026] In some implementations, the servers 108 generate programs, identify appropriate computing resources (e.g., a QPU or QVM) in the computing system 101 to execute the programs, and send the programs to the identified resources for execution. For example, the servers 108 may send programs to the quantum computing system 103A, the quantum computing system 103B, or any of the other resources 107. The programs may include classical programs, quantum programs, hybrid classical / quantum programs, and may include any type of function, code, data, instruction set, etc.

[0027] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108, on the quantum computing systems 103, or elsewhere. In some instances, programs can be formatted as compiled code, such as, for example, binary code (e.g., machine-level instructions) that can be executed directly by a computing resource. Each program may include instructions corresponding to computational tasks that, when performed by an appropriate computing resource, generate output data based on input data. For example, a program can include instructions formatted for a quantum computer system, a simulator, a digital microprocessor, coprocessor or other classical data processing apparatus, or another type of computing resource.

[0028] In some cases, a program may be expressed in a hardware-independent format. For example, quantum machine instructions may be provided in a quantum instruction language such as Quil, described in the publication "A Practical Quantum Instruction Set Architecture," arXiv:1608.03355v2, dated Feb. 17, 2017, or another quantum instruction language. For instance, the quantum machine instructions may be written in a format that can be executed by a broad range of quantum processing units or simulators. In some cases, a program may be expressed in high-level terms of quantum logic gates or quantum algorithms, in lower-level terms of fundamental qubit rotations and controlled rotations, orin another form. In some cases, a program may be expressed in terms of control signals (e.g., pulse sequences, delays, etc.) and parameters for the control signals (e.g., frequencies, phases, durations, channels, etc.). In some cases, a program may be expressed in another form or format. In some cases, a program may utilize Quil-T, described in the publication "Gain deeper control of Rigetti quantum processing units with Quil-T," available at https: / / medium.com / rigetti / gain-deeper-control-of-rigetti-quantum-processors-with- quil-t-ea8945061e5b dated Dec. 10, 2020, which is hereby incorporated by reference in the present disclosure.

[0029] In some implementations, the servers 108 include one or more compilers that convert programs between formats. For example, the servers 108 may include a compiler that converts hardware-independent instructions to binary programs for execution by the quantum computing systems 103A, 103B. In some cases, a compiler can compile a program to a format that targets a specific quantum resource in the computer system 101. For example, a compiler may generate a different binary program (e.g., from the same source code) depending on whether the program is to be executed by the quantum computing system 103A or the quantum computing system 103B.

[0030] In some cases, a compiler generates a partial binary program that can be updated, for example, based on specific parameters. For instance, if a quantum program is to be executed iteratively on a quantum computing system with varying parameters on each iteration, the compiler may generate the binary program in a format that can be updated with specific parameter values at runtime (e.g., based on feedback from a prior iteration, or otherwise); the parametric update can be performed without further compilation. In some cases, a compiler generates a full binary program that does not need to be updated or otherwise modified for execution.

[0031] In some implementations, the servers 108 generate a schedule for executing programs (e.g., the processes 200, 300 shown in FIGS. 2 and 3), allocate computing resources in the computing system 101 according to the schedule, and delegate the programs to the allocated computing resources. The servers 108 can receive, from each computing resource, output data from the execution of each program. Based on the outputdata, the servers 108 may generate additional programs that are then added to the schedule, output data that is provided back to a user device 110, or perform another type of action.

[0032] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment. For example, quantum programs can be formatted as hybrid classical / quantum programs that include instructions for execution by one or more quantum computing resources (e.g., the quantum-based algorithms) and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment, and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs), one or more quantum virtual machines (QVMs), one or more quantum simulators, or possibly other types of quantum resources. The classical computing resources in the hybrid environment may include, for example, one or more digital microprocessors, one or more specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), or other types of computing modules.

[0033] In some cases, the servers 108 can select the type of computing resource (e.g., quantum or classical) to execute an individual program, or part of a program, in the computing system 101. For example, the servers 108 may select a particular quantum processing unit (QPU) or other computing resource based on availability of the resource, speed of the resource, information or state capacity of the resource, a performance metric (e.g., process fidelity) of the resource, or based on a combination of these and other factors. In some cases, the servers 108 can perform load balancing, resource testing and calibration, and other types of operations to improve or optimize computing performance.

[0034] Each of the example quantum computing systems 103A, 103B shown in FIG. 1 can perform quantum computational tasks by executing quantum machine instructions (e.g., a binary program compiled for the quantum computing system). In someimplementations, a quantum computing system can perform quantum computation by storing and manipulating information within quantum states of a composite quantum system. For example, qubits (i.e., quantum bits) can be stored in, and represented by, an effective two-level sub-manifold of a quantum coherent physical system. In some instances, quantum logic can be executed in a manner that allows large-scale entanglement within the quantum system. Control signals can manipulate the quantum states of individual qubits and the joint states of multiple qubits. In some instances, information can be read out from the composite quantum system by measuring the quantum states of the qubits. In some implementations, the quantum states of the qubits are read out by measuring the transmitted or reflected signal from auxiliary quantum devices that are coupled to individual qubits.

[0035] In some implementations, a quantum computing system can operate using gatebased models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation.

[0036] In some models, fault-tolerance can be achieved by applying a set of high-fidelity control and measurement operations to the qubits. For example, quantum error correcting codes can be deployed to achieve fault-tolerant quantum computation. Other computational regimes may be used; for example, quantum computing systems may operate in non-fault-tolerant regimes. In some implementations, a quantum computing system is constructed and operated according to a scalable quantum computing architecture. For example, in some cases, the architecture can be scaled to a large numberof qubits to achieve large-scale general purpose coherent quantum computing. Other architectures may be used; for example, quantum computing systems may operate in small- scale or non-scalable architectures.

[0037] The example quantum computing system 103A shown in FIG. 1 includes a quantum processing unit 102A and a control system 105A, which controls the operation of the quantum processing unit 102A. Similarly, the example quantum computing system 103B includes a quantum processing unit 102B and a control system 105B, which controls the operation of a quantum processing unit 102B. A quantum computing system may include additional or different features, and the components of a quantum computing system may operate as described with respect to FIG. 1 or in another manner.

[0038] In some instances, all or part of the quantum processing unit 102A functions as a quantum processing unit, a quantum memory, or another type of subsystem. In some examples, the quantum processing unit 102A includes a superconducting quantum circuit system. The superconducting quantum circuit may include data qubit devices, stabilizer qubit devices, coupler devices, readout devices, and possibly other devices that are used to store and process quantum information. In some cases, multiple data qubit devices are operatively coupled to a single stabilizer check qubit device through respective coupler devices. In some implementations, the quantum processing unit 102A is implemented utilizing aspects designed or generated from the components and processes shown in FIGS. 2-4, or in another manner. In certain examples, the qubit devices and the coupler devices are implemented as superconducting quantum circuit devices that include Josephson junctions, for example, in Superconducting QUantum Interference Device (SQUID) loops or other arrangements, and are controlled by radio-frequency signals, microwave signals, and bias signals delivered to the quantum processing unit 102A.

[0039] In some instances, the quantum processing modules can include a superconducting quantum circuit that includes one or more quantum circuit devices. For instance, a superconducting quantum circuit may include qubit devices, readout resonator devices, Josephson junctions, or other quantum circuit devices. In some implementations, quantum circuit devices in a quantum processing unit can be collectively operated to definea single logical qubit. A logical qubit includes a quantum register, for instance multiple physical qubits or qudits, and associated circuitry, that supports physical operations which can be used to detect or correct errors associated with logical states in a quantum algorithm. Physical operations supported by the quantum register associated with a logical qubit may include single-qubit or multi-qubit quantum logic gates and readout mechanisms. Error detection or correction mechanisms associated with a logical qubit may be based on quantum error correction schemes such as the surface code, color code, Bacon- Shor codes, low-density parity check codes (LDPC), some combination of these, or others.

[0040] The quantum processing unit 102A may include, or may be deployed within, a controlled environment. The controlled environment can be provided, for example, by shielding equipment, cryogenic equipment, and other types of environmental control systems. In some examples, the components in the quantum processing unit 102A operate in a cryogenic temperature regime and are subject to very low electromagnetic and thermal noise. For example, magnetic shielding can be used to shield the system components from stray magnetic fields, optical shielding can be used to shield the system components from optical noise, thermal shielding and cryogenic equipment can be used to maintain the system components at controlled temperature, etc.

[0041] In some implementations, the example quantum processing unit 102A can process quantum information by applying control signals to the qubits in the quantum processing unit 102A. The control signals can be configured to encode information in the qubits, to process the information by performing quantum logic gates or other types of operations, or to extract information from the qubits. In some examples, the operations can be expressed as single-qubit quantum logic gates, two-qubit quantum logic gates, or other types of quantum logic gates that operate on one or more qubits. A quantum logic circuit, which includes a sequence of quantum logic operations, can be applied to the qubits to perform a quantum algorithm. The quantum algorithm may correspond to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations.

[0042] The example control system 105A includes controllers 106A and signal hardware 104A. Similarly, control system 105B includes controllers 106B and signal hardware 104B. All or part of the control systems 105A, 105B can operate in a roomtemperature environment or another type of environment, which may be located near the respective quantum processing units 102A, 102B. In some cases, the control systems 105A, 105B include classical computers, signaling equipment (microwave, radio, optical, bias, etc.), electronic systems, vacuum control systems, refrigerant control systems, or other types of control systems that support operation of the quantum processing units 102A, 102B.

[0043] The control systems 105A, 105B may be implemented as distinct systems that operate independent of each other. In some cases, the control systems 105A, 105B may include one or more shared elements; for example, the control systems 105A, 105B may operate as a single control system that operates both quantum processing units 102A, 102B. Moreover, a single quantum computing system may include multiple quantum processing units, which may operate in the same controlled (e.g., cryogenic) environment or in separate environments.

[0044] The example signal hardware 104A includes components that communicate with the quantum processing unit 102A. The signal hardware 104A may include, for example, waveform generators, amplifiers, digitizers, high-frequency sources, DC sources, AC sources, etc. The signal hardware may include additional or different features and components. In the example shown, components of the signal hardware 104A are adapted to interact with the quantum processing unit 102A. For example, the signal hardware 104A can be configured to operate in a particular frequency range, configured to generate and process signals in a particular format, or the hardware may be adapted in another manner.

[0045] In some instances, one or more components of the signal hardware 104A generate control signals, for example, based on control information from the controllers 106A. The control signals can be delivered to the quantum processing unit 102A during operation of the quantum computing system 103A. For instance, the signal hardware 104A may generate signals to implement quantum logic operations, readout operations, or othertypes of operations. As an example, the signal hardware 104A may include arbitrary waveform generators (AWGs) that generate electromagnetic waveforms (e.g., microwave or radio-frequency) or laser systems that generate optical waveforms. The waveforms or other types of signals generated by the signal hardware 104A can be delivered to devices in the quantum processing unit 102A to operate qubit devices, readout devices, bias devices, coupler devices, or other types of components in the quantum processing unit 102A.

[0046] In some instances, the signal hardware 104A receives and processes signals from the quantum processing unit 102A. The received signals can be generated by the execution of a quantum program on the quantum computing system 103A. For instance, the signal hardware 104A may receive signals from the devices in the quantum processing unit 102A in response to readout or other operations performed by the quantum processing unit 102A. Signals received from the quantum processing unit 102A can be mixed, digitized, filtered, or otherwise processed by the signal hardware 104A to extract information, and the information extracted can be provided to the controllers 106A or handled in another manner. In some examples, the signal hardware 104A may include a digitizer that digitizes electromagnetic waveforms (e.g., microwave or radiofrequency) or optical signals, and a digitized waveform can be delivered to the controllers 106A or to other signal hardware components. In some instances, the controllers 106A process the information from the signal hardware 104A and provide feedback to the signal hardware 104A; based on the feedback, the signal hardware 104A can in turn generate new control signals that are delivered to the quantum processing unit 102A.

[0047] In some implementations, the signal hardware 104A includes signal delivery hardware that interfaces with the quantum processing unit 102A. For example, the signal hardware 104A may include filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers, and other types of components. In some instances, the signal delivery hardware performs preprocessing, signal conditioning, or other operations to the control signals to be delivered to the quantum processing unit 102A. In some instances, signal delivery hardware performs preprocessing, signal conditioning, or other operations on readout signals received from the quantum processing unit 102A.

[0048] The example controllers 106A communicate with the signal hardware 104A to control the operation of the quantum computing system 103A. The controllers 106A may include classical computing hardware that directly interfaces with components of the signal hardware 104A. The example controllers 106A may include classical processors, memory, clocks, digital circuitry, analog circuitry, and other types of systems or subsystems. The classical processors may include one or more single- or multi-core microprocessors, digital electronic controllers, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit), or other types of data processing apparatus. The memory may include any type of volatile or non-volatile memory or another type of computer storage medium. The controllers 106A may also include one or more communication interfaces that allow the controllers 106A to communicate via the local network 109 and possibly other channels. The controllers 106A may include additional or different features and components.

[0049] In some implementations, the controllers 106A include memory or other components that store quantum state information, for example, based on qubit readout operations performed by the quantum computing system 103A. For instance, the states of one or more qubits in the quantum processing unit 102A can be measured by qubit readout operations, and the measured state information can be stored in a cache or other type of memory system in one or more of the controllers 106A. In some cases, the measured state information is subsequently used in the execution of a quantum program, a quantum error correction procedure, a quantum processing unit (QPU) calibration or testing procedure, or another type of quantum process.

[0050] In some implementations, the controllers 106A include memory or other components that store a quantum program containing quantum machine instructions for execution by the quantum computing system 103A. In some instances, the controllers 106A can interpret the quantum machine instructions and perform hardware-specific control operations according to the quantum machine instructions. For example, the controllers 106A may cause the signal hardware 104A to generate control signals that are delivered to the quantum processing unit 102A to execute the quantum machine instructions.

[0051] In some instances, the controllers 106A extract qubit state information from qubit readout signals, for example, to identify the quantum states of qubits in the quantum processing unit 102A or for other purposes. For example, the controllers may receive the qubit readout signals (e.g., in the form of analog waveforms) from the signal hardware 104A, digitize the qubit readout signals, and extract qubit state information from the digitized signals. In some cases, the controllers 106A compute measurement statistics based on qubit state information from multiple shots of a quantum program. For example, each shot may produce a bitstring representing qubit state measurements for a single execution of the quantum program, and a collection of bitstrings from multiple shots may be analyzed to compute quantum state probabilities.

[0052] In some implementations, the controllers 106A include one or more clocks that control the timing of operations. For example, operations performed by the controllers 106A may be scheduled for execution over a series of clock cycles, and clock signals from one or more clocks can be used to control the relative timing of each operation or groups of operations. In some implementations, the controllers 106A may include classical computer resources that perform some or all of the operations of the servers 108 described above. For example, the controllers 106A may operate a compiler to generate binary programs (e.g., full or partial binary programs) from source code; the controllers 106A may include an optimizer that performs classical computational tasks of a hybrid classical / quantum program; the controllers 106A may update binary programs (e.g., at runtime) to include new parameters based on an output of the optimizer, etc.

[0053] The other quantum computing system 103B and its components (e.g., the quantum processing unit 102B, the signal hardware 104B, and controllers 106B) can be implemented as described above with respect to the quantum computing system 103A; in some cases, the quantum computing system 103B and its components may be implemented or may operate in another manner.

[0054] In some implementations, the quantum computing systems 103A, 103B are disparate systems that provide distinct modalities of quantum computation. For example, the computer system 101 may include both an adiabatic quantum computing system and agate-based quantum computer system. As another example, the computer system 101 may include a superconducting circuit-based quantum computing system and an ion trap-based quantum computer system. In such cases, the computer system 101 may utilize each quantum computing system according to the type of quantum program that is being executed, according to availability or capacity, or based on other considerations.

[0055] In some instances, one or more components of the computing system 101 shown in FIG. 1 are configured to perform the operations of the example processes 200, 300, 400 in FIGS. 2, 3, 4A-4E, or another process. For example, as is discussed in greater detail below, a classical computing system (e.g., the classical processors 111 in the servers 108) can be configured to receive an initial quantum logic circuit and observables associated with the initial quantum logic circuit; determine light cones shown in FIG. 4D for qubits involved in the respective observables associated with the initial quantum logic circuit shown in FIG. 4A; and construct reduced quantum logic circuits for the respective observables based on the light cones. In some instances, the quantum processing unit can be configured to execute the reduced quantum logic circuits to obtain measured values of the respective observables. In some examples, the classical processing unit of the control system 105A or the servers 108 may be used to perform a quantum simulation by executing the reduced quantum logic circuits to obtain simulated values of the respective observables. In some instances, the components of the computing system 101 may be configured to perform other operations.

[0056] FIG. 2 is a flow chart showing aspects of an example computing process 200. In some instances, the example process 200 can be used to decompose a quantum logic circuit associated with a quantum algorithm into reduced quantum logic circuits according to a list of observables as desired output of the quantum logic circuit. In some instances, the computing process 200 may be performed by operation of one or more classical processing units in a computing system (e.g., the user devices or the classical processors 111 of the servers 108 in the computing system 101). The example process 200 may include additional or different operations, and the operations may be performed in the order shown or in another order. In some cases, operations in the example process 200 can be combined, iterated or otherwise repeated, or performed in another manner.

[0057] In some implementations, the method is agnostic to the hardware. In other words, the computing process 200 maybe used to construct reduced quantum logic circuits that can be executed on quantum processing units based on superconducting qubits, trapped ions, cold atoms, or other quantum processing units. The computing process 200 may be used to construct reduced quantum logic circuits that can be simulated on a quantum simulator or in another manner. In some implementations, the computing process 200 can construct reduced quantum logic circuits based on a quantum algorithm received, which may include a quantum logic circuit and associated observables that are considered as desired output of the quantum algorithm. In some instances, the computing process 200 can construct at least one reduced quantum logic circuit for each observable in the quantum logic circuit.

[0058] At 202, a quantum logic circuit defined over a plurality of qubits is obtained. In some implementations, the quantum logic circuit may be obtained from a quantum algorithm to be executed. In some instances, the quantum algorithm may be a quantum approximation optimization algorithm (QAOA), a quantum machine learning algorithm, a quantum relax-and-round algorithm, or another type of quantum algorithm that does not include desired output as a single bit string. In some instances, the quantum logic circuit may represent the quantum algorithm corresponding to a computational task, a hardware test, a quantum error correction procedure, a quantum state distillation procedure, or a combination of these and other types of operations. The quantum algorithm may be used to solve an optimization problem.

[0059] In some implementations, the quantum logic circuit includes a first sequence of quantum logic gates defined over the plurality of qubits, e.g., single-qubit quantum logic gates, multi-qubit quantum logic gates defined over two or more qubits, identity gates, and other quantum logic gates. In some instances, the first sequence may include one or more parametric quantum logic gates, e.g., a parametric single-qubit quantum logic gate, a parametric two-qubit quantum logic gate, or another parametric multi-qubit quantum logic gate. In some instances, the first sequence may include one or more non-parametric quantum logic gates. In some implementations, the quantum program may be a sourcecode quantum program, rather than a binary program that can be directly implemented ona quantum processing unit. In some instances, the quantum program can be a high-level program (e.g., a Quil program or a program in another high-level quantum programming language) received by a quantum computing system (e.g., the control system 105 of the quantum computing system 103 in FIG. 1) from a user device (e.g., the user device 110 as shown in FIG. 1), from another computer resource outside the local environment of the quantum computer system 103, or from another source.

[0060] In some implementations, a qubit device has two eigenstates that are used as computational basis states (e.g., |0) and |1)), and each qubit device can transition between its computational basis states or exist in an arbitrary superposition of its computational basis states. In some examples, the two lowest energy levels (e.g., the ground state and first excited state) of a qubit device are defined as a qubit and used as computational basis states for quantum computation. In some examples, higher energy levels (e.g., a second excited state or a third excited state) can be used to define a qubit, a qutrit, or a multi-level quantum computational device in some instances. Quantum states (e.g., qubits) of a qubit device can be manipulated by control signals.

[0061] At 204, the observables associated with the quantum logic circuit are obtained. In some instances, the observables are desired output from execution of the quantum logic circuit. For example, the observables associated with a quantum logic circuit in a quantum algorithm may be received with the quantum algorithm or in another manner. In some instances, the obtained observables may have a general form of [<AiBj...Mk>, ...], where <AiBj...Mk> represents an observable, and Ai, Bj, ..., MR represent single-qubit operators on qubits i, j, and k, respectively. For example, A, B, ..., M may be Pauli operators like Z, Y, X, or another type of single-qubit operator. In this case, the qubits i,j, .... and k are involved in determining the observable <AiBj...Mk>.

[0062] At 206, light cones for the plurality of qubits are determined. In some implementations, a light cone represents a connectivity map showing a mapping of entanglement between a selected qubit and other qubits that are directly or indirectly entangled with the selected qubit according to the quantum logic circuit. In some implementations, a light cone of a qubit q is defined as a set of qubits on which a reducedquantum logical circuit is applied. The reduced quantum logic circuit, when executed, determines any one-body observable on the qubit q. In some instances, a light cone can be represented by a graph. In some instances, a light cone may be described in another manner.

[0063] In some implementations, determining a light cone for a qubit includes determining whether quantum logic gates in a quantum logic circuit commute with each other. For example, each two-qubit quantum logic gate can be analyzed to determine whether it commutes with one or more previous two-qubit quantum logic gates. Qubits may then be added to the graph based on whether the quantum logic gates commute with each other. If two quantum logic gates commute with each other, they are logically equivalent when applied in either order; for example, if two quantum logic gates A and B commute, then their combined action is logically equivalent regardless of whether A is applied before or after B (i.e., AB is logically equivalent to BA). In some cases, whether two quantum logic gates commute can be determined based on their commutator [A,B], For example, quantum logic gates A and B commute with each other when their commutator [A,B] is zero, and quantum logic gates A and B do not commute with each other when their commutator [A,B] is non-zero. The commutator of two quantum logic gates can be defined, for example, as [A,B] = A*B-B*A, where * represents matrix multiplication. Accordingly, in some cases, determining whether quantum logic gates commute may include determining their commutator and comparing it to zero. In some cases, a commutator can be computed exactly, or a commutator can be estimated, and an absolute value less than a small threshold may be considered zero. In some cases, a database or other resources may be used to determine whether quantum logic gates commute with each other.

[0064] In some implementations, a light cone for a respective qubit can be determined by preprocessing the quantum logic circuit. A graph can be determined according to the preprocessed quantum logic circuit by reading the preprocessed quantum logic circuit from the start to the end. In some instances, a light cone for a respective qubit involved in an observable can be determined by performing operations in the example process 300, 400 shown in FIGS. 3, 4A-4D, or in another manner.

[0065] In some instances, preprocessing of an initial quantum logic circuit may include removing single-qubit quantum logic gates applied on respective single qubits at the beginning of the quantum logic circuit; and removing single-qubit quantum logic gates applied on respective single qubits at the end of the quantum logic circuit. As shown in the operation 410 of the example process 400, the quantum logic circuit 406 defined over a set of qubits 408 includes a first set of single-qubit quantum logic gates 402A, a first set of two- qubit quantum logic gates 404A, a second set of two-qubit quantum logic gates 404B, a second set of single-qubit quantum logic gates 402 B, a third set of two-qubit quantum logic gates 404C, a fourth set of two-qubit quantum logic gates 404D, and a third set of singlequbit quantum logic gates 402C. As shown in FIG. 4A, the first set of single-qubit quantum logic gates 402A reside at the beginning of the quantum logic circuit 406; and the third set of single-qubit quantum logic gates 402C reside at the end of the quantum logic circuit 406. Once the first set of single-qubit quantum logic gates 402A are determined as located at the beginning of the quantum logic circuit 406, the first set of single-qubit quantum logic gates 402A can be removed from the quantum logic circuit 406 during sub-operation 422A. Similarly, once the third set of single-qubit quantum logic gates 402C are determined as located at the end of the quantum logic circuit 406, the third set of single-qubit quantum logic gates 402C can be removed from the quantum logic circuit 406 during sub-operation 422B.

[0066] In some instances, preprocessing of an initial quantum logic circuit may include reorganizing intermediate quantum logic gates. Referring to the example process 400 shown in FIGS. 4A-4D, intermediate single-qubit quantum logic gates which include the second set of single-qubit quantum logic gates 402B and the third set of two-qubit quantum logic gates 404C can be combined to form a new set of unitary operations during suboperation 422C. In some instances, reorganizing the intermediate quantum logic gates may include compiling multi-qubit quantum logic gates that are applied on three or more qubits into a sequence of single- or two-qubit quantum logic gates. In some instances, preprocessing of an initial quantum logic circuit may include other types of operations.

[0067] In some instances, after the initial quantum logic circuit is pre-processed, a graph can be defined. For example, the graph can be defined based on the operations theexample process 300, the sub-operations 432A, 432B, 432C of the operation 430 in the example process 400, or in another manner.

[0068] FIG. 3 is a flow chart describing aspects of an example process 300. The example process 300 can be used to determine a light cone for a qubit based on an initial quantum logic circuit and observables associated with the initial quantum logic circuit. The quantum logic circuit may represent a quantum algorithm, e.g., a quantum approximation optimization algorithm, a quantum relax-and-round algorithm, a quantum machine learning algorithm, or another quantum algorithm.

[0069] At 302, an initial quantum logic circuit is preprocessed. In some instances, the preprocessing of the initial quantum logic circuit may be implemented as the suboperations 422A, 422B, 422C in the operation 420 of the example process 400 or in another manner.

[0070] At 304, a qubit q is selected. In some implementations, a qubit q is one of the qubits where the initial quantum logic circuit is defined over; and is one of the qubits that is involved in an observable associated with the initial quantum logic circuit. As shown in the example process 400, qubit 5 may be selected; and a corresponding light cone for qubit 5 can be determined. At the beginning of the process 300, the graph representing the light cone of the qubit q initially includes only one qubit, e.g., qubit q. As the process 300 proceeds, additional qubits are added to the graph, along with connections to other qubits in the graph. Accordingly, qubits may be represented by nodes in the graph, and connections between qubits may be represented by edges.

[0071] At 306, the preprocessed quantum logic circuit is read from its beginning. In some instances, the beginning of the preprocessed quantum logic circuit is when a first quantum logic operation is performed. Using the quantum logic circuit 406 in the example process 400 as an example, after preprocessing, the second set of two-qubit quantum logic gates 404A of the quantum logic circuit 406 are performed at the beginning of the quantum logic circuit. In other words, the quantum logic operations at the beginning of the quantum logic circuit are performed first relative to other quantum logic operations in the quantum logic circuit. In some implementations, the preprocessed quantum logic circuit is read fromthe beginning to the end (e.g., typically from left to right) to determine a light cone of a qubit.

[0072] At 308, a two-qubit quantum logic gate is encountered during the reading of the preprocessed quantum logic circuit. The two-qubit quantum logic gate is applied on qubits i and j. In some instances, a two-qubit quantum logic gate may include a XV gate, a Rxx gate, a Rzz gate, a controlled NOT (CNOT) gate, a SWAP gate, a controlled-Z (CZ) gate, a Controlled-phase (CPhase) gate, or another type of two-qubit quantum logic gates creating entanglement between the qubits i and j over which the two-qubit quantum logic gate is defined.

[0073] At 310, whether qubit i is the same qubit q is determined. Based on a determination that i + q, the example process 300 continues with operation 312. At 312, whether the qubit i is already in the current graph is determined. In response to a determination that qubit i is not in the current graph (in other words, the encountered two-qubit quantum logic gate is not applied on qubits that are included in the current graph), the example process 300 continues with operation 314. At 314, the encountered two-qubit quantum logic gate is removed from the preprocessed quantum logic circuit. Using the example quantum logic circuit 406 shown in the example process 400, at ti, the current graph associated with qubit 5 only includes qubit 5. During sub-operation 432A of the operation 430 shown in FIG. 4C, all Rzz gates that are applied to qubits 1 / 2, 3 / 4, and 7 / 8 at t2 are removed from the quantum logic circuit 406.

[0074] The example process 300 continues with operation 322. At 322, it is determined whether the end of the preprocessed quantum logic circuit has been reached. In response to a determination that the end of the quantum logic circuit has not been reached, the example process 300 continues with operation 306, and reading of the preprocessed quantum logic circuit continues.

[0075] At 312, in response to a determination that qubit i is already in the current graph, the example process 300 continues with operation 316. At 316, it is determined whether the encountered two-qubit quantum logic gate commutes with all previous quantum logic gates applied on the qubit i in the current graph. In some implementations,when two quantum logic gates A and B are defined in the Hilbert space of N qubits, the quantum logic gates A and B commute if their commutator is zero (i.e., if [A,B]=A*B-B*A=0, where * denotes matrix-matrix multiplication). Based on a determination that the encountered two-qubit quantum logic gate commutes with each of the previous quantum logic gates applied on qubit i, the example process continues with operation 318. At 318, the encountered two-qubit quantum logic gate is removed from the preprocessed quantum logic circuit. Using the example quantum logic circuit 406 shown in FIG. 4C as an example, during the sub-operation 432B, the Rzz gate applied on qubits 6 / 7 is removed since it commutes with the previous Rzz gate applied on qubits 5 / 6.

[0076] In response to a determination that the encountered two-qubit quantum logic gate does not commute with each of the previous quantum logic gates applied on qubit i during operation 316, the example process 300 continues with operation 320. At 320, qubit i is added to the graph, and the encountered two-qubit quantum logic gate is kept in the preprocessed quantum logic circuit. Using the example quantum logic circuit 406 shown in FIG. 4G as an example, during the sub-operation 432C, the unitary operation applied on the qubits 3 / 4 is kept in the quantum logic circuit because it does not commute with the previous Rzz gates applied on qubits 4 / 5. The example process 300 continues with operation 322.

[0077] When the qubit i is added to the graph, the graph is augmented to include qubit i. The graph may be augmented by adding a node to represent qubit i, and adding edges that connect the node to other existing nodes in the graph. In some cases, when qubit i is added to the graph, a connection between qubits i and j is also added based on the encountered two-qubit quantum logic gate applied to the qubits i and j in the quantum logic circuit.

[0078] During operation 310, based on a determination that the qubit i is the selected qubit q (e.g., i = q), the example process 300 continues with operation 330. At 330, whether the qubit j is included in the current graph is determined. At 334, in response to a determination that the qubit j is not included in the current graph, the graph is updated by adding the qubit j to the graph; and the encountered two-qubit quantum logic gate is keptin the preprocessed quantum logic circuit. Using the example quantum logic circuit 406 shown in FIG. 40, during the sub-operation 432B, the Rzz gate applied to the qubits 4 / 5 is kept in the quantum logic circuit; and the graph is updated by adding the qubit 4 into the graph. At this point, the graph includes qubits 4, 5, 6. The example process 400 continues with operation 322.

[0079] At 332, in response to a determination that qubit j is already included in the current graph, the encountered two-qubit quantum logic gate is kept in the quantum logic circuit. When the qubit j is added to the graph, the graph is augmented to include qubit j. The graph may be augmented by adding a node to represent qubit j, and adding edges that connect the node to other existing nodes in the graph. Using the example quantum logic circuit 406 shown in FIG. 40, during the sub-operation 432C, the unitary operation applied to the qubits 5 / 6 is kept in the preprocessed quantum logic circuit, because the graph at t4 includes qubits 4, 5, 6. For another example, during the sub-operation 432D, the Rzz gate applied on the qubits 4 / 5 is kept in the preprocessed quantum logic circuit since the qubits 4 and 5 are both in the current graph at the time te. The example process 400 continues with operation 322.

[0080] At 322, in response to a determination that all the quantum logic gates in the preprocessed quantum logic circuit have been considered, the example process 300 can be terminated. In some instances, other types of processes may be performed after the example process 300 is terminated. Using the example process shown in FIGS. 4A-4B, at the end of the operation 430, the graph has been completely updated. An example light cone 442 by the end of the operation 430 associated with the qubit 5 is shown in FIG. 40. The updated graph by the end of the operation 430 includes qubits 2, 3, 4, 5, 6, and 7, e.g., a subset of the qubits over which the initial quantum logic circuit is applied.

[0081] In some instances, the example process 300 may be repeated for other qubits involved in other observables until light cones are constructed for all respective qubits on which the initial quantum logic circuit is defined over. Once the light cones for all the respective qubits are determined, the reduced quantum logic circuits for respective observables may be constructed. In some implementations, constructing a reducedquantum logic circuit for a respective observable defined over two or more qubits includes determining whether the light cones of the two or more qubits have any overlapping qubits.

[0082] At 208, reduced quantum logic circuits for the respective observables are constructed. In some implementations, a reduced quantum logic circuit is based on a light cone. In some instances, the light cone can be a light cone for a respective qubit, or a light cone for two or more respective qubits by combing two or more respective light cones of the two or more respective qubits. In some instances, the operation 208 may include other operations.

[0083] Referring back to the example process 400 shown in FIGS. 4A-4E, after the light cone 442 for qubit 5 is determined by the end of the operation 430, a reduced quantum logic circuit 450 defined over the qubits included in the light cone 442 is constructed. As shown in FIG. 4D, the qubits included in the light cone 442 are just a subset of the qubits over which the initial quantum logic circuit is defined, e.g., without qubits 1 and 8. In some implementations, a reduced quantum logic circuit is constructed by including all the quantum logic gates in the initial quantum logic circuit that are only applied on the qubits included in the light cone 442. As shown in FIG. 4E, the reduced quantum logic circuit 450 includes all the single-qubit quantum logic gates in the first, second, and third sets of single-qubit quantum logic gates, all the two-qubit quantum logic gates in the first, second, third, and fourth sets of two-qubit quantum logic gates that are applied on the qubits 2, 3, 4, 5, 6, and 7 as defined by the light cone 442 shown in FIG. 4D.

[0084] FIGS. 5A-5B are schematic diagrams showing aspects of processes 500, 530 to construct a reduced quantum logic circuit. As shown in FIG. 5A, a first light cone 502 associated with qubit 512 includes qubits 512, 514, 516, 518; and a second light cone 504 associated with qubit 514 includes qubits 512, 514, 518, 520. Since the first and second light cones 502, 504 share three qubits 512, 514, 518, when a two-body observable defined over the qubits 512, 514 is one of the output from executing the quantum logic circuit, a reduced quantum logic circuit for the respective two-body observable can be constructed based on a combined light cone 506 of the first and second light cones 502, 504.

[0085] FIG. 5B shows three light cones, e.g., a first light cone 532 associated with qubit i, a second light cone 534 associated with qubit j; and a third light cone 536 associated with qubit k. Similar to the qubit sharing light cones 502, 504 shown in FIG. 5A, the first and second light cones 532, 534 share at least one qubit. In this case, when constructing a reduced quantum logic circuit for a two-body observable defined over qubits i and j, the first and second light cones 532, 534 can be combined. As shown in FIG. 5B, the third light cone 536 does not share any qubits with the first or second light cones 532, 534. In this case, constructing the reduced quantum logic circuit for a two-body observable defined over qubits i and k or qubits j and k includes constructing a reduced quantum logic circuit for each qubit involved in the two-body observable. In other words, two reduced quantum logic circuits for an observable that involves two qubits which do not have overlapping light cones can be constructed. Each of the two reduced quantum logic circuits are executed; and the values of the single-body observables may be multiplied to obtain the value of the two-body observable.

[0086] In some instances, constructing a reduced quantum logic circuit for a three-body observable defined over qubits i,j, and k includes constructing a first reduced quantum logic circuit based on combined first and second light cones 532, 534 and a second reduced quantum logic circuit based on the third light cone 536. The value of the three-body observable is a multiplication of values of the two-body observable from execution of the first reduced quantum logic circuit and the value of the single-body observable from execution of the second reduced quantum logic circuit. Using the observable in the form of <AiBj...Mk> as an example, when the qubits i,j, .... k overlap with one another, light cones for the qubits i,j, .... k can be combined into a new light cone; and a single reduced quantum logic circuit for the observable can be constructed. When the light cone for qubit k does not overlap with any other light cones of any other qubits i, j, ..., two reduced quantum logic circuits can be constructed based on a first light cone which is a combination of the light cones for the qubits i, j , ... and a second light cone which is the light cone for the qubit k. The original observable <AiBj...Mk> can be rewritten in a form of <Ai,Bj...xMk>. The value of the observable <Ai,Bj...> can be determined from the execution of the first reduced quantum logic circuit on the qubits i,j, ...; and the value of the observable <Mk>can be determined from the execution of the second reduced quantum logic circuit on the qubit k. In some implementations, the number of reduced quantum logic circuits for an observable is determined by the light cones of the qubits in respective observables.

[0087] At 210, the reduced quantum logic circuits for the respective observables are returned for execution. In some instances, the reduced quantum logic circuits for the respective observables are returned to the user device. In certain example, the reduced quantum logic circuits may be supplied to a quantum computing system for execution by a quantum processing unit and / or a classical processing unit (e.g., the quantum processing unit 102A and the classical processing unit of the control system 105A in the quantum computing system 103A as shown in FIG. 1) or in another manner. For example, the reduced quantum logic circuits can be executed by a quantum processing unit to determine measured values of the respective observables. For another example, the reduced quantum logic circuits may be simulated on a quantum simulator to determine values of the respective observables.

[0088] FIG. 6 is a plot 600 showing the number of reduced quantum logic circuits to run to compute all pairs of an observable (Z(Zy j in log scale as a function of the size of a problem (e.g., number of variables in the problem) in log scale for solving a quantum relax - and-round algorithm with p circuit layers. Becausethe total number of observables (Z^Zy) for all possible pairs (i',j) where i,j = 1, 2, . . ., N for N qubits is N • (N — 1) / 2, e.g., ~0( / V2) observables. The total number of circuits that is required to run all possible observables is defined by the number of observables, ~0( / V2). The number of circuits as a function of the number of qubits in this plot is represented by a straight line 602.

[0089] As shown in FIG. 6, the total number ~O(1V2) of observables includes one or more pairs of qubits (e.g., qubits i and k or qubits j and k as shown in FIG. 5B) that do not have overlapping light cones. In this case,0. For a problem with N qubits, the total number of observables that are not trivially zero is ~O( / V). In other words, the total number of circuits that is required to run all possible observables, which is ~ 0( / V2) circuits can be reduced to just ~0(iV) to compute nonzero observables (Z,Zk / Theseare labeled as "smart" represented by curves 604. The number of reduced quantum logic circuits needed to be executed for solving a quantum relax-and-round algorithm with a single circuit layer (p= 1) is represented by curve 612. The number of reduced quantum logic circuits needed to be executed for solving a quantum relax-and-round algorithm with two circuit layers (p =2) is represented by curve 614. The number of reduced quantum logic circuits need to be executed for solving a quantum relax-and-round algorithm with three circuit layers (p=3) is represented by curve 626.

[0090] Within the 0(A) observables that are not trivially zero a graph representing the light cone of the qubits i and k can be identical to a graph representing the light cones of at least one other pair of qubits, e.g. m and n. As such, (ZiZk) = (ZmZn). When N is large, the number of reduced quantum logic circuits required to run all the unique observables can be further reduced to —0(1). These are labeled as “smarter" represented by curves 606. As shown in FIG. 6, when a problem includes 1000 variables, instead of using a quantum logic circuit with A=1000 qubits for solving the problem, the number of reduced quantum logic circuits needed to be executed is 10 for solving a quantum relax-and-round algorithm with a single circuit layer (p=l, curve 622), 100 for solving a quantum relax-and-round algorithm with two circuit layers (p=2, curve 624), and 1000 for solving a quantum relax- and-round algorithm with three circuit layers (p=3, curve 626). In some implementations, the number of qubits in the reduced quantum logic circuits at different number of circuit layers in the quantum relax-and-round algorithm for solving a problem with 1000 variables are 7 atp=l, 19 atp=2; and 43 at p=3. In some implementations, the number of qubits needed in execution of a reduced quantum logic circuit is much less than the 1,000s of qubits needed for the initial problem.

[0091] Some of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Some of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, data-processing apparatus. Acomputer storage medium can be, or can be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Moreover, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially generated propagated signal. The computer storage medium can also be, or be included in, one or more separate physical components or media.

[0092] Some of the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0093] In a general aspect, reduced quantum logic circuits are constructed for processing in a quantum computing system.

[0094] In a first example, a computing method includes obtaining a quantum logic circuit defined over a plurality of qubits; determining a light cone for a respective qubit of the plurality of qubits, constructing a reduced quantum logic circuit for an observable based on the light cone. The light cone is determined by operations including defining a graph which includes the respective qubit; identifying a first subset of multi-qubit quantum logic gates applied to the respective qubit and a first subset of the qubits in the quantum logic circuit; adding the first subset of the qubits to the graph; identifying a second subset of multi-qubit quantum logic gates applied to at least one of the first subset of the qubits and at least one of a second subset of the qubits in the quantum logic circuit; and based on a determination that the second subset of multi-qubit quantum logic gates do not commute with at least one prior quantum logic gate in the quantum logic circuit, adding the second subset of the qubits to the graph

[0095] Implementations of the first example may include one or more of the following features. The quantum logic circuit corresponds to a quantum approximate optimization algorithm (QAOA) executed by a quantum processing unit and a classical processing unit. The quantum logic circuit corresponds to a quantum relax-and-round algorithm executed by a quantum processing unit and a classical processing unit. The quantum logic circuitcorresponds to a quantum machine learning algorithm executed by a quantum processing unit and a classical processing unit.

[0096] Implementations of the first example may include one or more of the following features. The quantum logic circuit includes single-qubit quantum logic gates and multiqubit quantum logic gates, and the light cone for the respective qubit is determined by operations including based on a determination that a first subset of the single-qubit quantum logic gates reside at the beginning of the quantum logic circuit, removing the first subset of the single-qubit quantum logic gates from the quantum logic circuit; and based on a determination that a second subset of the single-qubit quantum logic gates reside at the end of the quantum logic circuit, removing the second subset of the single-qubit quantum logic gates from the quantum logic circuit.

[0097] Implementations of the first example may include one or more of the following features. The light cone for each respective qubit is determined by operations including combining quantum logic gates in the quantum logic circuit. The light cone for each respective qubit is determined by operations including based on a determination that a third subset of the multi-qubit quantum logic gates are not applied to the respective qubit, removing the third subset of the multi-qubit quantum logic gate from the quantum logic circuit. The light cone for each respective qubit is determined by operations including based on a determination that a third subset of the multi-qubit quantum logic gates are not applied to the respective qubit, removing the third subset of the multi-qubit quantum logic gate from the quantum logic circuit. The light cone for each respective qubit is determined by operations including based on a determination that a third subset of the multi-qubit quantum logic gates are not applied to the respective qubit or to the first subset of the qubits, removing the third subset of the multi-qubit quantum logic gates from the quantum logic circuit. Constructing the reduced quantum logic circuit for an observable includes identifying, in the quantum logic circuit, a subset of quantum logic gates that are applied to qubits in the light cones identified for the subset of the qubits over which the observable is defined.

[0098] Implementations of the first example may include one or more of the following features. The observables include a two-body observable defined over a first qubit and a second qubit, and constructing a reduced quantum logic circuit for the two-body observable includes constructing a first reduced quantum logic circuit for qubits in the light cone identified for the first qubit; constructing a second reduced quantum logic circuit for qubits in the light cone identified for the second qubit; and combining the first and second reduced quantum logic circuits. Constructing the reduced quantum logic circuit for an observable based on the light cone includes excluding at least one quantum logic gate from the quantum logic circuit for the observable based on the light cone. The method includes returning the reduced quantum logic circuit for execution by a quantum computing resource. The method includes executing the reduced quantum logic circuits to determine values of the observables. The method includes obtaining observables associated with the quantum logic circuit, each of the observables being defined over a respective subset of the plurality of qubits; and determining a reduced quantum logic circuit for each of the observables.

[0099] In a second example, a computer system includes a classical processing unit and memory storing instructions that are operable, when executed by the classical processing unit to perform operations in the first example.

[0100] While this specification contains many details, these should not be understood as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples. Certain features that are described in this specification or shown in the drawings in the context of separate implementations can also be combined. Conversely, various features that are described or shown in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination.

[0101] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallelprocessing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single product or packaged into multiple products.

[0102] A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

CLAIMSWhat is claimed is:

1. A computing method comprising: obtaining a quantum logic circuit defined over a plurality of qubits; determining a light cone for a respective qubit of the plurality of qubits, the light cone being determined by operations comprising: defining a graph comprising the respective qubit; identifying a first subset of multi-qubit quantum logic gates applied to the respective qubit and a first subset of the qubits in the quantum logic circuit; adding the first subset of the qubits to the graph; identifying a second subset of multi-qubit quantum logic gates applied to at least one of the first subset of the qubits and at least one of a second subset of the qubits in the quantum logic circuit; and based on a determination that the second subset of multi-qubit quantum logic gates do not commute with at least one prior quantum logic gate in the quantum logic circuit, adding the second subset of the qubits to the graph; and constructing a reduced quantum logic circuit for an observable based on the light cone.

2. The method of claim 1, wherein the quantum logic circuit comprises single-qubit quantum logic gates and the multi-qubit quantum logic gates, and the light cone for the respective qubit is determined by operations comprising: based on a determination that a first subset of the single-qubit quantum logic gates reside at the beginning of the quantum logic circuit, removing the first subset of the singlequbit quantum logic gates from the quantum logic circuit; and based on a determination that a second subset of the single-qubit quantum logic gates reside at the end of the quantum logic circuit, removing the second subset of the single-qubit quantum logic gates from the quantum logic circuit.

3. The method of claim 2, wherein the light cone for each respective qubit is determined by operations comprising: combining quantum logic gates in the quantum logic circuit.

4. The method of claim 2, wherein the light cone for each respective qubit is determined by operations comprising: based on a determination that a third subset of the multi-qubit quantum logic gates are not applied to the respective qubit, removing the third subset of the multi-qubit quantum logic gate from the quantum logic circuit.

5. The method of claim 2, wherein the light cone for each respective qubit is determined by operations comprising: based on a determination that a third subset of the multi-qubit quantum logic gates are not applied to the respective qubit or to the first subset of the qubits, removing the third subset of the multi-qubit quantum logic gates from the quantum logic circuit.

6. The method of claim 1, wherein constructing the reduced quantum logic circuit for the observable comprises: identifying, in the quantum logic circuit, a subset of quantum logic gates that are applied to qubits in the light cones identified for the subset of the qubits over which the observable is defined.

7. The method of claim 6, wherein the observables comprise a two-body observable defined over a first qubit and a second qubit, and constructing a reduced quantum logic circuit for the two-body observable comprises: constructing a first reduced quantum logic circuit for qubits in the light cone identified for the first qubit; constructing a second reduced quantum logic circuit for qubits in the light cone identified for the second qubit; and combining the first and second reduced quantum logic circuits.

8. The method of any one of claims 1 to 7, wherein constructing the reduced quantum logic circuit for the observable based on the light cone comprises excluding at least onequantum logic gate from the quantum logic circuit for the observable based on the light cone.

9. The method of any one of claims 1 to 7, comprising: returning the reduced quantum logic circuit for execution by a quantum computing resource.

10. The method of any one of claims 1 to 7, comprising: executing the reduced quantum logic circuit to determine a value of the observable.

11. The method of any one of claims 1 to 7, wherein the quantum logic circuit corresponds to a quantum approximate optimization algorithm (QAOA) configured to be executed by a quantum processing unit and a classical processing unit.

12. The method of any one of claims 1 to 7, wherein the quantum logic circuit corresponds to a quantum relax-and-round algorithm configured to be executed by a quantum processing unit and a classical processing unit.

13. The method of any one of claims 1 to 7, wherein the quantum logic circuit corresponds to a quantum machine learning algorithm configured to be executed by a quantum processing unit and a classical processing unit.

14. The method of any one of claims 1 to 7, comprising: identifying a plurality of observables associated with the quantum logic circuit, each of the observables defined over a respective subset of the plurality of qubits; and determining a reduced quantum logic circuit for each of the observables.

15. A computer system comprising: a classical processing unit; and memory storing instructions that are operable, when executed by the classical processing unit, to: obtain a quantum logic circuit defined over a plurality of qubits; determine a light cone for a respective qubit of the plurality of qubits, the light cone being determined by operations comprising: defining a graph comprising the respective qubit;identifying a first subset of multi-qubit quantum logic gates applied to the respective qubit and a first subset of the qubits in the quantum logic circuit; adding the first subset of the qubits to the graph; identifying a second subset of the multi-qubit quantum logic gates applied to at least one of the first subset of the qubits and at least one of a second subset of the qubits in the quantum logic circuit; and based on a determination that the second subset of multi-qubit quantum logic gates do not commute with at least one prior quantum logic gate in the quantum logic circuit, adding the second subset of the qubits to the graph; and construct a reduced quantum logic circuit for an observable based on the light cone.

16. The system of claim 15, wherein the quantum logic circuit comprises single-qubit quantum logic gates and the multi-qubit quantum logic gates, and the light cone for the respective qubit is determined by operations comprising: based on a determination that a first subset of the single-qubit quantum logic gates reside at the beginning of the quantum logic circuit, removing the first subset of the singlequbit quantum logic gates from the quantum logic circuit; and based on a determination that a second subset of the single-qubit quantum logic gates reside at the end of the quantum logic circuit, removing the second subset of the single-qubit quantum logic gates from the quantum logic circuit.

17. The system of claim 16, wherein the light cone for each respective qubit is determined by operations comprising: combining quantum logic gates in the quantum logic circuit.

18. The system of claim 16, wherein the light cone for each respective qubit is determined by operations comprising: based on a determination that a third subset of the multi-qubit quantum logic gates are not applied to the respective qubit, removing the third subset of the multi-qubit quantum logic gate from the quantum logic circuit.

19. The system of claim 16, wherein the light cone for each respective qubit is determined by operations comprising: based on a determination that a third subset of multi-qubit quantum logic gates are not applied to the respective qubit or to the first subset of the qubits, removing the third subset of the multi-qubit quantum logic gates from the quantum logic circuit.

20. The system of claim 15, wherein constructing the reduced quantum logic circuit for an observable comprises: identifying, in the quantum logic circuit, a subset of quantum logic gates that are applied to qubits in the light cones identified for the subset of the qubits over which the observable is defined.

21. The system of claim 20, wherein the observable comprises a two-body observable defined over a first qubit and a second qubit, and constructing a reduced quantum logic circuit for the two-body observable comprises: constructing a first reduced quantum logic circuit for qubits in the light cone identified for the first qubit; constructing a second reduced quantum logic circuit for qubits in the light cone identified for the second qubit; and combining the first and second reduced quantum logic circuits.

22. The system of any one of claims 15 to 21, wherein constructing the reduced quantum logic circuit for the observable based on the light cone comprises excluding at least one quantum logic gate from the quantum logic circuit for the observable based on the light cone.

23. The system of any one of claims 15 to 21, comprising a quantum computing resource, wherein the instructions are operable, when executed by the classical processing unit, to: return the reduced quantum logic circuit for execution by the quantum computing resource.

24. The system of any one of claims 15 to 21, comprising a quantum computing resource configured to execute the reduced quantum logic circuit.

25. The system of any one of claims 15-21, wherein the quantum logic circuit corresponds to a quantum approximate optimization algorithm (QAOA).

26. The system of any one of claims 15-21, wherein the quantum logic circuit corresponds to a quantum relax-and-round algorithm.

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