Direct current solid-state circuit breakers

Abstract

An apparatus includes a first node coupled to a positive rail, a second node coupled to a protected circuit, and a common node coupled to a negative rail. A first transistor has a first source terminal coupled to the first node and a first drain terminal coupled to a mirroring node. A first transient damping network is coupled in parallel across the first transistor. A second resistor is coupled in parallel across the first transistor. A second transistor has a second drain terminal coupled to the mirroring node and a second source terminal coupled to the second node. A second transient damping network includes a second series combination of a second capacitor and a third resistor, and is coupled in parallel across the second transistor. A fourth resistor is coupled in parallel across the second transistor. A snubber circuit is coupled between the mirroring node and the common node.

Description

Atty Dkt No. UNCC-1007PCT (2025-014)DIRECT CURRENT SOLID-STATE CIRCUIT BREAKERSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application for patent claims priority- to and the benefit of provisional patent application number 63 / 706,809 entitled “Improved Fault Current Bypass-Based DC Solid-State Circuit Breaker” filed in the United States Patent and Trademark Office on October 14, 2024, the entire content of which is incorporated herein by reference as if fully set forth below in its entirety and for all applicable purposes.TECHNICAL FIELD

[0002] This application relates to solid-state circuit breakers, and more particularly to improved fault current bypass-based direct current (DC) solid-state circuit breakers including unidirectional and bidirectional Npes of DC solid-state circuit breakers.INTRODUCTION

[0003] Direct current (DC) circuit breakers may serve as protective devices within DC systems, such as, but not limited to, solar power systems, battery storage systems, electric vehicles, and DC microgrid systems. The DC circuit breaker plays an indispensable role in these and other DC systems, and has consistently garnered attention from both industry and academia. A DC circuit breaker is distinct from an alternating current (AC) circuit breaker. A DC circuit breaker interrupts direct current, which flows continuously in one direction and does not naturally drop to zero. Because of this, extinguishing an arc formed during circuit interruption in a DC system is more difficult and requires advanced techniques such as solid-state switching. In contrast, an AC circuit breaker interrupts alternating current, which reverses direction and crosses zero voltage multiple times per second. This zero-crossing helps extinguish the arc more easily, making AC breakers simpler and less costly to design. In DC systems, due to the absence of zero crossings and low source and load impedance compared to AC systems, short-circuit faults can lead to rapid increases in current. The magnitude of the short circuit currents may be great enough to damage equipment, which was not designed to handle the magnitude of the short circuit current. Because of the rapidity of the increase in current, DC fault current interruption circuits that can interrupt the short circuit current before it reaches a magnitude sufficient to damage equipment, are needed.

[0004] Compared to conventional mechanical circuit breakers, solid-state circuit breakers (SSCBs) provide advantages such as fast fault current interruption, arc-less operation, noiseless operation, and all without the use of moving parts. Among various types of DC SSCBs are faultAtty Dkt No. UNCC-1007PCT (2025-014) current bypass-based DC SSCBs. The fault current bypass-based DC SSCBs stand out because of their abi 1 i ty to rapidly decouple, at the onset of a fault, a source or load side of a circuit from whichever side is exhibiting the fault (e g., the short-circuit), thus isolating the faulted side of the circuit (be it source or load) from the other side. For example, an SSCB between a source side and a load side may decouple the load side from the power supply on the source side in response to a short circuit fault occurring on the load side. A rapid decoupling promotes safety, reduces a possibility7of damage to equipment, and facilitates troubleshooting of, and location of, the source of the fault.

[0005] By way of one example, a DC microgrid may be localized power system that distributes DC power and includes DC power sources (like generators, batteries, and solar panels), DC loads, and energy7storage, all controlled as a single entity7. The DC microgrid may serve many loads and may have several ways to source these loads. Therefore, use of a DC SSCB topology7, such as but not limited to a fault current bypass-based DC SSCB topology, to quickly isolate one faulted (e.g., short circuited) component, branch circuit, or load from the source side of the DC microgrid reduces the impact of the faulted item on all other loads served by (and sourced by) the DC microgrid.

[0006] Scientists and engineers continue with research and development programs related to improvements in all types of DC SSCBs, including but not limited to unidirectional and bidirectional ty pes, as well as fault current bypass-based DC SSCBs.BRIEF SUMMARY OF SOME EXAMPLES

[0007] The systems, methods, and devices disclosed herein each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.

[0008] The following presents a summary7of one or more aspects of the present disclosure, in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a form as a prelude to the more detailed description that is presented later.

[0009] In one example, an apparatus is described. The apparatus includes a first node configured to be coupled to a positive rail, a second node configured to be coupled to a protected circuit, and a common node configured to be coupled to a negative rail. The apparatus also includes a first transistor having a first source terminal coupled to the first node and a first drain terminal coupled to a mirroring node. The apparatus also includes a first transient damping network. The firstAtty Dkt No. UNCC-1007PCT (2025-014) transient damping network includes a first series combination of a first capacitor and a first resistor. The first transient damping network is coupled in parallel across the first source terminal and the first drain terminal of the first transistor. The apparatus also includes a second resistor coupled in parallel across the first source terminal and the first drain terminal of the first transistor. The second resistor is configured to conduct DC current from the first node to the mirroring node independent of conduction through the first transistor. The apparatus also includes a second transistor having a second drain terminal coupled to the mirroring node and a second source terminal coupled to the second node and a second transient damping network comprising a second series combination of a second capacitor and a third resistor, the second transient damping network coupled in parallel across the second source terminal and the second drain terminal of the second transistor. The apparatus also includes a fourth resistor coupled in parallel across the second source terminal and the second drain terminal of the second transistor, the fourth resistor configured to conduct the DC current independent of conduction through the second transistor. The apparatus also includes a snubber circuit coupled between the mirroring node and the common node.

[0010] In another example, a modular apparatus is described. The modular apparatus includes a first node configured to be coupled to a positive rail, a second node configured to be coupled to a protected circuit, and a common node configured to be coupled to a negative rail. The modular apparatus also includes a first switch having a first terminal coupled to the first node and a second terminal coupled to a mirroring node, a first transient damping network comprising a first series combination of a first capacitor and a first resistor, the first transient damping network coupled in parallel across the first terminal and the second terminal and configured to suppress voltage spikes and absorb high-frequency transients across the first switch, a second resistor coupled in parallel across the first terminal and the second terminal, the second resistor configured to conduct DC current from the first node to the mirroring node independent of conduction through the first switch. The apparatus also includes a second switch having a fourth terminal coupled to the mirroring node and a third terminal coupled to the second node, a second transient damping network comprising a second series combination of a second capacitor and a third resistor, the second transient damping network coupled in parallel across the third terminal and the fourth terminal and configured to suppress voltage spikes and absorb high-frequency transients across the second switch, a fourth resistor coupled in parallel across the third terminal and the fourth terminal, the fourth resistor configured to conduct the DC current independent of conduction through the second switch, a snubber circuit coupled between the mirroring node and the common node, a first shunt transient damping circuit coupled between the first node and the common node, a second shunt transient damping circuit coupled between the second node and the common node, where the first shuntAtty Dkt No. UNCC-1007PCT (2025-014) transient damping circuit and the second shunt transient damping circuit are configured to operate as reverse current clamps and transient discharge paths, each configured to divert reverse-polarity current and dissipate transient energy to ground during fault conditions or directional switching events.

[0011] According to another example, an apparatus is described. The apparatus includes an input node configured to be coupled to a positive rail, an output node, and a common node configured to be coupled to a negative rail. The apparatus also includes a first shunt branch coupled between the input node and the common node, a second shunt branch coupled between the output node and the common node, and a series branch coupled to the input node and the output node between the first shunt branch and the second shunt branch. According to some aspects, the first shunt branch comprises a snubber circuit, the series branch comprises a series switch, and the second shunt branch comprises a parallel combination of a metal oxide varistor (MOV) and a bypass switch both coupled at a first end to the output node and at a second end to an intermediate node, and a diode having a cathode coupled to the intermediate node and an anode coupled to the common node.

[0012] In another example, an apparatus is described. The apparatus includes a pi-shaped configuration of a shunt snubber circuit, a series switch, and a shunt combination of a parallel combination of a metal oxide varistor and a bypass switch. The parallel combination is in series with a reverse-biased diode.

[0013] Details of one or more implementations of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 is a block level schematic drawing illustrating a plurality of fault current bypassbased DC solid-state circuit breakers (SSCBs) in a DC microgrid system according to some aspects of the disclosure.

[0015] FIG. 2 is a simplified block diagram of a first fault current bypass-based DC SSCB according to some aspects of the disclosure.

[0016] FIG. 3 is the simplified block diagram of FIG. 2 with the series switch and bypass switch illustrations replaced with N-channel enhancement mode MOSFET symbols according to some aspects of the disclosure.

[0017] FIGs. 4A-4F are simplified schematic drawings showdng a progression of events in association w ith an occurrence of a fault according to some aspects of the disclosure.Atty Dkt No. UNCC-1007PCT (2025-014)

[0018] FIG. 5 is a plurality of electrical waveforms representing parameters of the circuit of FIGs. 4A-4F as the circuit of FIGs. 4A-4F progress through a fault event according to some aspects of the disclosure.

[0019] FIG. 6 shows experimental results of the topolog)’ of the apparatus of FIG. 3 according to some aspects of the disclosure.

[0020] FIG. 7 shows experimental results of the topology of the apparatus of FIG. 3 with respect to different switching sequences associated with an auxiliary switch in the topology of the apparatus of FIG. 3 according to some aspects of the disclosure.

[0021] FIG. 8 illustrates a bidirectional fault current bypass-based direct current solid-state circuit breaker according to some aspects of the disclosure.

[0022] FIG. 9 is a block diagram of a bidirectional fault current bypass-based direct current solid- state circuit breaker according to some aspects of the disclosure.

[0023] FIGs. 10A-10F are simplified schematic drawings showing a progression of events in association with an occurrence of a fault according to some aspects of the disclosure.

[0024] FIG. 11 is a plurality' of electrical waveforms representing parameters of the circuit of FIGs. 10A-10F as the circuit of FIGs. 10A-10F progress through a fault event according to some aspects of the disclosure.

[0025] FIG. 12 is a schematic diagram of a plurality of building block circuits that find utility in modular fault current bypass-based DC SSCBs according to some aspects of the disclosure.

[0026] FIG. 13 is a schematic diagram of a modular apparatus having two levels of modularity7according to some aspects of the disclosure.

[0027] FIG. 14 is a schematic diagram of a modular apparatus having three levels of modularity according to some aspects of the disclosure.

[0028] FIG. 1 is a schematic diagram of a modular apparatus that accommodates any level of modularity, n, where n is a positive integer greater than or equal to 1.

[0029] FIG. 16 shows the experimental results of the apparatus of FIG. 8 with various source and load inductances according to some aspects of the disclosure.

[0030] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0031] The present invention now will be described more fully hereinafter in the following detailed description, in which some, but not all embodiments of the invention are described. Indeed, this invention may be embodied in many different forms and should not be construed asAtty Dkt No. UNCC-1007PCT (2025-014) limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the singular forms "a." “an,” and “the” are intended to include the plural forms as well as the singular forms, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise,” “comprises.” “comprising,” “include,” “includes,” and / or “including” when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one having ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0034] It will be understood that a number of techniques and steps are disclosed in the descriptions herein. Each of these has individual benefit and each can also be used in conjunction with one or more, or in some cases all, of the other disclosed techniques. Accordingly, for the sake of clarity, this description will refrain from repeating every possible combination of the individual steps in an unnecessary fashion. Nevertheless, the specification and claims should be read with the understanding that such combinations are entirely within the scope of the invention and the claims.

[0035] FIG. 1 is a block level schematic drawing illustrating a plurality of DC solid-state circuit breakers in a DC microgrid system 100 according to some aspects of the disclosure. The DC microgrid system 100 includes an alternating current (AC) grid 102, which is represented as an inductively loaded sine wave generator. The AC grid 102 feeds an AC / DC converter 104. The DC output of the AC / DC converter 104 is coupled to a shared DC bus 106 via a first DC SSCB 108. The DC microgrid system 100 also includes a batter)' 112, which feeds a first DC / DC converter 114. The DC output of the first DC / DC converter 114 is coupled to the shared DC bus 106 via a second DC SSCB 118. The DC microgrid system 100 also includes a photovoltaic array 122, which feeds a second DC / DC converter 124. The DC output of the second DC / DC converter 124 is coupled to the shared DC bus 106 via a third DC SSCB 128. Accordingly, the shared DC bus 106Atty Dkt No. UNCC-1007PCT (2025-014) is protected from short circuits on the source side of the DC microgrid system 100 by at least the first DC SSCB 108, the second DC SSCB 118, and the third DC SSCB 128.

[0036] The shared DC bus 106 feeds a plurality of loads 110 that are protected by a respective plurality of DC SSCBs. A first DC load 134 is fed from the shared DC bus 106 via a fourth DC SSCB 130 in series with a third DC / DC converter 132. A second DC load 144 is fed from the shared DC bus 106 via a fifth DC SSCB 140 in series with a fourth DC / DC converter 142. A first AC load 154 is fed from the shared DC bus 106 via a sixth DC SSCB 150 in series with a DC / AC converter 152. The preceding lists are exemplary and not limiting.

[0037] The shared DC bus 106 in FIG. 1 is represented as a solid line for ease of illustration and not limitation. Also, for ease of illustration and not limitation, all circuits / sy stems coupled to the shared DC bus 106 are depicted with single-line inputs and outputs. However, as shown in the expanded schematic diagram 120 at the bottom of FIG. 1, the shared DC bus 106 may have at least a positive (+) bus / terminal / rail and a negative (-) bus / terminal / rail. The negative bus / terminal / rail may be referred to as a common and / or ground bus / terminal / rail. One or more DC bus capacitors, represented by DC bus capacitor 116, may be coupled across the positive and negative buses / terminals / rails of the shared DC bus 106.

[0038] For ease of illustration and not limitation, and to avoid cluttering the drawing, the expanded schematic diagram 120 provides examples of electrical schematics of the fifth DC SSCB 140 and the sixth DC SSCB 150. It is noted that all of the SSCBs 108, 118, 128, 130, 140, 150 may have the same or different schematic representations and be the same or different types of DC SSCBs. The fifth DC SSCB 140 and the sixth DC SSCB 150 are depicted as fault current bypassbased DC SSCBs in the example of FIG. 1; however, they are not limited to these types of DC SSCBs.

[0039] In each example of the electrical schematics of the fifth DC SSCB 140 and the sixth DC SSCB 150, an input inductor is coupled in series with an input node of the SSCB. A first input inductor 146 is coupled in series with the input node of the fifth DC SSCB 140. A second input inductor 156 is coupled in series with the input node of the sixth DC SSCB 150. The first input inductor 146 and the second input inductor 156 may be used to represent that the DC bus 106 may present an inductive source to the components coupled to the DC bus 106, including not only the fifth DC SSCB 140 and the sixth DC SSCB 150, but all DC SSCBs coupled to the DC bus 106.

[0040] In each example of the electrical schematics of the fifth DC SSCB 140 and the sixth DC SSCB 150, an output inductor is coupled in series with an output node of SSCB. A first output inductor 148 is coupled in series w ith the output node of the fifth DC SSCB 140. A second output inductor 158 is coupled in series with the output node of the sixth DC SSCB 150. The first outputAtty Dkt No. UNCC-1007PCT (2025-014) inductor 148 and the second output inductor 158 may be used to represent that the loads coupled to the outputs of all DC SSCBs, including the outputs of fifth DC SSCB 140 and the sixth DC SSCB 150, may be inductive loads.

[0041] DC SSCBs may be coupled to the DC bus 106 of the DC microgrid system 100 on either or both of the source side and the load side. In the example of FIG. 1, the DC SSCBs are coupled to both sides of the DC bus 106. All DC SSCBs of FIG. 1 may provide reliable and rapid fault interruption; however, the fifth DC SSCBs 140 and the sixth DC SSCB (which are both examples of fault current bypass-based DC SSCBs) have at least one drawback. The drawback being that the discharging time of a DC bus capacitor, such as the DC bus capacitor 116 of FIG. 1, increases due to the fault clearing time caused by the fault side inductance (e g., in cases where the short is on the load side, the first output inductor 148 of FIG. 1 or the second output inductor 158 of FIG. 1). The increase in discharging time of the DC bus capacitor 116 due to the fault interruption initiated by a DC SSCB in association with a load may lead to abnormal operation of other loads coupled to the shared DC bus 106 via other DC SSCBs, especially if multiple loads experience short circuit faults simultaneously in a worst-case scenario. Therefore, it is preferable to not only isolate short- circuit faults as quickly as possible, but also to minimize the impact of the operation of the DC SSCB on the source side. However, several drawbacks exist with today’s fault current bypassbased DC SSCBs topologies, such as the topologies of the fifth DC SSCB 140 and the sixth DC SSCB 150 of FIG. 1.

[0042] An example of a first topology' of fault current bypass-based DC SSCB is show n in the fifth DC SSCB 140 of FIG. 1. The first topology’ is represented as an apparatus that includes a circuit including: a positive rail 126 and a negative rail 136, an input node and an output node each disposed between the positive rail 126 and the negative rail 136, a first switch 160 (sometimes referred to as an auxiliary' switch, Sa a) having a first terminal coupled to the positive rail 126, and a second terminal coupled to a parallel arrangement of a resistor (R), a capacitor (C), and a metal oxide varistor (MOV) 162, where the resistor, the capacitor and the MOV 162 each have a first terminal coupled to the second terminal of the first switch 160 and a second terminal coupled to the negative rail 136. The first topology also includes a second switch 164 (sometimes referred to as a main switch, Sm m) having a first terminal coupled to the first terminal of the first switch 160 and the input node and a second terminal coupled to the output node and a first terminal of a diode 166, where the diode 166 has a second terminal coupled to the negative rail 136, and where the second switch 164 is disposed in series between the input node and the output node and in series with the positive rail 126.Atty Dkt No. UNCC-1007PCT (2025-014)

[0043] The first topology, shown in the fifth DC SSCB 140 of FIG. 1 , focused on eliminating a leakage current of the MOV 162, and decreasing a ratio between a clamping voltage of the MOV 162 and the DC link voltage present across the DC bus 106 (or across a capacitor bank represented as the DC bus capacitor 116), for example. The clamping voltage of a MOV such as the MOV 162, is the voltage level at which the MOV begins to conduct current, often to suppress a transient overvoltage / surge energy. Below the clamping voltage, the MOV behaves like an open circuit. At or above the clamping voltage the MOV conducts, diverting surge energy away from sensitive components. However, this topology requires the fault current to flow through a diode, such as diode 166, without any other energy absorbing circuitry. The diode 166 must be carefully designed to be large enough, especially when the output inductance (represented as the first output inductor 148) is high. Moreover, this topology requires an auxiliary power semiconductor device (not shown) with the same ratings as the second switch 164 (Smam) (where the second switch, Smam, is configured as an N-channel. enhancement mode, metal oxide field effect transistor (MOSFET)), resulting in high costs.

[0044] An example of second topology of fault current bypass-based DC SSCBs is shown in the example of the sixth DC SSCB 150 of FIG. 1. The second topology is represented as an apparatus that includes a circuit including: a positive rail 126 and a negative rail 136, an input node and an output node each disposed between the positive rail 126 and the negative rail 136, a capacitor (C) having a first terminal coupled to the positive rail 126 and a second terminal coupled to the negative rail 136, and a first switch 167 (also referred to as a main switch or a power transistor 1 (PQ1)) having a first terminal coupled to the first terminal of the capacitor and a second terminal coupled to a first terminal of a diode 165. The diode 165 has a second terminal coupled to the negative rail. The second topology also includes: a second switch 168 (also referred to as an auxiliary switch or a power transistor 2 (PQ2)) having a first terminal coupled to the second terminal of the first switch167 and to the first terminal of the diode 165, and a second terminal coupled to the output node. In the second topology, a metal oxide varistor (MOV) 170 is disposed in parallel with the second switch 168, the MOV 170 having a first terminal coupled to the first terminal of the second switch168 and a second terminal coupled to the second terminal of the second switch 168 and to the output node. The series combination of the first switch 167 and the second switch 168 (in parallel with the MOV 170) is disposed between the input node and the output node in series with the positive rail 126.

[0045] However, in the second topology, the current flows through the series combination of the first switch 167 and the second switch 168 (e.g., through the series combination of the two power transistors PQ1 and PQ2) (where the power transistors are configured as N-channel, enhancementAtty Dkt No. UNCC-1007PCT (2025-014) mode, MOSFETs) during normal operation. The current flowing through the series combination of the first switch 167 and the second switch 168 during normal operation (e.g., when no short circuit fault is occurring) results in low efficiency. Furthermore, in the second topology, the DC side (the input) will experience a high reverse current with the same amplitude as a fault current in response to a fault occurring. The high reverse current adversely affects the DC bus 106.

[0046] Accordingly, improved fault current bypass-based DC SSCBs are needed to overcome the drawbacks and deficiencies of at least the first topology and the second topology of fault current bypass-based DC SSCBs exemplified in the fifth DC SSCB 140 and the sixth DC SSCB of FIG. 1.

[0047] Therefore, topologies of improved fault current bypass-based DC SSCBs are provided herein, where FIGs. 2-7 are associated with unidirectional DC SSCBs and FIGs. 8-16 are associated with bidirectional DC SSCBs. The improved fault current bypass-based DC SSCBs (referred to individually or collectively hereinafter as apparatus) feature at least faster fault isolation and improved cost-effectiveness compared to other topologies such as the topologies illustrated in connection with the fifth DC SSCB 140 and the sixth DC SSCB 150 as shown and described in connection with FIG. 1.

[0048] FIG. 2 is a simplified block diagram of a first fault current bypass-based DC SSCB (“first apparatus 200"). according to aspects of the disclosure. The simplification replaces illustrations of the series transistor 314 and the bypass transistor 318 of FIG. 3 with illustrations of single-pole- single-throw (SPST) switches (e.g., a series switch 214 and a bypass switch 218), which may misleadingly suggest bidirectional operation. However, the SPST switches in FIG. 2, like the corresponding SPST switches of FIG. 3, are to be understood as constrained to unidirectional operation.

[0049] The effectiveness of the improved fault current bypass-based DC SSCBs represented by FIGs. 2-4 was verified through both simulation and experimental results. For example, a 400 V DC / 80 A prototype of the first apparatus 200 of FIG. 2 and a second apparatus 300 of FIG. 3 demonstrated the feasibility of the topology of those apparatus. The simulation and experimental results also showed that a clamping voltage of a MOV 216 may be lower than a DC link voltage (vc) present across a DC bus 206 coupled to an input node 202 of the first apparatus 200, and coupled to an input node 302 of the second apparatus 300. This result may occur because during normal operation, a (reverse-biased) diode 220 in the second shunt branch 209, 309 coupled to the output node 204, 304 prevents cunent from flowing between a positive rail 226 and a negative rail 236, through the second shunt branch 209, 309, which includes the MOV 216. According to some examples, the topologies of the first apparatus 200 and the second apparatus 300 provide a 99.82% efficiency and a 15% cost reduction for power semiconductor selection compared to, for example,Atty Dkt No. UNCC-1007PCT (2025-014) the topologies the fifth DC SSCB 140 and the sixth DC SSCB 150 as shown and described in connection with FIG. 1.

[0050] Turning now to FIG. 3, The second fault current bypass-based DC SSCB of FIG. 3 is referred to hereinafter as “second apparatus 300.”

[0051] A DC bus 206, similar to the DC bus 106 as shown and described in connection with FIG. 1, is illustrated. The DC bus 206 includes a positive rail 226 and the negative rail 236, similar to the positive rail 126 and the negative rail 136 as shown and described in connection with FIG. 1. The positive rail 226 may be referred to as a positive bus in some examples. The negative rail 236 may float or be coupled to ground in some examples. The negative rail 236 may be referred to as a common rail, a common bus, or a ground bus in some examples. An input node 202 and an output node 204 may each be disposed between the positive rail 226 and a common node 208 disposed on the negative rail 236. ADC voltage potential of Vdc is shown across the positive rail 226 and the negative rail 236.

[0052] One or more DC bus capacitors, represented by DC bus capacitor 116 as shown and described in connection with FIG. 1, may be coupled across the positive rail 226 and the negative rail 236 in some examples.

[0053] In the example of the electrical schematic of the first apparatus 200. an input inductor, also referred to as a source inductor 246 (A). similar to the first input inductor 146 as shown and described in connection with FIG. 1, is coupled in series with the input node 202 of the first apparatus 200. The source inductor 246 may be utilized to represent that the DC bus 206 may present an inductive source to the components coupled to the DC bus 206, including the first apparatus 200.

[0054] In the example of the electrical schematics of the first apparatus 200, an output inductor, also referred to as a load inductor 248 (Li), similar to the second output inductor 158 as shown and described in connection with FIG. 1, is coupled in series with the output node 204 of the first apparatus 200. The load inductor 248 may be utilized to represent that the load(s) coupled to the output node 204 of the first apparatus 200 may be inductive load(s).

[0055] The first apparatus 200 includes an input node 202 configured to be coupled to a positive rail 226, an output node 204, a common node 208 configured to be coupled to the negative rail 236, a first shunt branch 207 coupled between the input node 202 and the common node 208, a second shunt branch 209 coupled between the output node 204 (alternatively, the second shunt branch 209 may be described as being coupled between a second shunt branch first terminal, which is coupled to the output node 204) and the common node 208, and a series branch 210 coupled to the input node 202 and the output node 204 between the first shunt branch 207 and the secondAtty Dkt No. UNCC-1007PCT (2025-014) shunt branch 209. The first shunt branch 207 includes a snubber circuit 212. The series branch 210 includes a series switch 214. The second shunt branch 209 includes a parallel combination of a metal oxide varistor (MOV) 216 and a bypass switch 218, both coupled at a first end to the output node 204 (or alternatively to the second shunt branch first terminal that is coupled to the output node 204) and at a second end to an intermediate node. The intermediate node is coupled to the diode 220 having a cathode coupled to the intermediate node and an anode coupled to the common node 208 (alternatively, the anode of the diode 220 may be described as being coupled to a second sunt branch second terminal, which is coupled to the common node 208).

[0056] According to some examples, first apparatus 200, further includes one or more cunent sensors 222 configured to sense a current passing through at least the series switch 214 (the main switch, Sm), and further includes a controller circuit 224 (e.g., a processor circuit, a processing circuit) configured to: control the series switch 214 and the bypass switch 218, detect a fault in response to the current sensed by the one or more current sensors 222 exceeding a predetermined current threshold value, and turn off the series switch 214 first and the bypass switch 218 second in a sequence in which a predetermined delay occurs between the turning off of the series switch 214 and the bypass switch 218. According to some aspects, the predetermined delay may avoid a superimposed voltage spike across the series switch 214 (across the main switch or switches if present). The controller circuit 224, which may include one or more processors or controllers, may be coupled to one or more memories or computer readable media, represented herein as memory 223.

[0057] According to some examples, the first shunt branch 306, the second shunt branch 209, and the series branch 210 coupled between the first shunt branch 306 and the second shunt branch 209 together form a pi (n) shaped topology in which, under an operating configuration with a DC voltage (v*) applied across the input node 202 and the common node 208, and the series switch 214 and the bypass switch 218 both configured in a closed state: a DC current is prevented from flowing through the MOV 216 by a reverse-biasing of the diode 220 in the second shunt branch 209.

[0058] According to some aspects, the snubber circuit 212 includes a resistor 303 (FIG. 3) in series with a capacitor 305 (FIG. 3). In some examples, the capacitor 305 (FIG. 3) is a film capacitor. Film capacitors in this design topology have medium cost and improved lifetime compared to ceramic and electrolytic capacitors.

[0059] According to some aspects, the series switch 214 and the bypass switch 218 are the same model having identical electrical characteristics. According to other aspects, the series switch 214Atty Dkt No. UNCC-1007PCT (2025-014) and the bypass switch 218 are different models and the bypass switch 218 may have a lower breakdown voltage than the series switch 214.

[0060] Turning now to FIG. 3, which is the simplified block diagram of FIG. 2 in which the series switch 214 and bypass switch 218 (both SPST switches in these non-limiting examples) replaced a series transistor 314 and a bypass transistor 318, respectively, according to aspects of the disclosure. The series transistor 314 and the bypass transistor 318 are both represented as N- channel enhancement mode MOSFETs according to some aspects of the disclosure. The second fault cunent bypass-based DC SSCB of FIG. 3 is referred to hereinafter as the “second apparatus 300.”

[0061] TheN-channel enhancement-mode MOSFET (using the series transistor 314 for purposes of discussion) supports unidirectional current flow from drain to source when turned ON. Its body diode 315, oriented with a cathode at the drain and anode at the source, represents an intrinsic parasitic PN junction formed between theN-type drain and P-type body region. This parasitic diode is reverse-biased during normal conduction and becomes forward-biased only when the source potential exceeds the drain potential, allowing current flow from source to drain, even with the gate OFF. However, in the unidirectional current flow configuration of FIG. 3, a short circuit at the DC bus 206 side would collapse the drain voltage toward ground, preventing forward bias of the body diode 315 because both the drain and the source would be at ground potential. A bidirectional fault current bypass-based DC SSCB, derived from FIG. 3 and incorporating a mirrored circuit, is shown and described in connection with FIGs. 8-16 herein.

[0062] The series transistor 314 and bypass transistor 318 are each depicted as an N-channel enhancement-mode MOSFET; however, other types of transistors, such as but not limited to an insulated gate bipolar transistor (IGBT) may replace the N-channel enhancement-mode MOSFET and remain within the scope of the disclosure. An IGBT is a three terminal device that may combine a MOSFET input stage with a bipolar junction transistor (BJT) output stage. By such integration, the IGBT may achieve voltage controlled operation with high current capacity. For replacement terminology on a terminal-by-terminal basis, in one example, the terminal names of source and drain (of an N-channel enhancement-mode MOSFET) may be replaced with the terminal names of emitter and collector, respectively (of the IGBT). The name gate of the MOSFET is the same name used by the IGBT. In practice, the gate of an N-channel enhancement-mode MOSFET within the IGBT controls the forward flow of current between the collector and emitter of a BJT within the IGBT. Accordingly, circuits described herein utilizing recitations of a “source” and a “drain” of an N-channel enhancement-mode MOSFET may be interchangeable with circuits utilizing recitations of “emitter” and “collector,” respectively, herein. In one example, the series transistor 314 may beAtty Dkt No. UNCC-1007PCT (2025-014) an N-channel enhancement-mode MOSFET and the bypass transistor 318 may be an N-channel enhancement-mode MOSFET. In one example the series transistor 314 may be an IGBT and the bypass transistor 318 may be an IGBT. In one example the series transistor 314 may be an IGBT and the bypass transistor 318 may be an N-channel enhancement-mode MOSFET or vice versa. The preceding examples of configurations and types of transistors are exemplary and non-limiting.

[0063] For the sake of brevity7, all components with the same reference numbers (206 in FIG. 2 and 206 in FIG. 3) and like reference numbers (202 in FIG. 2 and 302 in FIG. 3) share the respective FIG. 2 descriptions in the context of FIG. 3.

[0064] FIG. 3 illustrates the direction of the current (6) flowing through the source inductor 246 (Ls), the current (zc) flowing through the series-coupled pair of the capacitor 305 (G) and the resistor (Rs) (e.g., the first shunt branch 306 of FIG. 3, the snubber circuit 212 of FIG. 2), the current ism) flowing through the series transistor 314 (Sm) (or more particularly, flowing through the drain-source junction of the series transistor 314). the current (imov flowing through the MOV 216, the current (6«) flowing through the bypass transistor 318, and the current flowing (zz) through the load inductor 248 (Li). FIG. 3 also shows the voltage (vsm) across the drain-source junction of the series transistor 314, the voltage (vd) across the diode 220, the gate-source voltage vgs-sm driving the gate of the series transistor 314 from a first output (labeled “1”) of the controller circuit 224, the gate-source voltage vgs.Sa driving the gate of the bypass transistor 318 from a second output (labeled “2”) of the controller circuit 224. All of the illustrated currents and voltages are present while the second apparatus 300 is operating with a voltage (vac) impressed across the input node 302 and the common node 308, with both the series transistor 314 and the bypass transistor 318 configured in the closed state (the ON state), and without any fault (short circuit) present. These currents and voltages are also illustrated in the plurality of circuit diagrams of FIGs. 4A-4F and the plurality7of graphs of FIGs. 5, 6, and 7 for various times (to - tL), which will be described in detail below.

[0065] In the fault current bypass-based direct current (DC) solid-state circuit breaker (SSCB) topologies (configurations) exemplified in the first apparatus 200 of FIG. 2 and the second apparatus 300 of FIG. 3, the term “bypass-based” refers to the bypassing of a fault current away from a main current-carrying path (also referred to as the positive rail 226) and through a bypass path that includes the bypass switch 218 of FIG. 2 and the bypass transistor 318 of FIG. 3 (both sometimes referred to herein as an auxiliary switch) that is in series with the diode 220 (which is reverse-biased in both configurations). In the examples provided herein, the bypass switch 218 or the bypass transistor 318 may be in parallel with a clamping device such as but not limited to the metal oxide varistor (MOV) 216. The diode 220, which is reverse-biased, controls current flow, isa,Atty Dkt No. UNCC-1007PCT (2025-014) through the bypass switch 218 or the bypass transistor 318 and the current flow, zmov, through the MOV 216 (in parallel with the bypass switch 218 or the bypass transistor 318) to and from the common node 208, 308 (and therefore to and from the negative rail 236) during both normal operation and a fault condition (such as a short circuit between the output node 204, 304 and the negative rail 236 / common node 208, 308).

[0066] During normal operation, current flow between the output node 304 and the common node 308 via the bypass transistor 318 is blocked by the diode 220, which is reverse-biased. The current is blocked even though the bypass transistor 318 may be in a closed state (e.g., the bypass transistor 318 / bypass switch 218 is in an ON state) during normal operation. The leakage current through the MOV 216 is effectively eliminated because the bypass transistor 318 is closed during normal operation, thus shorting out the MOV 216. Additionally, the MOV 216 is in a high impedance state during normal operation because the MOV 216 may be selected such that its clamping voltage (Vdamp in FIG. 9) is above the voltage differential between the positive rail 226 and the negative rail 236 (e.g., the DC link voltage, vc, minus a voltage drop, Vsm, across the series transistor 314 plus the clamping voltage (Vdamp in FIG. 9) of the MOV 216). However, to simplify the following explanations, the voltage drop, Vsm, across the series transistor 314 (Nm) during normal operation will be ignored.

[0067] The main current-carrying path is through the series transistor 314 (sometimes referred to the main switch, Sm), which is in series with the positive rail 226. The series transistor 314 and the bypass transistor 318 may each be configured as a semiconductor switch (e.g., a high-speed, high power semiconductor switch, a single pole single throw switch), such as, but not limited to, a MOSFET switch. In some examples, the series transistor 314 and the bypass transistor 318 may each be configured as, but not limited to, an N-channel enhancement mode MOSFET switch or an IGBT switch, according to some aspects of the disclosure.

[0068] According to some aspects, the series transistor 314 and the bypass transistor 318 may each be the same type of transistor (e.g., each has the same transistor characteristics). According to some aspects, the bypass transistor 318 may have a lower breakdown voltage than the series transistor 314.

[0069] During all states of operation, the controller circuit 224 may receive a measure of (e.g., a magnitude of, a value of) a current from the one or more current sensor(s) 222. The current may be, for example and without limitation, the source current, z«, the mam switch current, zsm, or some other current. During a fault (e.g., short circuit) condition, the controller circuit 224 may detect that the measure of current has exceeded a threshold value, Ith (in FIG. 5). In response to detecting that the measure of current has exceeded the threshold value, Ith, the controller circuit 224 may openAtty Dkt No. UNCC-1007PCT (2025-014) the series transistor 314 (the main switch) to remove the current from the output node 304. In some examples, the opening of the series transistor my occur suddenly. A sudden opening is in keeping with a practice of removing the fault condition as quickly as possible.

[0070] Using FIG. 3 as an example, during normal operation, the DC link voltage. Vdc. has DC- charged the effective inductor (e.g., the load inductor 248 (£ / )) on the load side of the second apparatus 300. When the series transistor 314 is suddenly opened, disconnecting the DC-charged load inductor 248 from the positive rail 226, the magnetic field of the load inductor 248 collapses rapidly and generates a high-voltage pulse sometimes referred to as an “inductive kick’' or “flyback voltage.” This happens because the load inductor 248 resists any change in the current, z7, flowing through the load inductor 248.

[0071] In more detail, during normal operation, while the series transistor 314 and the bypass transistor 318 are closed (before time to in FIG. 5), the DC voltage on the positive rail of the DC SSCB (the second apparatus 300) creates a magnetic field around the load inductor 248. This magnetic field stores energy. After a brief charging period, the load inductor 248 acts like a short circuit to the constant DC current.

[0072] At to in FIG. 5, a short circuit fault occurs. At ti in FIG. 5, in response to the controller circuit 224 sensing the measure of the current surpassing the current threshold, Ith, the controller circuit 224, via driver line 2 in FIG. 3, drives the series transistor 314 to the open state (the OFF state) (see Eg™). However, the controller circuit 224 leaves the bypass transistor 318 in the closed (the ON) state for a preconfigured duration (delay) before opening the bypass transistor 318 (see Vgssa). As shown in FIG. 9, the preconfigured duration (delay) lasts from ti (when the series transistor 314 is opened and Smturns OFF) to t2 (when the bypass transistor 318 is opened and Saturns OFF).

[0073] When the series transistor 314 is opened, the open switch presents the load inductor 248 with a high impedance. The high impedance forces the DC current flowing through the load inductor 249 to instantly drop to zero. However, the load inductor 248 resists this sudden decrease in current, and generates a high electromotive force (EMF) to try to maintain the flow of the DCcurrent. According to the formula for voltage across an inductor, V = Lthe almost instantaneouschange in current,results in a very large voltage, V, pulse. The collapsing magnetic field provides the energy for this voltage pulse. However, the polarity of this voltage pulse is reversed compared to the polarity of the original DC link voltage, vdc. The side of the load inductor 248 that was positive while charging (during normal operation) becomes highly negative (upon the series switch opening), and the negative side of the load inductor 248 becomes positive. This change inAtty Dkt No. UNCC-1007PCT (2025-014) polarity acts to forward bias the diode 220, allowing current to flow from the negative rail 236 (and therefore from the common node 308) into the anode of the diode 220, through the diode 220, out from the cathode of the diode 220 and into the bypass transistor 318, if the bypass transistor 318 is closed (Sais ON). While the bypass transistor 318 remains closed (between ti and t2 on FIG. 9), the voltage across the open series transistor 314 remains at Vdc (because one side of the series transistor 314 is tied to the DC bus 206 and the other side of the open series transistor 314 is shorted to the negative rail 236, which may be assumed to be tied to ground). However, once the bypass transistor 318 is opened (at t2 of FIG. 5) (Sais OFF) the voltage across the bypass transistor 318 is clamped to the value of the clamping voltage,clamp^ of the MOV 216, which raises the voltage, vSa, across the bypass transistor 318 from the voltage of the common node 308 (which is tied to the negative rail 236, which is assumed to be tied to ground) to the voltage across the MOV 216, Vdamp. The current and voltage responses at C, ts (where the bypass transistor 318 is turned on again (Sa is ON)), and t4 are self-explanatory.

[0074] According to some aspects, the second apparatus 300 of FIG. 3 may be described as an apparatus (e.g., a first apparatus 200, a second apparatus 300) including: an input node 202 configured to be coupled to a positive rail 226, an output node 204, a common node 208 configured to be coupled to the negative rail 236, a first shunt branch 306 coupled between the input node 202 and the common node 208, a second shunt branch 209 coupled between the output node 204 and the common node 208, and a series branch 210 coupled to the input node 202 and the output node 204 between the first shunt branch 306 and the second shunt branch 209. According to some aspects, the first shunt branch 306 may include a snubber circuit 212 (e.g., a series combination of a resistor 303 and a capacitor 305), the series branch 210 may include a series switch 214, and the second shunt branch 209 may include: a parallel combination of a metal oxide varistor (MOV) 216 and a bypass switch 218 both coupled at a first end to the output node 204 and at a second end to an intermediate node, and a diode 220 having a cathode coupled to the intermediate node and an anode coupled to the common node 208.

[0075] In some examples, the first apparatus 200 and / or the second apparatus 300 further includes one or more current sensors 222 configured to sense a current passing through at least the series switch 214. The first apparatus 200 and / or the second apparatus 300 further includes a controller circuit 224 configured to: control the series switch 214 and the bypass switch 218, detect a fault in response to the current sensed by the one or more current sensors 222 exceeding a predetermined current threshold value, and turn off the series switch 214 first and the bypass switch 218 second in a sequence in which a predetermined / preconfigured delay occurs between the turning off of the series switch 214 and the bypass switch 218.Atty Dkt No. UNCC-1007PCT (2025-014)

[0076] In some examples, the first shunt branch 306, the second shunt branch 209, and the series branch 210, which is coupled between the first shunt branch 306 and the second shunt branch 209, together form a pi (it) shaped topology; Under a normal operating configuration, a DC voltage is applied across the input node 202 and the common node 208, and the series switch 214 and the bypass switch 218 are both configured in a closed state. Under the normal operating condition, DC current is prevented from flowing through the MOV 216 by the diode 220 that is reverse-biased in the second shunt branch 209.

[0077] According to some aspects, the snubber circuit 212 includes a resistor 303 in series with a capacitor 305. According to some aspects, the capacitor 305 is a film capacitor.

[0078] In some examples, the series switch 214 and the bypass switch 218 of FIG. 2 are aunitary model (i.e., they are the same model / type of switch) having identical electrical characteristics. In some examples, the series transistor 314 and the bypass transistor 318 are a unitary' model (i.e., they are the same model / type of transistor) having identical electrical characteristics.

[0079] In some examples, the series switch 214 and the bypass switch 218 are different models / types of switches. In some examples, the series transistor 314 and the bypass transistor 318 are different models / ty pes of transistors. In some examples, the bypass switch 218 has a lower breakdown voltage than the series switch 214 of FIG. 2. In some examples, the bypass transistor 318 has a lower breakdown voltage than the series transistor 314.

[0080] According to some aspects, the series switch 214 of FIG. 2 and the series transistor 314 of FIG. 3 are a first N-channel enhancement mode metal oxide semiconductor field effect transistor (MOSFET) or a first insulated gate bipolar transistor (IGBT), and the bypass switch 218 of FIG. 2 and the bypass transistor 318 of FIG. 3 are a second N-channel enhancement mode MOSFET or a second IGBT. In such examples, the first N-channel enhancement mode MOSFET is different from the second N-channel enhancement mode MOSFET and the first IGBT is different from the second IGBT.

[0081] According to some aspects, the second apparatus 300 of FIG. 3 may be described as a pi- shaped configuration of: a shunt snubber circuit 212, a series switch 214, and a shunt combination of: a parallel combination of a metal oxide varistor (MOV) 216 and a bypass switch 218, the parallel combination in series with a diode 220 that is reverse-biased under normal operating conditions.

[0082] FIGs. 4A-4F are simplified schematic drawings, similar to those of FIG. 2 and FIG. 3, showing the progression of events in association with an occurrence of a fault according to some aspects of the disclosure. In FIGs. 4A-4F, the components that represent the series transistor 314 and the bypass transistor 318 in FIG. 3 are drawn as simple block diagram representations of SPSTAtty Dkt No. UNCC-1007PCT (2025-014) switches in the form of the series switch 214 and the bypass switch 218 of FIG. 2. This may misleadingly suggest bidirectional operation (as SPST switches are typically bidirectional). However, regardless of whether the transistors / switches are drawn as schematic symbols corresponding to N-channel enhancement mode MOSFETs, IGBTs, or simple block diagram representations of SPST switches, the SPST switches represented in all illustrations herein are to be understood as constrained to unidirectional operation.

[0083] For the sake of brevity7, the descriptions of the series switch 214, the series transistor 314, the bypass switch 218, and the bypass transistor 318 above are considered interchangeable and will not be repeated for the sale of brevity.

[0084] The configuration of FIG. 4A is intended to represent a time before normal operation, before to in FIG. 5, where the bypass switch 218 is turned ON (and placed into a closed state). The configuration of FIG. 4A may be referred to as a Mode 1 configuration.

[0085] The configuration of FIG. 4B is intended to represent a time during normal operation, still before to in FIG. 5, where the series switch 214 Sm) is turned ON (and the bypass switch 218 remains turned ON), that is they are both in the closed state. Once the series switch 214 (Sm) turns ON (e.g., is closed), the capacitor 305 (Cs) is charging. The configuration of FIG. 4B may be referred to as a Mode 2 configuration. In Mode 1 and Mode 2 (before to), before normal operation, the bypass switch 218 (Sa) turns on to bypass the MOV 216 bidirectionally. During normal operation, the series switch 214 (Sm) is in the ON state, and the snubber capacitor, Cs 305, will be charged. According to some aspects, a peak snubber voltage may be less than or equal to a main switch's (Sm, Smam) safety margin minus the MOV clamping voltage (Vdamp).

[0086] The configuration of FIG. 4C occurs at the time of the fault 402 (e.g., short circuit), which occurs at t = to in FIG. 5. At to, the snubber capacitor (Cs) begins discharging. The configuration of FIG. 4C may be referred to as a Mode 3 configuration.

[0087] The configuration of FIG. 4D occurs at t = ti, when the short-circuit current reaches Ith at ti, and Sm (the series switch 214) turns off. This configuration may be referred to as a Mode 4 configuration. When the series switch 214 turns off, the switch opens suddenly and the current, ism, through the series switch drops to zero rapidly, indicating that the source side is isolated from the fault location. The currents (flowing through the bypass switch 218) and id (flowing through the diode 220) reach Ith rapidly. The voltage vsmacross the drain source junction of the series switch 214 will be clamped at Vdc plus a voltage oscillation that occurs on the DC link snubber voltage.

[0088] FIG, 4E may be referred to as a Mode 5 configuration. At FIG. 4E, the bypass switch 218 (Sa) turns off at t = t2. The currents isa, ii, and id decrease under the clamping voltage. The voltage Vsm reaches Vdc+V a p, and the voltage vsais clamped at Vdamp.Atty Dkt No. UNCC-1007PCT (2025-014)

[0089] FIG. 4F may be referred to as a Mode 6 configuration. In FIG. 4F, switch Saturns on again at t.i when the load current It reaches zero, which can eliminate the MOV 216 leakage current. This result is because the MOV 216 can divide the voltage from the DC link voltage if switch Saremains in the OFF state when the fault current reaches zero.

[0090] FIG. 5 is a plurality of electrical waveforms 500 representing parameters of the circuits of FIG. 4A-4F as the circuit of FIGs. 4A-4F progress through a fault event according to some aspects of the disclosure. In FIG. 5, graphs (1), (2), (8), (9), and (10) depict graphs of voltage versus time, where voltage is on the vertical axis and time is on the horizontal axis. Graphs (3), (4), (5), (6), and (7) depict graphs of current versus time, where current is on the vertical axis and time is on the horizontal axis.

[0091] More specifically, graph (1) of FIG. 5 is a graph of gate voltage, Vgs-sm, of the of the series transistor 314, also referred to as the main switch Smain or Sm, herein according to some aspects of the disclosure. The annotation ‘A’mis ON” andis OFF” indicate that the series transistor 314 is either being driven to a closed state (where ‘A™ is ON”) or an open state (where ‘A™ is OFF”).

[0092] Graph (2) of FIG. 5 is a graph of gate voltage, Vgs-Sa, of the bypass switch 218, also referred to as the auxiliary7switch Sa, herein according to some aspects of the disclosure. The annotationis OFF” indicate that the bypass switch 218 is either being driven to a closed state (whereis ON”) or an open state (where ' is OFF”).

[0093] Graph (3) of FIG. 5 is a graph of source current, zs, which may be the current flowing through the source inductor 246 according to some aspects of the disclosure.

[0094] Graph (4) of FIG. 5 is a graph of drain to source current m of the series switch 214 according to some aspects of the disclosure.

[0095] Graph (5) of FIG. 5 is a graph of drain to source current Isaof the bypass switch 218 according to some aspects of the disclosure.

[0096] Graph (6) of FIG. 5 is a graph of the current, ii, flowing through the load inductor 248 according to some aspects of the disclosure.

[0097] Graph (7) of FIG. 5 is a graph of the current, id, flowing through the diode 220 according to some aspects of the disclosure.

[0098] Graph (8) of FIG. 5 is a graph of the voltage vsmacross the drain to source junction of the series transistor 314 to some aspects of the disclosure.

[0099] Graph (9) of FIG. 5 is a graph of the voltage vsaacross the drain to source junction of the bypass switch 218 to some aspects of the disclosure.

[0100] Graph (10) of FIG. 5 is a graph of the voltage vd across the diode 220 according to some aspects of the disclosure.Atty Dkt No. UNCC-1007PCT (2025-014)

[0101] In FIG. 5, graphs (1 ) to (10), Ith and In represent the threshold value of a protection current and anormal current, respectively. The parameters Vdc and Vdamp denote the DC link voltage and the clamping voltage of the MOV 216, respectively.

[0102] The main considerations for MOV design in the proposed topology are absorbing energy from the load inductance and clamping the voltage across power semiconductor devices to a safe level. Therefore, the MOV design requirement should meet the criteria of V amp < VBR - Vm x, where Vdamp is the clamping voltage of the MOV 216 and VBR is the breakdown voltage of the power semiconductor device.

[0103] It is noted that the main switch, Sm, can use a SiC MOSFET to reduce losses during normal operation. The auxiliary switch,can be selected as a device that has a small breakdown voltage. The topology of the second apparatus 300 of FIG. 3 and FIG. 4 has lower cost and higher efficiency compared with the topologies of FIG. 1 , and therefore has the best overall performance.

[0104] In order to verify the effectiveness of the second apparatus 300, a prototype with 400 VDC and 80 A protection current was built. A MOV-20D820K available from Bourns® of Riverside, CA, US was selected as the voltage clamping component. Rs and Cs are 0.5 Q and 33 pF, respectively.

[0105] FIG. 6 shows the experimental results 600 of the topology of the second apparatus 300 of FIG. 3 according to some aspects of the disclosure. Data for Vsm602, Vsa604, z / 606, and is 608 are provided. It can be seen that the main switch, Sm, is interrupted at 80 A, and the voltage across the main switch reaches the maximum voltage of 820 V using the designed snubber circuit. The source current, is. exhibits oscillation due to the RLC circuit. It is noted that the maximum clamping voltage of the MOV is 224 V, which is smaller than the DC link voltage. This characteristic helps to reduce the cost of the auxiliary pow er semiconductor devices.

[0106] FIG. 7 shows the experimental results 700 with different switching sequences in the auxiliary switch, Sa, in the topology of the second apparatus 300 of FIG. 3 according to some aspects of the disclosure. In FIG. 7 graph (1), Saturns off with a 600 ns delay compared to Sm. In FIG. 7 graph (2), Saturns off approximately 200 ns earlier than Sm. It can be seen that the maximum clamping voltage across the main switch is higher when Sais turned off earlier compared to when it is turned off with a delay. This is because the snubber circuit has a limited effect when Sais turned off too early. Therefore, an optimal approach is to turn off Sa with a delay relative to Sm. The clamping voltage performance improves if the auxiliary switch, &, turns off later than the main switch, Sm. It is noted that the lifetime of the MOV 216 (FIGs. 2 and 3) may be positively affected due to the lower capacity. As shown in graph (1), Vsm_pk 702 is 820 V and Vsa _pk 704 is 224 V. In graph (2), Vsm_pk 702 is 915 V and Vsa_pk 704 is 264 V. In graphs (1) and (2), Vsm708 is the firstAtty Dkt No. UNCC-1007PCT (2025-014)(top) trace, Vsa710 is the second trace, ii 706 is the third trace, Sm712 is the fourth trace, and Sa714 is the fifth (bottom) trace.

[0107] Turning now to FIG. 8, which illustrates a bidirectional fault current bypass-based direct current solid-state circuit breaker according to some aspects of the disclosure. In examples herein, the bidirectional fault current bypass-based direct current solid-state circuit breaker may be referred to as an apparatus 800, which includes a first node 802 configured to be coupled to a positive rail 835, a second node 804 configured to be coupled to a protected circuit 810 (where Ri represents the protected circuit 810), a common node 808 configured to be coupled to a negative rail 837, a first transistor 812 having a first source terminal 851 coupled to the first node 802 and a first drain terminal 852 coupled to a mirroring node 816, a first transient damping network 818 comprising a first series combination of a first capacitor 820 and a first resistor 822, the first transient damping network 818 coupled in parallel across the first source terminal 851 and the first drain terminal 852 and configured to suppress voltage spikes and absorb high-frequency transients across the first transistor 812, a second resistor 824 coupled in parallel across the first source terminal 851 and the first drain terminal 852, the second resistor 824 configured to conduct DC current from the first node 802 to the mirroring node 816 independent of conduction through the first transistor 812, a second transistor 826 having a second drain terminal 854 coupled to the mirroring node 816 and a second source terminal 853 coupled to the second node 804, a second transient damping network 830 comprising a second series combination of a second capacitor 832 and a third resistor 834, the second transient damping network 830 coupled in parallel across the second source terminal 853 and the second drain terminal 854 and configured to suppress voltage spikes and absorb high-frequency transients across the second transistor 826. a fourth resistor 836 coupled in parallel across the second source terminal 853 and the second drain terminal 854, the fourth resistor 836 configured to conduct the DC current independent of conduction through the second transistor 826, and a snubber circuit 838 coupled between the mirroring node 816 and the common node 808.

[0108] According to some aspects, the first transistor 812 is a first N-channel enhancement-mode metal oxide semiconductor field effect transistor (MOSFET), and the second transistor 826 is a second N-channel enhancement-mode MOSFET. The N-channel enhancement-mode MOSFETs supports unidirectional current flow from drain to source when turned ON.

[0109] According to some aspects, the first transistor 812 is a first insulated gate bipolar transistor (IGBT), the second transistor 826 is a second IGBT, and the terms source and drain (used in descriptions directed to MOSFETs herein) are replaced with the terms emitter and collector,Atty Dkt No. UNCC-1007PCT (2025-014) respectively. The TGBTs support unidirectional current flow from collector to emitter when turned ON.

[0110] According to some aspects, at least one of: the first transistor (812) or the second transistor (826) are N-channel enhancement-mode metal oxide semiconductor field effect transistors (MOSFETs). Alternatively, according to some aspects, at least one of: the first transistor (812) or the second transistor (826) are insulated gate bipolar transistors (IGBTs) and the terms source and drain (used in descriptions directed to MOSFETs herein) are replaced with the terms emitter and collector, respectively.

[0111] In some examples, the apparatus 800 further includes: a first gate terminal 814 of the first transistor 812 configured to receive a first bias voltage sufficient to turn the first transistor 812 ON, and a second gate terminal 828 of the second transistor 826 configured to receive a second bias voltage sufficient to turn the second transistor 826 ON.

[0112] In some examples, the snubber circuit 838 includes either: a first series combination 841 of a snubber resistor 840 (TN) and a parallel combination of a first snubber resistor 844 (Rsi) and a first snubber capacitor 842 (Csi), or a second series combination 843 of a second snubber resistor 846 (RS2) and a second snubber capacitor 848 (Cs ).

[0113] According to some aspects, the snubber circuit 838 is configured to at least one of: suppress voltage spikes, absorb high-frequency transients, or dissipate energy associated with inductive kickback at the mirroring node 816 during a fault condition, including a short-circuit event at the protected circuit 810 coupled to the second node 804.

[0114] According to some aspects, the apparatus 800 further includes a fault bypass path configured to conduct DC cunent from the first node 802 to the second node 804 in response to a conduction failure of the first transistor 812 or the second transistor 826. The fault bypass path may include the second resistor 824 and the fourth resistor 836, each configured to conduct DC current independent of transistor conduction. The fault bypass path may be configured to maintain current continuity from the first node 802 to the protected circuit 810 during a gate bias loss to a first gate terminal 814 of the first transistor 812 or a second gate terminal 828 of the second transistor 826, a first failure of the first transistor 812, a second failure of the second transistor 826, or a transient suppression event.

[0115] According to some aspects, the first transistor 812 and the second transistor 826 are configured to support bidirectional conduction under alternating gate bias conditions. In support of this aspect, the apparatus 800 further includes a controller circuit 806 configured to alternate gate bias voltages to enable bidirectional conduction between the first node 802 and the second node 804. The bidirectional conduction may be configured to support reverse current flow duringAtty Dkt No. UNCC-1007PCT (2025-014) regenerative braking, energy recovery, or load reversal conditions, for example. The controller circuit 806, which may include one or more processors or controllers, may be coupled to one or more memories or computer readable media, represented herein as memory 805.

[0116] According to some aspects, the apparatus 800 may further include the controller circuit 806 configured to selectively bias a first gate terminal 814 of the first transistor 812 and a second gate terminal 828 of the second transistor 826 to enable bidirectional conduction between the first node 802 and the second node 804. According to these aspects, the first transistor 812 conducts current from the second node 804 to the first node 802 when the first gate terminal 814 is biased ON and the second transistor 826 conducts current from the first node 802 to the second node 804 when the second gate terminal 828 is biased ON. Still further according to these aspects, the snubber circuit 838 is coupled between the mirroring node 816 and the common node 808, the snubber circuit 838 is configured to suppress voltage spikes, absorb high-frequency transients, and dissipate energy associated with inductive kickback during directional switching and fault conditions.

[0117] In some examples, the apparatus 800 further includes: a first shunt transient damping circuit 874 coupled between the first node 802 and the common node 808, a second shunt transient damping circuit 876 coupled between the second node 804 and the common node 808, wherein the first shunt transient damping circuit 874 and the second shunt transient damping circuit 876 are configured to operate as reverse current clamps and transient discharge paths, each configured to divert reverse-polarity current and dissipate transient energy to ground during fault conditions or directional switching events.

[0118] In such examples, the first shunt transient damping circuit 874 may include: a third transistor 850 having a third source terminal 855 coupled to the first node 802 and a third drain terminal 856 coupled to a first cathode 860 of a first diode 862 (Dpai), wherein a first anode 864 of the first diode 862 is coupled to the common node 808, and a first metal oxide varistor (MOV) 878 coupled in parallel with the third transistor 850 and configured to clamp voltage surges between the first node 802 and the common node 808. Furthermore, the second shunt transient damping circuit 876 may include: a fourth transistor 866 having a fourth source terminal 857 coupled to the second node 804 and a fourth drain terminal 858 coupled to a second cathode 868 of a second diode 870 (Dnai), wherein a second anode 872 of the second diode 870 (Dnai) is coupled to the common node 808, and a second metal oxide varistor (MOV) 880 coupled in parallel with the fourth transistor 866 and configured to clamp voltage surges between the second node 804 and the common node 808.Atty Dkt No. UNCC-1007PCT (2025-014)

[0119] In such examples, the third transistor 850 may be a third N-channel enhancement-mode metal oxide semiconductor field effect transistor (MOSFET), and the fourth transistor 866 may be a fourth N-channel enhancement-mode MOSFET.

[0120] In some examples, the apparatus 800 further includes: a first gate terminal 814 of the first transistor 812 configured to receive a first bias voltage, from a controller circuit 806, that selectively turns the first transistor 812 ON or OFF independently of the second transistor 826, the third transistor 850, and the fourth transistor 866, a second gate terminal 828 of the second transistor 826 configured to receive a second bias voltage, from the controller circuit 806, that selectively turns the second transistor 826 ON or OFF independently of the first transistor 812, the third transistor 850, and the fourth transistor 866, a third gate terminal 886 of the third transistor 850 configured to receive a third bias voltage, from the controller circuit 806, that selectively turns the third transistor 850 ON or OFF independently of the first transistor 812, the second transistor 826, and the fourth transistor 866, and a fourth gate terminal 888 of the fourth transistor 866 configured to receive a fourth bias voltage, from the controller circuit 806, that selectively turns the fourth transistor 866 ON or OFF independently of the first transistor 812, the second transistor 826, and the third transistor 850. The controller circuit 806 may also be configured to receive measurements from current sensor(s) 807, configured to measure current at various points in the apparatus 800.

[0121] In some examples, the first shunt transient damping circuit 874, further includes: a first damping resistor 882 (Rpai) coupled in parallel with the first diode 862 (Dpai), across the first anode 864 and the first cathode 860 of the first diode 862, and a second damping resistor 884 (Rnai) coupled in parallel with the second diode 870 (Dnai), across the second anode 872 and the second cathode 868 of the second diode 870.

[0122] FIG. 9 is a block diagram of a bidirectional fault current bypass-based direct current solid- state circuit breaker, according to some aspects of the disclosure. In examples herein, the bidirectional fault current bypass-based direct current solid-state circuit breaker may be interchangeably referred to as an apparatus 800 (FIG. 8) or a modular apparatus 900 (FIG. 9). The apparatus 800 (FIG. 8) or the modular apparatus 900 (FIG. 9) may include: a first node 802 configured to be coupled to a positive rail 835, a second node 804 configured to be coupled to a protected circuit 810, a common node 808 configured to be coupled to a negative rail 837, a first switch 813 having a first terminal 891 coupled to the first node 802 and a second terminal 892 coupled to a mirroring node 816, where the first switch 813 is a first unidirectional switch configured to pass DC current from the second terminal 892 to the first terminal 891 when a first gate terminal 815 of the first switch 813 is configured to receive a first bias voltage sufficient toAtty Dkt No. UNCC-1007PCT (2025-014) close the first switch 813, and configured to block DC current when the first gate terminal 815 of the first switch 813 is configured to receive a second bias voltage sufficient to open the first switch 813. The direction of current flow when the switch is biased closed (i.e., biased to be in the ON state) is provided as an arrow within the schematic representation of the first switch 813 in FIG. 9.

[0123] A first transient damping network 818 comprising a first series combination of a first capacitor 820 and a first resistor 822, the first transient damping network 818 coupled in parallel across the first terminal 891 and the second terminal 892 and configured to suppress voltage spikes and absorb high-frequency transients across the first transistor 812. A second resistor 824 is coupled in parallel across the first terminal 891 and the second terminal 892, the second resistor 824 configured to conduct DC current from the first node 802 to the mirroring node 816 independent of conduction through the first switch 813.

[0124] A second switch 827 having a fourth terminal 894 coupled to the mirroring node 816 and a third terminal 893 coupled to the second node 804. wherein the second switch 827 is a second unidirectional switch configured to pass DC current from the fourth terminal 894 to the third terminal 893 when a second gate terminal 828 of the second switch 827 is configured to receive a third bias voltage sufficient to close the second switch 827, and configured to block DC current when the second gate terminal 828 of the second switch 827 is configured to receive a fourth bias voltage sufficient to open the second switch 827. The direction of current flow when the switch is biased closed (biased to be in the ON state) is provided as an arrow within the schematic representation of the second switch 827 in FIG. 9.

[0125] A second transient damping network 830 comprising a second series combination of a second capacitor 832 and a third resistor 834. the second transient damping network 830 coupled in parallel across the third terminal 893 and the fourth terminal 894 and configured to suppress voltage spikes and absorb high-frequency transients across the second transistor 826. A fourth resistor 836 may be coupled in parallel across the third terminal 893 and the fourth terminal 894, the fourth resistor 836 configured to conduct the DC current independent of conduction through the second switch 827.

[0126] The modular apparatus 900 includes a snubber circuit 838 coupled between the mirroring node 816 and the common node 808, a first shunt transient damping circuit 874 coupled between the first node 802 and the common node 808, a second shunt transient damping circuit 876 coupled between the second node 804 and the common node 808, where the first shunt transient damping circuit 874 and the second shunt transient damping circuit 876 are configured to operate as reverse current clamps and transient discharge paths, each configured to divert reverse-polarity current and dissipate transient energy to ground during fault conditions or directional switching events.Atty Dkt No. UNCC-1007PCT (2025-014)

[0127] According to some aspects, the modular apparatus 900, may further include: one or more first directional building block circuits 1202 (FIG. 12), one or more second directional building block circuits 1204 (FIG. 12). In the example, a second direction of direct current (DC) current flow in each of the one or more second directional building block circuits 1204 is opposite to a first direction of direct cunent (DC) current flow in each of the one or more first directional building block circuits 1202. The modular apparatus also includes one or more first diode building block circuits 1206-1 (Dpan), one or more second diode building block circuits 1206-2 (£>»«»), and one or more snubber building block circuits 1208. Each set of building blocks (where a set comprises one each of 1202, 1204, 1206-1, 1206-2, and 1208) increases a maximum operating voltage of the modular apparatus 900 by a predetermined value.

[0128] FIGs. 10A-10F are simplified schematic drawings, similar to those of FIG. 8 and FIG. 9, showing the progression of events in association with an occurrence of a fault according to some aspects of the disclosure. In FIGs. 10A-10F, the series switches, SPiand Sni. and the bypass switches Spaand Sna, are drawn as simple block diagram representations of SPST switches. The simplification replaces the schematic representations of the transistor symbols with block diagram representations of single-pole-single-throw (SPST) switches. This may misleadingly suggest bidirectional operation. However, each switch or transistor configured as a switch herein is to be understood as constrained to unidirectional operation.

[0129] The configuration of FIG. 10A is intended to represent a time before normal operation, before to in FIG. 11. Before normal operation, the bypass switches Spaand Sna are turned ON (placed into a closed state). The configuration of FIG. 10A may be referred to as a Mode 1 configuration.

[0130] The configuration of FIG. 10B is intended to represent a time during normal operation before the fault at fe. The series switches SPiand Sni are turned ON (and the bypass switches Spaand Sna remain ON). Once the series switches Spiand Sni turn ON. the snubber capacitor, Cs, in the snubber circuit begins charging. The configuration of FIG. 10B may be referred to as a Mode 2 configuration. In Mode 1 and Mode 2 the bypass switches Spaand Sn turn on to bypass the MOVs 878 and 880 bidirectionally, respectively.

[0131] The configuration of FIG. 10C occurs at the time of the fault (e.g., short circuit), which occurs in FIG. 11 at t = t2. At ts, the snubber capacitor Cs begins discharging. The configuration of FIG. 10C may be referred to as a Mode 3 configuration.

[0132] The configuration of FIG. 10D occurs at ts in FIG. 11, when the short-circuit current reaches Ith at t = ts and the series switch Sni is turned OFF by the controller circuit. This configuration may be referred to as a Mode 4 configuration. When the series switch S„i turns OFF,Atty Dkt No. UNCC-1007PCT (2025-014) the switch opens suddenly and the current through the series switch, ini, drops to zero rapidly, indicating that the source side is isolated from the fault location. The snubber capacitor Cs charges and the current commutates to Sna. According to some aspects, a peak snubber voltage may be less than or equal to a main switch’s (SP, Sn) safety margin minus the MOV clamping voltage (Vdamp).

[0133] FIG. 10E may be referred to as a Mode 5 configuration. At FIG. 10E, the bypass switch Sna turns OFF at t = t4, after a predetermined delay.

[0134] FIG. 10F may be referred to as a Mode 6 configuration. In FIG. 10F, the bypass switch Sna turns ON again at t = ts when the load current h reaches zero. The series switch SPiturns OFF.

[0135] FIG. 11 is a plurality of electrical waveforms representing parameters of the circuit of FIG. 10A-10F as the circuit of FIGs. 10A-10F progress through a fault event according to some aspects of the disclosure. The graphs of FIG. 11 are similar to the graphs of FIG. 5 and are self- explanatory.

[0136] Graph (1) of FIG. 11 is a graph of the gate-source voltage Vgs-Piat the series transistor SPi.

[0137] Graph (2) of FIG. 11 is a graph of the gate-source voltage Vgs.niat the series transistor Sni.

[0138] Graph (3) of FIG. 11 is a graph of the gate-source voltage Vgs-sna at the bypass transistor Sna.

[0139] Graph (4) of FIG. 11 is a graph of source current, is, which may be the current flowing through the source inductor Ls according to some aspects of the disclosure.

[0140] Graph (5) of FIG. 11 is a graph of current iniof the series switch Sni according to some aspects of the disclosure.

[0141] Graph (6) of FIG. 11 is a graph of current inaof the bypass switch Snaaccording to some aspects of the disclosure.

[0142] Graph (7) of FIG. 11 is a graph of the load current, ii, flowing through the load inductor Li according to some aspects of the disclosure.

[0143] Graph (8) of FIG. 11 is a graph of the current, inai, flowing through the diode Dnai according to some aspects of the disclosure.

[0144] Graph (9) of FIG. 11 is a graph of the voltage v„i across the series switch Sni to some aspects of the disclosure.

[0145] Graph (10) of FIG. 11 is a graph of the voltage vnaacross the drain to source junction of the bypass switch Snaaccording to some aspects of the disclosure.

[0146] Graph ( 11 ) of FIG. 11 is a graph of the voltage vciacross the diode Dnai according to some aspects of the disclosure.

[0147] FIG. 12 is a schematic diagram of a plurality of building block circuits 1200 that find utility in modular fault current bypass-based DC SSCBs according to some aspects of theAtty Dkt No. UNCC-1007PCT (2025-014) disclosure. The building block circuits 1200 shown include a first directional building block circuit 1202.

[0148] The first directional building block circuit 1202 includes a first transistor 812 having a first source terminal 851 configured to be coupled to the first node 802 and a first drain terminal 852 configured to be coupled to a source terminal of a first transistor that precedes it.

[0149] The first directional building block circuit 1202 also includes a first transient damping network 818 comprising a first series combination of a first capacitor 820 and a first resistor 822, the first transient damping network 818 coupled in parallel across the first source terminal 851 and the first dram terminal 852 and configured to suppress voltage spikes and absorb high-frequency transients across the first transistor 812.

[0150] The first directional building block circuit 1202 also includes a second resistor 824 coupled in parallel across the first source terminal 851 and the first drain terminal 852, the second resistor 824 configured to conduct DC current from the first node 802 to the mirroring node 816 independent of conduction through the first transistor 812.

[0151] The first directional building block circuit 1202 also includes a first diode, Dpn, having a cathode coupled to the first drain terminal 852 and a first anode of first diode Dpnof the first directional building block circuit 1202 is configured to be coupled to the snubber building block circuit 1208 distal from the common node 808.

[0152] The building block circuits 1200 shown include a second directional building block circuit 1204.

[0153] The second directional building block circuit 1204 includes a second transistor 826 having a second source terminal 853 configured to be coupled to the second node 804 and a second drain terminal 854 configured to be coupled to a second source terminal 853 of a second transistor 826 that precedes it.

[0154] The second directional building block circuit 1204 also includes a second transient damping network 830 comprising a second series combination of a second capacitor 832 and a third resistor 834, the second transient damping network 830 coupled in parallel across the second source terminal 853 and the second drain terminal 854 and configured to suppress voltage spikes and absorb high-frequency transients across the second transistor 826.

[0155] The second directional building block circuit 1204 also includes a fourth resistor 836 coupled in parallel across the second source terminal 853 and the second drain terminal 854, the fourth resistor 836 configured to conduct DC current from the second node 804 to the mirroring node 816 independent of conduction through the second transistor 826.Atty Dkt No. UNCC-1007PCT (2025-014)

[0156] The second directional building block circuit 1204 also includes a second diode, Dm, having a cathode coupled to the second drain terminal 854 and a first anode of second diode, Dm, of the second directional building block circuit 1204 is configured to be coupled to the snubber building block circuit 1208 distal from the common node 808.

[0157] The building block circuits 1200 shown include a diode building block circuit 1206, which includes a first diode building block circuit 1206-1 (Dpan) and a second diode building block circuit 1206-2 (Dnan). The first diode building block circuit 1206-1 and the second diode building block circuit 1206-2 are the same or similar. The predominant, sometimes only, difference between the two is their location in a modular circuit, like a modular apparatus 1300 of FIG. 13. Both diode building block circuits 1206-1, 1206-2 include a diode in parallel with a resistor.

[0158] The building block circuits 1200 shown include a snubber building block circuit 1208. The snubber building block circuit 1208 includes a capacitor (Cn) in parallel with a resistor (Rsn).

[0159] In all of the building block circuits 1200, the index “n” is a positive integer that represents the modular level of the circuit. For example, n = 1 represents the base level of all modular assemblies. The first level above the n = 1 level is the n = 2 level.

[0160] FIG. 13 is a schematic diagram of a modular apparatus 1300 having two levels (n = 2) of modularity according to some aspects of the disclosure. The series transistors / switches of the first level (n = 1) include SPiand Sni. The bypass transistors / switches of the first level (n = 1) include Spaand Sn . The diodes associated with those bypass transistors / switches include Dpaiand Dnai, respectively. The parallel RC structure present in the snubber circuit 838 of the first level (n = 1) include Rsi and Csi.

[0161] As can be observed by considering the building block circuits 1200 of FIG. 12 in association with the modular apparatus 1300 of FIG. 13, the modular apparatus 1300 includes two levels (n = 2) of modularity. The first level of modularity (n = 1) in the illustration of FIG. 13 has all components of the electrical schematic draw n in solid line. The first level of modularity may be referred to as the baseline circuit. The second level of modularity (n = 2) in the illustration of FIG. 13 has all components of the electrical schematic drawn in dashed line. Accordingly, in the example of FIG. 13, the dashed line representations are not intended to represent optional components, rather, the dashed line representations identify the second modular level of building block circuits which were added to the baseline (solid line) portion of the modular apparatus 1300.

[0162] Accordingly, the modular apparatus 1300 of FIG. 13 includes one or more first directional building block circuits 1202 and one or more second directional building block circuits 1204. A second direction of direct current (DC) current flow in each of the one or more second directional building block circuits 1204 is opposite to a first direction of direct current (DC) current flow- inAtty Dkt No. UNCC-1007PCT (2025-014) each of the one or more first directional building block circuits 1202, including the building block circuits at both level 1 (n = 1) and level 2 (n = 2).

[0163] The modular apparatus 1300 of FIG. 13 also includes one or more first diode building block circuits 1206-1 (Dpan) and one or more second diode building block circuits 1206-2 (Dncm).

[0164] The modular apparatus 1300 of FIG. 13 also includes one or more snubber building block circuits 1208.

[0165] The complete configuration of the modular apparatus 1300 of FIG. 13 may include the baseline (n = 1) level of components and may additionally include: a snubber building block circuit 1208 coupled in series between the snubber circuit 838 and the common node 808, a first directional building block circuit 1202 configured in series between the first terminal 891 of the first switch 813 and the first node 802, wherein a first anode of a first diode 1201 (DP2) of the first directional building block circuit 1202 is coupled to the snubber building block circuit 1208 distal from the common node 808. a second directional building block circuit 1204 configured in series between the third terminal 893 of the second switch 827 and the second node 804, wherein a second anode of a second diode 1203 (Dn2) of the second directional building block circuit 1204 is coupled to the snubber building block circuit 1208 distal from the common node 808, a first diode building block circuit 1206-1 coupled between the first shunt transient damping circuit 874 and the common node 808, and a second diode building block circuit 1206-2 coupled between the second shunt transient damping circuit 876 and the common node 808.

[0166] According to some aspects, a modular apparatus having one level (n = 1) of modularity, that is, a baseline modular apparatus such as the apparatus 800 of FIG. 8, may provide protection for a DC bus voltage of 850 V. Therefore, the according to some aspects of the disclosure the modular apparatus 1300 having two levels (n = 2) of modularity may provide protection for a DC bus voltage of 1700 V (with fault interruption occurring at 150 A and normal operation of 50 A). Accordingly, the fault current bypass-based DC SSCBs described herein may be stacked, such that, given a baseline modular apparatus (n = 1) suitable for an 850 V DC bus voltage, an increase of one modular level will provide a modular apparatus (with n = 2) suitable for a 1700 V DC bus voltage. An increase of two modular levels will provide a modular apparatus (with n = 3) suitable for a 2,550 V DC bus voltage, and so on. A 1700 V / 150A prototype provided a DC voltage utilization ratio of 71%. The maximum voltage across the main switch of the prototype was smaller than the switches safety margin, and fault isolation time was only 18 ps.

[0167] It is believed that previous topologies could not be applied to 800 V DC systems with a 1200 V rated switch. It is noted that all examples as shown and described in connection with FIGs. 8-16 are common drain configurations. Aspects of these configurations that were the subject ofAtty Dkt No. UNCC-1007PCT (2025-014) experimental tests utilized silicon carbide (SiC) MOSFETs; however, other types of MOSFETs are within the scope of the disclosure.

[0168] FIG. 14 is a schematic diagram of a modular apparatus 1400 having three levels (n = 3) of modularity according to some aspects of the disclosure. All components of the schematic diagram are presented in solid line. The three levels of modularity may be observed by considering the index values (n values) presented in the schematic drawing. For example, SPi, Sni, Dpai, Dnai, Rsi and Csi are all members of the first level (n = 1). For example, SP2, Sn2, Dpa2, Dnas, Rss, and Css are all members of the second level (n = 2). For example, SP3, Sns, Dpa3^ Dna3.> Rss, and Cs3 are all members of the third level (n = 3).

[0169] FIG. 15 is a schematic diagram of a modular apparatus 1500 that accommodates any level of modularity', n, where n is a positive integer greater than or equal to 1. All components of the schematic diagram are presented in solid line. The unbounded ‘A"’ levels of modularity' may be observed by considering the index values (n values) presented in the schematic drawing. For example, Spi, Sni, Dpai, Dnai, Rsi, and Csi are all members of the first level (n = 1). For example, SP2, Sn2, Dpa2, Dna2, Rs2, and Css are all members of the second level (n = 2). For example, Spn, Sm, Dpan, Dnan, Rsn, and Csn are all members of the nth level (n = n).

[0170] FIG. 16 shows the experimental results 1600 of the apparatus 800 of FIG. 8 with various source and load inductances according to some aspects of the disclosure. In FIG. 16 graph (1), the source inductance (Ls) yvas 2 pH, the load inductance (Li) was 5 pH, and di / dt was 170 A / ps. In FIG. 16 graph (2), the source inductance (Ls) was 103 pH, the load inductance (Li) was 114 pH, and di / dt was 7.5 A / ps. The experimental results show that the maximum voltage across the main switch was smaller than safe margin of the main switch ( 1043 V = Vrating / 1. 15), and the maximum voltage remained yvithin the safe margin for all tested inductance values. In FIG. 1 chart (1) and chart (2), in the upper graphs, Vdc 1601 is 850 V, vni1604 is the first (top) trace, vs1603 is the second trace, vna1606 is the third trace, ina 1607 is hidden from vieyv, ii 1608 is the fourth trace, ini 1605 is the fifth trace. The lower graphs are enlarged versions of portions of the upper graphs, as indicated in the figures.

[0171] In accordance yvith various aspects of the disclosure, an element, any portion of an element, or any combination of elements may be implemented with a processing system that includes one or more processors / controllers (referred to herein as controller circuits (e g., 224 in FIGs. 2 and 3, 806 in FIGs. 8, 9, 13, 14, and 15). The one or more processors / controllers. as utilized in the apparatus 200, 300, 800, 900, 1300, 1400, 1500, may be configured to, individually or collectively, based at least in part on information stored in one or more memories (e.g., 223 in FIGs. 2 and 3, and 805 in FIGs. 8, 9, 13, 14, 15) and additionally or alternatively stored in one or more computer-Atty Dkt No. UNCC-1007PCT (2025-014) readable media (not shown) may implement any one or more of the methods or processes described herein and illustrated, for example, in FIGs. 4, 5, 10, and / or 11.

[0172] The following provides an overview of aspects of the present disclosure:

[0173] Aspect 1 : An apparatus (800) comprising: a first node (802) configured to be coupled to a positive rail (835), a second node (804) configured to be coupled to a protected circuit (810), a common node (808) configured to be coupled to a negative rail (837), a first transistor (812) having a first source terminal (851) coupled to the first node (802) and a first drain terminal (852) coupled to a mirroring node (816), a first transient damping network (818) comprising a first series combination of a first capacitor (820) and a first resistor (822), the first transient damping network (818) coupled in parallel across the first source terminal (851) and the first drain terminal (852), a second resistor (824) coupled in parallel across the first source terminal (851) and the first drain terminal (852), the second resistor (824) configured to conduct DC current from the first node (802) to the mirroring node (816) independent of conduction through the first transistor (812), a second transistor (826) having a second drain terminal (854) coupled to the mirroring node (816) and a second source terminal (853) coupled to the second node (804), a second transient damping network (830) comprising a second series combination of a second capacitor (832) and a third resistor (834), the second transient damping network (830) coupled in parallel across the second source terminal (853) and the second drain terminal (854), a fourth resistor (836) coupled in parallel across the second source terminal (853) and the second drain terminal (854), the fourth resistor (836) configured to conduct the DC current independent of conduction through the second transistor (826), and a snubber circuit (838) coupled between the mirroring node (816) and the common node (808).

[0174] Aspect 2: The apparatus of aspect 1, wherein: at least one of: the first transistor (812) or the second transistor (826) are N-channel enhancement-mode metal oxide semiconductor field effect transistors (MOSFETs), or at least one of: the first transistor (812) or the second transistor (826) are insulated gate bipolar transistors (IGBTs) and the terms source and drain are replaced with the terms emitter and collector, respectively.

[0175] Aspect 3: The apparatus of aspect 1 or aspect 2, further comprising: a first gate terminal (814) of the first transistor (812) configured to receive a first bias voltage sufficient to turn the first transistor (812) ON, and a second gate terminal (828) of the second transistor (826) configured to receive a second bias voltage sufficient to turn the second transistor (826) ON.

[0176] Aspect 4: The apparatus of any of aspects 1 through 3, wherein the snubber circuit (838) comprises either: a first series combination of a snubber resistor (840) (RS) and a parallel combination of a first snubber resistor (844) (RSI) and a first snubber capacitor (842) (CS1), or aAtty Dkt No. UNCC-1007PCT (2025-014) second series combination of a second snubber resistor (846) (RS2) and a second snubber capacitor (848) (CS2).

[0177] Aspect 5: The apparatus of any of aspects 1 through 4, wherein the snubber circuit (838) is configured to at least one of suppress voltage spikes, absorb high-frequency transients, or dissipate energy associated with inductive kickback at the mirroring node (816) during a fault condition, including a short-circuit event at the protected circuit (810) coupled to the second node (804).

[0178] Aspect 6: The apparatus of any of aspects 1 through 5, further comprising a fault bypass path configured to conduct DC current from the first node (802) to the second node (804) in response to a conduction failure of the first transistor (812) or the second transistor (826).

[0179] Aspect 7: The apparatus of aspect 6, wherein the fault bypass path comprises the second resistor (824) and the fourth resistor (836), each configured to conduct DC current independent of transistor conduction.

[0180] Aspect 8: The apparatus of aspect 7, wherein the fault bypass path is configured to maintain current continuity from the first node (802) to the protected circuit (810) during a gate bias loss to a first gate terminal (814) of the first transistor (812) or a second gate terminal (828) of the second transistor (826), a first failure of the first transistor (812), a second failure of the second transistor (826), or a transient suppression event.

[0181] Aspect 9: The apparatus of any of aspects 1 through 7, wherein the first transistor (812) and the second transistor (826) are configured to support bidirectional conduction under alternating gate bias conditions.

[0182] Aspect 10: The apparatus of aspect 9. further comprising a controller circuit (806) configured to alternate gate bias voltages to enable bidirectional conduction between the first node (802) and the second node (804).

[0183] Aspect 11 : The apparatus of aspect 10, wherein the bidirectional conduction is configured to support reverse current flow during regenerative braking, energy recovery, or load reversal conditions.

[0184] Aspect 12: The apparatus of any of aspects 1 through 11, further comprising a controller circuit (806) configured to selectively bias a first gate terminal (814) of the first transistor (812) and a second gate terminal (828) of the second transistor (826) to enable bidirectional conduction between the first node (802) and the second node (804), wherein the first transistor ( 12) conducts current from the second node (804) to the first node (802) when the first gate terminal (814) is biased ON and the second transistor (826) conducts current from the first node (802) to the second node (804) when the second gate terminal (828) is biased ON, and wherein the snubber circuitAtty Dkt No. UNCC-1007PCT (2025-014)(838) is coupled between the mirroring node (816) and the common node (808), the snubber circuit (838) is configured to suppress voltage spikes, absorb high-frequency transients, and dissipate energy associated with inductive kickback during directional switching and fault conditions.

[0185] Aspect 13: The apparatus of any of aspects 1 through 12, further comprising: a first shunt transient damping circuit (874) coupled between the first node (802) and the common node (808), a second shunt transient damping circuit (876) coupled between the second node (804) and the common node (808), wherein the first shunt transient damping circuit (874) and the second shunt transient damping circuit (876) are configured to operate as reverse current clamps and transient discharge paths, each configured to divert reverse-polarity current and dissipate transient energy to ground during fault conditions or directional switching events.

[0186] Aspect 14: The apparatus of aspect 13, wherein: the first shunt transient damping circuit (874), comprises: a third transistor (850) having a third source terminal (855) coupled to the first node (802) and a third drain terminal (856) coupled to a first cathode (860) of a first diode (862) (Dpai), wherein a first anode (864) of the first diode (862) is coupled to the common node (808), and a first metal oxide varistor (MOV) (878) coupled in parallel with the third transistor (850) and configured to clamp voltage surges between the first node (802) and the common node (808), and the second shunt transient damping circuit (876) comprises: a fourth transistor (866) having a fourth source terminal (857) coupled to the second node (804) and a fourth drain terminal (858) coupled to a second cathode (868) of a second diode (870) (Dnai), wherein a second anode (872) of the second diode (870) (Dnai) is coupled to the common node (808), and a second metal oxide varistor (MOV) (880) coupled in parallel with the fourth transistor (866) and configured to clamp voltage surges between the second node (804) and the common node (808).

[0187] Aspect 15: The apparatus of aspect 14, wherein: at least one of: the third transistor (850) or the fourth transistor (866) are N-channel enhancement-mode metal oxide semiconductor field effect transistors (MOSFETs), or at least one of: the third transistor (850) or the fourth transistor (866) are insulated gate bipolar transistors (IGBTs) and the terms source and drain are replaced with the terms emitter and collector, respectively.

[0188] Aspect 16: The apparatus of any of aspects 1 through 15, further comprising: a first gate terminal (814) of the first transistor (812) configured to receive a first bias voltage, from a controller circuit (806), that selectively turns the first transistor (812) ON or OFF independently of the second transistor (826), the third transistor (850), and the fourth transistor (866), a second gate terminal (828) of the second transistor (826) configured to receive a second bias voltage, from the controller circuit (806), that selectively turns the second transistor (826) ON or OFF independently of the first transistor (812), the third transistor (850), and the fourth transistor (866), a third gateAtty Dkt No. UNCC-1007PCT (2025-014) terminal (886) of the third transistor (850) configured to receive a third bias voltage, from the controller circuit (806), that selectively turns the third transistor (850) ON or OFF independently of the first transistor (812), the second transistor (826), and the fourth transistor (866), and a fourth gate terminal (888) of the fourth transistor (866) configured to receive a fourth bias voltage, from the controller circuit (806), that selectively turns the fourth transistor (866) ON or OFF independently of the first transistor (812), the second transistor (826), and the third transistor (850).

[0189] Aspect 17: The apparatus of any of aspects 1 through 16, wherein: the first shunt transient damping circuit (874), further comprises: a first damping resistor (882) (Rpai) coupled in parallel with the first diode (862) ( pai). across the first anode (864) and the first cathode (860) of the first diode (862), and a second damping resistor (884) (Rnai) coupled in parallel with the second diode (870) (Dnai), across the second anode (872) and the second cathode (868) of the second diode (870).

[0190] Aspect 18: A modular apparatus (900), comprising: a first node (802) configured to be coupled to a positive rail (835), a second node (804) configured to be coupled to a protected circuit (810), a common node (808) configured to be coupled to a negative rail (837), a first switch (813) having a first terminal (891) coupled to the first node (802) and a second terminal (892) coupled to a mirroring node (816), a first transient damping network (818) comprising a first series combination of a first capacitor (820) and a first resistor (822), the first transient damping network (818) coupled in parallel across the first terminal (891) and the second terminal (892) and configured to suppress voltage spikes and absorb high-frequency transients across the first switch (813), a second resistor (824) coupled in parallel across the first terminal (891) and the second terminal (892). the second resistor (824) configured to conduct DC current from the first node (802) to the mirroring node (816) independent of conduction through the first switch (813), a second switch (827) having a fourth terminal (894) coupled to the mirroring node (81 ) and a third terminal (893) coupled to the second node (804), a second transient damping network (830) comprising a second series combination of a second capacitor (832) and a third resistor (834), the second transient damping network (830) coupled in parallel across the third terminal (893) and the fourth terminal (894) and configured to suppress voltage spikes and absorb high-frequency transients across the second switch (827), a fourth resistor (836) coupled in parallel across the third terminal (893) and the fourth terminal (894), the fourth resistor (836) configured to conduct the DC current independent of conduction through the second switch (827), a snubber circuit (838) coupled between the mirroring node (816) and the common node (808), a first shunt transient damping circuit (874) coupled between the first node (802) and the common node (808), a second shunt transient damping circuit (876) coupled between the second node (804) and the common node (808), wherein the first shunt transient damping circuit (874) and the second shunt transientAtty Dkt No. UNCC-1007PCT (2025-014) damping circuit (876) are configured to operate as reverse current clamps and transient discharge paths, each configured to divert reverse-polarity current and dissipate transient energy' to ground during fault conditions or directional switching events.

[0191] Aspect 19: The modular apparatus of aspect 18. wherein: the first switch (813) is a first unidirectional switch configured to pass DC current from the second terminal (892) to the first terminal (891) when a first gate terminal (815) of the first switch (813) is configured to receive a first bias voltage sufficient to close the first switch (813), and configured to block DC current when the first gate terminal (815) of the first switch (813) is configured to receive a second bias voltage sufficient to open the first switch (813), and the second switch (827) is a second unidirectional switch configured to pass DC current from the fourth terminal (894) to the third terminal (893) when a second gate terminal (828) of the second switch (827) is configured to receive a third bias voltage sufficient to close the second switch (827), and configured to block DC current when the second gate terminal (828) of the second switch (827) is configured to receive a fourth bias voltage sufficient to open the second switch (827).

[0192] Aspect 20: The modular apparatus of aspect 18 or aspect 19, further comprising: one or more first directional building block circuits (1202), one or more second directional building block circuits (1204), wherein a second direction of direct current (DC) current flow in each of the one or more second directional building block circuits (1204) is opposite to a first direction of direct current (DC) current flow in each of the one or more first directional building block circuits (1202), one or more first diode building block circuits (1206-1), one or more second diode building block circuits (1206-2), and one or more snubber building block circuits (1208).

[0193] Aspect 21 : The modular apparatus of any of aspects 18 through 20, further comprising: a snubber building block circuit (1208) coupled in series between the snubber circuit (838) and the common node (808), a first directional building block circuit (1202) configured in series between the first terminal (891) of the first switch (813) and the first node (802), wherein a first anode of a first diode 1201 (DP2) of the first directional building block circuit (1202) is coupled to the snubber building block circuit (1208) distal from the common node (808), a second directional building block circuit (1204) configured in series between the third terminal (893) of the second switch (827) and the second node (804), wherein a second anode of a second diode 1203 D»2) of the second directional building block circuit (1204) is coupled to the snubber building block circuit (1208) distal from the common node (808), a first diode building block circuit (1206-1) coupled between the first shunt transient damping circuit (874) and the common node (808), and a second diode building block circuit (1206-2) coupled between the second shunt transient damping circuit (876) and the common node (808).Atty Dkt No. UNCC-1007PCT (2025-014)

[0194] Aspect 22: An apparatus (200) comprising: an input node (202) configured to be coupled to a positive rail (226), an output node (204), a common node (208) configured to be coupled to a negative rail (236), a first shunt branch (207) coupled between the input node (202) and the common node (208). a second shunt branch (209) coupled between the output node (204) and the common node (208), and a series branch (210) coupled to the input node (202) and the output node (204) between the first shunt branch (207) and the second shunt branch (209), wherein the first shunt branch (207) comprises a snubber circuit (212), the series branch (210) comprises a series switch (214). and the second shunt branch (209) comprises: a parallel combination of a metal oxide varistor (MOV) (216) and a bypass switch (218) both coupled at a first end to the output node (204) and at a second end to an intermediate node, and a diode (220) having a cathode coupled to the intermediate node and an anode coupled to the common node (208).

[0195] Aspect 23: The apparatus (200) of aspect 22, further comprising one or more current sensors (222) configured to sense a current passing through at least the series switch (214), and a controller circuit (224) configured to: control the series switch (214) and the bypass switch (218), detect a fault in response to the current exceeding a predetermined current threshold value, and turn off the series switch (214) first and the bypass switch (218) second in a sequence in which a predetermined delay occurs between the turning off of the series switch (214) and the bypass switch (218).

[0196] Aspect 24: The apparatus of aspect 22, wherein the first shunt branch (207), the second shunt branch (209), and the series branch (210) coupled between the first shunt branch (207) and the second shunt branch (209) together form a pi (n) shaped topology in which, under a normal operating configuration with a DC voltage applied across the input node (202) and the common node 208 and the series switch (214) and the bypass switch (218) are both configured in a closed state: DC current is prevented from flowing through the MOV (216) by the diode (220) in the second shunt branch (209).

[0197] Aspect 25: The apparatus of aspect 22 or aspect 23, wherein the snubber circuit (212) comprises: a resistor (303) in series with a capacitor (305).

[0198] Aspect 26: The apparatus of aspect 25, wherein the capacitor (305) is a film capacitor.

[0199] Aspect 27 : The apparatus of any of aspects 22 through 26, wherein the series switch (214) and the bypass switch (218) are a unitary model having identical electrical characteristics.

[0200] Aspect 28: The apparatus of any of aspects 22 through 27, wherein the series switch (214) and the bypass switch (218) are different models and the bypass switch (218) has a lower breakdow n voltage than the series switch (214).Atty Dkt No. UNCC-1007PCT (2025-014)

[0201] Aspect 29: The apparatus of any of aspects 22 through 28, wherein the series switch (214) is a first N-channel enhancement mode metal oxide semiconductor field effect transistor (MOSFET) or a first IGBT, and the bypass switch (218) is a second N-channel enhancement mode MOSFET or a second IGBT.

[0202] Aspect 30: An apparatus, comprising: a pi-shaped configuration of: a shunt snubber circuit (212), a series switch (214), and a shunt combination of: a parallel combination of a metal oxide varistor (216) and a bypass switch (218), the parallel combination in series with a reverse- biased diode (220).

[0203] One or more of the components, steps, features, and / or functions illustrated in FIGs. 1-16 may be rearranged and / or combined into a single component, step, feature, or function, or embodied in several components, steps, or functions. Additional elements, components, steps, and / or functions may also be added without departing from novel features disclosed herein. The apparatus, devices, and / or components illustrated in FIGs. 1-16 may be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein may also be efficiently implemented in software and / or embedded in hardware.

[0204] The previous description is provided to enable persons having skill in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to persons having skill in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more.

Claims

Atty Dkt No. UNCC-1007PCT (2025-014)CLAIMSWhat is Claimed Is:

1. An apparatus (800) comprising: a first node (802) configured to be coupled to a positive rail (835); a second node (804) configured to be coupled to a protected circuit (810); a common node (808) configured to be coupled to a negative rail (837); a first transistor (812) having a first source terminal (851) coupled to the first node (802) and a first dram terminal (852) coupled to a mirroring node (816); a first transient damping network (818) comprising a first series combination of a first capacitor (820) and a first resistor (822), the first transient damping network (818) coupled in parallel across the first source terminal (851) and the first drain terminal (852); a second resistor (824) coupled in parallel across the first source terminal (851) and the first drain terminal (852), the second resistor (824) configured to conduct DC current from the first node (802) to the mirroring node (816) independent of conduction through the first transistor (812); a second transistor (826) having a second drain terminal (854) coupled to the mirroring node (816) and a second source terminal (853) coupled to the second node (804); a second transient damping network (830) comprising a second series combination of a second capacitor (832) and a third resistor (834), the second transient damping network (830) coupled in parallel across the second source terminal (853) and the second drain terminal (854); a fourth resistor (836) coupled in parallel across the second source terminal (853) and the second drain terminal (854), the fourth resistor (836) configured to conduct the DC current independent of conduction through the second transistor (826); and a snubber circuit (838) coupled between the mirroring node (816) and the common node (808).

2. The apparatus of claim 1, wherein: at least one of: the first transistor (812) or the second transistor (826) are N-channel enhancement-mode metal oxide semiconductor field effect transistors (MOSFETs); or at least one of: the first transistor (812) or the second transistor (826) are insulated gate bipolar transistors (IGBTs) and the terms source and drain are replaced with the terms emitter and collector, respectively.Atty Dkt No. UNCC-1007PCT (2025-014)3. The apparatus of claim 1 , further comprising: a first gate terminal (814) of the first transistor (812) configured to receive a first bias voltage sufficient to turn the first transistor (812) ON; and a second gate terminal (828) of the second transistor (826) configured to receive a second bias voltage sufficient to turn the second transistor (826) ON.

4. The apparatus of claim 1, wherein the snubber circuit (838) comprises either: a first series combination of a snubber resistor (840) and a parallel combination of a first snubber resistor (844) and a first snubber capacitor (842); or a second series combination of a second snubber resistor (846) and a second snubber capacitor (848).

5. The apparatus of claim 1, wherein the snubber circuit (838) is configured to at least one of: suppress voltage spikes, absorb high-frequency transients, or dissipate energy associated with inductive kickback at the mirroring node (816) during a fault condition, including a short-circuit event at the protected circuit (810) coupled to the second node (804).

6. The apparatus of claim 1, further comprising a fault bypass path configured to conduct DC current from the first node (802) to the second node (804) in response to a conduction failure of the first transistor (812) or the second transistor (826).

7. The apparatus of claim 6, wherein the fault bypass path comprises the second resistor (824) and the fourth resistor (836), each configured to conduct DC current independent of transistor conduction.

8. The apparatus of claim 7, wherein the fault bypass path is configured to maintain current continuity from the first node (802) to the protected circuit (810) during a gate bias loss to a first gate terminal (814) of the first transistor (812) or a second gate terminal (828) of the second transistor (826), a first failure of the first transistor (812), a second failure of the second transistor (826), or a transient suppression event.

9. The apparatus of claim 1, wherein the first transistor (812) and the second transistor (826) are configured to support bidirectional conduction under alternating gate bias conditions.Atty Dkt No. UNCC-1007PCT (2025-014)10. The apparatus of claim 9, further comprising a controller circuit (806) configured to alternate gate bias voltages to enable bidirectional conduction between the first node (802) and the second node (804).

11. The apparatus of claim 10, wherein the bidirectional conduction is configured to support reverse current flow during regenerative braking, energy recovery', or load reversal conditions.

12. The apparatus of claim 1, further comprising a controller circuit (806) configured to selectively bias a first gate terminal (814) of the first transistor (812) and a second gate terminal (828) of the second transistor (826) to enable bidirectional conduction between the first node (802) and the second node (804); wherein the first transistor (812) conducts current from the second node (804) to the first node (802) when the first gate terminal (814) is biased ON and the second transistor (826) conducts current from the first node (802) to the second node (804) when the second gate terminal (828) is biased ON; and wherein the snubber circuit (838) is coupled between the mirroring node (816) and the common node (808), the snubber circuit (838) is configured to suppress voltage spikes, absorb high-frequency transients, and dissipate energy' associated with inductive kickback during directional switching and fault conditions.

13. The apparatus of claim 1, further comprising: a first shunt transient damping circuit (874) coupled between the first node (802) and the common node (808), a second shunt transient damping circuit (876) coupled between the second node (804) and the common node (808), wherein the first shunt transient damping circuit (874) and the second shunt transient damping circuit (876) are configured to operate as reverse current clamps and transient discharge paths, each configured to divert reverse-polarity7current and dissipate transient energy to ground during fault conditions or directional switching events.

14. The apparatus of claim 13, wherein: the first shunt transient damping circuit (874), comprises:Atty Dkt No. UNCC-1007PCT (2025-014) a third transistor (850) having a third source terminal (855) coupled to the first node (802) and a third drain terminal (856) coupled to a first cathode (860) of a first diode (862), wherein a first anode (864) of the first diode (862) is coupled to the common node (808); and a first metal oxide varistor (MOV) (878) coupled in parallel with the third transistor (850) and configured to clamp voltage surges between the first node (802) and the common node (808); and the second shunt transient damping circuit (876) comprises; a fourth transistor (866) having a fourth source terminal (857) coupled to the second node (804) and a fourth drain terminal (858) coupled to a second cathode (868) of a second diode (870), wherein a second anode (872) of the second diode (870) is coupled to the common node (808); and a second metal oxide varistor (MOV) (880) coupled in parallel with the fourth transistor (866) and configured to clamp voltage surges between the second node (804) and the common node (808).

15. The apparatus of claim 14, further comprising: a first gate terminal (814) of the first transistor (812) configured to receive a first bias voltage, from a controller circuit (806), that selectively turns the first transistor (812) ON or OFF independently of the second transistor (826), the third transistor (850), and the fourth transistor (866); a second gate terminal (828) of the second transistor (826) configured to receive a second bias voltage, from the controller circuit (806). that selectively turns the second transistor (826) ON or OFF independently of the first transistor (812), the third transistor (850), and the fourth transistor (866); a third gate terminal (886) of the third transistor (850) configured to receive a third bias voltage, from the controller circuit (806), that selectively turns the third transistor (850) ON or OFF independently of the first transistor (812), the second transistor (826), and the fourth transistor (866); and a fourth gate terminal (888) of the fourth transistor (866) configured to receive a fourth bias voltage, from the controller circuit (806), that selectively turns the fourth transistor (866) ON or OFF independently of the first transistor (812), the second transistor (826), and the third transistor (850).

16. The apparatus of claim 14, wherein:Atty Dkt No. UNCC-1007PCT (2025-014) the first shunt transient damping circuit (874), further comprises: a first damping resistor (882) coupled in parallel with the first diode (862), across the first anode (864) and the first cathode (860) of the first diode (862); and a second damping resistor (884) coupled in parallel with the second diode (870), across the second anode (872) and the second cathode (868) of the second diode (870).

17. A modular apparatus (900), comprising: a first node (802) configured to be coupled to a positive rail (835); a second node (804) configured to be coupled to a protected circuit (810); a common node (808) configured to be coupled to a negative rail (837); a first switch (813) having a first terminal (891) coupled to the first node (802) and a second terminal (892) coupled to a mirroring node (816), a first transient damping network (818) comprising a first series combination of a first capacitor (820) and a first resistor (822), the first transient damping network (818) coupled in parallel across the first terminal (891) and the second terminal (892); a second resistor (824) coupled in parallel across the first terminal (891) and the second terminal (892). the second resistor (824) configured to conduct DC cunent from the first node (802) to the mirroring node (816) independent of conduction through the first switch (813); a second switch (827) having a fourth terminal (894) coupled to the mirroring node (816) and a third terminal (893) coupled to the second node (804); a second transient damping network (830) comprising a second series combination of a second capacitor (832) and a third resistor (834), the second transient damping network (830) coupled in parallel across the third terminal (893) and the fourth terminal (894); a fourth resistor (836) coupled in parallel across the third terminal (893) and the fourth terminal (894), the fourth resistor (836) configured to conduct the DC current independent of conduction through the second switch (827); a snubber circuit (838) coupled betw een the mirroring node (816) and the common node (808); a first shunt transient damping circuit (874) coupled between the first node (802) and the common node (808). a second shunt transient damping circuit (876) coupled between the second node (804) and the common node (808), wherein the first shunt transient damping circuit (874) and the second shunt transient damping circuit (876) are configured to operate as reverse current clamps and transient dischargeAtty Dkt No. UNCC-1007PCT (2025-014) paths, each configured to divert reverse-polarity current and dissipate transient energy to ground during fault conditions or directional switching events.

18. The modular apparatus of claim 17, wherein: the first switch (813) is a first unidirectional switch configured to pass DC current from the second terminal (892) to the first terminal (891) when a first gate terminal (815) of the first switch (813) is configured to receive a first bias voltage sufficient to close the first switch (813), and configured to block DC current when the first gate terminal (815) of the first switch (813) is configured to receive a second bias voltage sufficient to open the first switch (813); and the second switch (827) is a second unidirectional switch configured to pass DC current from the fourth terminal (894) to the third terminal (893) when a second gate terminal (828) of the second switch (827) is configured to receive a third bias voltage sufficient to close the second switch (827). and configured to block DC current when the second gate terminal (828) of the second switch (827) is configured to receive a fourth bias voltage sufficient to open the second switch (827).

19. The modular apparatus of claim 17, further comprising: one or more first directional building block circuits (1202); one or more second directional building block circuits (1204), wherein a second direction of direct current (DC) current flow in each of the one or more second directional building block circuits (1204) is opposite to a first direction of direct current (DC) current flow in each of the one or more first directional building block circuits (1202); one or more first diode building block circuits (1206-1); one or more second diode building block circuits (1206-2), and one or more snubber building block circuits (1208).

20. The modular apparatus of claim 17, further comprising: a snubber building block circuit (1208) coupled in series between the snubber circuit (838) and the common node (808); a first directional building block circuit (1202) configured in series between the first terminal (891) of the first switch (813) and the first node (802), wherein a first anode of a first diode (1201) of the first directional building block circuit (1202) is coupled to the snubber building block circuit (1208) distal from the common node (808);Atty Dkt No. UNCC-1007PCT (2025-014) a second directional building block circuit (1204) configured in series between the third terminal (893) of the second switch (827) and the second node (804), wherein a second anode of a second diode (1203) of the second directional building block circuit (1204) is coupled to the snubber building block circuit (1208) distal from the common node (808); a first diode building block circuit (1206-1) coupled between the first shunt transient damping circuit (874) and the common node (808); and a second diode building block circuit (1206-2) coupled between the second shunt transient damping circuit (876) and the common node (808).

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