Device interconnection system, data processing method and apparatus, and device, non-volatile storage medium and product

Abstract

The present application relates to the technical field of data processing. Disclosed are a device interconnection system, a data processing method and apparatus, and a device, a non-volatile storage medium and a product. The device interconnection system comprises a processor and a plurality of computing devices, wherein the processor is connected to a processor memory, the computing devices are connected to computing device memories, and the processor is connected to the plurality of computing devices by means of a bus that conforms to a preset protocol; each computing device comprises target ports, different computing devices are directly connected by means of the target ports, and data is directly transmitted between the different computing devices by means of the target ports; and the processor memory and the plurality of computing device memories are addressed by using a unified addressing mode, and when a computing device memory is accessed, address mapping is performed between unified addressing and an internal address space of the computing device by means of the corresponding computing device. The present application improves the efficiency of data transmission between different computing devices, and simplifies an address access mode and a data transmission mode.

Description

Device interconnection systems, data processing methods, apparatus and equipment, non-volatile storage media and products

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411505240.7, filed on October 25, 2024, entitled "Device Interconnection System, Data Processing Method, Apparatus and Equipment, Medium and Product", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a device interconnection system, data processing method, apparatus and equipment, non-volatile storage medium and product. Background Technology

[0004] In device interconnect systems of related technologies, the processor is connected to multiple computing devices via a bus conforming to a preset protocol, such as PCIe (Peripheral Component Interconnect Express). Data transfer, whether between the processor and computing devices or between different computing devices, must be performed through this bus, resulting in high bus transmission load and low data transfer efficiency between different computing devices.

[0005] Therefore, there is a technical problem in the related technologies where the data transmission efficiency between different computing devices in the device interconnection system is low. Summary of the Invention

[0006] The purpose of this application is to provide a device interconnection system, data processing method, apparatus and equipment, non-volatile storage medium and product that improves the data transmission efficiency between different computing devices in the device interconnection system.

[0007] To achieve the above objectives, this application provides a device interconnection system, including a processor and multiple computing devices, wherein the processor is connected to processor memory, the computing devices are connected to computing device memory, and the processor and the multiple computing devices are connected via a bus conforming to a preset protocol;

[0008] Computing devices include target ports, through which different computing devices are directly connected and data is directly transmitted between them.

[0009] The processor memory and the memory of multiple computing devices are addressed using a unified addressing method. When the memory of a computing device is accessed, an address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0010] The computing device includes a first target port and a second target port. The computing device receives data sent by other computing devices through the first target port and sends data to other computing devices through the second target port.

[0011] The processor includes interconnected processor cores, port modules, and a first memory controller. The processor is connected to processor memory through the first memory controller. The port module includes multiple first ports conforming to a preset protocol.

[0012] The computing device includes a second port conforming to a preset protocol, a target port, an address translation unit, a computing unit, and a second memory controller. The address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller. The computing device is connected to the computing device memory through the second memory controller.

[0013] The processor connects to the second ports of different computing devices through multiple first ports.

[0014] The processor also includes a unified addressing management module, which is configured to perform unified addressing of the processor memory and the memory of multiple computing devices.

[0015] The computing device also includes a memory decoder. The computing unit connects to the second port and the target port through the memory decoder. The second memory controller connects to the computing unit, the second port, and the target port through the memory decoder. The memory decoder is configured to perform address mapping between the unified addressing and the internal address space of the computing device according to the usage scenario.

[0016] The memory decoder in the computing device is configured as follows:

[0017] When the processor accesses the computing device memory of the current computing device, it translates the unified addressing into an address on the device's internal bus;

[0018] When a computing unit of the current computing device accesses the computing device memory of the current computing device, the unified address is translated into an address on the device's internal bus;

[0019] When the computing unit of the current computing device accesses the processor memory, no address translation is performed;

[0020] When the computing unit of the current computing device accesses the computing memory of another computing device, no address translation is performed;

[0021] When a computing unit in another computing device accesses the computing device memory of the current computing device, the unified address is translated into an address on the device's internal bus.

[0022] The computing device is a field-programmable gate array (FPGA).

[0023] In this system, the (i-1)th computing device is connected to the ith computing device, 1 < i ≤ N, and N is the number of computing devices included in the device interconnection system.

[0024] The computing device includes a first target port and a second target port. The second target port of the (i-1)th computing device is connected to the first target port of the ith computing device. The (i-1)th computing device sends data to the ith computing device through the second target port of the (i-1)th computing device and the first target port of the ith computing device.

[0025] The processor is configured to write input data into processor memory.

[0026] The first computing device is configured to: obtain input data from the processor memory via a bus conforming to a preset protocol, perform calculations on the obtained data in its corresponding hidden layer to obtain the result data, and store it in its corresponding computing device memory;

[0027] The i-th computing device is configured to: obtain the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, perform calculations on the obtained data for its own corresponding hidden layer to obtain the result data, and store it in the computing device memory of its own corresponding computing device;

[0028] The Nth computing device writes the calculated result data as output data into the processor memory via a bus conforming to a preset protocol.

[0029] To achieve the above objectives, this application provides a data processing method applied to a computing device in a device interconnection system. The device interconnection system includes a processor and multiple computing devices. The processor is connected to processor memory, and the computing devices are connected to computing device memory. The processor and the multiple computing devices are connected via a bus conforming to a preset protocol. Each computing device includes a target port. The (i-1)th computing device is connected to the ith computing device via the target port, where 1 < i ≤ N, and N is the number of computing devices included in the device interconnection system.

[0030] The methods include:

[0031] The first computing device obtains input data from the processor memory through a bus conforming to a preset protocol, performs calculations on the obtained data in its corresponding hidden layer to obtain the result data, and stores it in its corresponding computing device memory;

[0032] The i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs its own corresponding hidden layer calculation on the obtained data to obtain the result data, and stores it in its own corresponding computing device memory;

[0033] The Nth computing device writes the calculated result data as output data into the processor memory via a bus conforming to a preset protocol.

[0034] The processor memory and the memory of multiple computing devices are addressed using a unified addressing method.

[0035] The method also includes:

[0036] Obtain the address mapping table; the address mapping table includes the correspondence between the starting source address and the starting destination address under different usage scenarios;

[0037] Match the corresponding target use case in the address mapping table based on the target originating source address of the data access request;

[0038] Based on the correspondence between the starting source address and the starting destination address in the address mapping table under the target usage scenario, determine the target starting source address corresponding to the target starting destination address.

[0039] Where the target usage scenario is processor access to the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined according to the correspondence between the starting source address and the starting destination address in the address mapping table under the target usage scenario, including:

[0040] The target start source address is converted to an address on the device's internal bus as the target start destination address.

[0041] Where the target usage scenario is the computing unit of the current computing device accessing the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined according to the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including:

[0042] The target start source address is converted to an address on the device's internal bus as the target start destination address.

[0043] Where the target usage scenario is the computing unit of the current computing device accessing the processor memory, then the target starting destination address corresponding to the target starting source address is determined according to the correspondence between the starting source address and the starting destination address in the address mapping table under the target usage scenario, including:

[0044] Use the target's starting source address directly as the target's starting destination address.

[0045] Where the target usage scenario involves the computing unit of the current computing device accessing the computing memory of another computing device, then the target starting destination address corresponding to the target starting source address is determined according to the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including:

[0046] Use the target's starting source address directly as the target's starting destination address.

[0047] Where the target usage scenario involves the computing unit of another computing device accessing the computing device memory of the current computing device, then the target starting destination address corresponding to the target starting source address is determined according to the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table, including:

[0048] The target start source address is converted to an address on the device's internal bus as the target start destination address.

[0049] To achieve the above objectives, this application provides a data processing apparatus for use in a computing device in a device interconnection system. The device interconnection system includes a processor and multiple computing devices. The processor is connected to processor memory, and the computing devices are connected to computing device memory. The processor and the multiple computing devices are connected via a bus conforming to a preset protocol. Each computing device includes a target port. The (i-1)th computing device is connected to the ith computing device via the target port, where 1 < i ≤ N, and N is the number of computing devices included in the device interconnection system.

[0050] The acquisition unit is configured to acquire input data from the processor memory via a bus conforming to a preset protocol, or acquire result data calculated by other computing devices via a target port.

[0051] The computing unit is configured to perform calculations on the acquired data using its corresponding hidden layer to obtain the result data, and then store it in the memory of its corresponding computing device.

[0052] The output unit is configured to write the calculated result data as output data to the processor memory via a bus conforming to a preset protocol.

[0053] To achieve the above objectives, this application provides an electronic device, comprising:

[0054] The memory is configured to store computer programs;

[0055] The processor is configured to perform the steps of the data processing method described above when executing a computer program.

[0056] To achieve the above objectives, this application provides a non-volatile storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the data processing method described above.

[0057] To achieve the above objectives, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data processing method described above.

[0058] As can be seen from the above scheme, the device interconnection system provided in this application includes a processor and multiple computing devices. The processor is connected to processor memory, and the computing devices are connected to computing device memory. The processor and the multiple computing devices are connected through a bus conforming to a preset protocol. The computing devices include target ports, and different computing devices are directly connected through the target ports to directly transmit data. The processor memory and the memory of the multiple computing devices are addressed using a unified addressing method. When the memory of a computing device is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0059] This application adds a target port to the computing device, allowing different computing devices to connect directly and transmit data directly through this port. This eliminates the need for a bus conforming to a preset protocol connected to the processor, reducing bus transmission load and improving data transmission efficiency between different computing devices. Furthermore, this application uses a unified addressing method to address the processor memory and the computing device memory. By mapping addresses between the unified addressing and the computing device's internal address space, the address access and data transmission methods are simplified. This application also discloses a data processing method, apparatus, electronic device, non-volatile storage medium, and computer program product, all of which achieve the same technical effects.

[0060] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings are used to provide a further understanding of this disclosure and constitute a part of the specification. They are used together with the following detailed description to explain this disclosure, but do not constitute a limitation of this disclosure. In the drawings:

[0062] Figure 1 is an architecture diagram of a device interconnection system in related technologies;

[0063] Figure 2 is a schematic diagram of a calculation process in an application scenario of a device interconnection system in related technologies;

[0064] Figure 3 is a schematic diagram of the connection between a processor and a single computing device in a device interconnection system in related technologies;

[0065] Figure 4 is a flowchart of the overall operation of the device interconnection system in the related technology;

[0066] Figure 5 is an architecture diagram of a device interconnection system according to an exemplary embodiment;

[0067] Figure 6 is a schematic diagram illustrating the connection between a single computing device and a processor according to an exemplary embodiment;

[0068] Figure 7 is an architecture diagram of another device interconnection system according to an exemplary embodiment;

[0069] Figure 8 is an architecture diagram of a device interconnection system in an application scenario provided in this application;

[0070] Figure 9 is a flowchart illustrating the computation of a computing unit according to an exemplary embodiment;

[0071] Figure 10 is a schematic diagram illustrating another connection between a single computing device and a processor according to an exemplary embodiment;

[0072] Figure 11 is an overall flowchart illustrating the operation of a device interconnection system according to an exemplary embodiment;

[0073] Figure 12 is a flowchart illustrating a data processing method according to an exemplary embodiment;

[0074] Figure 13 is a structural diagram of a data processing apparatus according to an exemplary embodiment;

[0075] Figure 14 is a structural diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0076] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, in the embodiments of this application, "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0077] In related technologies, the architecture of a device interconnection system is shown in Figure 1. The processor is connected to the processor memory, and the processor is connected to multiple computing devices via a bus conforming to a preset protocol. The preset protocol can be the PCIe protocol, meaning that multiple computing devices are inserted into the host's PCIe slots respectively. The processor is responsible for starting the AI ​​computing program and scheduling different computing devices to perform calculations. The processor places the source data to be calculated in the host memory and then notifies the computing devices to read it. The computing devices read the source data through the bus conforming to the preset protocol, perform the calculations, and then write the calculation results back to the processor memory or other computing devices through the bus conforming to the preset protocol.

[0078] In actual computing scenarios, computation is performed by computing devices, and various data are stored in the processor's memory or the computing device's internal memory. Within the same host, various devices and memory exchange data via a bus conforming to a preset protocol (such as the PCIe bus). Figure 2 illustrates a computation process in an application scenario, including the following steps:

[0079] ① The processor writes the input data into the processor memory.

[0080] ② The computing device 1 reads input data from the processor memory through a bus conforming to a preset protocol, performs operations (convolution, pooling, etc.) on the hidden layer 1, and obtains the result data of the hidden layer 1.

[0081] ③ The computing device 2 reads the data of the hidden layer 1 from the computing device 1 through a bus that conforms to a preset protocol, performs operations (convolution, pooling, etc.) on the hidden layer 2, and obtains the result data of the hidden layer 2.

[0082] ④ The computing device 3 reads the data of the hidden layer 2 from the computing device 2 through a bus that conforms to a preset protocol, performs operations (convolution, pooling, etc.) on the hidden layer 3, and obtains the result data of the hidden layer 3.

[0083] ⑤ The computing device 4 reads the data from the hidden layer 3 from the computing device 3 through a bus conforming to a preset protocol, performs the final calculation, and obtains the final result data.

[0084] ⑥ The computing device 4 writes the result data to the processor memory via a bus conforming to a preset protocol.

[0085] In the above scheme, the computational load is distributed across multiple computing devices, enabling pipelined operations. For example, the processor can continuously provide new input data. While computing device 1 is performing hidden layer 1 operations on the current batch of data, computing device 2 is performing hidden layer 2 operations on the previous batch of data. And so on. At any given time, the computation scenario in Figure 2 can simultaneously process four batches of data, fully utilizing the computing power of the devices.

[0086] However, the above scheme encounters a problem during implementation: almost every step of data transfer (except for step ①) requires the use of the preset protocol bus. As the entire process becomes pipelined, there may be situations where four computing devices simultaneously request to use the preset protocol bus. In this case, the preset protocol bus becomes the bottleneck of the entire system. For example, one computing device may need to wait for the data transfer of the other three computing devices to be completed before it can start working, which greatly reduces the overall system's computing speed.

[0087] Taking the connection between a processor and a single computing device as an example, as shown in Figure 3, a computing device typically provides at least two base address registers (Bars) for the processor to access. One is the VRAM (Video Random Access Memory) Bar. After mapping the address of this Bar, the processor can directly read and write the contents of the memory on the computing device through address access. This can be simply referred to as the computing device memory, which includes page tables. The other is the register Bar. After mapping the address of this Bar, the processor can use it to read and write various configurations and operate various functions in the computing device, such as initiating data transfer, reading interrupt status, and restarting the device.

[0088] The computing device contains multiple functional modules. Among them, the Artificial Intelligence (AI) computing unit is responsible for performing AI calculations; the communication component (MailBox) assists other modules in communicating with the processor; the MCU (Micro Controller Unit) handles functions such as restarting and power management; the DMA (Direct Memory Access) data transfer module accesses the processor's memory via DMA; and the address translation unit helps other modules translate virtual addresses into physical addresses before accessing the computing device's memory or the processor's memory. The computing device also includes an interrupt management module and modules configured to assist the processor in accessing VRAM.

[0089] The processor includes a virtual memory space, mapped video random access memory, and mapped registers. The software running on the processor can be divided into three main parts. The KMD (Kernel Mode Driver) has the highest system privileges. The Linux DRM (Direct Rendering Manager) driver is responsible for memory management; the computing device driver is responsible for initialization tasks such as bar mapping and firmware loading; and the IOCTL (Input Output Control) driver assists the UMD (User Mode Driver) in address translation, allocating VRAM address segments for various functions, creating pages for the computing device, and writing them to VRAM to assist the computing units and MCU in accessing VRAM or host memory. The KMD also handles error interrupts. The UMD acts as an intermediate layer. Its runtime library provides APIs (Application Programming Interfaces) and device management to applications. The computing module is responsible for device management, creating data streams (queues), deploying computing models, and initiating computations. The address mapping module maps memory to the computing device. The application resides at the top layer, directly calling ordinary Glibc dynamic libraries and the APIs provided by the UMD to execute the computational tasks required by the user. This can include AI computing applications.

[0090] Figure 4 illustrates a simplified workflow of the relevant technical solution, including system startup, initialization, and computation. The initialization process includes: loading KMD; KMD performing basic initialization of the computing device, such as mapping the bar and loading firmware; starting the application; and calling interfaces provided by UMD, such as DeviceInitial, SetDevice, CreateEngine, CreateContext, StreamCreate, and DeployNetwork. It also allocates buffers in both processor memory and VRAM to store source and result data. The computation process includes: writing source data to processor memory; initiating computation by writing registers to notify the computing device to read source data from processor memory into VRAM; performing computation; waiting for the computing device to complete the computation; writing the result from VRAM to the result data buffer in processor memory; determining whether computation is complete; and exiting if computation is complete, otherwise returning to the step of writing source data to processor memory. It is evident that each initialization process consumes a relatively long time, but the number of executions is limited, so it has almost no impact on overall computing performance. The time consumed in each calculation process has a significant impact on the overall computing performance, because it is usually executed many times.

[0091] In the aforementioned device interconnection system, data transmission between the processor and computing devices, as well as between different computing devices, must be carried out through a bus that conforms to a preset protocol. This results in a high transmission load on the bus and low data transmission efficiency between different computing devices.

[0092] Therefore, this application adds a target port to the computing device, and different computing devices can be directly connected through the target port to transmit data directly, without having to go through the bus that connects to the processor and conforms to a preset protocol. This reduces the transmission pressure on the bus and improves the data transmission efficiency between different computing devices.

[0093] This embodiment discloses a device interconnection system, as shown in FIG5, including a processor and multiple computing devices. The processor is connected to the processor memory, the computing devices are connected to the computing device memory, and the processor and the multiple computing devices are connected through a bus conforming to a preset protocol.

[0094] Computing devices include target ports, through which different computing devices are directly connected and data is directly transmitted between them.

[0095] The processor memory and the memory of multiple computing devices are addressed using a unified addressing method. When the memory of a computing device is accessed, an address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0096] In this embodiment, the computing device can be a GPU (Graphics Processing Unit). Optionally, the computing device can be an FPGA (Field-Programmable Gate Array), which offers greater flexibility in implementation compared to a GPU. The processor and multiple computing devices are connected via a bus conforming to a preset protocol, which can be a PCIe bus. The processor is connected to processor memory, and each computing device is connected to its own computing device memory. In this embodiment, the processor memory and computing device memory can be DDR (Double Data Rate Synchronous Dynamic Random-Access Memory).

[0097] In this embodiment, a target port is added to the computing device. The target ports of different computing devices are directly connected through SUB (Super United Bus, a custom consistency interconnect bus). Different computing devices can directly transmit data through the target port via the SUB bus without going through the bus that connects to the processor and conforms to a preset protocol. This reduces the transmission pressure on the bus and improves the data transmission efficiency between different computing devices.

[0098] In some embodiments, the computing device includes a first target port and a second target port. The computing device receives data sent by other computing devices through the first target port and sends data to other computing devices through the second target port.

[0099] In some embodiments, two target ports can be set on each computing device, namely a first target port and a second target port. The first target port is set to receive data and the second target port is set to send data, which realizes port isolation between receiving data and sending data, and enables simultaneous receiving and sending of data, further improving the data transmission efficiency between different computing devices.

[0100] In some embodiments, the processor includes interconnected processor cores, port modules, and a first memory controller. The processor is connected to processor memory through the first memory controller. The port module includes multiple first ports conforming to a preset protocol. The computing device includes a second port conforming to a preset protocol, a target port, an address translation unit, a computing unit, and a second memory controller. The address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller. The computing device is connected to computing device memory through the second memory controller. The processor is connected to the second ports of different computing devices through the multiple first ports.

[0101] In some embodiments, the connection between a single computing device and the processor is shown in Figure 6. The processor includes a processor core, a port module, and a first memory controller, which are interconnected. The port module includes multiple first ports conforming to a preset protocol, configured to connect to multiple different computing devices respectively. The first memory controller is connected to the processor memory and configured to read and write data in the processor memory. The computing device includes a second port conforming to a preset protocol, a target port, a computing unit, and a second memory controller. The second port is connected to the corresponding first port in the processor and configured to perform data transmission with the processor. The target port is connected to other computing devices and configured to perform data transmission with other computing devices. An address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller. The address translation unit is configured to perform the conversion between virtual addresses and physical addresses. The computing unit is configured to perform data calculations using the received data. The second memory controller can be connected to other components via an internal bus interface. The second memory controller is connected to the computing device memory and configured to read and write data in the computing device memory.

[0102] It is understandable that processor memory and computing device memory belong to different internal buses, and their addresses are independent and unrelated, or they can be said to belong to different address spaces. However, during computation, the data stored in these memories needs to be transferred between them. To simplify data transfer, this embodiment adopts globally unified addressing, that is, allocating non-overlapping addresses for data stored in processor memory and data stored in computing device memory within the same address space. This simplifies address access and data transfer when writing processor applications, computing units of computing devices, and configuring programs running in address translation units.

[0103] In some embodiments, the processor further includes a unified addressing management module, which is configured to perform unified addressing on the processor memory and the memory of multiple computing devices; the computing devices further include a memory decoder, the computing unit is connected to a second port and a target port through the memory decoder, and the second memory controller is connected to the computing unit, the second port and the target port through the memory decoder, and the memory decoder is configured to perform address mapping between unified addressing and the internal address space of the computing device according to the usage scenario.

[0104] In some embodiments, a memory decoder is added inside the computing device, between the address translation unit and the internal bus interface. Its main function is to perform address mapping between the processor address space and the computing device address space, as well as between the address spaces of different computing devices. Simultaneously, an address mapping table is added to the computing device memory, including the correspondence between start source addresses and start destination addresses under different usage scenarios. The memory decoder performs address mapping based on this address mapping table. In the processor, a unified addressing management module is added to the user-mode driver. This module calls the interface provided by the memory decoder configuration driver to generate the address mapping table and configures the addresses in the address mapping table to the memory decoder.

[0105] In some embodiments, the memory decoder in the computing device is configured to: translate uniform addressing into an address on the device's internal bus when the processor accesses the computing device memory of the current computing device; translate uniform addressing into an address on the device's internal bus when a computing unit of the current computing device accesses the computing device memory of the current computing device; not perform address translation when a computing unit of the current computing device accesses the processor's memory; not perform address translation when a computing unit of the current computing device accesses the computing device memory of another computing device; and translate uniform addressing into an address on the device's internal bus when a computing unit of another computing device accesses the computing device memory of the current computing device.

[0106] In some embodiments, the memory decoder is responsible for handling address translation between address spaces and determining the access port in the following use cases:

[0107] ① When the processor accesses the memory of the computing device, it translates the unified address into an address on the device's internal bus and accesses the device's internal bus interface.

[0108] ② When the computing unit of the current computing device accesses the computing device memory of the current computing device, it will convert the unified addressing into an address on the device's internal bus and access the device's internal bus interface.

[0109] ③ When the computing unit of the current computing device accesses the processor memory, no address translation is performed, and the port that conforms to the preset protocol is accessed.

[0110] ④ When the computing unit of the current computing device accesses the computing memory of another computing device, no address translation is performed, and the target port is accessed.

[0111] ⑤ When the computing unit of another computing device (via the SUB bus) accesses the computing device memory of the current computing device, the unified address will be translated into an address on the device's internal bus, and the device's internal bus interface will be accessed.

[0112] The processor software writes the address mapping method into the address mapping table, and then configures the address of the address mapping table itself into the computing device by writing to registers. After obtaining the address of the address mapping table, the computing device reads the contents of the address mapping table and performs address translation, access port selection, and other configurations (such as whether to enable caching) based on the start and destination addresses in the table entries. It should be noted that the number of table entries is not necessarily the same as the number of use cases; multiple table entries can exist for the same use case. The source addresses of all table entries cannot overlap, so the table entries can be indexed using the source address.

[0113] For example, the address mapping table is shown in Table 1:

[0114] Table 1

[0115] It should be noted that not all addresses need to be added to Table 1; a base address plus offset can be used. For example, the address mapping table has an entry with a starting source address of 0x00010000, an address length of 0x00001000, and a starting destination address of 0. When an address is accessed at 0x00010800, since it falls within the range of 0x00010000 to 0x00011000, it will be matched by the above entry. Its address offset relative to the starting source address is 0x800, so the destination address is the starting destination address (0) plus 0x800.

[0116] It is evident that using a unified addressing system with a memory decoder and address mapping table simplifies memory management, making it easier for software engineers to coordinate processor programs and programs running in the computing units of computing devices, thus reducing the likelihood of problems.

[0117] This application embodiment adds a target port to the computing device. Different computing devices are directly connected and transmit data directly through the target port, eliminating the need for a bus conforming to a preset protocol connected to the processor. This reduces the transmission load on the bus and improves the data transmission efficiency between different computing devices. Furthermore, this application embodiment uses a unified addressing method to address the processor memory and the computing device memory. By mapping addresses between the unified addressing and the computing device's internal address space, the address access and data transmission methods are simplified.

[0118] This embodiment discloses a device interconnection system, as shown in FIG7, including a processor and multiple computing devices. The processor is connected to the processor memory, the computing devices are connected to the computing device memory, and the processor and the multiple computing devices are connected through a bus conforming to a preset protocol.

[0119] The computing device includes a target port. The (i-1)th computing device is connected to the ith computing device through the target port. 1 < i ≤ N, where N is the number of computing devices included in the device interconnection system.

[0120] The processor memory and the memory of multiple computing devices are addressed using a unified addressing method. When the memory of a computing device is accessed, an address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

[0121] In some embodiments, multiple computing devices are serially connected through a target port. For a single computing device, it only needs to receive data sent by one other computing device and only needs to send data to one other computing device, which reduces the amount of data transmitted between different computing devices, reduces the transmission pressure on the SUB bus between target ports, and further improves the data transmission efficiency between computing devices.

[0122] In some embodiments, the computing device includes a first target port and a second target port. The second target port of the (i-1)th computing device is connected to the first target port of the ith computing device. The (i-1)th computing device sends data to the ith computing device through the second target port of the (i-1)th computing device and the first target port of the ith computing device.

[0123] In some embodiments, two target ports can be set on each computing device, namely a first target port and a second target port. The first target port is set to receive data and the second target port is set to send data, which realizes port isolation between receiving data and sending data, and enables simultaneous receiving and sending of data, further improving the data transmission efficiency between different computing devices.

[0124] The following describes an application scenario of this embodiment. As shown in Figure 8, target port 1 of computing device 1 is connected to target port 0 of computing device 2, target port 1 of computing device 2 is connected to target port 0 of computing device 3, target port 1 of computing device 3 is connected to target port 0 of computing device 4, and target port 0 of computing device 1 and target port 1 of computing device 4 are left unused.

[0125] In some embodiments, the processor is configured to: write input data into the processor memory; the first computing device is configured to: acquire input data from the processor memory via a bus conforming to a preset protocol, perform calculations on the acquired data for its corresponding hidden layer to obtain result data, and store it in its corresponding computing device memory; the i-th computing device is configured to: acquire the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device via a target port, perform calculations on the acquired data for its corresponding hidden layer to obtain result data, and store it in its corresponding computing device memory; wherein, the N-th computing device writes the calculated result data as output data into the processor memory via a bus conforming to a preset protocol.

[0126] The coordinated calculation process of each computing device is as follows:

[0127] ① The processor writes the input data into the processor memory.

[0128] ② The computing device 1 reads input data from the processor memory through a bus conforming to a preset protocol, performs operations (convolution, pooling, etc.) on the hidden layer 1, and obtains the result data of the hidden layer 1.

[0129] ③ The computing device 2 reads the data of the hidden layer 1 from the computing device 1 through the SUB bus, performs operations (convolution, pooling, etc.) on the hidden layer 2, and obtains the result data of the hidden layer 2.

[0130] ④ The computing device 3 reads the data of the hidden layer 2 from the computing device 2 through the SUB bus, performs (convolution, pooling, etc.) operations on the hidden layer 3, and obtains the result data of the hidden layer 3.

[0131] ⑤ The computing device 4 reads the data from the hidden layer 3 from the computing device 3 via the SUB bus, performs the final calculation, and obtains the final result data.

[0132] ⑥ The computing device 4 writes the result data to the processor memory via a bus conforming to a preset protocol.

[0133] The computation flow of each computing unit in the computing device is shown in Figure 9. The circles represent data, and the arrows represent the relationships between the data and the computation process. The raw data is first stored in the input layer, and after computation through multiple hidden layers, the final calculation result is put into the output layer. The hidden layers can be convolutional layers, pooling layers, fully connected layers, or any one or a combination of other computational methods.

[0134] Taking the connection between a processor and a single computing device as an example, as shown in Figure 10, a computing device typically provides at least two base registers (Bars) for the processor to access. One is the VRAM (Video Random Access Memory) Bar. After mapping the address of this Bar, the processor can directly read and write the contents of the memory on the computing device through address access. This can be simply referred to as the computing device memory, which includes page tables and address mapping tables. The other is the register Bar. After mapping the address of this Bar, the processor can use it to read and write various configurations and operate various functions in the computing device, such as initiating data transfer, reading interrupt status, and restarting the device.

[0135] The computing device contains multiple functional modules. The Artificial Intelligence (AI) computing unit performs AI calculations; the communication component (MailBox) assists other modules in communicating with the processor; the MCU (Micro Controller Unit) handles functions such as restarting and power management; the DMA (Direct Memory Access) data transfer module accesses processor memory via DMA; and the address translation unit helps other modules translate virtual addresses into physical addresses before accessing the computing device's memory or processor memory. The computing device also includes an interrupt management module and a module configured to assist the processor in accessing VRAM. Furthermore, the computing device includes a memory decoder and a target port control module. The memory decoder performs address mapping between the processor's address space and the computing device's address space, as well as between the address spaces of different computing devices. The target port control module controls data transfer between different computing devices via the target port.

[0136] The processor includes a virtual memory space, mapped video random access memory, and mapped registers. The software running on the processor can be divided into three main parts. KMD has the highest system privileges. The Linux DRM driver is responsible for memory management; the computing device driver handles initialization tasks such as bar mapping and firmware loading; the IOCTL driver assists UMD in address translation, allocates VRAM address segments for various functions, creates pages for the computing device, and writes them to VRAM to assist the computing units and MCU in accessing VRAM or host memory. The memory decoder configuration driver assists UMD in configuring the memory decoder and related address mapping tables. KMD also handles error interrupts. UMD acts as an intermediate layer. The runtime library provides APIs and device management to applications. The computing module is responsible for device management, creating data streams (queues), deploying computing models, and initiating computations. The address mapping module maps memory to the computing device. The unified addressing management module calls the interface provided by the memory decoder configuration driver to generate an address mapping table and configure the addresses in the address mapping table to the memory decoder. The application resides at the top layer, directly calling ordinary Glibc dynamic libraries and APIs provided by UMD to execute the computational tasks required by the user. This can include AI computing applications.

[0137] The overall flowchart of the device interconnection system is shown in Figure 11, including system startup, initialization, and computation. The initialization process includes: loading KMD; KMD performing basic initialization of the computing devices, such as mapping the bar and loading firmware; starting the application; calling interfaces provided by UMD, such as DeviceInitial (device initialization), SetDevice (device setup), CreateEngine (engine creation), CreateContext (context creation), StreamCreate (stream creation), and DeployNetwork (network deployment); allocating buffers for storing source and result data in both processor memory and computing device memory; creating address hardware; and writing register configurations to the computing devices. The computation process includes: writing source data to processor memory; initiating computation for all computing devices sequentially; writing registers to notify computing devices to read source data from processor memory or other computing device memory; performing computation; waiting for the computing devices to complete their computations; writing the results from their own computing device memory to the result data buffers of other computing devices or processor memory; determining whether computation is complete; exiting if computation is complete; otherwise, returning to the step of writing source data to processor memory.

[0138] As can be seen, in this embodiment, multiple computing devices are serially connected through the target port, and each computing device performs streaming computing tasks. Data transmission between adjacent computing devices does not need to pass through the bus that connects to the processor and conforms to the preset protocol, which reduces the transmission pressure on the bus and improves the data transmission efficiency between adjacent computing devices.

[0139] This application discloses a data processing method applied to a computing device in a device interconnect system. The device interconnect system includes a processor and multiple computing devices. The processor is connected to processor memory, and the computing devices are connected to computing device memory. The processor and the multiple computing devices are connected through a bus conforming to a preset protocol. Each computing device includes a target port. The (i-1)th computing device is connected to the ith computing device through the target port, where 1 < i ≤ N, and N is the number of computing devices included in the device interconnect system.

[0140] Referring to Figure 12, a flowchart of a data processing method according to an exemplary embodiment is shown in Figure 12, including:

[0141] S101: The first computing device obtains input data from the processor memory through a bus conforming to a preset protocol, performs calculations on the obtained data in its corresponding hidden layer to obtain the result data, and stores it in its corresponding computing device memory;

[0142] S102: The i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs its own corresponding hidden layer calculation on the obtained data to obtain the result data, and stores it in its own corresponding computing device memory;

[0143] S103: The Nth computing device writes the calculated result data as output data into the processor memory via a bus conforming to a preset protocol.

[0144] In some embodiments, a first computing device acquires input data from the processor memory via a bus conforming to a preset protocol, performs calculations on the acquired data using its corresponding hidden layer using its computing units, obtains the result data, and stores it in its own computing device memory. The hidden layer of the computing unit can be any one or a combination of convolutional layers, pooling layers, fully connected layers, or other computational methods. The first computing device sends the calculated result data to the first target port of a second computing device via its second target port. The second computing device then performs calculations on the acquired data using its corresponding hidden layer using its computing units, obtains the result data, and stores it in its own computing device memory. This process continues until the Nth computing device calculates the result data and writes it as output data into the processor memory via a bus conforming to a preset protocol.

[0145] As can be seen, in this embodiment, multiple computing devices are serially connected through the target port, and each computing device performs streaming computing tasks. Data transmission between adjacent computing devices does not need to pass through the bus that connects to the processor and conforms to the preset protocol, which reduces the transmission pressure on the bus and improves the data transmission efficiency between adjacent computing devices.

[0146] Based on the above embodiments, in some embodiments, the processor memory and the memory of multiple computing devices are addressed using a unified addressing method; the method further includes: obtaining an address mapping table; wherein, the address mapping table includes the correspondence between the starting source address and the starting destination address under different usage scenarios; matching the corresponding target usage scenario in the address mapping table according to the target starting source address of the data access request; and determining the target starting destination address corresponding to the target starting source address according to the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table.

[0147] In some embodiments, a globally unified addressing system is used, meaning that non-overlapping addresses are allocated to data stored in the processor's memory and data stored in the computing device's memory within the same address space. This simplifies address access and data transfer when writing processor applications, computing units of the computing device, and configuring programs running in the address translation unit. The processor software writes the address mapping method into an address mapping table, including the correspondence between start source addresses and start destination addresses under different usage scenarios. Then, the address of the address mapping table itself is configured in the computing device by writing to registers. After obtaining the address of the address mapping table, the computing device reads the contents of the address mapping table and performs address translation, access port selection, and other configurations (such as whether to enable caching) based on the start and destination addresses in the table entries.

[0148] In some embodiments, if the target use case is the processor accessing the computing device memory of the current computing device, the target starting source address is determined according to the correspondence between the starting source address and the starting destination address in the address mapping table under the target use case, including: converting the target starting source address into an address on the device's internal bus as the target starting destination address.

[0149] In some embodiments, when the processor accesses the memory of the computing device, it translates the unified addressing into an address on the device's internal bus and accesses the device's internal bus interface. This use case can be applied to the step of "the first computing device obtaining input data from the processor's memory through a bus conforming to a preset protocol".

[0150] In some embodiments, if the target use case is the computing unit of the current computing device accessing the computing device memory of the current computing device, then the target starting source address corresponding to the target starting destination address is determined according to the correspondence between the starting source address and the starting destination address in the address mapping table under the target use case, including: converting the target starting source address into an address on the device's internal bus as the target starting destination address.

[0151] In some embodiments, when a computing unit of a current computing device accesses the computing device memory of the current computing device, it translates the unified addressing into an address on the device's internal bus and accesses the device's internal bus interface. This use case can be applied to the step of "the computing device storing the calculation result into its corresponding computing device memory".

[0152] In some embodiments, if the target usage scenario is that the computing unit of the current computing device accesses the processor memory, the target starting source address corresponding to the target starting destination address is determined according to the correspondence between the starting source address and the starting destination address in the address mapping table under the target usage scenario, including: directly using the target starting source address as the target starting destination address.

[0153] In some embodiments, when the computing unit of the current computing device accesses the processor memory, no address translation is performed, and the port conforming to a preset protocol is accessed. This use case can be applied to the step of "the Nth computing device writing the calculated result data as output data to the processor memory through a bus conforming to a preset protocol".

[0154] In some embodiments, if the target use case is that the computing unit of the current computing device accesses the computing device memory of another computing device, then the target starting source address corresponding to the target starting destination address is determined according to the correspondence between the starting source address and the starting destination address in the address mapping table under the target use case, including: directly using the target starting source address as the target starting destination address.

[0155] In some embodiments, when the computing unit of the current computing device accesses the computing memory of another computing device, no address translation is performed, and the target port is accessed. This use case can be applied to the step of "the i-th computing device obtaining the result data calculated by the i-1-th computing device from the computing memory of the (i-1)-th computing device through the target port".

[0156] In some embodiments, if the target use case is that the computing unit of another computing device accesses the computing device memory of the current computing device, then the target starting source address corresponding to the target starting destination address is determined according to the correspondence between the starting source address and the starting destination address in the address mapping table under the target use case, including: converting the target starting source address into an address on the device's internal bus as the target starting destination address.

[0157] In some embodiments, when a computing unit of another computing device (via the SUB bus) accesses the computing device memory of the current computing device, the unified address is translated into an address on the device's internal bus, and the device's internal bus interface is accessed. This use case can be applied to the step of "the i-th computing device obtaining the result data calculated by the i-1-th computing device from the computing device memory of the (i-1)-th computing device through the target port".

[0158] It is evident that using a unified addressing system with a memory decoder and address mapping table simplifies memory management, making it easier for software engineers to coordinate processor programs and programs running in the computing units of computing devices, thus reducing the likelihood of problems.

[0159] The following describes a data processing apparatus provided by an embodiment of this application. The data processing apparatus described below can be referred to in conjunction with the data processing method described above. The data processing apparatus provided in this embodiment is applied to a computing device in a device interconnect system. The device interconnect system includes a processor and multiple computing devices. The processor is connected to processor memory, and the computing devices are connected to computing device memory. The processor and the multiple computing devices are connected through a bus conforming to a preset protocol. Each computing device includes a target port. The (i-1)th computing device is connected to the ith computing device through the target port, where 1 < i ≤ N, and N is the number of computing devices included in the device interconnect system.

[0160] Referring to FIG13, a structural diagram of a data processing apparatus according to an exemplary embodiment is shown in FIG13, comprising:

[0161] The acquisition unit 100 is configured to acquire input data from the processor memory via a bus conforming to a preset protocol, or acquire result data calculated by other computing devices via a target port.

[0162] The computing unit 200 is configured to perform calculations on the acquired data using its corresponding hidden layer to obtain the result data, and store it in the memory of its corresponding computing device.

[0163] Output unit 300 is configured to write the calculated result data as output data to the processor memory via a bus conforming to a preset protocol.

[0164] As can be seen, in this embodiment, multiple computing devices are serially connected through the target port, and each computing device performs streaming computing tasks. Data transmission between adjacent computing devices does not need to pass through the bus that connects to the processor and conforms to the preset protocol, which reduces the transmission pressure on the bus and improves the data transmission efficiency between adjacent computing devices.

[0165] Based on the above embodiments, in some embodiments, the processor memory and the memory of multiple computing devices are addressed using a unified addressing method;

[0166] The device also includes:

[0167] The address mapping unit is configured to obtain an address mapping table; wherein the address mapping table includes the correspondence between the starting source address and the starting destination address under different usage scenarios; match the corresponding target usage scenario in the address mapping table according to the target starting source address of the data access request; and determine the target starting destination address corresponding to the target starting source address based on the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table.

[0168] Based on the above embodiments, in some embodiments, if the target usage scenario is that the processor accesses the computing device memory of the current computing device, the address mapping unit is set to: convert the target starting source address into an address on the device's internal bus as the target starting destination address.

[0169] Based on the above embodiments, in some embodiments, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of the current computing device, the address mapping unit is set to: convert the target starting source address into an address on the device's internal bus as the target starting destination address.

[0170] Based on the above embodiments, in some embodiments, if the target usage scenario is that the computing unit of the current computing device accesses the processor memory, the address mapping unit is set to: directly use the target starting source address as the target starting destination address.

[0171] Based on the above embodiments, in some embodiments, if the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of other computing devices, the address mapping unit is set to: directly use the target starting source address as the target starting destination address.

[0172] Based on the above embodiments, in some embodiments, if the target usage scenario is that the computing unit of another computing device accesses the computing device memory of the current computing device, the address mapping unit is set to: convert the target starting source address into an address on the device's internal bus as the target starting destination address.

[0173] Regarding the apparatus in the above embodiments, the optional ways in which each module performs operations have been described in detail in the embodiments of the method, and will not be elaborated here.

[0174] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiments of this application, the embodiments of this application also provide an electronic device. FIG14 is a structural diagram of an electronic device according to an exemplary embodiment. As shown in FIG14, the electronic device includes:

[0175] Communication interface 1 enables information exchange with other devices, such as network devices;

[0176] Processor 2, connected to communication interface 1 to enable information exchange with other devices, is configured to execute data processing methods provided by one or more of the aforementioned technical solutions when running a computer program. The computer program is stored in memory 3.

[0177] Of course, in practical applications, the various components in the electronic device are coupled together through bus system 4. It can be understood that bus system 4 is used to achieve communication between these components. In addition to the data bus, bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled as bus system 4 in Figure 14.

[0178] In this embodiment, memory 3 is configured to store various types of data to support the operation of the electronic device. Examples of such data include any computer program used to operate on the electronic device.

[0179] It is understood that memory 3 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 3 described in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0180] The methods disclosed in the embodiments of this application can be applied to processor 2, or implemented by processor 2. Processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 2 or by instructions in the form of software. The processor 2 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the aforementioned method in combination with its hardware.

[0181] When processor 2 executes the program, it implements the corresponding processes in the various methods of the embodiments of this application. For the sake of brevity, these will not be described in detail here.

[0182] In an exemplary embodiment, this application also provides a non-volatile storage medium, which may be a non-volatile readable storage medium storing a computer program that can be executed by a processor 2 to complete the aforementioned method steps.

[0183] In an exemplary embodiment, this application also provides a computer program product, including a computer program that is executed by a processor 2 to perform the aforementioned method steps.

[0184] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to computer program instructions. The aforementioned computer program can be stored in a non-volatile storage medium, and when executed, it performs the steps of the above method embodiments. Alternatively, if the integrated units of this application are implemented as software functional modules and sold or used as independent products, they can also be stored in a non-volatile storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a non-volatile storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, network device, etc.) to execute all or part of the methods of the various embodiments of this application.

[0185] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A device interconnection system, characterized in that, It includes a processor and multiple computing devices, wherein the processor is connected to processor memory, the computing devices are connected to computing device memory, and the processor and the multiple computing devices are connected via a bus conforming to a preset protocol; The computing device includes a target port, through which different computing devices are directly connected and data is directly transmitted between them. The processor memory and the multiple computing device memories are addressed using a unified addressing method. When the computing device memory is accessed, address mapping is performed between the unified addressing and the internal address space of the computing device through the corresponding computing device.

2. The device interconnection system according to claim 1, characterized in that, The computing device includes a first target port and a second target port. The computing device receives data sent by other computing devices through the first target port and sends data to other computing devices through the second target port.

3. The device interconnection system according to claim 1, characterized in that, The processor includes interconnected processor cores, port modules, and a first memory controller. The processor is connected to the processor memory through the first memory controller. The port module includes multiple first ports conforming to a preset protocol. The computing device includes a second port conforming to a preset protocol, a target port, an address translation unit, a computing unit, and a second memory controller. The address translation unit is connected to the computing unit, the second port, the target port, and the second memory controller. The computing device is connected to the computing device memory through the second memory controller. The processor is connected to the second ports of different computing devices through multiple first ports.

4. The device interconnection system according to claim 3, characterized in that, The processor also includes a unified addressing management module, which is configured to perform unified addressing of the processor memory and the memory of the multiple computing devices. The computing device further includes a memory decoder. The computing unit connects to the second port and the target port through the memory decoder. The second memory controller connects to the computing unit, the second port, and the target port through the memory decoder. The memory decoder is configured to perform address mapping between the unified addressing and the internal address space of the computing device according to the usage scenario.

5. The device interconnection system according to claim 4, characterized in that, The memory decoder in the computing device is configured as follows: When the processor accesses the computing device memory of the current computing device, it translates the unified addressing into an address on the device's internal bus; When the computing unit of the current computing device accesses the computing device memory of the current computing device, the unified addressing is translated into an address on the internal bus of the device; When the computing unit of the current computing device accesses the processor memory, no address translation is performed; When the computing unit of the current computing device accesses the computing memory of another computing device, no address translation is performed; When a computing unit of another computing device accesses the computing device memory of the current computing device, the unified addressing is translated into an address on the internal bus of the device.

6. The device interconnection system according to claim 1, characterized in that, The computing device is a field-programmable gate array (FPGA).

7. The device interconnection system according to claim 1, characterized in that, The (i-1)th computing device is connected to the ith computing device, 1 < i ≤ N, where N is the number of computing devices included in the device interconnection system.

8. The device interconnection system according to claim 7, characterized in that, The computing device includes a first target port and a second target port. The second target port of the (i-1)th computing device is connected to the first target port of the ith computing device. The (i-1)th computing device sends data to the ith computing device through the second target port of the (i-1)th computing device and the first target port of the ith computing device.

9. The device interconnection system according to claim 7, characterized in that, The processor is configured to write input data into the processor memory; The first computing device is configured to: acquire input data from the processor memory via a bus conforming to a preset protocol, perform calculations on the acquired data for its corresponding hidden layer to obtain result data, and store it in its corresponding computing device memory; The i-th computing device is configured to: obtain the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, perform calculations on the obtained data for its own corresponding hidden layer to obtain the result data, and store it in its own corresponding computing device memory; The Nth computing device writes the calculated result data as output data into the processor memory via a bus conforming to a preset protocol.

10. A data processing method, characterized in that, A computing device is applied to a device interconnection system, the device interconnection system includes a processor and multiple computing devices, the processor is connected to processor memory, the computing devices are connected to computing device memory, the processor and the multiple computing devices are connected through a bus conforming to a preset protocol, each computing device includes a target port, the (i-1)th computing device is connected to the ith computing device through the target port, 1 < i ≤ N, and N is the number of computing devices included in the device interconnection system; The method includes: The first computing device obtains input data from the processor memory through a bus conforming to a preset protocol, performs calculations on the obtained data in its corresponding hidden layer to obtain result data, and stores it in its corresponding computing device memory; The i-th computing device obtains the result data calculated by the i-1-th computing device from the computing device memory of the i-1-th computing device through the target port, performs its own corresponding hidden layer calculation on the obtained data to obtain the result data, and stores it in its own corresponding computing device memory; The Nth computing device writes the calculated result data as output data into the processor memory via a bus conforming to a preset protocol.

11. The data processing method according to claim 10, characterized in that, The processor memory and the multiple computing device memories are addressed using a unified addressing method; The method further includes: Obtain the address mapping table; wherein, the address mapping table includes the correspondence between the starting source address and the starting destination address under different usage scenarios; Match the corresponding target use case in the address mapping table according to the target originating source address of the data access request; Based on the correspondence between the starting source address and the starting destination address in the target usage scenario described in the address mapping table, the target starting source address corresponding to the target starting destination address is determined.

12. The data processing method according to claim 11, characterized in that, If the target usage scenario is that the processor accesses the computing device memory of the current computing device, then according to the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table, the target starting source address corresponding to the target starting destination address is determined, including: The target starting source address is converted into an address on the device's internal bus as the target starting destination address.

13. The data processing method according to claim 11, characterized in that, If the target usage scenario is that the computing unit of the current computing device accesses the computing device memory of the current computing device, then according to the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table, the target starting source address corresponding to the target starting destination address is determined, including: The target starting source address is converted into an address on the device's internal bus as the target starting destination address.

14. The data processing method according to claim 11, characterized in that, If the target usage scenario involves the computing unit of the current computing device accessing the processor memory, then based on the correspondence between the starting source address and the starting destination address in the address mapping table under the target usage scenario, the target starting source address is determined, including: The target starting source address is directly used as the target starting destination address.

15. The data processing method according to claim 11, characterized in that, If the target usage scenario involves the computing unit of the current computing device accessing the computing memory of another computing device, then based on the correspondence between the starting source address and the starting destination address under the target usage scenario in the address mapping table, the target starting source address corresponding to the target starting destination address is determined, including: The target starting source address is directly used as the target starting destination address.

16. The data processing method according to claim 11, characterized in that, If the target usage scenario involves a computing unit of another computing device accessing the computing memory of the current computing device, then based on the correspondence between the starting source address and the starting destination address in the address mapping table under the target usage scenario, the target starting source address is determined, including: The target starting source address is converted into an address on the device's internal bus as the target starting destination address.

17. A data processing apparatus, characterized in that, A computing device is applied to a device interconnection system, the device interconnection system includes a processor and multiple computing devices, the processor is connected to processor memory, the computing devices are connected to computing device memory, the processor and the multiple computing devices are connected through a bus conforming to a preset protocol, each computing device includes a target port, the (i-1)th computing device is connected to the ith computing device through the target port, 1 < i ≤ N, and N is the number of computing devices included in the device interconnection system; The acquisition unit is configured to acquire input data from the processor memory via a bus conforming to a preset protocol, or acquire result data calculated by other computing devices via the target port. The computing unit is configured to perform calculations on the acquired data using its corresponding hidden layer to obtain the result data, and then store it in the memory of its corresponding computing device. The output unit is configured to write the calculated result data as output data into the processor memory via a bus conforming to a preset protocol.

18. An electronic device, characterized in that, include: The memory is configured to store computer programs; The processor is configured to implement the steps of the data processing method as described in any one of claims 10 to 16 when executing the computer program.

19. A non-volatile storage medium, characterized in that, The non-volatile storage medium stores a computer program, which, when executed, implements the steps of the data processing method as described in any one of claims 10 to 16.

20. A computer program product, characterized in that, It includes a computer program that, when executed, implements the steps of the data processing method as described in any one of claims 10 to 16.

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