Device bandwidth allocation system and method, device, medium and product

Abstract

Provided in the embodiments of the present application are a device bandwidth allocation system and method, a device, a medium and a product. The system comprises a target device and a central processing unit, wherein a weak potential sensing amplification circuit and a channel induced electric field register are provided on a slot of the target device, the slot supporting a number of channels corresponding to the type of the target device, and the channel induced electric field register being connected to the central processing unit; the weak potential sensing amplification circuit is used for, upon detecting an alternating voltage across channels at two ends of the target device, measuring an induced electromotive force corresponding to each channel, and, on the basis of the induced electromotive force, determining an induced voltage state corresponding to each channel; the channel induced electric field register is used for storing the value of the induced voltage state corresponding to each channel; the central processing unit reads the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and, on the basis of values of induced voltage states in the channel induced electric field register within target bandwidths, determines a bandwidth allocation state of each channel.

Description

Equipment bandwidth allocation systems, methods, equipment, media and products

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411488160.5, filed on October 24, 2024, entitled “Equipment Bandwidth Allocation System, Method, Apparatus, Medium and Product”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of server technology, and in particular to a device bandwidth allocation system, method, device, medium and product. Background Technology

[0004] Server motherboards typically use PCIe (Peripheral Component Interconnect express) slots, specifically PCIe x8 and PCIe x16 slots, to facilitate the installation of various expansion cards. Even if an expansion card has x2 or x4 contacts, it can still be plugged into a PCIe x8 or PCIe x16 slot. However, currently, the CPU directly provides the maximum bandwidth to PCIe x8 and PCIe x16 slots, resulting in wasted PCIe resources and CPU performance loss. For example, two PCIe x8 devices cannot be plugged into two PCIe x16 slots, preventing the use of a single x16 slot for two x8 devices. Furthermore, automatic PCIe recognition and bandwidth allocation are not possible.

[0005] Currently, PCIe automatic bandwidth allocation uses an expansion processor instead of GPIO (General-purpose input / output) for dynamic bandwidth configuration. However, this method requires adding a bandwidth allocation table to the non-configuration program, using the expansion processor or physical resistor to detect changes. After obtaining the data, the values ​​need to be matched with the pre-set bandwidth allocation table and the corresponding number of lanes. Then, the central processing unit analyzes and allocates the corresponding bandwidth. In the early stage, it is necessary to collect data from different expansion cards to simulate and build the table. The types and models of the expansion cards are fixed. If an expansion card that is not in the table is inserted, there will be identification errors. When using it, the table needs to be matched, resulting in low efficiency of overall bandwidth identification and allocation. Summary of the Invention

[0006] The purpose of this application is to provide a device bandwidth allocation system, method, device, medium, and product, the specific technical solution of which is as follows:

[0007] In a first aspect of this application, a device bandwidth allocation method is provided. The device bandwidth allocation system includes a target device and a central processing unit. A weak potential sensing amplifier circuit and a channel sensing electric field register are provided on the slot of the target device. The slot supports a number of channels based on the type of the target device. The channel sensing electric field register is connected to the central processing unit.

[0008] The weak potential induction amplifier circuit is used to detect the induced electromotive force corresponding to each channel when an alternating voltage is detected at both ends of the target device, and to determine the induced voltage state corresponding to each channel based on the induced electromotive force.

[0009] The channel-induced electric field register is used to store the value of the induced voltage state corresponding to each channel;

[0010] The central processing unit reads the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0011] In some embodiments, the weak potential sensing amplifier circuit is an analog voltage amplifier circuit based on gate circuits.

[0012] In some embodiments, the weak potential sensing amplifier circuit includes several NOT gates connected in series and several NOT gates connected in parallel with the target resistor.

[0013] In some embodiments, each channel includes four signal lines, including a transmit positive signal line, a transmit negative signal line, a receive positive signal line, and a receive negative signal line.

[0014] In some embodiments, the induced voltage state includes any one of a negative voltage state, a positive voltage state, and a state without induced voltage.

[0015] In some embodiments, the channels at both ends of the target device include a first channel and a second channel. The state of no induced voltage is determined by the first channel and the second channel being assigned to different PCIe devices to generate a non-closed electric field.

[0016] In a second aspect of this application, a device bandwidth allocation method is also provided, applied to any device bandwidth allocation system of the first aspect, the method comprising:

[0017] When alternating voltage is detected at both ends of the target device, the induced electromotive force corresponding to each channel is detected, the induced voltage state corresponding to each channel is determined based on the induced electromotive force, and the value of the induced voltage state corresponding to each channel is stored.

[0018] Read the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determine the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0019] In some embodiments, determining the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth includes:

[0020] According to the preset bandwidth allocation rules, determine whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent, and output the bandwidth allocation status of each channel.

[0021] In some embodiments, the target bandwidth includes a first bandwidth, a second bandwidth, a third bandwidth, a fourth bandwidth, and a fifth bandwidth.

[0022] In some embodiments, the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are sequentially determined according to a preset bandwidth allocation rule to determine whether they are consistent, and the bandwidth allocation state of each channel is output, including:

[0023] Determine whether the induced voltage states in the channel induced electric field register within the first bandwidth are consistent;

[0024] If the induced voltage states in the channel induced electric field registers within the first bandwidth are inconsistent, then determine whether the induced voltage states in the channel induced electric field registers within the second bandwidth are consistent, wherein the second bandwidth is smaller than the first bandwidth.

[0025] If the induced voltage states in the channel induced electric field registers within the second bandwidth are inconsistent, then determine whether the induced voltage states in the channel induced electric field registers within the third bandwidth are consistent, wherein the third bandwidth is smaller than the second bandwidth.

[0026] If the induced voltage states in the channel induced electric field registers within the third bandwidth are inconsistent, then determine whether the induced voltage states in the channel induced electric field registers within the fourth bandwidth are consistent, where the fourth bandwidth is smaller than the third bandwidth.

[0027] If the induced voltage states in the channel induced electric field registers within the fourth bandwidth are inconsistent, then the two channels corresponding to the fourth bandwidth will be allocated to the fifth bandwidth, and the bandwidth allocation state of each channel will be the fifth bandwidth, wherein the fifth bandwidth is less than the fourth bandwidth.

[0028] In some embodiments, before the step of detecting the induced electromotive force corresponding to each channel and determining the induced voltage state corresponding to each channel based on the induced electromotive force when an alternating voltage is detected at both ends of the target device, the method includes:

[0029] Apply alternating voltages in opposite directions to the positive signal line corresponding to any first channel and the negative signal line corresponding to any second channel, respectively.

[0030] If the first channel and the second channel correspond to the same target device, then the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel generate an effective closed electric field.

[0031] If the first channel and the second channel correspond to different target devices, then the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel will generate an invalid non-closed electric field.

[0032] In some embodiments, after the step of generating an effective closed electric field on the positive signal line corresponding to the first channel and the negative signal line corresponding to the second channel if the first channel and the second channel correspond to the same target device, the method includes:

[0033] Target-induced magnetic field is generated based on an effectively closed electric field;

[0034] The induced electromotive force corresponding to each channel is obtained through a weak potential induction amplifier circuit in the target induced magnetic field.

[0035] In a third aspect of this application, a device bandwidth allocation apparatus is also provided, the apparatus comprising:

[0036] The first module is used to detect the induced electromotive force corresponding to each channel when an alternating voltage is detected at both ends of the target device, determine the induced voltage state corresponding to each channel based on the induced electromotive force, and store the value of the induced voltage state corresponding to each channel.

[0037] The second module is used to read the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determine the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0038] In a fourth aspect of this application, a communication device is also provided, comprising: a transceiver, a memory, a processor, and a program stored in the memory and executable on the processor;

[0039] A processor for reading programs from memory to implement device bandwidth allocation methods as described in any of the first aspects.

[0040] In a fifth aspect of this application, a computer non-volatile readable storage medium is also provided, wherein instructions are stored in the computer, which, when executed on a computer, cause the computer to implement the device bandwidth allocation method as described in any of the first aspects.

[0041] In a sixth aspect of this application, a computer program product is also provided, including a computer program / instructions that, when executed by a processor, implement the bandwidth allocation method of any device in the first aspect.

[0042] The device bandwidth allocation system provided in this application includes a target device and a central processing unit (CPU). The target device's slot is equipped with a weak potential sensing amplifier circuit and a channel sensing electric field register. The slot supports a number of channels corresponding to the target device type. The channel sensing electric field register is connected to the CPU. The weak potential sensing amplifier circuit detects the induced electromotive force (EMF) corresponding to each channel when alternating voltage is detected at both ends of the target device, and determines the induced voltage state of each channel based on the induced EMF. The channel sensing electric field register stores the value of the induced voltage state corresponding to each channel. The CPU reads the value of the induced voltage state corresponding to each channel from the channel sensing electric field register and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel sensing electric field register within the target bandwidth. The detection mechanism in this application is stable and reliable; it does not require GPIO resources or additional IIC (Inter-Integrated Circuit) communication interfaces. It achieves fully automated and intelligent identification and allocation of bandwidth for server PCIe devices. Each device only needs a weak potential sensing amplification circuit on each PCIe lane to detect the presence of an induced electromotive force in that lane and write the corresponding induced voltage state value into the induced electric field register. By applying an alternating voltage to the lanes across each PCIe Port x16 and detecting whether the state of the lane induced electric field register within its bandwidth is consistent, the bandwidth allocation for each lane is ultimately determined. This results in more accurate and faster bandwidth allocation, avoiding the need for verification using an intermediate bandwidth allocation table, thus improving bandwidth allocation efficiency. This allows multiple devices to be plugged into a single PCIe slot without being affected by bandwidth differences, avoiding the small error that can occur when directly sampling the voltage value of the PCIe slot. This also improves the accuracy of the CPU in identifying PCIe devices and in allocating bandwidth. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0044] Figure 1 is a schematic diagram of a device bandwidth allocation system provided in an embodiment of this application;

[0045] Figure 2 is a flowchart of a device bandwidth allocation method provided in an embodiment of this application;

[0046] Figure 3 is a device block diagram of a device bandwidth allocation apparatus provided in an embodiment of this application;

[0047] Figure 4 is a schematic diagram of a communication device provided in an embodiment of this application;

[0048] Figure 5 is a circuit connection diagram of a weak potential induction amplifier circuit provided in an embodiment of this application;

[0049] Figure 6 is a schematic diagram of the current and magnetic field direction of an alternating voltage between each lane provided in an embodiment of this application;

[0050] Figure 7 is a schematic diagram of the gate circuit transfer characteristic curve provided in an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable readers to better understand this application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0052] It should be noted that, in order to facilitate a better understanding of this application by those skilled in the art, the relevant technologies are described in the embodiments of this application before the overall technical solution is described.

[0053] First, Faraday's law of electromagnetic induction states that the induced electromotive force in a closed loop is proportional to the rate of change of the magnetic flux through that loop. Although it describes a phenomenon caused by a change in magnetic flux, Maxwell's equations show that a changing magnetic field also produces an electric field, thus indirectly leading to the generation of an induced electromotive force.

[0054] Second, the eddy current effect: In an alternating electric field, if a conductor (such as a metal block) is placed within that field, the change in the electric field will induce eddy currents, i.e., eddy currents, within the conductor. These eddy currents generate their own magnetic fields, which interact with the original electric field's magnetic field, leading to energy loss and heat generation.

[0055] Third, electromagnetic heating: using the eddy current effect generated by an alternating electric field, conductors can be heated in a non-contact manner. This principle is widely used in electromagnetic induction heating equipment, such as induction furnaces and induction hardening.

[0056] Fourth, wireless power transfer: Alternating electric fields and the resulting alternating magnetic fields can be used for wireless power transfer, such as wireless charging technology, in which the transmitter generates an alternating electric field, and the coil in the receiver induces a current, thereby realizing the wireless transfer of energy.

[0057] Fifth, communication technology: In wireless communication, antennas transmit information by transmitting and receiving alternating electric fields (and accompanying magnetic fields). For example, Wi-Fi, Bluetooth, and cellular networks are all based on this principle.

[0058] PCIe represents a fundamental shift in bus architecture, primarily in two aspects: first, it changed from a parallel bus to a serial bus; second, it adopted point-to-point interconnection. The single bus connecting devices under a bridge in the original parallel bus architecture was transformed into a link. A link can contain one or more paths, each consisting of two pairs of differential signal lines forming a double-simplex serial transmission channel. There are no dedicated data, address, control, or clock lines; various transactions on the bus are organized into information packets for transmission. PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect the central processing unit (CPU) and various expansion cards, such as graphics cards, sound cards, and network adapters. PCIe bandwidth is closely related to its version and the number of lanes. The following is detailed information on different versions of PCIe and their bandwidth:

[0059] PCIe 1.0: The online bit transfer rate is 2.5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 1.0x1 is 250MB / s.

[0060] PCIe 2.0: The online bit transfer rate doubles to 5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 2.0x1 is 500MB / s.

[0061] PCIe 3.0: The online bit transfer rate is 8Gb / s, using 128 / 130 encoding, therefore the bandwidth of PCIe 3.0x1 is 1GB / s.

[0062] PCIe 4.0: Online bit transfer rate increased to 16GT / s.

[0063] PCIe 5.0: The maximum bit transfer rate on the line can reach 32GT / s.

[0064] Furthermore, PCIe bandwidth is also related to the number of lanes. For example, the theoretical maximum bandwidth of a PCIe x1 slot is 1GB / s, suitable for devices with low data transfer requirements; the theoretical maximum bandwidth of a PCIe x4 slot is 4GB / s, suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of a PCIe x8 slot is 8GB / s, suitable for devices with higher data transfer speed requirements; and the PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s, widely used to connect high-performance graphics cards.

[0065] Therefore, in this embodiment, in the alternating induced magnetic field generated by the alternating electric field, each PCIe lane of the central processing unit is equivalent to cutting magnetic field lines. Since the direction of the magnetic poles inside the closed magnetic field is opposite to the direction of the magnetic poles outside the closed magnetic field at the same time, the direction of the induced electromotive force of lanes (HSOn(1) and HSOp(N)) and Lane2-LaneN-1 inside the closed magnetic field is opposite to the direction of the induced electromotive force of lanes (LaneM and other lanes) outside the closed magnetic field at the same time. Each PCIe lane of the central processing unit is designed with a weak potential induction amplifier circuit. Whether there is an induced electromotive force on this lane, the corresponding induced voltage state: 0x00 (negative voltage), 0x01 (positive voltage), 0xFF (no induced voltage) value will be written into the induced electric field register. Therefore, by applying alternating voltage to the lanes at both ends of each PCIe Port X16, the state of the lane-induced electric field register within the X16 bandwidth is detected to see if they are consistent. If the state of the lane-induced electric field register is consistent, the bandwidth of that Port is allocated as X16. If the state of the lane-induced electric field register is inconsistent, alternating voltage is applied to the lanes at both ends of each X8 of that Port to detect them. The state of the lane-induced electric field register within the X8 bandwidth is read to see if they are consistent. If the state of the lane-induced electric field register is still inconsistent, the detection operation for lanes X4 and X2 is performed in the same way. If the state of the induced electric field register is still inconsistent when detecting the lane state of X2, both lanes of X2 are allocated as X1, and the bandwidth allocation of each lane is finally determined.

[0066] Referring to Figure 1, the device bandwidth allocation system includes: a target device and a central processing unit. The slot of the target device is equipped with a weak potential sensing amplifier circuit and a channel sensing electric field register. The slot supports a number of channels based on the type of the target device. The channel sensing electric field register is connected to the central processing unit.

[0067] The weak potential induction amplifier circuit is used to detect the induced electromotive force corresponding to each channel when an alternating voltage is detected at both ends of the target device, and to determine the induced voltage state corresponding to each channel based on the induced electromotive force.

[0068] The channel-induced electric field register is used to store the value of the induced voltage state corresponding to each channel;

[0069] The central processing unit reads the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0070] In some embodiments, each channel includes four signal lines, including a transmit positive signal line, a transmit negative signal line, a receive positive signal line, and a receive negative signal line.

[0071] It should be noted that, in the embodiments of this application, the target device includes the target PCIe device, and the final bandwidth allocation status of each channel is determined by the central processing unit. During the power-on process, the CPU (Central Processing Unit) can read the value of the induced voltage status corresponding to each channel in the channel induced electric field register by loading the BIOS (Basic Input Output System) code, and determine the bandwidth allocation status of each channel based on the value of the induced voltage status in the channel induced electric field register within the target bandwidth.

[0072] It should be noted that, referring to Figure 6, which is a schematic diagram of the current and magnetic field direction of the alternating voltage between each lane according to an embodiment of this application, each lane in the PCIe slot has four lines (HSOp, HSOn, HSIp, HSIn), where p is positive and n is negative. Specifically, the transmit (Tx) pairs are: HSOp: High Speed ​​Output Positive, transmitting a positive signal line, and HSOn: High Speed ​​Output Negative, transmitting a negative signal line. The receive (Rx) pairs are: HSIp: High Speed ​​Input Positive, receiving a positive signal line, and HSIn: High Speed ​​Input Negative, receiving a negative signal line. Therefore, each pair of differential signal lines constitutes a lane.

[0073] In Figure 6, alternating voltages in opposite directions are applied to HSOp(1) and HSOn(N) with a period of f. During the first half-period (0-f / 2), the voltage of HSOp(1) changes from 0 to VCC, and the voltage of HSOn(N) changes from VCC to 0. During the second half-period (f / 2-f), the voltage of HSOp(1) changes from VCC to 0, and the voltage of HSOn(N) changes from 0 to VCC. Assuming that Lane1 and LaneN are assigned to the same PCIe device, HSOp(1) and HSOn(N) can form an effective closed electric field. According to the right-hand rule, during the first half-period (0-f / 2), the direction of the magnetic field is from the outside to the inside, as shown in the figure. During the second half-period (f / 2-f), the direction of the magnetic field is from the inside to the outside, as shown in the figure. If Lane1 and LaneN are not assigned to the same PCIe device, a closed electric field cannot be effectively generated, nor can a corresponding induced magnetic field be generated.

[0074] In some embodiments, the induced voltage state includes any one of a negative voltage state, a positive voltage state, and a state without induced voltage.

[0075] In some embodiments, the channels at both ends of the target device include a first channel and a second channel. The state of no induced voltage is determined by the first channel and the second channel being assigned to different PCIe devices to generate a non-closed electric field.

[0076] In the alternating induced magnetic field generated by the alternating electric field, each PCIe lane of the central processing unit is equivalent to cutting magnetic field lines. Since the direction of the magnetic poles inside the closed magnetic field is opposite to the direction of the magnetic poles outside the closed magnetic field at the same time, the direction of the induced electromotive force of lanes (HSOn(1) and HSOp(N)) and Lane2-LaneN-1 inside the closed magnetic field is opposite to the direction of the induced electromotive force of lanes (LaneM and other lanes) outside the closed magnetic field at the same time.

[0077] Each PCIe lane in the central processing unit is designed with a weak potential sensing amplifier circuit. Whether there is an induced electromotive force on this lane will be determined by writing the corresponding induced voltage state: 0x00 (negative voltage), 0x01 (positive voltage), 0xFF (no induced voltage) value into the lane induced electric field register.

[0078] In Figure 1, each PCIe Port X16 slot is equipped with a weak potential induction amplifier circuit and a lane induction electric field register. The lane induction electric field register is connected to the central processing unit, and the central processing unit reads the amplified induced electromotive force state written in the lane induction electric field register.

[0079] In some embodiments, the weak potential sensing amplifier circuit is an analog voltage amplifier circuit based on gate circuits.

[0080] In some embodiments, the weak potential sensing amplifier circuit includes several NOT gates connected in series and several NOT gates connected in parallel with the target resistor.

[0081] It should be noted that, in this embodiment, the weak potential sensing amplifier circuit is shown in Figure 5 below. This circuit is an analog voltage amplifier circuit composed of gate circuits, consisting of three NOT gates D1, D2, and D3 connected in series, with a large resistor R2 connected in parallel across the three NOT gates. Here, Ui is the input alternating voltage, Uo is the output alternating voltage, R1 is the input resistor, and R2 is the feedback bias resistor, biasing the operating point of the three NOT gates near 1 / 2VDD.

[0082] The amplification factor of the circuit is A = R2 / R1. If the parameters R1 = 10K and R2 = 1M are set, then the amplification factor A = 100 times.

[0083] The working principle of a weak potential induction amplifier circuit: The output characteristic curve of a gate circuit, also known as the transfer characteristic curve, is shown in Figure 7. From this curve, we can see a relatively steep section in the middle. This section (the part enclosed by the dashed line AB in Figure 7) is called the state transition region of the NOT gate circuit. The voltage input corresponding to the midpoint Q of this curve is called the state transition voltage, denoted by UT. Generally, UT is UDD / 2, that is, half of the power supply voltage. In the transition region, because the curve is relatively steep, even a small change in the input voltage will cause a large change in the output voltage. Therefore, the NOT gate has a voltage amplification effect in the state transition region. This region is also called the linear amplification region. Here, we use the characteristics of this region to form an amplifier using gate circuits to amplify the signal.

[0084] As can be seen from Figure 7, the state transition region of the gate circuit is very small, namely segment AB in the figure. If the input signal cannot enter this region, the amplifier will not be able to amplify or will cause severe distortion of the amplified signal.

[0085] In transistor amplifiers, a suitable bias circuit is needed to amplify the input signal without distortion. Similarly, amplifiers composed of gate circuits also require appropriate static bias. This biasing method typically involves biasing the input terminal at point Q on the curve, i.e., at half the operating supply voltage UDD, where the circuit's dynamic range for the input signal is maximized.

[0086] Therefore, an alternating voltage is applied to the lanes at both ends of each PCIe Port X16, and the state of the lane-induced electric field register within the X16 bandwidth is detected to see if they are consistent. If the state of the lane-induced electric field registers is consistent, the bandwidth of the Port is allocated to X16. If the state of the lane-induced electric field registers is inconsistent, an alternating voltage is applied to the lanes at both ends of each X8 of the Port to detect them, and the state of the lane-induced electric field register within the X8 bandwidth is read to see if they are consistent. If the state of the lane-induced electric field registers is still inconsistent, the detection operation of lanes X4 and X2 is performed in the same way. If the state of the lane-induced electric field register is still inconsistent when detecting the lane state of X2, both lanes of X2 are allocated to X1, and the bandwidth allocation of each lane is finally determined.

[0087] The device bandwidth allocation system provided in this application includes a target device and a central processing unit (CPU). The target device's slot is equipped with a weak potential sensing amplifier circuit and a channel sensing electric field register. The slot supports a number of channels corresponding to the target device type. The channel sensing electric field register is connected to the CPU. The weak potential sensing amplifier circuit detects the induced electromotive force (EMF) corresponding to each channel when alternating voltage is detected at both ends of the target device, and determines the induced voltage state of each channel based on the induced EMF. The channel sensing electric field register stores the value of the induced voltage state corresponding to each channel. The CPU reads the value of the induced voltage state corresponding to each channel from the channel sensing electric field register and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel sensing electric field register within the target bandwidth. The detection mechanism in this application is stable and reliable; it does not require GPIO resources or additional IIC or other communication interfaces. It achieves fully automated and intelligent identification and allocation of bandwidth for server PCIe devices. Only a weak potential sensing amplifier circuit on each PCIe lane of each device is needed to determine whether an induced EMF exists on that lane, and the corresponding induced voltage state value will be written to the sensing electric field register. By applying alternating voltages to the lanes at both ends of each PCIe Port X16, the system detects whether the state of the lane-induced electric field register within its bandwidth is consistent, ultimately determining the bandwidth allocation for each lane. This results in more accurate and faster bandwidth allocation, avoiding the need for verification using an intermediate bandwidth allocation table, thus improving bandwidth allocation efficiency. This allows multiple devices to be plugged into a single PCIe slot without being affected by bandwidth differences. It also avoids the small error that can occur when directly sampling the voltage values ​​of the PCIe slot, improving the accuracy of the CPU in identifying PCIe devices and in allocating bandwidth.

[0088] Referring to Figure 2, a flowchart of the steps of the device bandwidth allocation method provided in this application embodiment is shown. The method may include:

[0089] Step 101: When alternating voltage is detected at both ends of the target device, the induced electromotive force corresponding to each channel is detected, the induced voltage state corresponding to each channel is determined based on the induced electromotive force, and the value of the induced voltage state corresponding to each channel is stored.

[0090] Step 102: Read the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determine the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0091] In some embodiments, determining the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth includes:

[0092] According to the preset bandwidth allocation rules, determine whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent, and output the bandwidth allocation status of each channel.

[0093] In some embodiments, the target bandwidth includes a first bandwidth, a second bandwidth, a third bandwidth, a fourth bandwidth, and a fifth bandwidth.

[0094] In some embodiments, the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are sequentially determined according to a preset bandwidth allocation rule to determine whether they are consistent, and the bandwidth allocation state of each channel is output, including:

[0095] Determine whether the induced voltage states in the channel induced electric field register within the first bandwidth are consistent;

[0096] If the induced voltage states in the channel induced electric field registers within the first bandwidth are inconsistent, then determine whether the induced voltage states in the channel induced electric field registers within the second bandwidth are consistent, wherein the second bandwidth is smaller than the first bandwidth.

[0097] If the induced voltage states in the channel induced electric field registers within the second bandwidth are inconsistent, then determine whether the induced voltage states in the channel induced electric field registers within the third bandwidth are consistent, wherein the third bandwidth is smaller than the second bandwidth.

[0098] If the induced voltage states in the channel induced electric field registers within the third bandwidth are inconsistent, then determine whether the induced voltage states in the channel induced electric field registers within the fourth bandwidth are consistent, where the fourth bandwidth is smaller than the third bandwidth.

[0099] If the induced voltage states in the channel induced electric field registers within the fourth bandwidth are inconsistent, then the two channels corresponding to the fourth bandwidth will be allocated to the fifth bandwidth, and the bandwidth allocation state of each channel will be the fifth bandwidth, wherein the fifth bandwidth is less than the fourth bandwidth.

[0100] It should be noted that, in the embodiments of this application, the first bandwidth, the second bandwidth, the third bandwidth, the fourth bandwidth, and the fifth bandwidth are X16, X8, X4, X2, and X1, respectively.

[0101] An alternating voltage is applied to the lanes at both ends of each PCIe Port X16, and the state of the lane-induced electric field register within the X16 bandwidth is detected to see if they are consistent. If the state of the lane-induced electric field register is consistent, the bandwidth of the Port is allocated to X16. If the state of the lane-induced electric field register is inconsistent, an alternating voltage is applied to the lanes at both ends of each X8 of the Port to detect them, and the state of the lane-induced electric field register within the X8 bandwidth is read to see if they are consistent. If the state of the lane-induced electric field register is still inconsistent, the detection operation for lanes X4 and X2 is performed in the same way. If the state of the lane-induced electric field register is still inconsistent when detecting the lane state of X2, both lanes of X2 are allocated to X1, and the bandwidth allocation of each lane is finally determined.

[0102] In some embodiments, before the step of detecting the induced electromotive force corresponding to each channel and determining the induced voltage state corresponding to each channel based on the induced electromotive force when an alternating voltage is detected at both ends of the target device, the method includes:

[0103] Apply alternating voltages in opposite directions to the positive signal line corresponding to any first channel and the negative signal line corresponding to any second channel, respectively.

[0104] If the first channel and the second channel correspond to the same target device, then the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel generate an effective closed electric field.

[0105] If the first channel and the second channel correspond to different target devices, then the positive signal transmission line corresponding to the first channel and the negative signal transmission line corresponding to the second channel will generate an invalid non-closed electric field.

[0106] It should be noted that, in the embodiments of this application, the weak potential sensing amplifier circuit on each PCIe LAN determines whether the state of the sensing electric field register of each lane is consistent by identifying the consistency of the state of the lane sensing electric field register, and then determines whether the same device is plugged into adjacent lanes.

[0107] In some embodiments, after the step of generating an effective closed electric field on the positive signal line corresponding to the first channel and the negative signal line corresponding to the second channel if the first channel and the second channel correspond to the same target device, the method includes:

[0108] Target-induced magnetic field is generated based on an effectively closed electric field;

[0109] The induced electromotive force corresponding to each channel is obtained through a weak potential induction amplifier circuit in the target induced magnetic field.

[0110] The detection mechanism in this application is stable and reliable; it does not require GPIO resources or additional communication interfaces such as IIC. It achieves fully automated and intelligent identification and allocation of bandwidth for server PCIe devices. Each device only needs a weak potential sensing amplifier circuit on each PCIe lane to detect the presence of an induced electromotive force in that lane, writing the corresponding induced voltage state value into the induced electric field register. By applying an alternating voltage to the lanes at both ends of each PCIe Port X16, the consistency of the lane induced electric field register state within its bandwidth is detected, ultimately determining the bandwidth allocation for each lane. This results in more accurate and faster bandwidth allocation, avoiding the need for intermediate bandwidth allocation tables for verification, improving bandwidth allocation efficiency, and enabling multiple devices to be plugged into a single PCIe slot without being affected by bandwidth limitations. It also avoids the small errors associated with directly sampling the voltage values ​​of the PCIe slot, improving the accuracy of the central processing unit's identification of PCIe devices and the accuracy of bandwidth allocation.

[0111] Referring to Figure 3, this application embodiment also provides a device bandwidth allocation apparatus, the apparatus comprising:

[0112] The first module 301 is used to detect the induced electromotive force corresponding to each channel when an alternating voltage is detected at both ends of the target device, determine the induced voltage state corresponding to each channel based on the induced electromotive force, and store the value of the induced voltage state corresponding to each channel.

[0113] The second module 302 reads the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0114] The device bandwidth allocation apparatus provided in this application embodiment has a stable and reliable detection mechanism; it does not require GPIO resources or additional IIC or other communication interfaces. It achieves fully automated and intelligent identification and allocation of bandwidth for server PCIe devices. Each device only needs a weak potential sensing amplifier circuit on each PCIe lane to detect the presence of an induced electromotive force in that lane, writing the corresponding induced voltage state value into the induced electric field register. By applying an alternating voltage to the lanes at both ends of each PCIe Port X16, the consistency of the lane induced electric field register state within its bandwidth is detected, ultimately determining the bandwidth allocation for each lane. This results in more accurate and faster bandwidth allocation, avoiding the need for intermediate bandwidth allocation tables for verification, improving bandwidth allocation efficiency, and enabling multiple devices to be plugged into a single PCIe slot without being affected by bandwidth limitations. It also avoids the small errors associated with directly sampling the voltage values ​​of the PCIe slot, improving the accuracy of the central processing unit's identification of PCIe devices and the accuracy of bandwidth allocation.

[0115] This application embodiment also provides a communication device, as shown in FIG4, including a processor 401, a communication interface 402, a memory 403, and a communication bus 404, wherein the processor 401, the communication interface 402, and the memory 403 communicate with each other through the communication bus 404.

[0116] Memory 403 is used to store computer programs;

[0117] When processor 401 executes the program stored in memory 403, it can perform the following steps:

[0118] When alternating voltage is detected at both ends of the target device, the induced electromotive force corresponding to each channel is detected, the induced voltage state corresponding to each channel is determined based on the induced electromotive force, and the value of the induced voltage state corresponding to each channel is stored.

[0119] Read the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determine the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

[0120] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and the memory. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor can be transmitted over a wired medium or wirelessly via an antenna, which further receives and transmits data to the processor. The processor manages the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. The memory can be used to store data used by the processor during operation.

[0121] The communication bus mentioned above can be a PCI (Peripheral Component Interconnect) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0122] The communication interface is used for communication between the aforementioned terminal and other devices.

[0123] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0124] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0125] In another embodiment provided in this application, a computer non-volatile readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform any of the device bandwidth allocation methods described in the above embodiments.

[0126] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the device bandwidth allocation methods described in the above embodiments.

[0127] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer non-volatile readable storage medium or transmitted from one computer non-volatile readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer non-volatile readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0128] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0129] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0130] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A device bandwidth allocation system, characterized in that, The device bandwidth allocation system includes a target device and a central processing unit. The slot of the target device is equipped with a weak potential sensing amplifier circuit and a channel sensing electric field register. The slot supports a number of channels based on the type of the target device. The channel sensing electric field register is connected to the central processing unit. The weak potential sensing amplifier circuit is configured to detect the induced electromotive force corresponding to each channel when an alternating voltage is detected at both ends of the target device, and determine the induced voltage state corresponding to each channel based on the induced electromotive force. The channel induced electric field register is configured to store the value of the induced voltage state corresponding to each channel; The central processing unit reads the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determines the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

2. The system according to claim 1, characterized in that, The weak potential sensing amplifier circuit is an analog voltage amplifier circuit based on gate circuits.

3. The system according to claim 2, characterized in that, The weak potential sensing amplifier circuit includes several NOT gates connected in series, and several NOT gates connected in parallel with the target resistor.

4. The system according to claim 1, characterized in that, Each of the channels includes four signal lines, namely a transmit positive signal line, a transmit negative signal line, a receive positive signal line, and a receive negative signal line.

5. The system according to claim 4, characterized in that, The induced voltage state includes any one of the following: negative voltage state, positive voltage state, and no induced voltage state.

6. The system according to claim 5, characterized in that, The target device has two channels, including a first channel and a second channel. The state of no induced voltage is determined by the first channel and the second channel being distributed to different devices to generate a non-closed electric field.

7. The system according to claim 1, characterized in that, The channel is composed of each pair of differential signals.

8. The system according to claim 1, characterized in that, The central processing unit is configured to read the amplified induced electromotive force state written to the channel induced electric field register.

9. The system according to claim 1, characterized in that, The target device includes a target PCIe device.

10. The system according to claim 4, characterized in that, The positive signal line and the negative signal line are subjected to alternating voltages in opposite directions.

11. The system according to claim 3, characterized in that, The operating point of the NOT gate is biased at the state transition voltage, which is half of the operating power supply voltage.

12. A method for allocating device bandwidth, characterized in that, Applied to the device bandwidth allocation system according to any one of claims 1-11, the method includes: When alternating voltage is detected at both ends of the target device, the induced electromotive force corresponding to each channel is detected, the induced voltage state corresponding to each channel is determined based on the induced electromotive force, and the value of the induced voltage state corresponding to each channel is stored. Read the value of the induced voltage state corresponding to each channel in the channel induced electric field register, and determine the bandwidth allocation state of each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth.

13. The method according to claim 12, characterized in that, The determination of the bandwidth allocation state for each channel based on the value of the induced voltage state in the channel induced electric field register within the target bandwidth includes: According to the preset bandwidth allocation rules, determine whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent, and output the bandwidth allocation status of each channel.

14. The method according to claim 13, characterized in that, The target bandwidth includes a first bandwidth, a second bandwidth, a third bandwidth, a fourth bandwidth, and a fifth bandwidth.

15. The method according to claim 14, characterized in that, The step of determining whether the values ​​of the induced voltage states in the channel induced electric field registers within different target bandwidths are consistent according to the preset bandwidth allocation rules, and outputting the bandwidth allocation state of each channel includes: Determine whether the induced voltage state in the channel induced electric field register within the first bandwidth is consistent; If the induced voltage states in the channel induced electric field registers within the first bandwidth are inconsistent, then determine whether the induced voltage states in the channel induced electric field registers within the second bandwidth are consistent, wherein the second bandwidth is smaller than the first bandwidth. If the induced voltage states in the channel induced electric field registers within the second bandwidth are inconsistent, then it is determined whether the induced voltage states in the channel induced electric field registers within the third bandwidth are consistent, wherein the third bandwidth is smaller than the second bandwidth. If the induced voltage states in the channel induced electric field registers within the third bandwidth are inconsistent, then it is determined whether the induced voltage states in the channel induced electric field registers within the fourth bandwidth are consistent, wherein the fourth bandwidth is smaller than the third bandwidth. If the induced voltage states in the channel induced electric field registers within the fourth bandwidth are inconsistent, then the two channels corresponding to the fourth bandwidth are allocated to the fifth bandwidth, and the bandwidth allocation state of each channel is the fifth bandwidth, wherein the fifth bandwidth is less than the fourth bandwidth.

16. The method according to claim 12, characterized in that, Before the step of detecting the induced electromotive force corresponding to each channel when an alternating voltage is detected at both ends of the target device, and determining the induced voltage state corresponding to each channel based on the induced electromotive force, the method includes: Apply alternating voltages in opposite directions to the positive signal line corresponding to any first channel and the negative signal line corresponding to any second channel, respectively. If the first channel and the second channel correspond to the same target device, then the positive signal line corresponding to the first channel and the negative signal line corresponding to the second channel generate an effective closed electric field. If the first channel and the second channel correspond to different target devices, then the positive signal line corresponding to the first channel and the negative signal line corresponding to the second channel generate an invalid non-closed electric field.

17. The method according to claim 16, characterized in that, After the step of generating an effective closed electric field by the positive signal line corresponding to the first channel and the negative signal line corresponding to the second channel if the first channel and the second channel correspond to the same target device, the method includes: A target induced magnetic field is generated based on the aforementioned effective closed electric field; The induced electromotive force corresponding to each channel is obtained in the target induced magnetic field through a weak potential induction amplifier circuit.

18. A communication device, characterized in that, include: A transceiver, a memory, a processor, and a program stored in the memory and executable on the processor; The processor is configured to read a program from the memory to implement the device bandwidth allocation method as described in any one of claims 12 to 17.

19. A non-volatile readable storage medium configured to store a program, characterized in that, When the program is executed by the processor, it implements the device bandwidth allocation method as described in any one of claims 12 to 17.

20. A computer program product comprising instructions stored on a non-transitory, computer-readable storage medium, which, when executed by a computer, implement the device bandwidth allocation method as described in any one of claims 12 to 17.

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