Silicon carbide power device cell structure and preparation method therefor, and semiconductor device

Abstract

The present application belongs to the technical field of semiconductors. Disclosed are a silicon carbide power device cell structure and a preparation method therefor, and a semiconductor device. A silicon carbide power device comprises a substrate, source structures, a gate structure, and electric-field shielding structures, wherein the gate structure is disposed in the substrate; the source structures are disposed on the substrate and surround at least part of side faces of the gate structure; and the electric-field shielding structures are disposed in the substrate, surround the bottom of the gate structure and are connected to the source structures. The present application can redistribute to the electric-field shielding structures an electric field of a gate dielectric layer of a silicon carbide semiconductor device cell structure in a reverse blocking state, so as to maximize the shielding effect, thereby reducing the electric field of the gate dielectric layer, such that the semiconductor device has high reliability.

Description

Cell structure and fabrication method of silicon carbide power devices, semiconductor devices

[0001] This application claims priority to Chinese Patent Application No. 202411492977.X, filed on October 23, 2024, entitled "Silicon Carbide Power Device and Preparation Method Thereof, Semiconductor Device", the entire contents of which are incorporated herein by reference.

[0002] This application claims priority to Chinese Patent Application No. 202411495509.8, filed on October 23, 2024, entitled "Cellular Structure of Silicon Carbide Power Device and Preparation Method Thereof, Semiconductor Device", the entire contents of which are incorporated herein by reference.

[0003] This application claims priority to Chinese Patent Application No. 202411489677.6, filed on October 23, 2024, entitled "Silicon Carbide Power Device Cell and Preparation Method Thereof, Semiconductor Device", the entire contents of which are incorporated herein by reference.

[0004] This application claims priority to Chinese Patent Application No. 202411491146.0, filed on October 23, 2024, entitled "Cellular Structure of Silicon Carbide Power Device and Preparation Method Thereof, Semiconductor Device", the entire contents of which are incorporated herein by reference. Technical Field

[0005] This application relates to the field of semiconductor technology, and in particular to a silicon carbide power device cell structure and its fabrication method, and a semiconductor device. Background Technology

[0006] Silicon carbide semiconductors have superior properties such as wide bandgap, high thermal conductivity, high breakdown field strength, and high electron saturation velocity, and have been widely used in power devices.

[0007] When silicon carbide power devices are in reverse blocking mode, the high breakdown field strength of silicon carbide makes the gate dielectric layer easily broken down, leading to a decrease in the performance of the silicon carbide power devices or even failure. In related technologies, an electric field shielding structure is usually wrapped around the trench gate in the drift region of the epitaxial layer. The electric field shielding structure is used to withstand the voltage of the silicon carbide power device in reverse blocking mode, thereby reducing the electric field of the gate dielectric layer.

[0008] However, the shielding effect of the above-mentioned electric field shielding structure is poor. Summary of the Invention

[0009] In view of the above problems, this application provides a silicon carbide power device cell structure and its fabrication method, as well as a semiconductor device. When the silicon carbide power device is in reverse blocking state, it can distribute the electric field of the gate dielectric layer to the electric field shielding layer, thereby helping to reduce the electric field strength of the gate dielectric layer in the reverse blocking state of the silicon carbide power device, thereby improving the reliability of the gate dielectric layer and improving the shielding effect. At the same time, the silicon carbide power device can further reduce the cell size and reduce the forward conduction resistance, thereby ensuring the performance and reliability of the semiconductor device.

[0010] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0011] The first aspect of this application provides a silicon carbide power device cell structure, including:

[0012] Base;

[0013] A gate structure, wherein the gate structure is disposed within the substrate;

[0014] A source structure disposed on the substrate and surrounding at least a portion of the sidewalls of the gate structure;

[0015] An electric field shielding structure is disposed within the substrate, wherein the electric field shielding structure surrounds the bottom of the gate structure and is connected to the source structure.

[0016] A second aspect of this application provides a method for fabricating a silicon carbide power device cell structure, comprising the following steps:

[0017] Provide a base;

[0018] A source structure is formed, wherein the source structure is disposed on the substrate;

[0019] An electric field shielding structure and a gate structure are formed within the substrate, the source structure surrounds at least a portion of the sidewalls of the gate structure, and the electric field shielding structure surrounds the bottom of the gate structure and is connected to the source structure.

[0020] A third aspect of this application provides a semiconductor device including the silicon carbide power device cell structure described in the first aspect.

[0021] This application provides a silicon carbide power device cell structure and its fabrication method, as well as a semiconductor device. An electric field shielding structure surrounds the gate structure and is connected to the source structure. This effectively distributes the electric field of the gate dielectric layer onto the electric field shielding layer, thereby helping to reduce the electric field in the reverse blocking state of the silicon carbide power device. It prevents the electric field from accumulating at the bottom of the gate dielectric layer, improving the reliability of the gate dielectric layer and avoiding gate structure failure due to gate dielectric layer breakdown. This ensures the performance and reliability of the gate structure, further guaranteeing the performance and reliability of the semiconductor device.

[0022] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, the silicon carbide power device cell structure and its preparation method, other technical problems that semiconductor devices can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 is a schematic diagram of the silicon carbide power device provided in the first embodiment of this application;

[0025] Figure 2 is a schematic diagram of the structure of the silicon carbide power device provided in the first embodiment of this application;

[0026] Figure 3 is a cross-sectional view along the AA direction in Figure 1;

[0027] Figure 4 is another cross-sectional view along the AA direction in Figure 1;

[0028] Figure 5 is a cross-sectional view along the BB direction in Figure 2;

[0029] Figure 6 is a cross-sectional view along the CC direction in Figure 2;

[0030] Figure 7 is a process flow diagram of the method for fabricating silicon carbide power devices provided in the first embodiment of this application;

[0031] Figure 8 shows the arrangement of an electric field shielding layer and a gate structure provided in the first embodiment of this application;

[0032] Figure 9 shows another arrangement of the electric field shielding layer and gate structure provided in the first embodiment of this application;

[0033] Figure 10 is a schematic diagram of the cell structure of the silicon carbide power device provided in the second embodiment of this application;

[0034] Figure 11 is a cross-sectional view along the AA direction in Figure 10;

[0035] Figure 12 is a cross-sectional view along the BB direction in Figure 10;

[0036] Figure 13 is a cross-sectional view along the CC direction in Figure 10;

[0037] Figure 14 is a cross-sectional view along the DD direction in Figure 10;

[0038] Figure 15 is a schematic diagram of the cell structure of the silicon carbide power device provided in the second embodiment of this application;

[0039] Figure 16 is a cross-sectional view along the EE direction in Figure 15;

[0040] Figure 17 is a cross-sectional view along the FF direction in Figure 15;

[0041] Figure 18 is a diagram showing the arrangement of the cell structure of the silicon carbide power device provided in the second embodiment of this application.

[0042] Figure 19 is a second arrangement diagram of the cell structure of the silicon carbide power device provided in the second embodiment of this application;

[0043] Figure 20 is a process flow diagram of the method for fabricating the cell structure of silicon carbide power devices provided in the second embodiment of this application;

[0044] Figure 21 is a schematic diagram of the formation of gate trenches in the method for fabricating the cell structure of silicon carbide power devices provided in the second embodiment of this application;

[0045] Figure 22 is a schematic diagram of the cell structure of the silicon carbide power device provided in the third embodiment of this application;

[0046] Figure 23 is a cross-sectional view along the AA direction in Figure 22;

[0047] Figure 24 is a cross-sectional view along the BB direction in Figure 23;

[0048] Figure 25 is a process flow diagram of the method for fabricating the cell structure of silicon carbide power devices provided in the third embodiment of this application;

[0049] Figure 26 is a schematic diagram of the part of the method for fabricating the cell structure of silicon carbide power device provided in the third embodiment of this application, in which the protruding structure is formed.

[0050] Figure 27 is a schematic diagram of the formation of the protruding structure in the method for fabricating the cell structure of the silicon carbide power device provided in the third embodiment of this application;

[0051] Figure 28 is a schematic diagram of the formation of the source structure in the method for fabricating the cell structure of the silicon carbide power device provided in the third embodiment of this application;

[0052] Figure 29 is a schematic diagram of the second gate trench on the first cross-section in the method for fabricating the cell structure of the silicon carbide power device provided in the third embodiment of this application;

[0053] Figure 30 is a schematic diagram of the second gate trench on the second cross section in the method for fabricating the cell structure of the silicon carbide power device provided in the third embodiment of this application;

[0054] Figure 31 is a schematic diagram of the formation of the first gate trench in the method for fabricating the cell structure of the silicon carbide power device provided in the third embodiment of this application;

[0055] Figure 32 illustrates the formation of the gate structure in the method for fabricating the cell structure of a silicon carbide power device according to the third embodiment of this application.

[0056] Figure 33 is a schematic diagram of the structure of a silicon carbide power device cell provided in the fourth embodiment of this application;

[0057] Figure 34 is a top view of a second type of silicon carbide power device cell provided in the fourth embodiment of this application;

[0058] Figure 35 is a cross-sectional view of a second type of silicon carbide power device cell provided in the fourth embodiment of this application;

[0059] Figure 36 is a top view of a third type of silicon carbide power device cell provided in the fourth embodiment of this application;

[0060] Figure 37 is a cross-sectional view along the AA direction in Figure 36;

[0061] Figure 38 is a cross-sectional view along the BB direction in Figure 36;

[0062] Figure 39 is a process flow diagram of the first method for fabricating silicon carbide power device cells provided in the fourth embodiment of this application;

[0063] Figure 40 is a schematic diagram of the formation of the first source structure material layer in the first method for fabricating silicon carbide power device cells provided in the fourth embodiment of this application;

[0064] Figure 41 is a schematic diagram of the formation of a gate trench in the first method for fabricating a silicon carbide power device cell provided in the fourth embodiment of this application;

[0065] Figure 42 is a schematic diagram of the formation of the gate structure in the first method for fabricating silicon carbide power device cells provided in the fourth embodiment of this application;

[0066] Figure 43 is a schematic diagram of the formation of a sub-gate structure in the first method for fabricating silicon carbide power device cells provided in the fourth embodiment of this application;

[0067] Figure 44 is a schematic diagram of the formation of an insulating layer in the first method for fabricating silicon carbide power device cells provided in the fourth embodiment of this application;

[0068] Figure 45 is a schematic diagram of the formation of the ohmic contact layer and the source electrode layer in the first method for fabricating silicon carbide power device cells provided in the fourth embodiment of this application. Detailed Implementation

[0069] Currently, trench-gate silicon carbide (SiC) power devices, compared to planar-gate SiC power devices, have smaller cell sizes and higher channel mobility, resulting in lower forward on-resistance. Therefore, trench-gate SiC power devices are gradually becoming the future development direction for SiC power devices and are widely used in various semiconductor device fields. However, the reliability of the gate dielectric layer in trench-gate SiC power devices is relatively poor. When the trench-gate SiC power device is in reverse blocking mode, the electric field of the gate dielectric layer is mainly concentrated at the bottom of the trench, making the gate dielectric layer prone to breakdown and thus affecting the reliability of the trench-gate SiC power device.

[0070] In related technologies, to protect the gate dielectric layer and improve the reliability of trench-gate silicon carbide semiconductor devices, an electric field shielding structure is typically formed in the epitaxial layer through high-temperature ion implantation. This electric field shielding structure blocks the electric field in the epitaxial layer when the silicon carbide power device is in reverse blocking mode. However, in these technologies, the shielding effect of the electric field shielding structure is poor. Moreover, setting an electric field shielding layer in a trench gate structure requires high-energy ion implantation, which is difficult to process and increases epitaxial defects. Furthermore, the presence of the electric field shielding layer prevents further reduction in the individual cell size, hindering further reduction in the forward conduction resistance of the silicon carbide power device and thus affecting its performance.

[0071] To address the aforementioned technical problems, this application provides a silicon carbide power device and its fabrication method, as well as a semiconductor device, in which an electric field shielding layer surrounds the bottom of the gate structure and is connected to the source structure. This maximizes the distribution of the electric field from the gate dielectric layer onto the electric field shielding layer, thereby helping to reduce the electric field in the reverse blocking state of the silicon carbide power device. It prevents the electric field from accumulating at the bottom of the gate dielectric layer, improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure due to gate dielectric layer breakdown. This ensures the performance and reliability of the gate structure, further guaranteeing the performance and reliability of the semiconductor device.

[0072] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0073] This application provides a silicon carbide power device cell structure that can be applied to semiconductor devices. This embodiment primarily uses a trench-gate silicon carbide power device as an example. Referring to Figures 1 to 45, the silicon carbide power device cell structure includes a substrate 100.

[0074] Gate structure 200 is disposed within substrate 100.

[0075] A source structure 300 is disposed on a substrate 100 and surrounds at least a portion of the side surface of the gate structure 200.

[0076] An electric field shielding structure is disposed within the substrate 100, wherein the electric field shielding structure surrounds the bottom of the gate structure 200 and is connected to the source structure 300.

[0077] In this way, the electric field of the gate dielectric layer can be distributed to the electric field shielding layer to the maximum extent, which helps to reduce the electric field of silicon carbide power devices in reverse blocking state. It can prevent the electric field from accumulating at the bottom of the gate dielectric layer, improve the reliability of the gate dielectric layer, avoid the problem of gate structure failure caused by the breakdown of the gate dielectric layer, and thus ensure the performance and reliability of the gate structure, and further ensure the performance and reliability of semiconductor devices.

[0078] This application also provides a method for fabricating the cell structure of a silicon carbide power device. This method is used to fabricate the silicon carbide power device cell structure described in the above embodiments, and includes the following steps:

[0079] Provide a base;

[0080] A source structure is formed, and the source structure is disposed on the substrate;

[0081] An electric field shielding structure and a gate structure are formed within a substrate. The source structure surrounds at least a portion of the sidewalls of the gate structure, and the electric field shielding structure surrounds the bottom of the gate structure and is connected to the source structure.

[0082] It should be noted that, given that this preparation method is used to prepare the silicon carbide power device cell structure described in the above embodiments, it possesses all the structure and beneficial effects of the silicon carbide power device cell structure, and will not be described in detail here.

[0083] It should also be noted that the electric field shielding structure surrounding the bottom of the gate structure 200 can be implemented in various ways, and the following will describe in detail the different implementation methods.

[0084] As shown in Figures 1 to 6, the silicon carbide power device in Embodiment 1 includes a substrate 100.

[0085] Referring to Figures 3 to 6, the substrate 100 includes a substrate 110. The substrate 110 serves as a support component for the silicon carbide power device, supporting other components disposed thereon. The substrate 110 may be made of a semiconductor material. For example, the material of the substrate 110 may include silicon carbide.

[0086] The front side of the substrate 110 is provided with an epitaxial layer 120 of a first conductivity type, and the back side of the substrate 110 is provided with a drain electrode layer. Here, the front side of the substrate 110 refers to the upper surface of the substrate 110, and the back side of the substrate 110 refers to the lower surface of the substrate 110.

[0087] It should be noted that the doping concentration of the epitaxial layer 120 is not limited in this embodiment, and can be prepared according to actual needs. Furthermore, the conductivity type of the epitaxial layer 120 is not limited. For example, the conductivity type of the epitaxial layer 120 can be either the first conductivity type N-type, or the second conductivity type P-type.

[0088] In this embodiment, the first conductivity type epitaxial layer 120 is mainly described as the first conductivity type N-type.

[0089] Referring to Figures 1 to 6, a silicon carbide power device may include a gate structure 200 disposed within a substrate 110, such that the gate structure 200 forms a trench gate. Compared to planar gate semiconductor devices, trench gate semiconductor devices can have smaller cell sizes and higher channel mobility. Therefore, trench gate silicon carbide power devices significantly reduce the resistance during forward conduction, thereby improving the performance of the silicon carbide power device.

[0090] Referring to Figures 3 to 6, the gate structure 200 includes a gate 210 and a gate dielectric layer 220, with the gate dielectric layer 220 covering the bottom and side surfaces of the gate 210. In the specific fabrication process, a first conductivity type epitaxial layer 120 can be grown on the substrate 110 firstly, and then a gate trench can be formed by patterning and etching on the first conductivity type epitaxial layer 120. Subsequently, the gate dielectric layer 220 is formed on the inner wall of the gate trench using thermal oxidation or deposition processes, followed by the formation of the gate 210, which fills the area enclosed by the gate dielectric layer 220. Thus, the gate dielectric layer 220 covers the bottom and side surfaces of the gate 210. The gate dielectric layer 220 is made of silicon oxide. The gate 210 is made of polysilicon.

[0091] In this embodiment, the number of gate structures 200 is not limited. For example, there may be multiple gate structures 200; the number of gate structures 200 may include two; or, the number of gate structures 200 may include five; or, the number of gate structures 200 may include more than one. This embodiment does not limit this.

[0092] In this configuration, multiple gate structures 200 are spaced apart along a second direction, which may intersect the extension direction of each gate structure 200. For example, each gate structure 200 extends along a first direction. Taking the orientation shown in Figures 1 and 2 as an example, the first direction can be the Y direction in Figures 1 and 2, and correspondingly, the second direction can be the X direction in Figures 1 and 2.

[0093] This facilitates the arrangement of multiple gate structures 200 and increases the space occupied by the gate structure 200 in the cell structure, thereby increasing the conduction channel area of ​​the gate structure 200 during the operation of the silicon carbide power device, and thus effectively reducing the channel resistance.

[0094] Referring to FIG5, the silicon carbide power device includes a source structure 300 disposed within a substrate 100. The source structure 300 surrounds at least a portion of the sidewalls of the gate structure 200, thereby forming a channel region between the source structure 300 and the gate structure 200, facilitating the formation of a trench transistor. It should be noted that when the substrate 100 includes a substrate 110 and a first conductivity type epitaxial layer 120, the source structure 300 is disposed on the first conductivity type epitaxial layer 120.

[0095] It should be understood that when the source structure 300 is formed through a doping process, the source structure 300 is disposed within the epitaxial layer 120 of the first conductivity type; when the source structure 300 is formed through a combination of deposition and doping processes, the source structure 300 can be disposed on the epitaxial layer 120 of the first conductivity type. Specifically, this can be understood based on the differences in the actual fabrication process.

[0096] Referring to FIG5, the source structure 300 includes a second conductivity type source active region 310 and a first conductivity type source region 320 stacked together. Along the thickness direction of the substrate 100, the second conductivity type source active region 310 is disposed on the substrate 100, and the first conductivity type source region 320 is disposed on the second conductivity type source active region 310.

[0097] The first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0098] In this embodiment, the first conductivity type source region 320 and the first conductivity type epitaxial layer 120 are N-type, and the second conductivity type source active region 310 is P-type, as an example for illustration.

[0099] When a positive voltage is applied to the gate structure 200, the portion of the second conductivity type source active region 310 that contacts the gate structure 200 can be inverted, so that the conductivity type of the inverted portion of the second conductivity type source active region 310 becomes the first conductivity type. This allows the first conductivity type source region 320 and the first conductivity type epitaxial layer 120 of the silicon carbide power device to be connected through the inversion layer formed by the second conductivity type source active region 310, thereby ensuring that the silicon carbide power device is in a conducting state.

[0100] Referring to Figure 3, the electric field shielding structure is an electric field shielding layer 400, which is disposed within the substrate 100. It should be noted that when the substrate 100 includes a substrate 110 and a first conductivity type epitaxial layer 120, the electric field shielding layer 400 is disposed within the first conductivity type epitaxial layer 120.

[0101] The electric field shielding layer 400 covers the bottom of at least a portion of the cross-section of the gate structure 200, and the electric field shielding layer 400 is connected to the source structure 300. It should be understood that when there are multiple gate structures 200, the electric field shielding layer 400 covers at least a portion of the cross-section of all gate structures 200.

[0102] In this embodiment of the application, "at least a partial cross-section" refers to the cross-section of the gate structure 200 in a partial direction. For example, referring to FIG1, the "at least a partial cross-section" of the gate structure 200 can be the cross-section formed when a section line is drawn along the AA direction in FIG1, or, referring to FIG2, the "at least a partial cross-section" of the gate structure 200 can be the cross-section formed when a section line is drawn along the BB direction in FIG2.

[0103] In this embodiment, the bottom of the gate structure 200 is defined with reference to the substrate 100. The bottom of the gate structure 200 can be understood as the portion facing the bottom surface of the substrate 100, and this bottom can include the bottom surface of the gate structure 200, and can also include the bottom surface and part of the side surface of the gate structure 200. Taking the orientation shown in FIG1 as an example, the bottom surface of the gate structure 200 is the surface facing the bottom surface of the substrate 100, which can be the lower surface of the substrate 100.

[0104] In this embodiment, when the silicon carbide power device is in reverse blocking state, the electric field shielding layer 400 can deplete the electric field accumulated in the substrate 100 to reduce the electric field of the gate dielectric layer 220, thereby ensuring device reliability. Simultaneously, in this embodiment, the electric field shielding layer 400 is connected to the source structure 300, forming a conductive path. Thus, when the silicon carbide power device cell structure is in reverse bias state, it can prevent the electric field from accumulating at the bottom of the gate dielectric layer 220, improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure due to gate dielectric layer breakdown, thereby ensuring the performance and reliability of the gate structure, and further ensuring the performance and reliability of the semiconductor device.

[0105] The electric field shielding layer 400 covers at least a portion of the bottom cross-section of the gate structure 200, forming an intermittent structure. This helps to further optimize the electric field distribution in the substrate 100, reducing excessive concentration of the electric field in specific areas, thereby improving the overall reliability and performance of the silicon carbide power device. Furthermore, the intermittent structure of the electric field shielding layer 400 ensures effective coverage of the protected area while avoiding overlap with the source structure 300, thus ensuring the performance of the silicon carbide power device.

[0106] To further improve the shielding effect of the electric field shielding layer 400, in this embodiment, the extension depth of the electric field shielding layer 400 to the bottom surface of the substrate 100 is greater than the depth of the gate structure 200. Thus, compared to related technologies, when the silicon carbide power device is in a reverse blocking state, the electric field shielding layer 400 can block the electric field, thereby distributing the electric field of the gate dielectric layer 220 onto the electric field shielding layer 400. This helps to shield the gate dielectric layer electric field 122 when the silicon carbide power device is in a reverse blocking state, improving the reliability of the gate dielectric layer 220 and preventing the gate structure 200 from failing due to the breakdown of the gate dielectric layer 220. This ensures the performance and reliability of the gate structure 200, and further guarantees the performance and reliability of the silicon carbide power device.

[0107] In one possible implementation, referring to Figures 3 and 4, the electric field shielding layer 400 may include at least a first sub-electric field shielding layer 410 and a second sub-electric field shielding layer 420, which are respectively disposed on both sides of at least a portion of the cross-section of the gate structure 200.

[0108] It should be noted that the positions of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 are shown in Figures 3, 4 and 6. In Figures 3 and 4, the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 are located in the area above the dashed line and are disposed on the left and right sides of the gate structure 200 in the vertical direction.

[0109] In this configuration, at least one of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 is connected to the source structure 300. That is, the source structure 300 can be connected to one of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420, or the source structure 300 can be connected to both the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 simultaneously.

[0110] It should be noted that at least some of the cross-sections can be such that, on the cross-section along the AA direction, the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 are located on opposite sides of the gate structure 200. Taking the orientation shown in Figure 4 as an example, the first sub-electric field shielding layer 410 is located on the left side of the gate structure 200, and the second sub-electric field shielding layer 420 is located on the right side of the gate structure 200. Both the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 extend along the thickness direction of the substrate 100, such that the ends of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 facing the bottom surface of the substrate 100 are positioned near the bottom of the gate structure 200.

[0111] With this configuration, at least one of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 effectively shields electric field interference from both sides of the gate structure 200, which can significantly reduce the capacitive coupling between the gate structure 200 and the surrounding structure, thereby reducing the impact of the electric field on the device performance.

[0112] On the two vertical sides of the gate structure 200, only one side of the gate structure 200 may be wrapped, while the other side may not be wrapped; or both sides of the gate structure 200 may be wrapped. For example, the first sub-electric field shielding layer 410 and / or the second sub-electric field shielding layer 420 cover the entire bottom surface of at least a portion of the cross-section of the gate structure 200.

[0113] That is, the first sub-electric field shielding layer 410 may extend in a direction perpendicular to the substrate 100 and cover the entire bottom surface of at least a portion of the cross-section of the gate structure 200; or, the second sub-electric field shielding layer 420 may extend in a direction perpendicular to the substrate 100 and cover the entire bottom surface of at least a portion of the cross-section of the gate structure 200; or, it may extend and cover the entire bottom surface of the gate structure 200 simultaneously. This embodiment does not limit this.

[0114] In this embodiment, the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420 are electrically connected. This helps to increase the area of ​​the electric field shielding layer 400, further enhancing the shielding effect; in addition, it also facilitates connection with the source structure 300.

[0115] In one possible implementation, referring to Figures 3 and 4, the electric field shielding layer 400 may further include a third sub-electric field shielding layer 430, which may be disposed on the bottom surface of at least a portion of the cross-section of the gate structure 200.

[0116] It should be noted that the position of the third sub-electric field shielding layer 430 is shown in Figures 3 and 4. In Figures 3 and 4, the third sub-electric field shielding layer 430 is located in the region below the dashed line and is disposed at the bottom of the gate structure 200 in the direction perpendicular to the substrate 100.

[0117] In this embodiment, the third sub-electric field shielding layer 430 is electrically connected to at least one of the first sub-electric field shielding layer 410 and the second sub-electric field shielding layer 420. This helps to increase the area of ​​the electric field shielding layer 400, further enhancing the shielding effect; in addition, it also facilitates connection with the source structure 300.

[0118] In this embodiment, the third sub-electric field shielding layer 430, the first sub-electric field shielding layer 410, and the second sub-electric field shielding layer 420 can be disposed on the same cross-section of the gate structure 200. While ensuring that the third sub-electric field shielding layer 430 is connected to the first sub-electric field shielding layer 410 and / or the second sub-electric field shielding layer 420, and increasing the area of ​​the electric field shielding layer 400, the fabrication process of the electric field shielding layer 400 can be simplified, and the fabrication difficulty of the electric field shielding layer 400 can be reduced.

[0119] It should be noted that the third sub-electric field shielding layer 430, the first sub-electric field shielding layer 410, and the second sub-electric field shielding layer 420 can also be disposed on different cross-sections of the gate structure 200. In this way, the optimal configuration position of the electric field shielding layer can be selected according to specific application requirements and design considerations to adapt to different working environments and performance requirements.

[0120] In one possible implementation, referring to Figures 4 and 6, the electric field shielding layer 400 has a protrusion 446 extending toward the bottom surface of the substrate 100, and the protrusion 446 is opposite to the gate structure 200 in a direction perpendicular to the substrate 100. Alternatively, the protrusion 446 is located directly below the gate structure 200 in a direction perpendicular to the substrate 100.

[0121] This configuration increases the depth of the electric field shielding layer 400 in the direction perpendicular to the substrate 100, making the depth of the electric field shielding layer 400 much greater than the depth of the gate structure 200. This increases the area of ​​the electric field shielding layer 400, which in turn effectively shields the electric field around the gate structure 200, reducing the risk of electric field concentration in the gate dielectric layer 220 of the gate structure 200. This reduces the risk of silicon carbide power device breakdown and improves the reliability of the silicon carbide power device.

[0122] It should be noted that the protrusion 446 may extend only in a direction perpendicular to the base 100, or other options may be available. For example, referring to FIG6, the protrusion 446 may include a main body 441 and an extension 442.

[0123] Along a direction perpendicular to the substrate 100, the main body portion 441 is opposite to the gate structure 200, and the main body portion 441 covers the bottom surface of the gate structure 200.

[0124] The extension 442 is connected to the side of the main body 441 and extends toward the source structure 300. The extension 442 also covers at least a portion of the side of the gate structure 200 and is connected to the source structure 300. In this way, the main body 441 can be connected to the electric field shielding layer 400 located on both sides of the gate structure 200 through the extension 442.

[0125] In this embodiment, the cross-sectional shape of the protrusion 446 on the cross-section perpendicular to the substrate 100 is similar to an inverted convex shape, which can help increase the area of ​​the protrusion 446, thereby increasing the area of ​​the electric field shielding layer 400, effectively shielding the electric field around the gate structure 200, and reducing the risk of electric field concentration in the gate dielectric layer 220 in the gate structure 200.

[0126] In this embodiment, the number of extensions 442 is not limited. For example, the number of extensions 442 may include two, with the two extensions 442 located on opposite sides of the main body 441.

[0127] In this embodiment, within the same main body 441, two extensions 442 are arranged opposite each other, parallel to the plane of the substrate 100 and along the second direction; or, within the same main body 441, two extensions 442 are staggered relative to each other, parallel to the plane of the substrate 100 and along the second direction. In this embodiment, referring to FIG6, the example of two extensions 442 being opposite each other is used for explanation. Thus, while ensuring an increase in the channel length of the silicon carbide power device, the fabrication difficulty of the electric field shielding layer 400 can be reduced.

[0128] In one possible implementation, referring to Figures 1 and 2, the gate structure 200 is strip-shaped on a plane parallel to the substrate 100, and the gate structure 200 extends along a first direction. That is, the gate structure 200 is a strip trench gate.

[0129] The source structure 300 includes a plurality of source portions 330, which are spaced apart along a first direction, and each source portion 330 surrounds a portion of the side surface of the gate structure 200; an electric field shielding layer 400 covering the side surface of the gate structure 200 extends along the bottom surface away from the substrate 100 and extends between adjacent source portions 330.

[0130] In this embodiment, both the source structure 300 and the electric field shielding layer 400 are discontinuous, such that the electric field shielding layer 400 is located between any two adjacent source structures 300. Compared to the strip-shaped source structure 300, the discontinuous source structure 300 provides more space for the electric field shielding layer 400, thereby increasing its area. Furthermore, the arrangement of the source structures 300 helps reduce capacitive coupling between the gate structure 200 and the source structure 300, thereby reducing power consumption and increasing the switching speed of the device.

[0131] It is important to understand that the electric field shielding layer 400 needs to be connected to the source structure 300. When the source structure 300 includes multiple source portions 330, the electric field shielding layer 400 located between adjacent source portions 330 is connected to at least one of the two adjacent source portions 330. In one example, the electric field shielding layer 400 located between adjacent source portions 330 is connected to one of the two adjacent source portions 330; in another example, the electric field shielding layer 400 located between adjacent source portions 330 is connected to both of the adjacent source portions 330.

[0132] In this way, the overlap between the source structure 300 and the electric field shielding layer 400 can be avoided, thereby preventing the current flow of the source structure 300 from interfering with the electric field distribution of the electric field shielding layer 400 and ensuring the shielding effect of the electric field shielding layer 400.

[0133] It should be noted that in this embodiment, the electric field shielding layer 400 can be directly connected to the source structure 300 or indirectly connected. For example, the electric field shielding layer 400 covering the side of the gate structure 200 extends along the bottom surface away from the substrate 100, and the extension height is large enough so that the electric field shielding layer 400 extends between adjacent source portions 330 and contacts the source portions 330; in this case, the electric field shielding layer 400 can be directly connected to the source structure 300.

[0134] For example, the electric field shielding layer 400 covering the side of the gate structure 200 extends along the bottom surface away from the substrate 100. When the extension height is small, it can also be connected to the source structure 300 through other components. Exemplarily, the electric field shielding layer 400 is connected to the source structure 300 through a second conductivity type ohmic contact layer 600 and a source electrode layer 800.

[0135] The electric field shielding layer 400 located between any two adjacent source electrode portions 330 can have various orthographic projection shapes on the substrate 100. In one feasible embodiment, referring to Figures 1 and 2, the electric field shielding layer 400 located between any two adjacent source electrode portions 330 has a strip shape in its orthographic projection on the substrate 100. The strip shape can be understood as a straight line extending along the second direction; for example, the strip shape can be a square or a rectangle.

[0136] In another possible implementation, referring to Figures 8 and 9, the electric field shielding layer 400 located between any adjacent source electrode portions 330 has a bent shape in its orthographic projection onto the substrate 100. The bent shape can be serrated, wall-like, or other shapes.

[0137] For example, the electric field shielding layer 400 located between any adjacent source electrode portions 330 includes a plurality of shielding extension segments 444 and shielding connection segments 445 in the orthographic projection shape of the substrate 100. Two adjacent shielding extension segments 444 are connected by shielding connection segments 445, and any two adjacent shielding extension segments 444 are spaced out and staggered in a second direction; wherein the second direction and the first direction intersect each other.

[0138] The electric field shielding layers 400 located on both sides of the same gate structure 200 can have the same or different shapes. In one example, the electric field shielding layers 400 located on both sides of the gate structure 200 are arranged in a centrally symmetrical manner with respect to the gate structure 200, as shown in Figure 8. In another example, the electric field shielding layers 400 located on both sides of the gate structure 200 are arranged axially symmetrical with respect to the gate structure 200.

[0139] This enhances the structural symmetry of the entire silicon carbide power device, which not only facilitates the standardization of silicon carbide power devices but also improves the mechanical and thermal stability of the devices.

[0140] In one possible implementation, referring to Figures 2 and 6, each gate structure 200 includes a gate body 230 and a gate protrusion 240. The gate body 230 extends along a first direction, and the gate protrusion 240 protrudes at least one side of the gate body 230 along a second direction. The first and second directions intersect each other.

[0141] In this embodiment, the first direction can be referred to as the Y direction in Figures 1 and 2, and the second direction can be referred to as the X direction in Figures 1 and 2.

[0142] For example, along the second direction, the gate protrusion 240 may protrude from one side of the gate body 230; or, the gate protrusion 240 may protrude from both sides of the gate body 230, so that a stepped surface is formed between the gate protrusion 240 and the gate body 230. This embodiment does not limit this.

[0143] In this embodiment, the example of gate protrusions 240 protruding from both sides of the gate body 230 is used for illustration. In this example, the two gate protrusions 240 can be arranged opposite to each other relative to the gate body 230; alternatively, the two gate protrusions 240 can be staggered. This embodiment does not limit this arrangement.

[0144] The gate protrusion 240 protrudes from one side of the gate body 230, making the gate structure 200 cross-shaped. Compared with a cylindrical gate structure, this greatly extends the channel area of ​​the silicon carbide power device, thereby increasing the forward conduction path and reducing the forward conduction resistance of the device, resulting in higher output characteristics for the silicon carbide power device.

[0145] In this embodiment, the gate protrusion 240 allows the gate structure 200 to be stepped. Accordingly, when fabricating the gate structure 200 and the electric field shielding layer 400, a gate trench needs to be fabricated first. When the gate structure 200 is stepped, the gate trench can be a multi-level trench.

[0146] When the electric field shielding layer 400 is fabricated using a low-energy ion implantation process, the implanted ions will preferentially contact the step surface of the gate trench, thus allowing implantation of the region surrounding the bottom sidewall of the gate trench and the region surrounding the sidewall of the gate trench.

[0147] In this way, on the one hand, by using a lower-energy ion implantation process to prepare the electric field shielding layer 400, the implantation depth and distribution of ions can be controlled more precisely, ensuring that the required electric field shielding layer 400 is formed in a specific region of the gate trench; on the other hand, a lower-energy ion implantation process can prepare a deep electric field shielding layer 400, thereby simplifying the requirements for ion implantation equipment and reducing manufacturing costs and process complexity.

[0148] In addition, the above method can better connect the electric field shielding layer 400 at the bottom of the gate structure 200 and the electric field shielding layer 400 of the source structure 300 during ion implantation. This can avoid the problem that the electric field shielding layer 400 of the source structure 300 cannot connect with the electric field shielding layer 400 at the bottom of the trench when the implantation depth of the bottom electric field shielding layer 400 is less than the trench depth. This ensures that the electric field shielding layer 400 at the bottom of the trench is in contact with the source structure 300, thereby improving the reliability of silicon carbide power devices.

[0149] It should be noted that the gate structure 200 can be stepped, with two, three, or even more steps. Taking a three-step gate structure 200 as an example, based on the above-mentioned gate structure 200 formation process, the gate trench forming the gate structure 200 can be divided into a first gate trench, a second gate trench, and a third gate trench connected in sequence. Along the thickness direction of the substrate 110, and from top to bottom, the diameters of the first, second, and third gate trenches gradually decrease, so that the gate trench includes two step surfaces, namely the first step surface and the second step surface. In this way, a lower energy ion implantation process can be used to prepare the electric field shielding layer 400. Ions will also be implanted downwards through the first and second step surfaces for doping, so that the formed electric field shielding layer 400 can cover the bottom wall and sidewalls of the third gate trench, the step surface between the third and second gate trenches, the sidewalls of the second gate trench, and a portion of the step surface between the second and first gate trenches. In this way, an ideal electric field shielding layer 400 can be obtained using a lower energy ion implantation process. This can reduce the fabrication difficulty and production cost of silicon carbide power devices, improve the shielding effect of the electric field shielding layer 400, and thus improve the performance of silicon carbide power devices.

[0150] Referring to Figures 3 to 6, in one possible implementation, the silicon carbide power device further includes a source electrode layer 800, which is disposed on and connected to the source structure 300.

[0151] When the source structure 300 includes a second conductivity type source active region 310 and a first conductivity type source region 320 stacked together, the source electrode layer 800 can be connected to at least one of the second conductivity type source active region 310 and the first conductivity type source region 320 in order to provide an electrical signal to the source structure 300.

[0152] The source electrode layer 800 and the source structure 300 can be directly connected or indirectly connected. For example, the silicon carbide power device also includes a second conductivity type ohmic contact layer 600, through which the source electrode layer 800 and the source structure 300 are connected.

[0153] The doping concentration of the second conductivity type ohmic contact layer 600 is greater than that of the second conductivity type source active region 310. Thus, the second conductivity type ohmic contact layer 600 provides a low-resistance path, reducing the contact resistance between the source electrode layer 800 and the second conductivity type source active region 310, thereby improving the device performance.

[0154] The second conductivity type ohmic contact layer 600 may include multiple layers, which extend along a first direction parallel to the plane of the substrate 100 and are spaced apart along a second direction. Each source portion 330 can be connected to the source electrode layer 800 through one second conductivity type ohmic contact layer 600. In this way, the contact resistance between the first conductivity type source region 320 and the source electrode layer 800 can be minimized, thereby improving the performance of the silicon carbide power device.

[0155] When the electric field shielding layer 400 is indirectly connected to the source structure 300, the electric field shielding layer 400 can be connected to the source structure 300 through the second conductivity type ohmic contact layer 600. For example, the second conductivity type ohmic contact layer 600 is disposed within the electric field shielding layer 400; and the electric field shielding layer 400 is connected to the source structure 300 through the second conductivity type ohmic contact layer 600 and the source electrode layer 800.

[0156] In one feasible embodiment, referring to Figures 3 to 6, the silicon carbide power device further includes an insulating layer 500 covering the gate structure 200 and the first conductivity type source region 320 to achieve insulation between the gate structure 200 and the first conductivity type source region 320. The insulating layer 500 may include silicon oxide, silicon nitride, aluminum oxide, or other insulating materials.

[0157] Referring to Figure 7, this application embodiment provides a method for fabricating a silicon carbide power device, including the following steps:

[0158] Step S100: Provide a substrate.

[0159] Step S200: Form a source structure, which is disposed on a substrate.

[0160] Step S300: An electric field shielding layer and a gate structure are formed in the substrate, the source structure surrounds at least a portion of the side surface of the gate structure, the electric field shielding layer covers at least a portion of the bottom of the cross section of the gate structure, and the electric field shielding layer is connected to the source structure.

[0161] The electric field shielding layer in the silicon carbide power device prepared by this method covers at least part of the bottom of the cross-section of the gate structure. This can maximize the distribution of the electric field of the gate dielectric layer onto the electric field shielding layer, thereby helping to reduce the electric field of the silicon carbide power device in the reverse blocking state, improving the reliability of the gate dielectric layer, avoiding the problem of gate structure failure caused by the breakdown of the gate dielectric layer, thus ensuring the performance and reliability of the gate structure, and further ensuring the performance and reliability of the semiconductor device.

[0162] In one possible implementation, the fabrication method of silicon carbide power devices further includes:

[0163] Steps for providing the substrate:

[0164] Provide substrate;

[0165] An epitaxial layer of a first conductivity type is formed and disposed on a substrate.

[0166] For example, an epitaxial layer 120 of a first conductivity type can be formed on the substrate 110 using an epitaxial process. The conductivity type of the first conductivity type epitaxial layer 120 is the same as that of the substrate 110. For example, both the first conductivity type epitaxial layer 120 and the substrate 110 are N-type. The thickness of the first conductivity type epitaxial layer 120 can be 12 micrometers.

[0167] In one possible implementation, the fabrication method of silicon carbide power devices further includes:

[0168] The steps for forming the source structure include:

[0169] A source structure material layer is formed, which is disposed on the first conductivity type epitaxial layer 120. It should be noted that, depending on the fabrication process of the source structure material layer, the source structure material layer can be disposed on or within the first conductivity type epitaxial layer 120.

[0170] In this embodiment, the source structure 300 includes a second conductivity type source active region 310 and a first conductivity type source region 320 stacked together. Therefore, the source structure material layer also includes two layers, which can be referred to as the second conductivity type source active region material layer and the first conductivity type source region material layer.

[0171] For example, the first conductivity type epitaxial layer 120 is processed using an ion implantation process or an ion doping process to form a second conductivity type source active region material layer of a certain thickness in the first conductivity type epitaxial layer 120; wherein, the conductivity type of the first conductivity type epitaxial layer 120 is different from the conductivity type of the second conductivity type source active region material layer. For example, the conductivity type of the second conductivity type source active region material layer is N-type.

[0172] Subsequently, ion implantation or ion doping is used to implant ions into the second conductivity type source active region material layer to form a first conductivity type source active region material layer of a certain thickness within the second conductivity type source active region material layer. The conductivity type of the first conductivity type source active region material layer differs from that of the second conductivity type source active region material layer; for example, the second conductivity type source active region material layer is N-type, while the first conductivity type source active region material layer is P-type.

[0173] Subsequently, a first mask layer with multiple first mask openings is formed on the source structure material layer. The multiple first mask openings are spaced apart along a second direction, and each first mask opening extends along a first direction. The first mask layer can be a photoresist layer or a hard mask layer. For example, the material of the first mask layer includes silicon oxide, but is not limited to this.

[0174] Subsequently, the source structure material layer and part of the first conductivity type epitaxial layer 120 exposed within the first mask opening are removed by an etching process to form a gate trench 250 (see Figure 1); wherein, the remaining source structure material layer constitutes the source structure 300. It should be noted that the etching process in this embodiment can be dry etching or wet etching, and this embodiment does not make specific limitations.

[0175] It should be noted that the etching process can be performed once or multiple times, depending on the structure of the gate trench. For example, if the gate trench 250 is a single-stage trench, then the gate trench 250 can be formed in a single etching process.

[0176] For example, gate trench 250 is a multi-level trench. In this way, multi-level gate trenches can be formed in the substrate through multiple etching processes; wherein, along the direction pointing to the bottom surface of the substrate, the diameter of the gate trench gradually decreases.

[0177] For example, the gate trench extends along the thickness direction of the substrate 100, and the bottom of the gate trench is located within the first conductivity type epitaxial layer 120. The following description will take the gate trench as a secondary trench as an example.

[0178] For example, a first gate trench can be formed first, which penetrates the second conductivity type source active region 310 and the first conductivity type source region 320 and extends into the first conductivity type epitaxial layer 120; then, the first gate trench is filled with a dielectric layer and the dielectric layer is patterned to form an etching opening; the dielectric layer and the first conductivity type epitaxial layer 120 are removed along the etching opening to form a second gate trench, the axes of the second gate trench and the first gate trench are collinear, and the second gate trench is located at the center of the first gate trench, and the bottom of the second gate trench is lower than the bottom of the first gate trench.

[0179] The remaining dielectric layer is removed to form a gate trench in the first conductivity type epitaxial layer 120. The gate trench includes a first gate trench and a second gate trench connected sequentially in the thickness direction of the substrate 100; and the diameters of the first gate trench and the second gate trench gradually decrease from top to bottom, so as to form a step surface between the first gate trench and the second gate trench.

[0180] After the gate trench 250 is formed, the remaining first mask layer can be removed by a cleaning process.

[0181] In one possible implementation, the steps of forming the electric field shielding layer and the gate structure include:

[0182] A second mask layer is formed, which fills the gate trench and covers the top surface of the source structure. The fabrication process and materials of the second mask layer can be the same as or different from those of the first mask layer.

[0183] Subsequently, the second mask layer is patterned to form a plurality of second mask openings; the plurality of second mask openings are spaced apart along a first direction, and each second mask opening extends along a second direction; that is, the extension direction of the second mask opening is perpendicular to the extension direction of the gate trench 250.

[0184] In this embodiment, the gate trench 250 is exposed by the second mask opening.

[0185] Subsequently, using the second mask layer as a mask, an electric field shielding layer is formed at least on the inner wall of the exposed gate trench through an ion implantation process.

[0186] The remaining second mask layer can then be removed using a cleaning process.

[0187] Finally, a gate structure is formed, which is disposed within the gate trench.

[0188] For example, a gate dielectric layer 220 is formed on the inner wall of the gate trench using a deposition process, wherein the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0189] Subsequently, a gate 210 is formed in the region enclosed by the gate dielectric layer 220, and the gate 210 and the gate dielectric layer 220 constitute a gate structure 200.

[0190] Following the step of forming the gate structure, the fabrication method of silicon carbide power devices further includes:

[0191] A second type of conductive ohmic contact layer is formed, wherein the second type of conductive ohmic contact layer is disposed on the electric field shielding layer 400.

[0192] For example, an insulating layer is formed covering the gate structure and the source structure; wherein the insulating layer 500 is made of silicon oxide, silicon nitride, aluminum oxide or other insulating materials.

[0193] Part of the insulating layer is removed to form an opening in the insulating layer that exposes a portion of the electric field shielding layer. Then, ion doping is performed into the opening through a doping process to form an ohmic contact layer of the second conductivity type.

[0194] Afterward, the insulating layer is backfilled and then patterned to form the source metal contact hole 700; the source metal contact hole 700 extends along the first direction and exposes a portion of the second conductivity type source active region 310.

[0195] The source electrode layer 800 is formed by deposition process to complete the fabrication of trench gate silicon carbide power devices.

[0196] This application also provides a semiconductor device, including the silicon carbide power device described in any of the above embodiments. The power device formed in this embodiment is not limited to devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs); any silicon carbide power device is within the scope of this patent.

[0197] It should be noted that the beneficial effects of the silicon carbide power device provided in this application embodiment are the same as those of the silicon carbide power device provided in the above embodiments, and will not be elaborated further in this embodiment.

[0198] The silicon carbide power devices provided in this application embodiment can be applied to vehicles, for example, to key electric drive and control components such as main drive inverters, converters, on-board chargers (OBC), and on-board charging piles. The vehicles can be electric vehicles, hybrid vehicles, or new energy vehicles.

[0199] Therefore, embodiments of this application provide a silicon carbide power device and its fabrication method, as well as a semiconductor device. An electric field shielding layer covers at least a portion of the bottom surface of the cross-section of the gate structure. This maximizes the distribution of the electric field of the gate dielectric layer onto the electric field shielding layer, thereby helping to reduce the electric field of the silicon carbide power device in the reverse blocking state, improving the reliability of the gate dielectric layer, and avoiding the problem of gate structure failure due to gate dielectric layer breakdown. This ensures the performance and reliability of the gate structure, further guaranteeing the performance and reliability of the semiconductor device. By connecting the electric field shielding layer to the source structure, the reverse bias current in the epitaxial layer is blocked as much as possible at the electric field shielding layer, forming a depletion region. This allows electrons to be depleted as much as possible at the electric field shielding layer, better shielding the electric field of the gate dielectric layer of the silicon carbide power device, thereby preventing gate dielectric layer breakdown and improving the reliability of the silicon carbide power device.

[0200] Example 2:

[0201] This application provides a silicon carbide power device cell structure that can be applied to semiconductor devices. Referring to Figures 10 to 14, the silicon carbide power device cell structure provided in this application includes a substrate 100, which serves as a support component for supporting other components disposed thereon. The substrate 100 can be made of a semiconductor material. The substrate 100 may include a substrate 120 and a first conductivity type epitaxial layer 130. The first conductivity type epitaxial layer 130 is disposed on the substrate 120, and the substrate 100 is made of silicon carbide. That is, during the fabrication process, an epitaxial layer can be epitaxially grown on the substrate 100, wherein the conductivity type of the epitaxial layer is the first conductivity type. It should be understood that the first conductivity type can be N-type or P-type.

[0202] The cell structure of the silicon carbide power device also includes a source structure 300, which is disposed on the substrate 100. When the substrate 100 includes a substrate 120 and a first conductivity type epitaxial layer 130, the source structure 300 is disposed on the first conductivity type epitaxial layer 130. It should be understood that when the source structure 300 is formed by a doping process, the source structure 300 is disposed within the first conductivity type epitaxial layer 130; when the source structure 300 is formed by a combination of deposition and doping processes, the source structure 300 can be disposed on the first conductivity type epitaxial layer 130. Specifically, this can be understood according to the differences in the actual fabrication process.

[0203] Referring to Figures 12 and 13, the source structure 300 includes a second conductivity type source active layer 310 and a first conductivity type source layer 320 stacked together. For example, the second conductivity type source active layer 310 and the first conductivity type source layer 320 are sequentially disposed on the first conductivity type epitaxial layer 130. The first conductivity type source layer 320 and the first conductivity type epitaxial layer 130 have the same conductivity type, but different from the conductivity type of the second conductivity type source active layer 310. In one example, the conductivity type of the second conductivity type source active layer 310 is P-type, and the conductivity types of the first conductivity type source layer 320 and the first conductivity type epitaxial layer 130 are N-type. In another example, the conductivity type of the second conductivity type source active layer 310 is N-type, and the conductivity types of the first conductivity type source layer 320 and the first conductivity type epitaxial layer 130 are P-type.

[0204] The cell structure of the silicon carbide power device also includes a gate structure 200. A portion of the gate structure 200 is disposed within the substrate 100, or more specifically, a portion of the gate structure 200 is disposed within a first conductivity type epitaxial layer 130, and the remaining portion of the gate structure 200 protrudes from the first conductivity type epitaxial layer 130, such that the source structure 300 surrounds at least a portion of the sidewalls of the gate structure 200. This configuration results in a trench gate for the gate structure 200 provided in this embodiment. Compared to planar gate silicon carbide power devices, trench gate silicon carbide power devices can have smaller cell structure sizes and higher channel mobility. Therefore, trench gate silicon carbide power devices significantly reduce the resistance during forward conduction, improving the performance of the silicon carbide power device.

[0205] The gate structure 200 includes a first gate structure 230 and at least one second gate structure 240. The at least one second gate structure 240 is disposed on one side of the first gate structure 230 and connected to the first gate structure 230. The first gate structure 230 can be the portion within the dashed box in Figure 11. The second gate structure 240 can be the portion of the gate structure 200 located outside the dashed box.

[0206] Both the first gate structure 230 and at least one second gate structure 240 include a gate 210 and a gate dielectric layer 220, with the gate dielectric layer 220 covering the bottom and side surfaces of the gate 210. In the specific fabrication process, a first conductivity type epitaxial layer 130 substrate can be patterned first to form a gate trench in the first conductivity type epitaxial layer 130. Then, a gate dielectric layer 220 is formed on the inner wall of the gate trench using a deposition process or an in-situ deposition process, followed by the formation of the gate 210, which fills the area enclosed by the gate dielectric layer 220. Thus, the gate dielectric layer 220 covers the bottom and side surfaces of the gate 210, effectively isolating the gate 210. The gate dielectric layer 220 is made of silicon oxide. The gate 210 is made of polysilicon.

[0207] The depth of the gate structure 200 is lower than that of the second conductivity type source active layer 310 so that the channel is located on the sidewall of the trench-type gate structure 200. When the substrate provides voltage to the gate structure 200, the portion of the second conductivity type source active layer 310 that contacts the gate structure 200 can be inverted so that the conductivity type of the inverted portion of the second conductivity type source active layer 310 becomes the first conductivity type. This allows the first conductivity type source layer 320 and the first conductivity type epitaxial layer 130 of the silicon carbide power device cell structure to be connected through the inversion layer formed by the second conductivity type source active layer 310, thereby ensuring that the silicon carbide power device cell structure is in a conducting state.

[0208] In this embodiment, the second gate structure 240 is disposed on one side of the first gate structure 230, meaning the second gate structure 240 protrudes from the outer surface of the first gate structure 230. The contact area between the source structure 300 and the gate structure 200 forms a channel. Compared to a single first gate structure, this increases the contact area between the source structure 300 and the gate structure 200, thereby maximizing the channel area during forward conduction of the silicon carbide power device, reducing the forward conduction resistance, and ultimately improving the performance of the silicon carbide power device.

[0209] In addition, on the one hand, it can further enhance the control capability of the gate structure 200 over the channel region and improve the switching performance of silicon carbide power devices; on the other hand, the connection between the second gate structure 240 and the first gate structure 230 helps to optimize the electric field distribution around the gate structure 200, reduce the electric field concentration effect, thereby reducing the risk of the gate dielectric layer 220 being broken down and improving the reliability of silicon carbide power devices.

[0210] Referring to Figures 11 and 16, the gate structure 200 is formed within the substrate 100, making the gate structure 200 a trench structure. Accordingly, the number of trench levels in the gate structure 200 needs to be designed based on the function of the silicon carbide power device.

[0211] In one example, the gate structure 200 is a multi-level trench structure formed by multiple etching processes. The multi-level trench structure can include a two-level trench structure, a three-level trench structure, or more. For example, after forming the second conductivity type source active layer 310 and the first conductivity type source layer 320, a three-level trench is formed by three etching processes. In another example, the gate structure 200 is a single-level trench structure formed by a single etching process. For example, after forming the second conductivity type source active layer 310 and the first conductivity type source layer 320, a single-level trench is formed by a single etching process.

[0212] In one possible implementation, referring to FIG11, the first gate structure 230 includes at least one first step surface 250, and the bottom surface of the second gate structure 240 and the side surface of the first gate structure 230 together form a second step surface 260, thereby enabling the gate structure 200 to form a three-level trench structure.

[0213] The cross-sectional shape of the gate structure 200 can be rectangular or other shapes in a direction perpendicular to the substrate 100. For example, referring to Figures 11 and 12, the gate structure 200 includes a first gate structure 230. The first gate structure 230 can be the portion within the dashed box in Figure 11. It should be noted that the difference between a multi-level trench structure and a single-level trench structure lies in the gate composition of the first gate structure 230.

[0214] Along the thickness direction of the substrate 100, the gate of the first gate structure 230 includes at least a first gate layer 211 and a second gate layer 212, which are stacked and interconnected. The first gate layer 211 is located at the bottom of the second gate layer 212 and covers a portion of the bottom surface of the second gate layer 212; that is, the projection of the first gate layer 211 onto the second gate layer 212 covers a portion of the second gate layer 212, so that the gate of the first gate structure 230 forms an inverted convex shape.

[0215] The bottom surface of the second gate layer 212 and the side surface of the first gate layer 211 together form the first step surface 250. The electric field shielding layer 400 covers the bottom surface of the first gate layer 211, the first step surface 250, and part of the side surface of the second gate layer 212, so that the electric field shielding layer 400 forms an inverted convex structure.

[0216] This configuration effectively increases the electric field control range of the gate structure 200 over the channel region. Especially in nanoscale processes where the short-channel effect is becoming increasingly significant, this design can more effectively suppress leakage current and improve the current switching ratio, thereby improving the performance and reliability of power devices.

[0217] In one possible implementation, referring to Figures 10 to 17, the electric field shielding structure of the silicon carbide power device cell structure is an electric field shielding layer 400. The electric field shielding layer 400 is disposed within the substrate 100, wherein the electric field shielding layer 400 at least covers a portion of the bottom of the gate structure 200 and is connected to the source structure 300. It should be understood that, in this embodiment, the bottom of the gate structure 200 is defined with reference to the substrate 100. The bottom of the gate structure 200 can be understood as the portion facing the substrate 100, and this bottom can include the bottom surface of the gate structure 200, or the bottom surface and a portion of the side surface of the gate structure 200. Specifically, the bottom surface of the gate structure 200 is the surface facing the bottom surface of the substrate 100; taking the orientation shown in Figure 10 as an example, the bottom surface of the substrate 100 is the lower surface in Figure 10.

[0218] It should be understood that when the source structure 300 includes a second conductivity type source active layer 310 and a first conductivity type source layer 320 stacked together, the electric field shielding layer 400 is connected to the second conductivity type source active layer 310.

[0219] As an example, the electric field shielding layer 400 can cover the bottom surface of the gate structure 200, and the connection between the second conductivity type source active layer 310 and the electric field shielding layer 400 can be achieved by increasing the depth of the second conductivity type source active layer 310. As another example, the electric field shielding layer 400 can also cover the bottom surface and part of the side surface of the gate structure 200, and the connection between the second conductivity type source active layer 310 and the electric field shielding layer 400 can be achieved by the electric field shielding layer 400 covering the side surface of the gate structure 200 contacting the second conductivity type source active layer 310.

[0220] When the silicon carbide power device is in reverse blocking mode, the electric field shielding layer 400 can deplete the electric field accumulated in the substrate 100, thereby reducing the electric field of the gate dielectric layer 220 and ensuring device reliability. Simultaneously, in this embodiment, the electric field shielding layer 400 is connected to the source structure 300, forming a conductive path. Thus, when the silicon carbide power device cell structure is in reverse bias mode, it can prevent the electric field from accumulating at the bottom of the gate dielectric layer 220, thereby better shielding the electric field of the silicon carbide power device, avoiding breakdown of the gate dielectric layer 220, and improving the reliability of the silicon carbide power device.

[0221] In this embodiment, the gate structure 200 has a cross-shaped cross section parallel to the substrate 100. This configuration increases the channel area of ​​the silicon carbide power device, increases the forward conduction path, thereby reducing the forward conduction resistance and enabling the silicon carbide power device to have higher output performance.

[0222] In fabricating the electric field shielding layer 400 and the gate structure, it is typically necessary to first pattern the substrate 100 to form gate trenches within it. Then, the electric field shielding layer 400 is formed within the gate trenches using an ion implantation process. To improve the shielding effect of the electric field shielding layer 400, it is better for it to extend deeper than the bottom of the gate structure 200. Achieving this effect requires increasing the implantation energy of the ion implantation process and employing multiple ion implantations, which increases the fabrication difficulty of the electric field shielding layer 400 and makes it difficult to achieve the desired shielding effect.

[0223] This embodiment improves the structure of the first gate structure 230 so that the gate of the first gate structure 230 includes at least a first gate layer 211 and a second gate layer 212 stacked together, and a first step surface 250 is formed between the first gate layer 211 and the second gate layer 212. In other words, if a stepped first gate structure 230 is desired, the shape of the gate trench is also stepped. When the gate trench is doped using a low-energy ion implantation process, the implanted ions will preferentially touch the step surface of the gate trench, thus allowing implantation of the area surrounding the bottom sidewall region of the gate trench and the sidewall region of the gate trench, so that the formed electric field shielding layer 400 is an inverted convex structure.

[0224] This setup allows for more precise control of ion implantation depth and distribution by using a lower-energy ion implantation process to dope the gate trench, ensuring the formation of the required doping concentration in specific areas of the gate trench, thereby guaranteeing the formation of the inverted convex electric field shielding layer 400. Furthermore, the lower-energy ion implantation process simplifies the requirements for ion implantation equipment, thereby reducing manufacturing costs and process complexity.

[0225] On the other hand, the inverted convex-shaped electric field shielding layer 400 can better connect with the second conductivity type source active layer 310 and form a conductive path; thus, the electric field in the substrate 100 can be better depleted at the electric field shielding layer 400, which can better shield the electric field of the silicon carbide power device, thereby avoiding the breakdown of the gate dielectric layer 220 and improving the reliability of the silicon carbide power device.

[0226] In one possible implementation, the electric field shielding layer 400 includes a main body 410 and an extension 420. The main body 410 covers the bottom surface of the gate dielectric layer 220. The extension 420 extends toward the source structure 300 and covers at least a portion of the side surface of the gate structure 200. That is, the extension 420 can cover at least a portion of the side surface of the gate dielectric layer 220, so that the cross-sectional shape of the electric field shielding layer 400 in the direction perpendicular to the substrate 100 is U-shaped.

[0227] The main body 410 is connected to the source structure 300 via the extension 420. It should be understood that when the source structure 300 includes a second conductivity type source active layer 310 and a first conductivity type source layer 320 stacked together, the main body 410 is connected to the second conductivity type source active layer 310 via the extension 420.

[0228] In this embodiment, the extension 420 covers the first step surface 250, the second step surface 260, and a portion of the side surface of the second gate structure 240; the extension covering a portion of the side surface of the second gate structure 240 is connected to the source structure 300. That is, the extension 420 covering a portion of the side surface of the second gate structure 240 contacts the source structure 300 to achieve the connection between the extension 420 and the source structure 300.

[0229] In this embodiment, the electric field shielding layer 400 has a U-shaped cross-section in the direction perpendicular to the substrate 100. This increases the contact area between the electric field shielding layer 400 and the gate dielectric layer 220, effectively shielding the electric field around the gate structure 200 and reducing the risk of electric field concentration in the gate dielectric layer 220. This reduces the risk of breakdown in the silicon carbide power device and improves its reliability. Furthermore, the extension 420 extends towards the second conductivity type source active layer 310, covering the side of the gate dielectric layer 220, which effectively reduces the leakage current of the silicon carbide power device and improves the switching performance and energy efficiency of the silicon carbide power device's cell structure.

[0230] Based on the above-described gate structure formation process, the gate trench forming the gate structure 200 can be divided into a first gate trench, a second gate trench, and a third gate trench connected in sequence. Along the thickness direction of the substrate 100, and from top to bottom, the diameters of the first gate trench, the second gate trench, and the third gate trench gradually decrease, so that the gate trench includes two step surfaces. In this way, when the low-energy ion implantation process does dope the first conductivity type epitaxial layer 130 exposed in the gate trench, ions will also be implanted downwards through the two step surfaces, so that the formed electric field shielding layer 400 can cover the bottom wall and sidewalls of the third gate trench, the step surface between the third gate trench and the second gate trench, the sidewalls of the second gate trench, the step surface between the second gate trench and the first gate trench, and part of the sidewalls of the first gate trench. Thus, the electric field shielding layer 400 covers the bottom surface of the first gate layer 211, the first step surface 250, the second step surface 260, and part of the side surface of the second gate structure 240.

[0231] Compared with related technologies, the ideal electric field shielding layer 400 can be obtained by using a lower energy ion implantation process. This can reduce the fabrication difficulty and production cost of silicon carbide power devices, improve the shielding effect of the electric field shielding layer 400, and thus improve the performance of silicon carbide power devices.

[0232] Referring to Figures 10 and 15, the number of second gate structures 240 is at least two, and the arrangement of these at least two second gate structures 240 can be varied. For example, at least two second gate structures 240 are spaced apart on the periphery of the first gate structure 230, and the second gate structures 240 between adjacent cells are not connected. Another example is that at least two second gate structures 240 are symmetrically arranged on the periphery of the first gate structure 230. This arrangement increases the channel area of ​​the silicon carbide power device, increases the forward conduction path, thereby reducing the forward conduction resistance and improving the output performance of the silicon carbide power device.

[0233] It should be noted that in this embodiment, the number of second gate structures 240 is at least two, which can be understood as two, three, four, or even more. In one example, there are two second gate structures 240, which are symmetrically arranged on both sides of the first gate structure 230. In this way, the reliability of the gate dielectric layer 220 can be guaranteed while increasing the channel area of ​​the silicon carbide power device.

[0234] In another example, there are four second gate structures 240, symmetrically arranged around the first gate structure 230, making the gate structure 200 cross-shaped. Taking the orientation shown in Figure 10 as an example, the channel length of the silicon carbide power device is the outer peripheral surface of the gate structure. Compared with a cylindrical gate structure, this greatly extends the channel area of ​​the silicon carbide power device, thereby increasing the forward conduction path and reducing the forward conduction resistance of the device, resulting in higher output characteristics for the silicon carbide power device.

[0235] In one possible implementation, as shown in Figures 18 and 19, there are multiple gate structures 200 arranged in an array along the thickness direction intersecting the substrate 100. It should be noted that the thickness direction intersecting the substrate 100 can be understood as the horizontal direction of the substrate 100, i.e., the X and Y directions in Figures 18 and 19.

[0236] Multiple gate structures 200 are arranged in an array on the substrate 100, which can integrate more silicon carbide power device cell structures within the limited substrate 100, improve the chip integration and functional density, and thus realize high-performance silicon carbide power devices.

[0237] In this configuration, at least a portion of the adjacent gate structures 200 are spaced apart. This can be understood as all adjacent gate structures 200 being spaced apart, or only a portion of the adjacent gate structures 200 being spaced apart. In one example, the multiple gate structures 200 are arranged in multiple rows and columns; the row direction and column direction intersect and both cross the thickness direction of the substrate 100; wherein the row direction can be the X direction in Figures 15 and 16, and the column direction can be the Y direction in Figures 18 and 19.

[0238] Gate structures 200 located in the same row are spaced apart, and gate structures 200 located in the same column are interconnected to form a branch structure; or, as shown in FIG19, gate structures 200 located in the same column are spaced apart, and gate structures 200 located in the same row are interconnected to form a branch structure. The interconnected gate structures 200 are connected by their respective second gate structures 240. To facilitate a detailed description of the beneficial effects achieved by arranging multiple gate structures 200 in multiple rows and columns, the following description will use the example of gate structures 200 located in the same row being interconnected and gate structures 200 located in the same column being spaced apart. In this example, the second gate structures 240 of the gate structures 200 located in the same row are connected together to form branches; while the second gate structures 240 located in the column direction are spaced apart and not connected together to form branches; wherein, branches and columns constitute a branch structure. Furthermore, the area within the dashed box in FIG19 indicates the location where the electric field shielding layer 400 is disposed.

[0239] Each gate structure 200 located in the same column has a second conductivity type source active layer 310 and is surrounded by the second conductivity type source active layer 310. In this configuration, any adjacent gate structures 200 located in the same column are separated by the second conductivity type source active layer 310. On the one hand, the area that was originally a gate structure is replaced by the second conductivity type source active layer 310, which reduces the area of ​​the gate dielectric layer 220 in the silicon carbide power device, thereby reducing the gate oxide electric field formed by the silicon carbide power device and reducing or even avoiding the risk of the gate dielectric layer 220 being broken down. On the other hand, each gate structure 200 and the second conductivity type source active layer 310 adds two channels. The added channels can be referred to as the area indicated by the dashed line in Figure 16. This allows the gate structure 200 to have a channel in the circumferential direction, reducing the forward conduction resistance of the silicon carbide power device and improving the reliability of the silicon carbide power device.

[0240] In one possible implementation, adjacent gate structures 200 are spaced apart. For example, referring to Figure 18, multiple gate structures 200 are arranged in multiple rows and columns, with gate structures 200 in the same row spaced apart and gate structures 200 in the same column spaced apart. Both adjacent gate structures 200 in the same row and column have a second conductivity type source active layer 310. This significantly reduces the electric field of the gate dielectric layer in the reverse blocking state of the silicon carbide power device, thereby reducing or even avoiding the risk of the gate dielectric layer 220 being broken down. Furthermore, each gate structure 200 and the second conductivity type source active layer 310 have two additional channels, maximizing the channel length, reducing the forward conduction resistance of the silicon carbide power device, and further improving the reliability of the silicon carbide power device. The added channels can be the areas indicated by the arrows in Figure 18.

[0241] To ensure the normal operation of the silicon carbide power device, referring to Figure 13, the cell structure of the silicon carbide power device provided in this embodiment further includes a first electrode layer 700. The first electrode layer 700 is disposed on the source structure 300 and connected to the source structure 300. It should be understood that when the source structure 300 includes a second conductivity type source active layer 310 and a first conductivity type source layer 320 stacked together, the first electrode layer 700 and the first conductivity type source layer 320 are electrically connected.

[0242] It is important to understand that the first electrode layer 700 and the second conductivity type source active layer 310 can be directly electrically connected or indirectly electrically connected. In one example, the first electrode layer 700 and the second conductivity type source active layer 310 are interconnected to form electrical conductivity, which simplifies the fabrication process of the silicon carbide power device cell structure and reduces the production cost of the semiconductor structure. In another example, referring to Figures 10, 13, and 15, the silicon carbide power device cell structure also includes a second conductivity type ohmic contact layer 800, through which the first electrode layer 700 and the second conductivity type source active layer 310 form electrical conductivity. This embodiment utilizes the second conductivity type ohmic contact layer 800 to provide a low-resistance path, making the electrical conductivity between the first electrode layer 700 and the second conductivity type source active layer 310 more efficient, thereby reducing contact resistance and improving the conductivity performance of the device. In addition, the second conductivity type ohmic contact layer 800 also helps to optimize the carrier transport path and improve the current drive capability and overall performance of silicon carbide power devices.

[0243] In one possible implementation, referring to Figures 10 and 15, along the thickness direction intersecting the substrate 100, a second conductivity type ohmic contact layer 800 is located between spaced second gate structures 240, so that there can be multiple second conductivity type ohmic contact layers 800. Multiple second conductivity type ohmic contact layers 800 are spaced apart in the substrate 100. In this way, the contact resistance between the second conductivity type source active layer 310 and the first electrode layer 700 can be reduced to the greatest extent, thereby improving the performance of silicon carbide power devices.

[0244] In one possible implementation, the silicon carbide power device cell structure further includes an insulating layer 900 covering the gate structure 200 and the first conductivity type source layer 320 to achieve insulation between the gate structure 200 and the first electrode layer 700, ensuring insulation between the electrodes of the silicon carbide power device cell structure. The insulating layer 900 may include silicon oxide, silicon nitride, or other insulating materials.

[0245] Referring to Figure 20, this application also provides a method for fabricating a silicon carbide power device cell structure, comprising the following steps:

[0246] Step S100: Provide a substrate.

[0247] Step S200: Form a source structure, which is disposed on a substrate.

[0248] Step S300: Form a gate structure, the gate structure portion being disposed within the substrate; a source structure surrounding at least a portion of the side surface of the gate structure; wherein, the gate structure is disposed within the substrate; the gate structure includes a first gate structure and at least one second gate structure, the at least one second gate structure being disposed on one side of the first gate structure and connected to the first gate structure.

[0249] In the silicon carbide power device cell structure prepared by this method, the second gate structure 240 is disposed on one side of the first gate structure 230, meaning the second gate structure 240 protrudes from the outer surface of the first gate structure 230. The contact area between the source structure 300 and the gate structure 200 forms a channel. Compared to a single first gate structure, this method increases the contact area between the source structure 300 and the gate structure 200, thereby maximizing the channel area during forward conduction of the silicon carbide power device, reducing the forward conduction resistance, and ultimately improving the performance of the silicon carbide power device.

[0250] In one possible implementation, the fabrication method of the silicon carbide power device cell structure also includes:

[0251] The steps for providing the substrate include:

[0252] Provide substrate;

[0253] An epitaxial layer of a first conductivity type is formed and disposed on a substrate; wherein the substrate and the epitaxial layer of the first conductivity type constitute a base.

[0254] For example, an epitaxial layer of a first conductivity type can be formed on substrate 120 using an epitaxial process. The conductivity type of the first conductivity type epitaxial layer 130 is the same as that of substrate 120. For example, the conductivity type of both substrate 120 and the first conductivity type epitaxial layer 130 is N-type. The thickness of the first conductivity type epitaxial layer 130 is 12 micrometers.

[0255] The steps to form the source structure include:

[0256] A source structure is formed within a first conductivity type epitaxial layer, wherein the source structure includes a second conductivity type source active layer and a first conductivity type source layer stacked together, and the first conductivity type source layer is disposed on the second conductivity type source active layer.

[0257] For example, the first conductivity type epitaxial layer 130 is processed using an ion implantation process or an ion doping process to form a second conductivity type source active layer 310 of a certain thickness in the first conductivity type epitaxial layer 130, wherein the conductivity type of the first conductivity type epitaxial layer 130 is different from the conductivity type of the second conductivity type source active layer 310. For example, the conductivity type of the second conductivity type source active layer 310 is P-type.

[0258] Subsequently, a second ion implantation process or ion doping process is used to implant the second conductivity type source active layer 310 with ions, so as to form a first conductivity type source layer 320 of a certain thickness in the second conductivity type source active layer 310. The conductivity type of the first conductivity type source layer 320 is different from that of the second conductivity type source active layer 310. For example, the conductivity type of the second conductivity type source active layer 310 is P-type, and the conductivity type of the first conductivity type source layer 320 is N-type.

[0259] In one possible implementation, the steps for forming the gate structure include:

[0260] Step S310: Through multiple etching processes, a multi-level gate trench is formed in the substrate; wherein, along the direction pointing to the bottom surface of the substrate, the diameter of the gate trench gradually decreases. Referring to Figure 21, the gate trench extends along the thickness direction of the substrate 100, and the bottom of the gate trench 110 is located within the first conductivity type epitaxial layer 130; the following description will take a three-level trench as an example.

[0261] For example, a first gate trench 111 can be formed first, penetrating the second conductivity type source active layer 310 and the first conductivity type source layer 320, and extending into the first conductivity type epitaxial layer 130. Then, the first gate trench 111 is filled with a first dielectric layer, and the first dielectric layer is patterned to form a second gate trench 112 in the first dielectric layer and the first conductivity type epitaxial layer 130. The axes of the second gate trench 112 and the first gate trench 111 are collinear, and the second gate trench 112 is located at the center of the first gate trench 111, with the bottom of the second gate trench 112 lower than the bottom of the first gate trench 111. Subsequently, a second dielectric layer is formed in the second gate trench 112 and the second dielectric layer is patterned to form a third gate trench 113 in the second dielectric layer and the first conductivity type epitaxial layer 130. The third gate trench 113 is collinear with the axes of the second gate trench 112 and the first gate trench 111, and the third gate trench 113 is located at the center of the second gate trench 112. The bottom of the third gate trench 113 is lower than the bottom of the second gate trench 112.

[0262] The remaining first and second dielectric layers are removed to form a gate trench 110 in the first conductivity type epitaxial layer 130. In the thickness direction of the substrate 100, the gate trench 110 includes a first gate trench 111, a second gate trench 112, and a third gate trench 113 connected in sequence. From top to bottom, the diameters of the first gate trench 111, the second gate trench 112, and the third gate trench 113 gradually decrease, so that a step surface is formed between the first gate trench 111 and the second gate trench 112, and a step surface is formed between the second gate trench 112 and the third gate trench 113.

[0263] Step S320: Form an electric field shielding layer, which covers at least the inner wall of the gate trench closest to the bottom surface of the substrate.

[0264] When the first conductivity type epitaxial layer 130 exposed in the gate trench 110 is ion-doped using an ion implantation process, the ions can touch the two step surfaces and dop into the substrate of the first conductivity type epitaxial layer 130 along a direction perpendicular to the step surfaces. In this way, the electric field shielding layer 400 formed by the low-energy ion implantation process can cover the bottom wall and side wall of the third gate trench 113, the step surface between the third gate trench 113 and the second gate trench 112, the side wall of the second gate trench 112, and a portion of the step surface between the second gate trench 112 and the first gate trench 111, thereby increasing the area of ​​the electric field shielding layer 400 and improving the shielding effect of the electric field shielding layer 400.

[0265] Furthermore, it facilitates the connection between the electric field shielding layer 400 and the second conductivity type source active layer 310, forming a conductive path. Consequently, when the silicon carbide power device is in reverse blocking mode, the electric field shielding layer 400 can deplete the electric field accumulated in the substrate 100, reducing the electric field of the gate dielectric layer 220, thereby ensuring device reliability. In addition, in this embodiment, the electric field shielding layer 400 is connected to the source structure 300, forming a conductive path; thus, when the silicon carbide power device cell structure is in reverse bias mode, it can prevent the electric field from accumulating at the bottom of the gate dielectric layer 220, thereby better shielding the electric field of the silicon carbide power device, avoiding breakdown of the gate dielectric layer 220, and improving the reliability of the silicon carbide power device.

[0266] Step S330: Form a gate structure, which is disposed within a multi-level gate trench.

[0267] For example, a gate dielectric layer 220 is formed on the inner wall of the gate trench 110 using a deposition process, wherein the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0268] Subsequently, a gate 210 is formed in the region enclosed by the gate dielectric layer 220, and the gate 210 and the gate dielectric layer 220 constitute a gate structure 200.

[0269] Following the step of forming the gate structure, the method for fabricating the cell structure of silicon carbide power devices also includes:

[0270] An insulating layer 900 is formed covering the gate structure, wherein the insulating layer 900 is made of silicon oxide, silicon nitride or other insulating materials.

[0271] The insulating layer 900 is patterned to form contact holes in the insulating layer 900 that expose a portion of the second conductivity type source active layer 310.

[0272] Next, a second type of conductive ohmic contact layer 800 is formed. It should be noted that the second type of conductive ohmic contact layer 800 can be a P-type doped region or an N-type doped region.

[0273] In this embodiment, by providing an electric field shielding layer connected to the source at the bottom of the gate trench, the electric field shielding layer can reduce the electric field of the dielectric layer at the bottom of the gate when the silicon carbide power device is in reverse bias state, which can better ensure the gate reliability of the silicon carbide power device in reverse blocking state.

[0274] When the cell structure of a silicon carbide power device includes multiple gate structures, these gate structures can be spaced apart and not connected together. In this way, the unconnected gate structures can maximize the channel area of ​​the silicon carbide power device during forward conduction, reduce the forward conduction resistance, and thus improve the device performance.

[0275] This application also provides a semiconductor device, including the silicon carbide power device cell structure described in any of the above embodiments. The semiconductor device formed in this embodiment is not limited to devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs); any silicon carbide power device is within the scope of this patent.

[0276] It should be noted that the beneficial effects of the semiconductor device provided in this application embodiment are the same as the beneficial effects of the silicon carbide power device cell structure provided in the above embodiment, and will not be elaborated further in this embodiment.

[0277] The semiconductor devices provided in this application embodiment can be applied to vehicles, for example, to key electric drive and control components such as vehicle main drive inverters, converters, on-board chargers (OBC), and on-board charging piles. The vehicle can be an electric vehicle, a hybrid electric vehicle, or other new energy vehicle.

[0278] Example 3

[0279] Referring to FIG22, an embodiment of this application provides a silicon carbide power device cell structure.

[0280] Referring to Figures 22 to 24, the cell structure of a silicon carbide power device includes a substrate 100.

[0281] The substrate 100 includes a substrate 110. The substrate 110 serves as a support component for the cell structure of the silicon carbide power device, supporting other components disposed thereon. The substrate 110 may be made of a semiconductor material. For example, the material of the substrate 110 may include silicon carbide.

[0282] An epitaxial layer 120 is disposed on the front side of the substrate 110, and a drain electrode layer is disposed on the back side of the substrate 110. Herein, the front side of the substrate 110 refers to the upper surface of the substrate 110, and the back side of the substrate 110 refers to the lower surface of the substrate 110.

[0283] It should be noted that the doping concentration of the epitaxial layer 120 is not limited in this embodiment, and can be prepared according to actual needs. Furthermore, the conductivity type of the epitaxial layer 120 is not limited. For example, the conductivity type of the epitaxial layer 120 can be either the first conductivity type N-type or the first conductivity type P-type.

[0284] In this embodiment, the example of the first conductivity type N-type of the epitaxial layer 120 is used for illustration.

[0285] Referring to Figures 22 to 24, the cell structure of the silicon carbide power device includes a gate structure 200, the gate structure 200 includes at least two first gate structures 210, and the at least two first gate structures 210 are disposed at intervals within the substrate 100.

[0286] Referring to Figures 22 to 24, the first gate structure 210 includes a gate dielectric layer 212, which covers the bottom and side surfaces of the first gate structure 210. In the specific fabrication process, an epitaxial layer 120 can be grown on the substrate 110 first, and then the epitaxial layer 120 can be patterned to form a gate trench in the epitaxial layer 120. Subsequently, the gate dielectric layer 212 is formed on the inner wall of the gate trench using thermal oxidation or deposition processes, and then the gate is formed, filling the area enclosed by the gate dielectric layer 212; thus, the gate dielectric layer 212 covers the bottom and side surfaces of the gate. The gate dielectric layer 212 is made of silicon oxide. The gate is made of polysilicon.

[0287] For example, a gate dielectric layer 212 can be grown on the sidewall of the gate trench using a deposition process, wherein the gate dielectric layer 212 also covers the top surface of the exposed epitaxial layer 120. Then, doped polysilicon is deposited in the gate trench to fill the gate trench and form the gate. The polysilicon and the gate dielectric layer are etched back, and the gate dielectric layer and the gate located in the gate trench are retained, thereby forming the first gate structure 210.

[0288] The silicon carbide power device cell structure includes a source structure 300 disposed on a substrate 100 and surrounding at least a portion of the sides of two first gate structures 210. In one example, the source structure 300 may surround a portion of the sides of the first gate structures 210, thus ensuring that the substrate 100 has both source and drain structures, thereby guaranteeing normal transistor operation. It should be understood that the source structure 300 may surround the top, bottom, or other locations of the sides of the first gate structures 210. Exemplarily, the source structure 300 may surround the first gate structures 210, thus ensuring that the source structure 300 is located on top of the epitaxial layer 120, reducing the doping difficulty of the source structure 300 and helping to reduce the manufacturing cost of the source structure 300.

[0289] In order to better shield the gate oxide electric field and ensure the output characteristics of silicon carbide power devices, in this embodiment of the application, the source structure 300 located between any two adjacent first gate structures 210 extends toward the bottom surface of the substrate 100 to form a protruding structure 330, and a portion of the protruding structure 330 constitutes an electric field shielding structure.

[0290] In this way, on the one hand, the area of ​​the source structure 300 can be increased, thereby better shielding the gate oxide electric field. In addition, the increase in the source structure 300 can provide more charge carriers, and the increase in area can further reduce the concentration of the source structure, thereby appropriately increasing the short-circuit withstand capability of the device. On the other hand, when the extended source structure 300 acts as an electric field shielding structure, it can effectively shield the gate oxide electric field when the device is in the reverse blocking state, thereby maximizing the shielding effect of the gate oxide electric field.

[0291] In one feasible implementation, referring to Figures 21 to 24, both the source structure 300 and the protrusion structure 330 include a first conductivity type source layer 310 and a second conductivity type source active layer 320, wherein the second conductivity type source active layer 320 is disposed on the substrate 100, and the first conductivity type source layer 310 is disposed on the second conductivity type source active layer 320.

[0292] The first conductivity type source layer 310 and the second conductivity type source active layer 320 both extend toward the bottom surface of the substrate 100; at least a portion of the second conductivity type source active layer 320 forms an electric field shielding structure.

[0293] The first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0294] In this embodiment, the description mainly takes the second conductivity type source active layer 320 as the first conductivity type P-type and the first conductivity type source layer 310 as the second conductivity type P-type.

[0295] When a positive voltage is applied to the first gate structure 210, the second conductivity type source active layer 320 forms an inversion region around a portion of the first gate structure 210, i.e., a channel region, so that the conductivity type of the channel region is the same as the conductivity type of the first conductivity type source layer 310, thereby making the silicon carbide power device cell structure in a conducting state.

[0296] Compared with the first conductivity type source layer 310, the second conductivity type source active layer 320 is closer to the bottom surface of the substrate 100. This can increase the depth of the electric field shielding structure. When the device is in reverse blocking state, it can effectively and timely block the gate oxide electric field formed by silicon carbide power, thereby maximizing the shielding effect of the gate oxide electric field.

[0297] In one feasible implementation, the first gate structure 210 has a first extension; the first extension extends in a direction away from the first gate structure 210. Alternatively, the first extension protrudes at least from one side of the first gate structure 210. This increases the contact area between the source structure 300 and the first gate structure 210, thereby maximizing the channel area of ​​the silicon carbide power device during forward conduction, reducing the forward conduction resistance, and ultimately improving the performance of the silicon carbide power device.

[0298] Furthermore, the first gate structure 210 can be further enhanced to control the channel region, thereby improving the switching performance of silicon carbide power devices.

[0299] In one possible implementation, as shown in FIG23, the gate structure 200 may further include a second gate structure 220; the second gate structure 220 is located between the two first gate structures 210 and is connected to the electric field shielding structure.

[0300] It should be noted that the reason for further setting the second gate structure 220 is that, in existing trench-gate silicon carbide power devices, the gate oxide layer is more prone to breakdown due to the high breakdown electric field and high dielectric constant of silicon carbide, resulting in poor device reliability. To solve this problem, an electric field shielding layer is generally set on the device. However, the introduction of the electric field shielding layer will increase the forward conduction resistance. Therefore, while ensuring the reliability of the gate oxide layer, the forward conduction resistance needs to be further reduced.

[0301] Therefore, in this embodiment, a second gate structure 220 is provided, which forms a deep electric field shielding structure. This also helps to increase the channel at the electric field shielding structure without affecting the electric field shielding effect. It can ensure the reliability of the gate oxide while increasing the channel of the silicon carbide power device, thereby reducing the forward conduction resistance of the silicon carbide power device and improving the output performance of the silicon carbide power device.

[0302] In one feasible implementation, the second gate structure 220 can be a planar gate structure, located above the protruding structure 330, with its bottom surface in contact with the protruding structure 330. Here, a planar gate means that both the gate and the gate dielectric layer are located on the silicon wafer surface, forming a horizontal current channel. Furthermore, the gate dielectric layer of the second gate structure 220 covers the bottom surface of the gate.

[0303] In one feasible implementation, the second gate structure 220 can be a trench gate structure, and the second gate structure 220 is located within the protruding structure 330. The trench gate is where the gate is embedded inside the silicon wafer, forming a vertical current channel.

[0304] In this embodiment, the second gate structure 220 also includes a gate 211 and a gate dielectric layer 212, with the gate dielectric layer 212 covering the bottom and side surfaces of the gate 211.

[0305] In this embodiment, referring to FIG23, the description mainly takes the second gate structure 220 as a trench gate structure. Compared with the planar gate silicon carbide power device cell structure, the cell structure of the trench gate silicon carbide power device can be smaller in size and has a higher channel mobility. Therefore, the trench gate silicon carbide power device greatly reduces the resistance of the silicon carbide power device during forward conduction and improves the performance of the silicon carbide power device cell structure.

[0306] In one feasible implementation, the source structure 300 also surrounds a portion of the sidewalls of the second gate structure 220, such that the second gate structure 220, the source structure 300, and a portion of the epitaxial layer 120 constitute a transistor. This allows for the arrangement of more cell structures within the same area, thereby increasing the overall current handling capability of the power device or reducing the size of the device to meet the needs of higher power density and more compact design.

[0307] To clearly illustrate the relative positional relationship between the source structure 300 and the protrusion structure 330 and the second gate structure 220, we can use two cross-sections as examples. For instance, a cross-sectional view is taken along the section line AA in Figure 22 to form the first cross-section. Another example is a cross-sectional view taken along the section line BB in Figure 22 to form the second cross-section.

[0308] Referring to Figure 23, in a first cross-section, the first conductivity type source layer 310 of the protruding structure 330 covers at least a portion of the side surfaces of the second gate structure 220. In one example, the first conductivity type source layer 310 of the protruding structure 330 covers a portion of the side surfaces of the second gate structure 220. In another example, the first conductivity type source layer 310 of the protruding structure 330 covers all the side surfaces of the second gate structure 220.

[0309] In this embodiment, by adjusting the contact area between the first conductivity type source layer 310 of the protruding structure 330 and the second gate structure 220, the current regulation area of ​​the source structure (protruding structure 330) by the second gate structure 220 can be effectively increased. This makes the electric field distribution of the channel region by the second gate structure 220 more uniform, thereby improving the control capability of carrier movement in the channel and helping to achieve more precise current control and higher device performance.

[0310] In order to further rationally control the contact area between the first conductivity type source layer 310 of the protruding structure 330 and the second gate structure 220, the silicon carbide power device cell structure provided in this application embodiment has, on the first cross-section, the first conductivity type source layer 310 of the protruding structure 330 covers at least a portion of the bottom surface of the second gate structure 220.

[0311] In other words, the first conductivity type source layer 310 of the protruding structure 330 can cover all sides and part of the bottom surface of the second gate structure 220, or the first conductivity type source layer 310 of the protruding structure 330 can cover all sides and the entire bottom surface of the second gate structure 220.

[0312] Furthermore, in the first cross-section, the second conductivity type source active layer 320 of the protruding structure 330 covers the first conductivity type source layer 310, such that the second conductivity type source active layer 320 of the protruding structure 330 covers the entire bottom surface and the entire side surface of the second gate structure 220.

[0313] This increases the area of ​​the second conductivity type source active layer 320. On one hand, when the device is in reverse blocking mode, it can greatly improve the electric field shielding effect of the second conductivity type source active layer 320. On the other hand, it helps to improve the current carrying capacity and thermal stability of the silicon carbide power device cell structure, thereby extending the service life of the silicon carbide power device cell structure.

[0314] In one feasible implementation, on the second cross-section, the second conductivity type source active layer 320 of the protruding structure 330 covers at least a portion of the bottom surface of the second gate structure 220; wherein the first cross-section and the second cross-section are different cross-sections.

[0315] With this configuration, the second gate structure 220 is partially surrounded by the source structure 300 at certain locations. When a voltage is applied to the second gate structure 220, the second gate structure 220, the source structure 300, and part of the epitaxial layer 120 can be turned on more effectively, thereby forming a transistor with more stable performance and lower on-resistance.

[0316] Referring to Figures 22 and 23, in one feasible embodiment, the second gate structure 220 has a main stem 221 and a second extension 222. The second extension 222 is connected to the side of the main stem 221 and extends toward the first gate structure 210. The main stem direction of the main stem 221 is a first direction, and the extension direction of the second extension 222 is a second direction. The first direction and the second direction intersect. The second conductivity type source active layer 320 does not extend beyond the second extension 222 along its extension direction. The first direction is the X direction in Figure 1, and the second direction is the Y direction in Figure 22.

[0317] In this embodiment, both the first gate structure 210 and the second gate structure 220 are trench gates. Therefore, the first gate structure 210 is formed in the first gate trench, and the second gate structure 220 is formed in the second gate trench, wherein the second gate trench extends toward the first gate trench. For example, referring to Figures 22 and 23, the extension direction of the first gate trench can be shown by arrow a in Figure 23, and the extension direction of the second gate trench can be shown by arrows b2 and b1 in Figure 23.

[0318] An electric field shielding structure located around the second gate trench is connected to the source structure 300, thereby enabling the electric field shielding structure located around the second gate trench to further shield the electric field located around the first gate trench.

[0319] Furthermore, the second extension 222 of the second gate structure 220 is surrounded by the source structure 300, which increases the channel formed between the second gate structure 220 and the source structure 300. For example, two channels are added between the second gate structure 220 and the source structure 300. The added channels can be referred to as the area indicated by arrow b2 in Figure 22. This allows the second gate structure 220 to have a channel in the circumference, reducing the forward conduction resistance of the silicon carbide power device and improving the reliability of the silicon carbide power device.

[0320] In this embodiment, referring to FIG22, the second conductivity type source active layer 320 does not extend beyond the second extension portion 222 along the extension direction. It should be noted that if the second conductivity type source active layer 320 extends beyond the second extension portion 222, it will completely enclose the trench, and the channel will not exist, thus failing to achieve the effect of increasing the channel of the silicon carbide power device. Therefore, in this embodiment, this limitation ensures the existence of the channel, thereby helping to increase the channel of the silicon carbide power device.

[0321] In one feasible implementation, as shown in FIG22, there may be multiple second extensions 222, and the arrangement of the multiple second extensions 222 of the second gate structure 220 can be set according to actual needs.

[0322] For example, a plurality of second extensions 222 may be disposed on one side of the second gate structure 220 along a direction parallel to the plane of the substrate 100 and arranged at intervals along the first direction.

[0323] It should be noted that there are multiple second gate structures 220 and multiple first gate structures 210. The multiple second gate structures 220 are arranged at intervals along the second direction, and each second gate structure 220 is located between any two adjacent first gate structures 210.

[0324] When there are multiple second gate structures 220, the second extension 222 of each second gate structure 220 is located on the same side of the corresponding second gate structure 220; for example, the second extension 222 of each second gate structure 220 is located on the left or right side of the corresponding second gate structure 220.

[0325] Alternatively, the second extensions 222 of each second gate structure 220 can be located on opposite sides of the corresponding gate structure 200. For example, in any two adjacent second gate structures 220, the second extension 222 of one second gate structure 220 is located on its left side, and the second extension 222 of the other second gate structure 220 is located on its right side. This allows for diverse arrangements of the second extensions 222, enabling more second extensions 222 to be placed on a limited structure, increasing the channel length of the silicon carbide power device cell structure, and facilitating more complex and high-performance circuit designs.

[0326] In one possible implementation, the second extension 222 includes a plurality of second extensions 222; on a plane parallel to the substrate 100, the plurality of second extensions 222 are disposed on opposite sides of the second gate structure 220 along a second direction; and the plurality of second extensions 222 located on the same side are arranged at intervals along a first direction.

[0327] In this way, the number of second extensions 222 can be increased as much as possible, thereby increasing the channel length as much as possible, reducing the forward conduction resistance of silicon carbide power devices, and improving the reliability of silicon carbide power devices.

[0328] When multiple second extensions 222 are disposed on opposite sides of the second gate structure 220 along the second direction, the second extensions 222 located on both sides of the same second gate structure 220 are disposed opposite each other along the second direction; or, the second extensions 222 located on both sides of the same second gate structure 220 are disposed offset along the second direction. In this way, by flexibly arranging the second extensions 222 located on both sides of the same second gate structure 220, the current distribution in the silicon carbide power device can be further optimized, significantly reducing the current congestion effect inside the device and improving the current carrying capacity of the device.

[0329] In one feasible implementation, referring to FIG23, the silicon carbide power device cell structure further includes a source electrode layer 600, which is disposed on and connected to the source structure 300. It should be understood that when the source structure 300 includes a first conductivity type source layer 310 and a second conductivity type active source layer 320 stacked together, the source electrode layer 600 and the second conductivity type active source layer 320 are electrically connected.

[0330] It is important to understand that the source electrode layer 600 and the second conductivity type source active layer 320 can be directly electrically connected or indirectly electrically connected. In one example, the source electrode layer 600 and the second conductivity type source active layer 320 are interconnected to form electrical conductivity, which simplifies the fabrication process of the silicon carbide power device cell structure and reduces the production cost of the semiconductor structure. In another example, as shown in Figures 22 to 24, the silicon carbide power device cell structure also includes a second conductivity type source ohmic contact layer 500. The source electrode layer 600 and the source structure 300 are connected through the second conductivity type source ohmic contact layer 500, or in other words, the source electrode layer 600 and the second conductivity type source active layer 320 are connected through the second conductivity type source ohmic contact layer 500.

[0331] This embodiment utilizes a second conductivity type source ohmic contact layer 500 to provide a low-resistance path, making the electrical conduction between the source electrode layer 600 and the second conductivity type source active layer 320 more efficient, thereby reducing contact resistance and improving the device's conductivity. Furthermore, the second conductivity type source ohmic contact layer 500 also helps optimize the carrier transport path, improving the current drive capability and overall performance of the silicon carbide power device.

[0332] In one possible implementation, referring to Figures 23 and 24, an insulating layer 400 may be included, which covers the gate structure 200 to achieve insulation between the first gate structure 210 and the second gate structure 220. The insulating layer 400 may include silicon oxide, silicon nitride, or other insulating materials.

[0333] Referring to Figure 25, this application embodiment also provides a method for fabricating a silicon carbide power device cell structure, comprising the following steps:

[0334] Step S100: Provide a substrate.

[0335] Step S200: A source structure and a gate structure are formed on the substrate. The gate structure includes two first gate structures. The source structure at least surrounds a portion of the side surfaces of the two first gate structures, and a portion of the source structure located between the two first gate structures extends toward the bottom surface of the substrate to form a protruding structure. A portion of the protruding structure constitutes an electric field shielding structure.

[0336] The silicon carbide power device cell structure prepared by this method has an added source structure, which can be better used to shield the gate oxide electric field. In addition, the addition of the source structure can provide more charge carriers, and the increase in area can further reduce the concentration of the source structure, thereby appropriately increasing the short-circuit withstand capability of the device.

[0337] Referring to Figure 25, in one possible implementation, the method for fabricating silicon carbide power device cells further includes:

[0338] The step of providing the substrate includes:

[0339] Provide substrate;

[0340] An epitaxial layer is formed on the substrate.

[0341] For example, an epitaxial layer can be formed on a substrate using an epitaxial process. The conductivity type of the epitaxial layer is the same as that of the substrate. For instance, both the substrate and the epitaxial layer may be of a first conductivity type, which can be either N-type or P-type. As an example, the first conductivity type can be N-type.

[0342] In one possible implementation, the steps for forming the source structure include:

[0343] A protruding structure is formed, which is located within the substrate.

[0344] For example, referring to FIG26, a first photoresist layer 700 is formed and patterned to form a first mask opening 710 in the first photoresist layer 700. The first mask opening 710 exposes a portion of the substrate 100.

[0345] Using the first photoresist layer 700 as a mask, the substrate 100 exposed within the opening 710 of the first mask is doped using an ion doping process to form a second conductivity type source active layer 320. It should be noted that when the substrate 100 includes a substrate 110 and an epitaxial layer 120, this step involves doping the epitaxial layer 120 to form the second conductivity type source active layer 320 within the epitaxial layer 120.

[0346] Then, the first photoresist layer 700 is removed.

[0347] Referring to Figure 27, a second photoresist layer 800 is formed and patterned to form a second mask opening 810 within the second photoresist layer 800. The second mask opening 810 exposes a portion of the second conductivity type source active layer 320. In other words, the area of ​​the second mask opening 810 is smaller than the area of ​​the first mask opening 710.

[0348] Using the second photoresist layer 800 as a mask, the second conductivity type source active layer 320 exposed within the opening 810 of the second mask is doped using an ion doping process to form the first conductivity type source layer 310. The first conductivity type source layer 310 and the second conductivity type source active layer 320 constitute the structure.

[0349] Then, the second photoresist layer 800 is removed.

[0350] A source structure is formed, which surrounds a portion of the outer peripheral surface of the protruding structure and is connected to the first source structure; the portion of the protruding structure constitutes an electric field shielding structure.

[0351] Referring to Figure 28, a third photoresist layer (not shown in the figure) is formed, which covers the first conductivity type source layer 310 of the protruding structure 330, exposing the remaining locations of the substrate 100.

[0352] Using the third photoresist layer as a mask, an ion doping process is employed to dope at least the substrate 100 or the epitaxial layer 120 to form a second conductivity type source active layer 320.

[0353] The second conductivity type source active layer 320 is further doped using ion doping technology to form a first conductivity type source layer 310 within the second conductivity type source active layer 320. The first conductivity type source layer 310 and the second conductivity type source active layer 320 formed here constitute the source structure 300.

[0354] In one possible implementation, after the step of forming the source structure and before the step of forming the gate structure, the method further includes:

[0355] A second conductivity type source ohmic contact layer is formed and disposed on the source structure. It should be noted that the second conductivity type source ohmic contact layer may be located within the first conductivity type source layer 310 of the source structure 300, or within the second conductivity type source active layer 320 of the source structure 300, or simultaneously located within both the first conductivity type source layer 310 and the second conductivity type source active layer 320 constituting the source structure 300.

[0356] In one possible implementation, the steps for forming the gate structure include:

[0357] At least two spaced-apart first gate structures are formed, and a source structure is disposed in each first gate structure in a direction perpendicular to the substrate, such that the source structure surrounds a portion of the outer peripheral surface of each first gate structure.

[0358] A second gate structure is formed, which is located within the protruding structure.

[0359] For example, referring to Figures 29 and 30, the protrusion structure 330 is patterned to form a second gate trench 250 in the protrusion structure 330, the depth direction of the second gate trench 250 being perpendicular to the substrate 100. The bottom of the second gate trench 250 may be located within the first conductivity type source layer 310 of the protrusion structure 330, or it may be located within the second conductivity type source active layer 320.

[0360] Referring to Figure 31, a fourth photoresist layer 900 is formed. The fourth photoresist layer 900 fills the second gate trench 250 and covers the top surface of the protruding structure 330 and part of the top surface of the source structure 300.

[0361] Using the fourth photoresist layer 900 as a mask, a portion of the exposed source structure 300 and a portion of the substrate 100 are removed to form a first gate trench 240. The depth of the first gate trench 240 is less than the depth of the second gate trench 250.

[0362] Next, the fourth photoresist layer 900 is removed.

[0363] Referring to Figure 32, a first gate structure 210 is formed in the first gate trench 240, and a second gate structure 220 is formed in the second gate trench 250.

[0364] Please refer to Figure 23. After the step of forming the gate structure, the method for fabricating the cell structure of silicon carbide power devices also includes:

[0365] Form an insulating layer covering the gate structure;

[0366] A patterned insulating layer is used to form source metal contact holes in the insulating layer that expose a portion of the second conductivity type source active layer.

[0367] Fabricate the source electrode layer to complete the fabrication of the trench gate silicon carbide power device.

[0368] For example, the insulating layer 400 may be made of silicon oxide, silicon nitride, aluminum oxide, or other insulating materials.

[0369] This application also provides a semiconductor device, including the silicon carbide power device cell structure described in any of the above embodiments. The semiconductor device formed in this embodiment is not limited to devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs); any device having a silicon carbide power device cell structure is within the scope of this patent.

[0370] It should be noted that the beneficial effects of the semiconductor device provided in this application embodiment are the same as the beneficial effects of the silicon carbide power device cell structure provided in the above embodiment, and will not be elaborated further in this embodiment.

[0371] The semiconductor devices provided in this application embodiment can be applied to vehicles, for example, to key electric drive and control components such as the vehicle's main drive inverter, converter, on-board charger (OBC), and on-board charging pile. The vehicle can be an electric vehicle, a hybrid vehicle, or a new energy vehicle.

[0372] Therefore, embodiments of this application provide a silicon carbide power device cell structure and its fabrication method, as well as a semiconductor device, including a source structure disposed on a substrate and at least surrounding a portion of the side surfaces of two first gate structures 210; a portion of the source structure located between the two first gate structures 210 extends toward the bottom surface of the substrate to form an electric field shielding structure. In this way, increasing the source structure can better shield the gate oxide electric field. Furthermore, increasing the source structure can provide more charge carriers, and the increased area can further reduce the concentration of the source structure, thereby appropriately increasing the device's short-circuit withstand capability.

[0373] Example 4:

[0374] Referring to Figures 33 to 38, this application provides a silicon carbide power device cell. In this embodiment, a trench-type silicon carbide power device cell is used as an example for illustration.

[0375] Referring to FIG33, the silicon carbide power device cell includes a substrate 100.

[0376] The substrate 100 includes a substrate 110. The substrate 110 serves as a support component for the silicon carbide power device cell, supporting other components disposed thereon. The substrate 110 may be made of a semiconductor material. For example, the material of the substrate 110 may include silicon carbide.

[0377] An epitaxial layer 120 is disposed on the front side of the substrate 110, and a drain electrode layer is disposed on the back side of the substrate 110. Herein, the front side of the substrate 110 refers to the upper surface of the substrate 110, and the back side of the substrate 110 refers to the lower surface of the substrate 110.

[0378] It should be noted that the doping concentration of the epitaxial layer 120 is not limited in this embodiment, and can be prepared according to actual needs. Furthermore, the conductivity type of the epitaxial layer 120 is not limited. For example, the conductivity type of the epitaxial layer 120 can be either the first conductivity type N-type or the first conductivity type P-type.

[0379] In this embodiment, the example of the first conductivity type N-type of the epitaxial layer 120 is used for illustration.

[0380] Referring again to Figure 33, the silicon carbide power device cell includes a gate structure 200 disposed within the substrate 110, such that the gate structure 200 forms a trench gate. Compared to planar gate semiconductor devices, trench gate semiconductor devices can have smaller cell sizes and higher channel mobility. Therefore, trench gate silicon carbide power devices significantly reduce the resistance during forward conduction, thereby improving the performance of the silicon carbide power device cell.

[0381] Referring to FIG33, the gate structure 200 includes a gate 210 and a gate dielectric layer 220, the gate dielectric layer 220 covering the bottom and side surfaces of the gate 210. In the specific fabrication process, an epitaxial layer 120 of a first conductivity type can be grown first on a substrate 110 of a first conductivity type. Then, the epitaxial layer 120 is patterned to form a gate trench within the epitaxial layer 120. Subsequently, the gate dielectric layer 220 is formed on the inner wall of the gate trench using thermal oxidation or deposition processes, followed by the formation of the gate 210, which fills the area enclosed by the gate dielectric layer 220. Thus, the gate dielectric layer 220 covers the bottom and side surfaces of the gate 210. The gate dielectric layer 220 is made of silicon oxide. The gate 210 is made of polysilicon.

[0382] For example, a gate dielectric layer 220 can be grown on the sidewall of the gate trench using a deposition process, wherein the gate dielectric layer 220 also covers the top surface of the exposed epitaxial layer 120. Then, doped polysilicon is deposited in the gate trench to fill the gate trench and form the gate. The polysilicon and the gate dielectric layer are etched back, and the gate dielectric layer and the gate located in the gate trench are retained, thereby forming the gate structure 200.

[0383] Referring again to FIG33, in this embodiment of the application, the silicon carbide power device cell includes a source structure 300 and a source electrode layer 800. The source structure 300 is disposed within the substrate 100 and surrounds at least a portion of the sidewalls of the gate structure 200. The source electrode layer 800 is disposed on the source structure 300 and connected to the source structure 300.

[0384] In order to increase the channel area and reduce the forward conduction resistance of silicon carbide power devices during forward conduction, in this embodiment of the application, as shown in FIG33, the source structure 300 may include a first source structure 310 and a second source structure 320, wherein the first source structure 310 is connected to the second source structure 320 through the source electrode layer 800.

[0385] In this embodiment, the positions of the first source structure 310 and the second source structure 320 are not specifically limited, and can be set according to actual needs. For example, referring to FIG33, the first source structure can surround the top of the gate structure 200, and the second source structure 320 can at least cover a portion of the bottom of the gate structure 200.

[0386] In this way, the present application adds a channel extending upward from the bottom of the trench on the trench sidewall, which further increases the channel length, thereby maximizing the channel area of ​​the silicon carbide power device during forward conduction and reducing the forward conduction resistance of the device. Compared with related technologies, the present application can ensure the gate oxide reliability of the silicon carbide power device when it is in reverse blocking state, while further increasing the channel passage on the trench sidewall, thereby minimizing the channel resistance during forward conduction, reducing the forward conduction resistance of the silicon carbide power device, and improving the output characteristics of the silicon carbide power device.

[0387] In this embodiment, the portion of the structure at the bottom of the second source structure 320 can serve as an electric field shielding structure. In this way, when the silicon carbide power device cell structure is in a reverse bias state, the electric field can be prevented from accumulating at the bottom of the gate dielectric layer 220, thereby improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure caused by the breakdown of the gate dielectric layer. This ensures the performance and reliability of the gate structure and further guarantees the performance and reliability of the semiconductor device.

[0388] In one possible implementation, referring to FIG33, along the thickness direction of the substrate 100, the first source structure 310 includes a first source layer 311 of a first conductivity type and a first source active layer 312 of a second conductivity type. The first source active layer 312 of the second conductivity type is disposed on the substrate 100, and the first source layer 311 of the first conductivity type is disposed on the first source active layer 312 of the second conductivity type; the first source active layer 312 of the second conductivity type is connected to the second source structure 320 through the source electrode layer 800.

[0389] The first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0390] In this embodiment, the first source active layer 312 of the second conductivity type is P-type and the first source layer 311 of the first conductivity type is N-type, as an example for illustration.

[0391] When a positive voltage is applied to the gate structure 200, the first source active layer 312 of the second conductivity type forms an inversion region around a portion of the gate structure 200, i.e., a channel region, so that the conductivity type of the channel region is the same as the conductivity type of the first source layer 311 of the first conductivity type, thereby making the silicon carbide power device in the conducting state.

[0392] In this embodiment, at least one of the first source active layer 312 of the second conductivity type and the first source layer 311 of the first conductivity type is connected to the second source structure 320 through the source electrode layer 800. That is, one of the first source active layer 312 of the second conductivity type and the first source layer 311 of the first conductivity type is connected to the second source structure 320 through the source electrode layer 800, or both the first source active layer 312 of the second conductivity type and the first source layer 311 of the first conductivity type are connected to the second source structure 320 through the source electrode layer 800 (see Figure 38). In this way, a channel is also formed between the second source structure 320, which covers at least a portion of the bottom of the gate structure 200, and the gate structure 200. This can maximize the channel area when the silicon carbide power device is forward-biased and reduce the forward-biased resistance of the device.

[0393] In one possible implementation, referring to Figures 33, 35, 37, and 38, along the thickness direction of the substrate, the second source structure 320 includes a second source layer 321 of a first conductivity type and a second source active layer 322 of a second conductivity type; wherein, the second source active layer 322 of the second conductivity type is disposed on the substrate 100, and the second source layer 321 of the first conductivity type is disposed on the second source active layer 322 of the second conductivity type. The first source active layer 312 of the second conductivity type is connected to the second source active layer 322 of the second conductivity type through a source electrode layer 800.

[0394] In this embodiment, the second source active layer 322 of the second conductivity type is P-type and the second source layer 321 of the first conductivity type is N-type, which is used as an example for illustration.

[0395] When a positive voltage is applied to the gate structure 200, the second source active layer 322 of the second conductivity type forms an inversion region around a portion of the gate structure 200, i.e., a channel region, so that the conductivity type of the channel region is the same as the conductivity type of the second source layer 321 of the first conductivity type, thereby making the silicon carbide power device in the conducting state.

[0396] In this embodiment, at least one of the second source layer 321 of the first conductivity type and the second source active layer 322 of the second conductivity type is connected to the first source structure 310 through the source electrode layer 800. Thus, when the source electrode layer 800 applies a voltage to the first source structure 310, it also simultaneously applies a voltage to the second source structure 320, forming a channel between the second source structure 320 and the gate structure 200. This configuration ensures that channels are formed between both the first source structure 310 and the second source structure 320 and the gate structure 200, thereby maximizing the channel area during forward conduction of the silicon carbide power device and reducing the forward conduction resistance of the device.

[0397] It should be noted that, in this embodiment, the second source active layer 322 of the second conductivity type serves as an electric field shielding structure. In this way, when the silicon carbide power device cell structure is in a reverse bias state, the electric field can be prevented from accumulating at the bottom of the gate dielectric layer 220, thereby improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure caused by the breakdown of the gate dielectric layer. This ensures the performance and reliability of the gate structure and further guarantees the performance and reliability of the semiconductor device.

[0398] In one possible implementation, a second source layer 321 of the first conductivity type covers the bottom and part of the sides of the gate structure 200. The second source layer 321 of the first conductivity type is not connected to the first source structure 310, thus ensuring the normal operation of the transistor formed by the gate structure 200 and the source structure 300.

[0399] In one possible implementation, the second source active layer 322 of the second conductivity type covers the bottom and part of the sides of the second source active layer 321 of the first conductivity type. Thus, the second source active layer 322 of the second conductivity type is partially enclosed in the second source active layer 321 of the first conductivity type, which reduces the fabrication difficulty of the second source active layer 322 of the second conductivity type.

[0400] It should be noted that the second source active layer 322 of the second conductivity type not only partially encloses the second source layer 321 of the first conductivity type, but can also have other structures. For example, the second source active layer 322 of the second conductivity type covers a portion of the side of the gate structure 200. That is, the second source active layer 322 of the second conductivity type not only covers the second source layer 321 of the first conductivity type, but also extends towards the first source structure and covers a portion of the side of the gate structure 200. With this configuration, the second source active layer 322 of the second conductivity type is in direct contact, increasing the contact area between the gate structure 200 and the second source active layer 322 of the second conductivity type, thereby enhancing the control capability of the gate structure 200 over the channel region. When a voltage is applied to the gate structure 200, the contact area between the second source active layer 322 of the second conductivity type and the gate structure 200 can undergo inversion more quickly, improving the transistor's response speed.

[0401] When the second source active layer 322 of the second conductivity type covers a portion of the side of the gate structure 200, the second source active layer 322 of the second conductivity type is not connected to the first source structure 310. This design, where the second source active layer 321 of the first conductivity type is not connected to the first source structure 310, ensures that the substrate 100 has both source and drain structures, thus guaranteeing the normal operation of the transistor.

[0402] In one possible implementation, as shown in FIG33, the silicon carbide power device cell may further include an ohmic contact layer 600, the conductivity type of the ohmic contact layer 600 being a second conductivity type; the doping concentration of the second conductivity type of the ohmic contact layer 600 is greater than the doping concentration of the second conductivity type in the first source active layer 312 of the second conductivity type.

[0403] The first source structure 310 and the second source structure 320 are electrically connected to the source electrode layer 800 via an ohmic contact layer 600. Since the doping concentration of the second conductivity type in the ohmic contact layer 600 is greater than the doping concentration of the second conductivity type in the first source active layer 312, the second conductivity type ohmic contact layer 600 provides a low-resistance path, reducing the contact resistance between the source electrode layer 800 and the first source structure 310, and between the source electrode layer 800 and the second source structure 320, thereby improving device performance.

[0404] To facilitate a detailed description of the connection between the ohmic contact layer 600 and the first source structure 310 or the second source structure 320, the ohmic contact layer 600 can be divided.

[0405] For example, the ohmic contact layer 600 may include a first ohmic contact layer 610. The first source active layer 312 of the second conductivity type is connected to the source electrode layer 800 through the first ohmic contact layer 610.

[0406] In this embodiment, the first ohmic contact layer 610 is doped in the first source active layer 312 of the second conductivity type. Its structure is shown in Figure 33.

[0407] Alternatively, in this embodiment, the first ohmic contact layer 610 is doped in the first source layer 311 of the first conductivity type. See Figure 35 for the structure.

[0408] Alternatively, in this embodiment, the first ohmic contact layer 610 is simultaneously doped in the first source layer 31 of the first conductivity type and the first source active layer 312 of the second conductivity type. See Figure 38 for the structure.

[0409] In this embodiment, the location of the ohmic contact layer 600 is flexibly designed, for example, by doping it in the first source active layer 312 of the second conductivity type or the first source layer 311 of the first conductivity type, to adapt to different device structures and performance requirements.

[0410] In this embodiment, the ohmic contact layer 600 further includes a second ohmic contact layer 620; the second source active layer 322 of the second conductivity type is connected to the source electrode layer 800 through the second ohmic contact layer 620.

[0411] The first ohmic contact layer 610, projected onto the substrate 100, surrounds the outer periphery of the second ohmic contact layer 620, projected onto the substrate 100. This helps to distribute current more evenly, preventing excessive current concentration in certain areas that could lead to overheating or damage to the device, thereby improving the device's reliability and stability.

[0412] In other embodiments, referring to FIG34, the orthographic projection of the gate structure 200 onto the substrate 100 surrounds the outer periphery of the orthographic projection of the second ohmic contact layer 620 onto the substrate 100. This arrangement allows the gate structure 200 to more effectively control the electric field distribution of the second source active layer 322 of the second conductivity type and its surroundings, thereby improving the gate structure 200's control over the channel region and contributing to improved device switching speed and response characteristics.

[0413] In one possible implementation, the second ohmic contact layer 620 is doped in the second source active layer 322 of the second conductivity type. Alternatively, the second ohmic contact layer 620 is doped in the second source active layer 321 of the first conductivity type. Thus, by flexibly designing the placement of the second ohmic contact layer 620, such as doping it in the second source active layer 322 of the second conductivity type or the second source active layer 321 of the first conductivity type, different device structures and performance requirements can be accommodated.

[0414] In one possible implementation, the first source structure 310 can be positioned close to the top of the gate structure 200. Given that the first source structure 310 is typically fabricated using a doping process, a position close to the top of the gate structure 200 may make it easier to achieve the required process conditions, thereby reducing the difficulty and complexity of the doping process. Furthermore, the depth and concentration of doping can be more easily controlled, improving doping precision and uniformity, which helps ensure that the first source structure 310 possesses the required electrical properties, thus enhancing the overall device performance and reliability.

[0415] In this embodiment, the shape of the gate structure 200 can be selected in various ways. In one possible implementation, as shown in FIG34, the gate structure 200 is a ring structure on the plane parallel to the substrate 100.

[0416] Accordingly, on a plane parallel to the substrate 100, the first ohmic contact layer 610 is a ring structure and surrounds the gate structure 200. The ring structure of the gate structure 200 can more effectively control the electric field distribution around it, which helps to reduce electric field concentration and leakage current, thereby improving the breakdown voltage and reliability of the device.

[0417] Referring to Figure 36, in another possible implementation, the gate structure 200 is a strip structure on a plane parallel to the substrate 100. Correspondingly, both the first ohmic contact layer 610 and the second ohmic contact layer 620 include multiple ohmic contacts; these multiple ohmic contacts are spaced apart along the extension direction of the gate structure 200. This configuration reduces the area of ​​the first ohmic contact layer 610 and the second ohmic contact layer 620, reduces parasitic capacitance, optimizes current distribution, improves the switching speed and reliability of the device, while simultaneously reducing manufacturing costs and increasing device flexibility.

[0418] Referring again to FIG33, in this embodiment of the application, the gate structure 200 may include at least two sub-gate structures 230, which are isolated from each other to ensure that the at least two sub-gate structures 230 are independent of each other. This helps to avoid the problem of mutual interference between the current flow directions of the at least two sub-gate structures 230, thereby ensuring that the current can flow along the two symmetrical channel segments, further ensuring that the channel area is increased during forward conduction, minimizing the channel resistance during forward conduction, and ensuring the reliability of the silicon carbide power device cell.

[0419] It should be noted that, in this embodiment, the isolation method between at least two sub-gate structures 230 is not limited. For example, an insulating spacer may be provided between at least two sub-gate structures 230, or an isolation hole may be formed on the gate structure 200, through which at least two sub-gate structures 230 are isolated. This embodiment does not limit this approach.

[0420] In this embodiment, the number of sub-gate structures 230 is not limited. Exemplarily, the number of sub-gate structures 230 can be two, three, or more. At least two sub-gate structures 230 can be arranged circumferentially along the gate structure 200. Exemplarily, when the number of sub-gate structures 230 includes two, the two sub-gates can be arranged symmetrically circumferentially along the gate structure 200; when the number of sub-gate structures 230 includes three or more, the three or more sub-gates can be arranged spaced apart circumferentially along the gate structure 200.

[0421] In one possible implementation, as shown in FIG33, the source electrode layer 800 may include an extension 810 located in the gate structure 200 and dividing the gate structure 200 into at least two sub-gate structures 230; the extension 810 is electrically insulated from each sub-gate structure 230.

[0422] In this embodiment, the shape, size, and position of the extension 810 are not limited. For example, the extension 810 can be a columnar structure, and the extension 810 can separate the gate structure 200 into two sub-gate structures 230, which are symmetrically distributed on both sides of the extension 810.

[0423] When a forward voltage is applied to the gate structure 200, the first source active layer 312 of the second conductivity type and the second source active layer 322 of the second conductivity type respectively form inversion regions around portions of the two sub-gate structures 230, i.e., respectively form channel regions. Compared with related technologies, this application is beneficial in avoiding the problem of sacrificing the channel on one side of the trench in related technologies, increasing the number of conducting channels, thereby helping to ensure a higher channel mobility when the silicon carbide power device cell is forward-biased, thereby increasing the channel area during forward conduction, increasing the active region area, thereby minimizing the channel resistance during forward conduction, and thus reducing the on-resistance, improving the operating performance and reliability of the silicon carbide power device cell.

[0424] In this embodiment, referring to FIG33, two sub-gate structures 230 are symmetrically distributed on both sides of the extension 810. This ensures that both sides of the trench have channels, allowing current to flow along the two symmetrical channels, increasing the channel area during forward conduction, and thus minimizing the channel resistance during forward conduction. Furthermore, compared to the single channel of related technologies, this application helps avoid deeper ion implantation in the P-type source region, thereby saving material and consequently reducing costs.

[0425] In this embodiment, the end of the extension 810 facing the bottom surface of the substrate 100 may extend into the second source structure 320, or may have other structures.

[0426] In one example, referring to FIG33, the end of the extension 810 toward the bottom surface of the substrate 100 extends into the second source structure 320; for example, the end of the extension 810 toward the bottom surface of the substrate 100 extends into the second source layer 321 of the first conductivity type, or extends into the second source active layer 322 of the second conductivity type, or extends to the interface between the second source layer 321 of the first conductivity type and the second source active layer 322 of the second conductivity type.

[0427] In another example, referring to Figures 35 and 38, the end of the extension 810 facing the bottom surface of the substrate 100 extends to the top surface of the second source structure 320.

[0428] This allows for reasonable adjustment of the dimensions of the extension 810 in the direction perpendicular to the substrate 100, based on the formation position of the ohmic contact layer 600, thereby improving the design flexibility of the extension 810.

[0429] In one possible implementation, the silicon carbide power device cell further includes an ohmic contact layer 600, which has a second conductivity type. The ohmic contact layer 600 contacts the bottom surface of the extension 810 facing the substrate 100 and protrudes from the extension 810. Alternatively, the area of ​​the ohmic contact layer 600 is larger than the area of ​​the extension 810, thereby maximizing the contact area between the ohmic contact layer 600 and the extension 810, and thus reducing the contact resistance between the source electrode layer 800 and the ohmic contact layer 600.

[0430] It should be noted that the area of ​​the ohmic contact layer 600 is not limited to being larger than the area of ​​the extension 810; other options are also possible. For example, the area of ​​the ohmic contact layer 600 may be less than or equal to the area of ​​the extension 810. In this way, the area of ​​the ohmic contact layer 600 can be reasonably set according to the doping concentration of the ohmic contact layer 600 to achieve optimal performance and cost-effectiveness.

[0431] In one possible implementation, referring to FIG33, an insulating layer 500 may also be included, which is located between the source electrode layer 800 and the gate structure 200, and between the extension 810 and the sub-gate structure 230. The insulating layer 500 has an insulating function, which is beneficial to achieving electrical insulation between the source electrode layer 800 and the gate structure 200, and between the extension 810 and the sub-gate structure 230.

[0432] In this embodiment, the shape, size, and position of the insulating layer 500 are not limited. For example, the insulating layer 500 may be L-shaped, wherein the horizontal segment of the insulating layer 500 may be located between the source electrode layer 800 and the gate structure 200, and the vertical segment of the insulating layer 500 may be located between the extension 810 and the sub-gate structure 230. Alternatively, the insulating layer 500 may have other shapes. This embodiment does not limit these aspects.

[0433] In this embodiment, the number of insulating layers 500 is not limited. For example, the number of insulating layers 500 may include one, two, or more. In this embodiment, the example of two insulating layers 500 is used for illustration, and the two insulating layers 500 are symmetrically arranged.

[0434] It should be noted that the structure of the silicon carbide power device cell in this embodiment includes the three structures mentioned above, and the specific structure can be set according to actual needs.

[0435] Referring to Figures 39 to 45, this application also provides a method for fabricating silicon carbide power device cells.

[0436] Step S100: Provide a substrate.

[0437] Step S200: Form a source structure and place it in the substrate; wherein the source structure includes a first source structure and a second source structure arranged at intervals.

[0438] Step S300: Form a gate structure, which is disposed in a substrate; a first source structure surrounds at least a portion of the side of the gate structure; a second source structure covers at least the bottom of the gate structure, and a portion of the second source structure serves as an electric field shielding structure.

[0439] Step S400: Form a source electrode layer, which connects the first source structure and the second source structure.

[0440] The first source structure in the silicon carbide power device cell prepared by this method is connected to the second source structure through a source electrode layer; part of the second source structure serves as an electric field shielding structure. This adds channels upwards from the bottom of the trench to the trench sidewalls, further increasing the channel density and thus maximizing the channel area during forward conduction of the silicon carbide power device, thereby reducing the forward conduction resistance of the device.

[0441] Referring to Figure 40, in one possible implementation, the method for fabricating silicon carbide power device cells further includes:

[0442] The step of providing the substrate includes:

[0443] Provide substrate;

[0444] An epitaxial layer is formed on the substrate.

[0445] For example, an epitaxial layer can be formed on a substrate using an epitaxial process. The conductivity type of the epitaxial layer is the same as that of the substrate. For instance, both the substrate and the epitaxial layer may be of a first conductivity type, which can be either N-type or P-type. As an example, the first conductivity type can be N-type.

[0446] Referring to Figures 40 and 41, in one possible implementation, the step of forming the source structure includes:

[0447] A first source structure material layer is formed, which is disposed on the epitaxial layer.

[0448] It should be noted that, in this embodiment, the first source structure material layer can be formed in the epitaxial layer, for example, by ion implantation into the epitaxial layer through a doping process to form the first source structure material layer. Alternatively, the first source structure material layer can be formed on the epitaxial layer, for example, by deposition on the epitaxial layer through a deposition process.

[0449] A portion of the first source structure material layer and a portion of the substrate are removed to form a gate trench; the depth direction of the gate trench is perpendicular to the substrate, and the bottom of the gate trench extends into the epitaxial layer; wherein, the remaining first source structure material layer constitutes the first source structure.

[0450] In this step, a first photoresist layer 130 with a first mask opening 131 can be formed on the first source structure material layer.

[0451] Subsequently, using the first photoresist layer 130 as a mask, an etching process is performed to remove the first source structure material layer and a portion of the substrate 100 exposed within the first mask opening 131, thereby forming a gate trench. It should be noted that when the substrate 100 includes a substrate 110 and an epitaxial layer 120, this step involves removing the first source structure material layer and a portion of the epitaxial layer 120 exposed within the first mask opening 131 to form a gate trench.

[0452] It should be noted that in this embodiment, the shape of the first source structure 310 matches the shape of the gate trench. If the gate trench is cylindrical, the first source structure 310 is annular; if the gate trench is strip-shaped, the first source structure 310 is strip-shaped and is located on both sides along the extension direction perpendicular to the strip shape.

[0453] A second source structure is formed, which at least covers a portion of the bottom of the gate trench.

[0454] For example, using the first photoresist layer 130 as a mask, the epitaxial layer 120 exposed at the bottom of the gate trench is doped using an ion doping process to form a second source active layer 322 of the second conductivity type.

[0455] The second source active layer 322 of the second conductivity type is further doped using ion doping technology to form a second source layer 321 of the first conductivity type within the second source active layer 322 of the second conductivity type.

[0456] In one possible implementation, the steps for forming the gate structure include:

[0457] Referring to Figure 42, a gate dielectric layer 220 is formed on the inner wall of the gate trench using a deposition process, which includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0458] Subsequently, a deposition process is used to form a gate 210, which fills the area enclosed by the gate dielectric layer 220. The gate 210 and the gate dielectric layer 220 together constitute the gate structure 200.

[0459] It should be noted that the gate structure 200 can be a single structure or it can include multiple sub-gate structures 230. When the gate structure 200 includes multiple sub-gate structures 230, the steps for forming the gate structure further include:

[0460] Referring to Figure 11, a second photoresist layer 140 with a second mask opening 141 is formed, and the second mask opening exposes a portion of the gate structure 200.

[0461] Using the second photoresist layer 140 as a mask, an etching process is performed to remove the gate structure 200 exposed in the second mask opening 141, thereby forming an etch hole 240 in the gate structure 200. The etch hole 240 extends in a direction perpendicular to the substrate 100, thus dividing the gate structure 200 into at least two sub-gate structures 230. Taking the orientation shown in FIG11 as an example, the blank area above the dashed line is the second mask opening 141, and the blank area below the dashed line is the etch hole 240.

[0462] The bottom of the etched hole can be located at the interface between the second source structure 320 and the gate structure 200, or it can be located inside the second source structure 320. The specific location can be freely set according to the design requirements of the product.

[0463] The second photoresist layer 140 can then be removed by ashing or a cleaning process.

[0464] Referring to Figures 44 and 45, after the step of forming the gate structure and before the step of forming the source electrode layer, the method includes:

[0465] An ohmic contact layer is formed, comprising a first ohmic contact layer and a second ohmic contact layer; the first ohmic contact layer is disposed on the first source structure, and the second ohmic contact layer is disposed on the second source structure.

[0466] For example, referring to FIG44, an insulating layer 500 is formed, which covers the sidewall of the etched hole, the top surface of the gate structure 200, and a portion of the top surface of the first source structure 310, so that the remaining top surface of the first source structure 310 and the bottom wall of the etched hole are exposed.

[0467] Using the insulating layer 500 as a mask, a doping process is performed to ion-dopat the exposed first source structure 310 and second source structure 320 to form a first ohmic contact layer 610 and a second ohmic contact layer 620; wherein, the first ohmic contact layer 610 is disposed on the first source structure 310, the second ohmic contact layer 620 is disposed on the second source structure 320, and the first ohmic contact layer 610 and the second ohmic contact layer 620 constitute an ohmic contact layer 600.

[0468] In this embodiment, the insulating layer 500 is made of silicon oxide, silicon nitride, aluminum oxide, or other insulating materials.

[0469] Please refer to Figure 45 to continue. Use the deposition process to form the source electrode layer 800 covering the ohmic contact layer 600 and the insulating layer 500, thus completing the fabrication of the trench gate silicon carbide power device.

[0470] This application also provides a power device, including the silicon carbide power device cell described in any of the above embodiments. The power device formed in this embodiment is not limited to devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs); any device that is a silicon carbide power device cell is within the scope of this patent.

[0471] It should be noted that the beneficial effects of the power device provided in this application embodiment are the same as the beneficial effects of the silicon carbide power device cell provided in the above embodiment, and will not be elaborated further in this embodiment.

[0472] The power devices provided in this application embodiment can be applied to vehicles, for example, to key electric drive and control components such as vehicle main drive inverters, converters, on-board chargers (OBC), and on-board charging piles. The vehicle can be an electric vehicle, a hybrid electric vehicle, or a new energy vehicle.

[0473] Therefore, this application provides a silicon carbide power device cell and its fabrication method, as well as a semiconductor device. The source structure includes a first source structure and a second source structure, with the first source structure connected to the second source structure via a source electrode layer. A portion of the second source structure serves as an electric field shielding structure. Thus, when a portion of the second source structure acts as an electric field shielding structure, it can effectively shield the gate oxide electric field when the device is in reverse blocking mode. Simultaneously, channels extending upwards from the bottom of the trench are added to the trench sidewalls, further increasing the channel density. This maximizes the channel area during forward conduction of the silicon carbide power device, reducing the forward conduction resistance. Compared to related technologies, this application ensures gate oxide reliability when the silicon carbide power device is in reverse blocking mode while further increasing the channel path on the trench sidewalls, thereby minimizing the channel resistance during forward conduction, reducing the forward conduction resistance of the silicon carbide power device, and improving the output characteristics of the silicon carbide power device.

[0474] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0475] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0476] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A cell structure for a silicon carbide power device, wherein, include: Base (100); A gate structure (200) is disposed within the substrate (100); A source structure (300) is disposed on the substrate (100) and surrounds at least a portion of the sidewalls of the gate structure (200); An electric field shielding structure is disposed within the substrate (100), wherein the electric field shielding structure surrounds the bottom of the gate structure (200) and is connected to the source structure (300).

2. The silicon carbide power device cell structure according to claim 1, wherein, The electric field shielding structure is an electric field shielding layer (400), which covers at least a portion of the bottom of the cross-section of the gate structure (200).

3. The silicon carbide power device cell structure according to claim 2, wherein, The electric field shielding layer (400) extends to the bottom surface of the substrate (100) at a depth greater than the depth of the gate structure (200).

4. The silicon carbide power device cell structure according to claim 3, wherein, Along the thickness direction of the substrate (100), the electric field shielding layer (400) includes at least a first sub-electric field shielding layer (410) and a second sub-electric field shielding layer (420), wherein the first sub-electric field shielding layer (410) and the second sub-electric field shielding layer (420) are respectively disposed on both sides of at least a portion of the cross-section of the gate structure (200); In this process, at least one of the first sub-electric field shielding layer (410) and the second sub-electric field shielding layer (420) is connected to the source structure (300).

5. The silicon carbide power device cell structure according to claim 4, wherein, The first sub-electric field shielding layer (410) and / or the second sub-electric field shielding layer (420) cover the entire bottom surface of at least a portion of the cross-section of the gate structure (200).

6. The silicon carbide power device cell structure according to claim 5, wherein, The first sub-electric field shielding layer (410) and the second sub-electric field shielding layer (420) are electrically connected.

7. The silicon carbide power device cell structure according to claim 6, wherein, The electric field shielding layer (400) further includes a third sub-electric field shielding layer (430), which is disposed on the bottom surface of at least a portion of the cross-section of the gate structure (200).

8. The silicon carbide power device cell structure according to claim 7, wherein, The third sub-electric field shielding layer (430) is electrically connected to the first sub-electric field shielding layer (410) and / or the second sub-electric field shielding layer (420).

9. The silicon carbide power device cell structure according to claim 7, wherein, The third sub-electric field shielding layer (430) is disposed on the same cross section of the gate structure (200) as the first sub-electric field shielding layer (410) and the second sub-electric field shielding layer (420).

10. The silicon carbide power device cell structure according to any one of claims 2-9, wherein, The electric field shielding layer (400) has a protrusion (446) extending toward the bottom surface of the substrate (100); Along a direction perpendicular to the substrate (100), the protrusion (446) is opposite to the gate structure (200).

11. The silicon carbide power device cell structure according to claim 10, wherein, The protrusion (446) includes a main body (441) and an extension (442); Along a direction perpendicular to the substrate (100), the main body (441) is opposite to the gate structure (200), and the main body (441) covers the bottom surface of the gate structure (200); The extension (442) is connected to the side of the main body (441) and extends toward the source structure (300); wherein the extension (442) also covers at least a portion of the side of the gate structure (200) and is connected to the source structure (300).

12. The silicon carbide power device cell structure according to claim 11, wherein, The number of the extensions (442) includes two, and the two extensions (442) are located on opposite sides of the main body (441).

13. The silicon carbide power device cell structure according to claim 12, wherein, In the same main body (441), two extensions (442) are arranged opposite each other, parallel to the plane of the base (100) and along the second direction; or, in the same main body (441), two extensions (442) are staggered relative to each other, parallel to the plane of the base (100) and along the second direction.

14. The silicon carbide power device cell structure according to any one of claims 11-13, wherein, On a plane parallel to the substrate (100), the gate structure (200) is strip-shaped and extends along a first direction; The source structure (300) includes a plurality of source portions (330), which are spaced apart along the first direction, and each source portion (330) surrounds a portion of the side surface of the gate structure (200); An electric field shielding layer (400) covering the side of the gate structure (200) extends along the bottom surface away from the substrate (100) and extends between adjacent source portions (330).

15. The silicon carbide power device cell structure according to claim 14, wherein, The electric field shielding layer (400) located between adjacent source portions (330) is connected to at least one of the two adjacent source portions (330).

16. The silicon carbide power device cell structure according to claim 15, wherein, The electric field shielding layer (400) located between any adjacent source electrode portions (330) has a strip shape in the orthographic projection onto the substrate (100).

17. The silicon carbide power device cell structure according to claim 15, wherein, The electric field shielding layer (400) located between any adjacent source electrode portions (330) has a bent shape in the orthographic projection of the substrate (100).

18. The silicon carbide power device cell structure according to claim 17, wherein, The electric field shielding layer (400) located between any two adjacent source poles (330) includes a plurality of shielding extension segments (444) and shielding connection segments (445) in the orthographic projection shape of the substrate (100). Two adjacent shielding extension segments (444) are connected by the shielding connection segments (445), and any two adjacent shielding extension segments (444) are staggered in the second direction. The second direction and the first direction intersect each other.

19. The silicon carbide power device cell structure according to claim 18, wherein, The electric field shielding layers (400) located on both sides of the gate structure (200) are arranged in a centrally symmetrical manner with respect to the gate structure (200); Alternatively, the electric field shielding layer (400) located on both sides of the gate structure (200) is arranged symmetrically with respect to the gate structure (200).

20. The silicon carbide power device cell structure according to any one of claims 15-19, wherein, The gate structure (200) includes a plurality of gate structures (200), which are spaced apart along a second direction; The electric field shielding layer (400) covers at least a portion of the cross-section of the entire gate structure (200).

21. The silicon carbide power device cell structure according to claim 20, wherein, Each of the gate structures (200) includes a gate body (230) and a gate protrusion (240), the gate body (230) extending along the first direction, and the gate protrusion (240) protruding at least one side of the gate body (230) along the second direction.

22. The silicon carbide power device cell structure according to any one of claims 2-9, wherein, The source structure (300) includes a second conductivity type source active region (310) and a first conductivity type source region (320); Along the thickness direction of the substrate (100), the second conductivity type source active region (310) is disposed on the substrate (100), and the first conductivity type source region (320) is disposed on the second conductivity type source active region (310).

23. The silicon carbide power device cell structure according to any one of claims 2-9, wherein, The silicon carbide power device further includes a source electrode layer (800), which is disposed on the source structure (300) and connected to the source structure (300).

24. The silicon carbide power device cell structure according to claim 23, wherein, The silicon carbide power device further includes a second conductivity type ohmic contact layer (600), and the source electrode layer (800) and the source structure (300) are connected through the second conductivity type ohmic contact layer (600).

25. The silicon carbide power device cell structure according to claim 24, wherein, The second type of conductive ohmic contact layer (600) is disposed within the electric field shielding layer (400); The electric field shielding layer (400) is connected to the source structure (300) through the second conductivity type ohmic contact layer (600) and the source electrode layer (800).

26. The silicon carbide power device cell structure according to any one of claims 2-9, wherein, The substrate (100) includes a substrate (110) and a first conductivity type epitaxial layer (120), the first conductivity type epitaxial layer (120) being disposed on the substrate (110).

27. The silicon carbide power device cell structure according to any one of claims 2-9, wherein, The gate structure (200) includes a gate (210) and a gate dielectric layer (220), the gate dielectric layer (220) covering the bottom and side surfaces of the gate (210).

28. The silicon carbide power device cell structure according to claim 2, wherein, The electric field shielding structure is an electric field shielding layer (400), which at least covers the bottom of the gate structure (200) and is connected to the source structure (300).

29. The silicon carbide power device cell structure according to claim 28, wherein, The electric field shielding layer (400) includes a main body (410) and an extension (420), the main body (410) covering the bottom surface of the gate structure (200); the extension (420) extends toward the source structure (300) and covers at least a portion of the side surface of the gate structure (200). The main body (410) is connected to the source structure (300) via the extension (420).

30. The silicon carbide power device cell structure according to claim 29, wherein, The gate structure (200) includes a first gate structure (230) and at least one second gate structure (240), wherein at least one second gate structure (240) is disposed on one side of the first gate structure (230) and connected to the first gate structure (230).

31. The silicon carbide power device cell structure according to claim 30, wherein, The gate structure (200) is a multi-level trench structure; or, the gate structure (300) is a single-level trench structure.

32. The silicon carbide power device cell structure according to claim 31, wherein, The first gate structure (230) includes at least one first step surface (250); the bottom surface of the second gate structure (240) and the side surface of the first gate structure (230) together form a second step surface (260); At least one of the first step surfaces (250) is located on the side of the second step surface (260) facing the bottom surface of the base (100).

33. The silicon carbide power device cell structure according to claim 32, wherein, Along the thickness direction of the substrate (100), the gate of the first gate structure (230) includes at least a first gate layer (211) and a second gate layer (212) that are stacked and interconnected. The first gate layer (211) is located at the bottom of the second gate layer (212) and covers part of the bottom surface of the second gate layer (212); the bottom surface of the second gate layer (212) and the side surface of the first gate layer (211) together form a first step surface (250).

34. The silicon carbide power device cell structure according to claim 32, wherein, The extension (420) covers part of the first step surface (250), the second step surface (260), and the second gate structure (240); The extension covering a portion of the side of the second gate structure (240) is connected to the source structure (300).

35. The silicon carbide power device cell structure according to claim 34, wherein, The source structure (300) includes a first conductivity type source layer (320) and a second conductivity type source active layer (310); A second conductivity type source active layer (310) is disposed on a substrate (100), and a first conductivity type source layer (320) is disposed on the second conductivity type source active layer (310); The main body (410) is connected to the second conductivity type source active layer (310) via the extension (420).

36. The silicon carbide power device cell structure according to any one of claims 30-35, wherein, The number of the second gate structure (240) is at least two, and the at least two second gate structures (240) are disposed at intervals around the periphery of the first gate structure (230).

37. The silicon carbide power device cell structure according to any one of claims 30-35, wherein, The number of the second gate structure (240) is at least two, and at least two second gate structures (240) are symmetrically arranged on the periphery of the first gate structure (230).

38. The silicon carbide power device cell structure according to claim 37, wherein, The second gate structure (240) includes two, and the two second gate structures (240) are symmetrically disposed on both sides of the first gate structure (230); Alternatively, the second gate structure (240) may include four, with the four second gate structures (240) symmetrically arranged around the first gate structure (230).

39. The silicon carbide power device cell structure according to any one of claims 30-35, wherein, There are multiple gate structures (200), and the multiple gate structures (200) are arranged in an array along the thickness direction intersecting the substrate (100); At least a portion of the adjacent gate structures (200) are spaced apart.

40. The silicon carbide power device cell structure according to claim 39, wherein, The plurality of gate structures (200) are arranged in multiple rows and columns; the row direction and the column direction intersect, and both intersect the thickness direction of the substrate (100); The gate structures (200) located in the same row are spaced apart, and the gate structures (200) located in the same column are interconnected to form a branch structure; Alternatively, the gate structures (200) in the same column are spaced apart, and the gate structures (200) in the same row are interconnected to form a branch structure.

41. The silicon carbide power device cell structure according to claim 40, wherein, The interconnected gate structures are connected through their respective second gate structures.

42. The silicon carbide power device cell structure according to claim 41, wherein, Each adjacent gate structure (200) is spaced apart.

43. The silicon carbide power device cell structure according to any one of claims 30-35, wherein, The substrate (100) includes a substrate (120) and a first conductivity type epitaxial layer (130), the first conductivity type epitaxial layer (130) being disposed on the substrate (120).

44. The silicon carbide power device cell structure according to any one of claims 30-35, wherein, The gate structure (200) includes a gate (210) and a gate dielectric layer (220), the gate dielectric layer (220) covering the bottom and side surfaces of the gate (210).

45. The silicon carbide power device cell structure according to any one of claims 30-35, wherein, The silicon carbide power device cell structure further includes a first electrode layer (700), which is disposed on the source structure (300) and connected to the source structure (300).

46. ​​The silicon carbide power device cell structure according to claim 45, wherein, The silicon carbide power device cell structure further includes a second conductivity type ohmic contact layer (800), and the first electrode layer (700) is connected to the source structure (300) through the second conductivity type ohmic contact layer (800).

47. The silicon carbide power device cell structure according to claim 46, wherein, Along the thickness direction intersecting the substrate (100), the second conductivity type ohmic contact layer (800) is located between spaced second gate structures (240).

48. The silicon carbide power device cell structure according to claim 2, wherein, The gate structure (200) includes at least two first gate structures (210), which are disposed at intervals within the substrate (100); A portion of the source structure (300) located between any two adjacent first gate structures (210) extends toward the bottom surface of the substrate (100) to form a protruding structure (330); a portion of the protruding structure (330) constitutes an electric field shielding structure.

49. The silicon carbide power device cell structure according to claim 48, wherein, Both the source structure (300) and the protruding structure (330) include a first conductivity type source layer (310) and a second conductivity type source active layer (320); The second conductivity type source active layer (320) is disposed on the substrate (100), and the first conductivity type source layer (310) is disposed on the second conductivity type source active layer (320); At least a portion of the second conductivity type source active layer (320) in the protruding structure (330) forms the electric field shielding structure.

50. The silicon carbide power device cell structure according to claim 49, wherein, The source structure (300) surrounds a portion of the side of the first gate structure (210).

51. The silicon carbide power device cell structure according to claim 50, wherein, The source structure (300) surrounds the top of the first gate structure (210).

52. The silicon carbide power device cell structure according to any one of claims 48-51, wherein, The first gate structure (210) has a first extension; the first extension extends in a direction away from the first gate structure (210).

53. The silicon carbide power device cell structure according to any one of claims 48-51, wherein, The gate structure (200) further includes a second gate structure (220); The second gate structure (220) is located between the two first gate structures (210).

54. The silicon carbide power device cell structure according to claim 53, wherein, The second gate structure (220) is a planar gate structure. The second gate structure (220) is located above the protruding structure (330), and the bottom surface of the second gate structure (220) is in contact with the protruding structure (330).

55. The silicon carbide power device cell structure according to claim 54, wherein, The second gate structure (220) is a trench gate structure, and the second gate structure (220) is located within the protruding structure (330).

56. The silicon carbide power device cell structure according to claim 55, wherein, The source structure (300) also surrounds a portion of the side surface of the second gate structure (220).

57. The silicon carbide power device cell structure according to claim 56, wherein, In a first cross-section, the first conductivity type source layer (310) of the protruding structure (330) covers at least a portion of the side surface of the second gate structure (220).

58. The silicon carbide power device cell structure according to claim 57, wherein, On the first cross-section, the first conductivity type source layer (310) of the protruding structure (330) covers at least a portion of the bottom surface of the second gate structure (220).

59. The silicon carbide power device cell structure according to claim 58, wherein, On the first cross section, the second conductivity type source active layer (320) of the protruding structure (330) covers the first conductivity type source layer (310) such that the second conductivity type source active layer (320) of the protruding structure (330) covers the entire bottom surface and the entire side surface of the second gate structure (220).

60. The silicon carbide power device cell structure according to claim 59, wherein, In the second cross-section, the second conductivity type source active layer (320) of the protruding structure (330) covers at least a portion of the bottom surface of the second gate structure (220); The first cross-section and the second cross-section are different cross-sections.

61. The silicon carbide power device cell structure according to any one of claims 55-60, wherein, The second gate structure (220) has a main stem (221) and a second extension (222), the second extension (222) being connected to the side of the main stem (221) and extending toward the first gate structure (210); The main stem (221) has a first direction in its main direction, and the extension of the second extension (222) has a second direction in its extension direction. The first direction and the second direction intersect.

62. The silicon carbide power device cell structure according to claim 61, wherein, The second conductivity type source active layer (320) of the protruding structure (330) does not extend beyond the extension (1222) at its end in the second direction.

63. The silicon carbide power device cell structure according to claim 62, wherein, The second extension (222) includes a plurality of portions; On a plane parallel to the substrate (100), a plurality of second extensions (222) are disposed on one side of the second gate structure (220) and are spaced apart along the first direction.

64. The silicon carbide power device cell structure according to claim 63, wherein, The second gate structure (220) includes a plurality of second gate structures (220) arranged at intervals along the second direction; The second extension (222) of each of the second gate structures (220) is located on the same side of the corresponding second gate structure (220).

65. The silicon carbide power device cell structure according to claim 64, wherein, The second extension (222) of each of the second gate structures (220) is located on the opposite side of the corresponding gate structure (200).

66. The silicon carbide power device cell structure according to claim 62, wherein, The second extension (222) includes a plurality of portions; On a plane parallel to the substrate (100), a plurality of second extensions (222) are disposed on opposite sides of the second gate structure (220) along a second direction; and a plurality of second extensions (222) located on the same side are spaced apart along the first direction.

67. The silicon carbide power device cell structure according to claim 66, wherein, The second extensions (222) located on both sides of the same second gate structure (220) are disposed opposite to each other along the second direction; Alternatively, the second extensions (222) located on both sides of the same second gate structure (220) are offset along the second direction.

68. The silicon carbide power device cell structure according to claim 53, wherein, The silicon carbide power device cell structure further includes a source electrode layer (600), which is disposed on the source structure (300) and connected to the source structure (300).

69. The silicon carbide power device cell structure according to claim 68, wherein, The silicon carbide power device cell structure further includes a second conductivity type source ohmic contact layer (500), and the source electrode layer (600) and the source structure (300) are connected through the second conductivity type source ohmic contact layer (500).

70. The silicon carbide power device cell structure according to claim 69, wherein, Along the thickness direction intersecting the substrate (100), the second conductivity type source ohmic contact layer (500) is located between the first gate structure (210) and the second gate structure (220).

71. The silicon carbide power device cell structure according to any one of claims 48-51, wherein, The substrate (100) includes a substrate (110) and an epitaxial layer (120), the epitaxial layer (120) being disposed on the substrate (110).

72. The silicon carbide power device cell structure according to any one of claims 48-51, wherein, The gate structure (200) includes a gate (211) and a gate dielectric layer (212), the gate dielectric layer (212) covering the bottom and side surfaces of the gate (211).

73. The silicon carbide power device cell structure according to claim 2, wherein, The source structure (300) includes a first source structure (310) and a second source structure (320), wherein the first source structure (310) is connected to the second source structure (320) through a source electrode layer (800); The second source structure (320) covers at least a portion of the bottom of the gate structure (200), and a portion of the structure of the second source structure (320) serves as an electric field shielding structure.

74. The silicon carbide power device cell structure according to claim 73, wherein, Along the thickness direction of the substrate (100), the first source structure (310) includes a first source layer (311) of a first conductivity type and a first source active layer (312) of a second conductivity type; The first source active layer (312) of the second conductivity type is disposed on the substrate (100), and the first source layer (311) of the first conductivity type is disposed on the first source active layer (312) of the second conductivity type; At least one of the first source active layer (312) of the second conductivity type and the first source layer (311) of the first conductivity type is connected to the second source structure (320) through the source electrode layer (800).

75. The silicon carbide power device cell structure according to claim 74, wherein, Along the thickness direction of the substrate, the second source structure (320) includes a second source layer (321) of the first conductivity type and a second source active layer (322) of the second conductivity type; A second source active layer (322) of the second conductivity type is disposed on the substrate (100), and a second source active layer (321) of the first conductivity type is disposed on the second source active layer (322) of the second conductivity type; At least one of the second source layer (321) of the first conductivity type and the second source active layer (322) of the second conductivity type is connected to the first source structure (310) through the source electrode layer (800); The second source active layer (322) of the second conductivity type serves as an electric field shielding structure.

76. The silicon carbide power device cell structure according to claim 75, wherein, The second source layer (321) of the first conductivity type covers the bottom and part of the side of the gate structure (200).

77. The silicon carbide power device cell structure according to claim 76, wherein, The second source active layer (322) of the second conductivity type covers at least the bottom and part of the side of the second source layer (321) of the first conductivity type.

78. The silicon carbide power device cell structure according to claim 77, wherein, The second source active layer (322) of the second conductivity type also covers a portion of the side of the gate structure and is not connected to the first source structure (310).

79. The silicon carbide power device cell structure according to any one of claims 74-78, wherein, The silicon carbide power device cell also includes an ohmic contact layer (600), the conductivity type of which is a second conductivity type; The first source structure (310) and the second source structure (320) are electrically connected to the source electrode layer (800) through the ohmic contact layer (600).

80. The silicon carbide power device cell structure according to claim 79, wherein, The ohmic contact layer (600) includes a first ohmic contact layer (610); The first source active layer (312) of the second conductivity type is connected to the source electrode layer (800) through the first ohmic contact layer (610).

81. The silicon carbide power device cell structure according to claim 80, wherein, The first ohmic contact layer (610) is doped in the first source active layer (312) of the second conductivity type.

82. The silicon carbide power device cell structure according to claim 80, wherein, The first ohmic contact layer (610) is doped in the first source layer (311) of the first conductivity type.

83. The silicon carbide power device cell structure according to any one of claims 79-82, wherein, The ohmic contact layer (600) includes a second ohmic contact layer (620); The second source active layer (322) of the second conductivity type is connected to the source electrode layer (800) through the second ohmic contact layer (620).

84. The silicon carbide power device cell structure according to claim 83, wherein, The first ohmic contact layer (610) in the orthographic projection of the substrate surrounds the outer periphery of the second ohmic contact layer (620) in the orthographic projection of the substrate (100).

85. The silicon carbide power device cell structure according to claim 84, wherein, The gate structure (200) is projected onto the substrate (100) and surrounds the outer periphery of the second ohmic contact layer (620) projected onto the substrate (100).

86. The silicon carbide power device cell structure according to claim 83, wherein, The second ohmic contact layer (620) is doped in the second source active layer (322) of the second conductivity type.

87. The silicon carbide power device cell structure according to claim 83, wherein, The second ohmic contact layer (620) is doped in the second source layer (321) of the first conductivity type.

88. The silicon carbide power device cell structure according to any one of claims 73-78, wherein, The first source structure (310) surrounds the top of the gate structure (200).

89. The silicon carbide power device cell structure according to any one of claims 79-82, wherein, The gate structure (200) is a ring structure on a plane parallel to the substrate (100).

90. The silicon carbide power device cell structure according to claim 89, wherein, On a plane parallel to the substrate (100), the first ohmic contact layer (610) has a ring structure and surrounds the gate structure (200).

91. The silicon carbide power device cell structure according to any one of claims 79-82, wherein, The gate structure (200) is a strip structure on a plane parallel to the substrate (100).

92. The silicon carbide power device cell structure according to claim 91, wherein, Both the first ohmic contact layer (610) and the second ohmic contact layer (620) include multiple ohmic contact portions; The plurality of ohmic contacts are arranged at intervals along the extension direction of the gate structure (200).

93. The silicon carbide power device cell structure according to any one of claims 73-78, wherein, The gate structure (200) includes at least two sub-gate structures (230), and the at least two sub-gate structures (230) are isolated from each other.

94. The silicon carbide power device cell structure according to claim 93, wherein, The source electrode layer (800) includes an extension (810) located in the gate structure (200) and dividing the gate structure (200) into at least two sub-gate structures (230); The extension (810) is electrically insulated from each of the sub-gate structures (230).

95. The silicon carbide power device cell structure according to claim 94, wherein, The number of the sub-gate structures (230) is two; the two sub-gate structures (230) are symmetrically distributed on both sides of the extension (810).

96. The silicon carbide power device cell structure according to claim 95, wherein, The extension (810) extends from the end of the substrate (100) toward the bottom surface into the second source structure (320); Alternatively, the extension (810) extends from the end of the base (100) toward the bottom surface to the top surface of the second source structure (320).

97. The silicon carbide power device cell structure according to claim 96, wherein, The silicon carbide power device cell also includes an ohmic contact layer (600), the conductivity type of which is a second conductivity type; The ohmic contact layer (600) contacts the bottom surface of the extension (810) facing the substrate (100) and protrudes from the extension (810).

98. The silicon carbide power device cell structure according to any one of claims 94-97, wherein, It also includes an insulating layer (500) located between the source electrode layer (800) and the gate structure (200), and between the extension (810) and the sub-gate structure (230).

99. The silicon carbide power device cell structure according to any one of claims 73-78, wherein, The gate structure (200) includes a gate (210) and a gate dielectric layer (220), the gate dielectric layer (220) covering the bottom and side surfaces of the gate (210).

100. The silicon carbide power device cell structure according to any one of claims 73-78, wherein, The substrate (100) includes a substrate (110) and an epitaxial layer (120), the epitaxial layer (120) being disposed on the substrate (110).

101. A method for fabricating a cell structure of a silicon carbide power device, comprising: Provide a base; A source structure is formed, wherein the source structure is disposed on the substrate; An electric field shielding structure and a gate structure are formed within the substrate, the source structure surrounds at least a portion of the sidewalls of the gate structure, and the electric field shielding structure surrounds the bottom of the gate structure and is connected to the source structure.

102. The method for fabricating the cell structure of a silicon carbide power device according to claim 101, wherein, include: The electric field shielding structure is an electric field shielding layer that covers at least a portion of the bottom of the cross-section of the gate structure and is connected to the source structure.

103. The method for fabricating the cell structure of a silicon carbide power device according to claim 102, wherein, The steps for forming the source structure include: A source electrode structure material layer is formed, wherein the source electrode structure material layer is disposed on the substrate; A first mask layer having a plurality of first mask openings is formed on the source structure material layer, the plurality of first mask openings being arranged at intervals along a second direction, and each first mask opening extending along a first direction; wherein the first direction and the second direction intersect each other; The source structure material layer and part of the substrate exposed in the first mask opening are removed to form a gate trench; wherein the remaining source structure material layer constitutes the source structure; Remove the first mask layer.

104. The method for fabricating the cell structure of a silicon carbide power device according to claim 103, wherein, The steps of forming the electric field shielding layer and the gate structure include: A second mask layer is formed, which fills the gate trench and covers the top surface of the source structure; The second mask layer is patterned to form a plurality of second mask openings; the plurality of second mask openings are spaced apart along the first direction, and each second mask opening extends along the second direction; wherein the second mask opening exposes a portion of the gate trench; Using the second mask layer as a mask, an electric field shielding layer is formed at least on the inner wall of the exposed gate trench through an ion implantation process; Remove the second mask layer; A gate structure is formed, wherein the gate structure is disposed within the gate trench.

105. The method for fabricating the cell structure of a silicon carbide power device according to claim 104, wherein, The step of forming the gate trench includes: Through multiple etching processes, multi-level gate trenches are formed in the substrate; wherein, along the direction pointing to the bottom surface of the substrate, the diameter of the gate trenches gradually decreases.

106. The method for fabricating the cell structure of a silicon carbide power device according to claim 105, wherein, The step of providing the substrate includes: Provide substrate; An epitaxial layer of a first conductivity type is formed, and the first conductivity type epitaxial layer is disposed on the substrate.

107. The method for fabricating the cell structure of a silicon carbide power device according to claim 101, wherein, The steps for forming the gate structure also include: The gate structure includes a first gate structure and at least one second gate structure, wherein at least one second gate structure is disposed on one side of the first gate structure and connected to the first gate structure.

108. The method for fabricating the cell structure of a silicon carbide power device according to claim 107, wherein, The steps for forming the gate structure include: Through multiple etching processes, multi-level gate trenches are formed in the substrate; wherein, along the direction pointing to the bottom surface of the substrate, the diameter of the gate trenches gradually decreases; An electric field shielding layer is formed, which at least covers the inner wall of the gate trench closest to the bottom surface of the substrate; A gate structure is formed, wherein the gate structure is disposed within the multi-level gate trench.

109. The method for fabricating the cell structure of a silicon carbide power device according to claim 108, wherein, The step of providing the substrate includes: Provide substrate; An epitaxial layer of a first conductivity type is formed and disposed on the substrate; wherein the substrate and the first conductivity type epitaxial layer constitute the substrate; The steps to form the source structure include: A source structure is formed within the first conductivity type epitaxial layer, wherein the source structure includes a second conductivity type source active layer and a first conductivity type source layer stacked together, and the first conductivity type source layer is disposed on the second conductivity type source active layer.

110. The method for fabricating the cell structure of a silicon carbide power device according to claim 101, wherein, The steps for forming the gate structure also include: The gate structure includes two first gate structures; the source structure at least surrounds a portion of the side surfaces of the two first gate structures, and the portion of the source structure located between the two first gate structures extends toward the bottom surface of the substrate to form a protruding structure; a portion of the protruding structure constitutes an electric field shielding structure. The steps for forming the source structure include: A protruding structure is formed, the protruding structure being disposed within the substrate; A source structure is formed, which surrounds a portion of the outer peripheral surface of the protruding structure and is connected to the protruding structure; wherein, a portion of the protruding structure constitutes the electric field shielding structure.

111. The method for fabricating the cell structure of a silicon carbide power device according to claim 110, wherein, After the step of forming the source structure and before the step of forming the gate structure, the method further includes: A second conductivity type source ohmic contact layer is formed, and the second conductivity type source ohmic contact layer is disposed on the source structure.

112. The method for fabricating the cell structure of a silicon carbide power device according to claim 111, wherein, The steps for forming the gate structure include: At least two spaced-apart first gate structures are formed, each first gate structure passing through the source structure in a direction perpendicular to the substrate, such that the source structure surrounds a portion of the side surface of each first gate structure; A second gate structure is formed, which is located within the protruding structure.

113. The method for fabricating the cell structure of a silicon carbide power device according to claim 101, wherein, The steps of forming the source structure include: forming a first source structure and a second source structure that are spaced apart, wherein the first source structure and the second source structure constitute the source structure; The steps of forming the gate structure include: a first source structure surrounding at least a portion of the side surface of the gate structure; a second source structure at least covering the bottom of the gate structure, wherein a portion of the second source structure serves as an electric field shielding structure; A source electrode layer is formed, wherein the source electrode layer connects the first source structure and the second source structure.

114. The method for fabricating the cell structure of a silicon carbide power device according to claim 113, wherein, The step of providing the substrate includes: Provide substrate; An epitaxial layer of a first conductivity type is formed, and the first conductivity type epitaxial layer is disposed on the substrate.

115. The method for fabricating the cell structure of a silicon carbide power device according to claim 114, wherein, The steps for forming the source structure include: A first source structure material layer is formed, wherein the first source structure material layer is disposed on the epitaxial layer; A portion of the first source structure material layer and a portion of the substrate are removed to form a gate trench; the depth direction of the gate trench is perpendicular to the substrate, and the bottom of the gate trench extends into the epitaxial layer; wherein the remaining first source structure material layer constitutes the first source structure; A second source structure is formed, which at least covers a portion of the bottom of the gate trench.

116. The method for fabricating the cell structure of a silicon carbide power device according to claim 115, wherein, The steps to form the second source structure include: Using an ion doping process, at least the epitaxial layer exposed at the bottom of the gate trench is doped to form a second source active layer of a second conductivity type; The second source active layer of the second conductivity type is further doped using ion doping technology to form a second source layer of the first conductivity type within the second source active layer of the second conductivity type.

117. The method for fabricating the cell structure of a silicon carbide power device according to any one of claims 113-116, wherein, The steps for forming the gate structure also include: A second photoresist layer is formed having a second mask opening, the second mask opening exposing a portion of the gate structure; Using the second photoresist layer as a mask, the gate structure exposed by the opening of the second mask is removed to form an etch hole in the gate structure, the etch hole dividing the gate structure into at least two sub-gate structures.

118. The method for fabricating the cell structure of a silicon carbide power device according to any one of claims 113-116, wherein, After the step of forming the gate structure and before the step of forming the source electrode layer, the method includes: An ohmic contact layer is formed, the ohmic contact layer including a first ohmic contact layer and a second ohmic contact layer; the first ohmic contact layer is disposed on the first source structure, and the second ohmic contact layer is disposed on the second source structure.

119. A semiconductor device, wherein, Including the silicon carbide power device cell structure as described in any one of claims 1-100.

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