Array substrate, display panel and display apparatus

Abstract

Provided is an array substrate, comprising a plurality of pixel regions arranged in an array. The array substrate comprises: a base substrate; a plurality of pixel driving circuits, which are located in the plurality of pixel regions, wherein each pixel driving circuit comprises a driving transistor and a storage capacitor, which storage capacitor comprises a first capacitor electrode, a second capacitor electrode and a third capacitor electrode; an organic insulating layer, which is located on the side of the driving transistor away from the base substrate; and a pixel electrode layer, which is located on the side of the organic insulating layer away from the base substrate, wherein the pixel electrode layer comprises a plurality of pixel electrodes that are spaced apart from each other and are respectively located in the plurality of pixel regions, the organic insulating layer has first via holes located in the pixel regions, the pixel electrodes are electrically connected to the driving transistors by means of the first via holes, and the orthographic projections of the first via holes on the base substrate are spaced apart from the orthographic projections of at least one of the first capacitor electrodes, the second capacitor electrodes and the third capacitor electrodes on the base substrate.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] Electrophoretic display (EPD) is a mainstream electronic paper display technology that does not emit light by itself, relies on natural light reflection to form an image, and maintains a static image by bistability. It has the advantages of energy saving and environmental protection. Since it realizes the display of pictures by reflecting black and white particles, it has a paper-like display effect without glare, and is particularly suitable for reading in strong outdoor light. Compared with rigid electronic paper displays, the main difference between flexible electronic paper displays is that a flexible substrate is used instead of a glass substrate of a rigid electronic paper display, so that more diverse display forms can be realized. However, the flexible substrate is prone to deformation under external force, which causes the film layer attached thereto to crack or even fall off, thereby causing display problems. How to improve the manufacturing yield of flexible electronic paper products is one of the issues that display product researchers are concerned about.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and therefore, the above information can include information that does not constitute the prior art. SUMMARY

[0004] In one aspect, an array substrate is provided, comprising a display area and a peripheral area located at a periphery of the display area, the display area comprising a plurality of pixel areas arranged in an array, the array substrate comprising:

[0005] a substrate substrate;

[0006] a plurality of pixel driving circuits located on the substrate substrate, the plurality of pixel driving circuits being respectively located in the plurality of pixel areas, the pixel driving circuit comprising a driving transistor and a storage capacitor, the storage capacitor comprising a first capacitor electrode, a second capacitor electrode located on a side of the first capacitor electrode away from the substrate substrate, and a third capacitor electrode located on a side of the second capacitor electrode away from the substrate substrate;

[0007] an organic insulating layer located on a side of the driving transistor away from the substrate substrate; and

[0008] a pixel electrode layer located on a side of the organic insulating layer away from the substrate substrate, the pixel electrode layer comprising a plurality of pixel electrodes arranged at intervals, the plurality of pixel electrodes being respectively located in the plurality of pixel areas;

[0009] The organic insulating layer has a first via hole in the pixel region, the first via hole exposing at least a portion of the driving transistor, and the pixel electrode is electrically connected to the driving transistor through the first via hole.

[0010] The first via hole is spaced apart from at least one of the first, second, and third capacitor electrodes.

[0011] According to some exemplary embodiments, a projection of any one of the first, second, and third capacitor electrodes on the substrate is at least partially overlapped with a projection of the pixel electrode on the substrate.

[0012] According to some exemplary embodiments, the first and second capacitor electrodes are located on a side of the organic insulating layer close to the substrate, and the third capacitor electrode is located between the organic insulating layer and the pixel electrode layer.

[0013] According to some exemplary embodiments, the array substrate further comprises a first insulating layer between the first and second capacitor electrodes, and the first and second capacitor electrodes are spaced apart by the first insulating layer.

[0014] The array substrate further comprises a second insulating layer between the second and third capacitor electrodes, and the second and third capacitor electrodes are spaced apart by the second insulating layer.

[0015] According to some exemplary embodiments, the array substrate further comprises a first insulating layer between the first and second capacitor electrodes, and the first and second capacitor electrodes are spaced apart by the first insulating layer.

[0016] The array substrate further comprises a second insulating layer between the second and third capacitor electrodes, and the second and third capacitor electrodes are electrically connected.

[0017] According to some exemplary embodiments, the organic insulating layer has a second via hole in the pixel region, the second via hole exposing at least a portion of the second capacitor electrode, and the portion of the second capacitor electrode exposed by the second via hole is spaced apart from the third capacitor electrode by the second insulating layer.

[0018] According to some exemplary embodiments, an area of a projection of the second via hole on the substrate is greater than an area of a projection of the first via hole on the substrate; and / or,

[0019] A projection of the second via on the substrate is spaced apart from a projection of the first via on the substrate by a predetermined distance.

[0020] According to some exemplary embodiments, a projection of the second capacitor electrode on the substrate is located within a projection of the second via on the substrate.

[0021] According to some exemplary embodiments, the drive transistor includes a source and a drain, the drain and the second capacitor electrode are located on the same layer; and

[0022] a first separation portion is provided between the drain and the second capacitor electrode, the second capacitor electrode and the drain are located on two sides of the first separation portion along a row direction, a projection of the organic insulating layer on the substrate at least partially overlaps with a projection of the first separation portion on the substrate; and / or,

[0023] a second separation portion is provided between the drain and the second capacitor electrode, the second capacitor electrode and the drain are located on two sides of the second separation portion along a column direction, a projection of the organic insulating layer on the substrate at least partially overlaps with a projection of the second separation portion on the substrate.

[0024] According to some exemplary embodiments, the second insulating layer is located on a side of the organic insulating layer close to the substrate.

[0025] According to some exemplary embodiments, the drive transistor includes a source and a drain, the third capacitor electrode is electrically connected with the drain through the first via and the third capacitor electrode is electrically connected with the pixel electrode;

[0026] the first capacitor electrode is electrically connected with the drain; and

[0027] the second capacitor electrode is spaced apart from the drain and is configured to access a common electrode voltage.

[0028] According to some exemplary embodiments, the array substrate further includes a third insulating layer located between the third capacitor electrode and the pixel electrode layer, the third capacitor electrode and the pixel electrode layer are spaced apart by the third insulating layer.

[0029] According to some exemplary embodiments, the third capacitor electrode is configured to access a common electrode voltage.

[0030] According to some exemplary embodiments, the drive transistor includes a source and a drain, the first capacitor electrode and the drain are electrically connected, and the second capacitor electrode and the third capacitor electrode are electrically connected.

[0031] According to some exemplary embodiments, the organic insulating layer has a third via located in the pixel region, the third via exposing a portion of the second capacitor electrode, the third capacitor electrode being electrically connected to the second capacitor electrode through the third via.

[0032] According to some exemplary embodiments, the array substrate further includes a first connection portion and a second connection portion located in the peripheral region. The first connection portion and the second capacitor electrode are located on the same layer and the first connection portion is electrically connected to the second capacitor electrode. The second connection portion and the third capacitor electrode are located on the same layer and the second connection portion is electrically connected to the third capacitor electrode. Furthermore, the first connection portion and the second connection portion are electrically connected.

[0033] According to some exemplary embodiments, multiple second capacitor electrodes located in the same column are sequentially electrically connected to form a single structure and electrically connected to the first connection portion; and / or,

[0034] Multiple third capacitor electrodes located in the same column are sequentially electrically connected to form an integral structure and electrically connected to the second connection part.

[0035] According to some exemplary embodiments, the driving transistor includes a source and a drain, the second capacitor electrode is electrically connected to the drain, and the first capacitor electrode is electrically connected to the third capacitor electrode.

[0036] According to some exemplary embodiments, the second capacitor electrode, the source electrode, and the drain electrode are located on the same layer, and the second capacitor electrode and the drain electrode are connected to form a conductive functional part of an integral structure; and

[0037] The first via exposes at least a portion of the conductive functional part, and the pixel electrode is electrically connected to the conductive functional part through the first via.

[0038] According to some exemplary embodiments, the array substrate includes a third metal layer located between the organic insulating layer and the third insulating layer, the third capacitor electrode is located on the third metal layer, and a plurality of the third capacitor electrodes are connected in a single structure; and

[0039] The third metal layer has an eleventh via located in the pixel region. The orthographic projection of the first via on the substrate and the orthographic projection of the eleventh via on the substrate at least partially overlap. The pixel electrode is directly connected to the driving transistor through the eleventh via and the first via.

[0040] According to some exemplary embodiments, the array substrate includes a bridging electrode located in the pixel region, the bridging electrode and the third capacitor electrode being located on the same layer and spaced apart; and

[0041] The bridging electrode is directly connected to the driving transistor through the first via, and the bridging electrode is electrically connected to the pixel electrode.

[0042] According to some exemplary embodiments, the third insulating layer has a twelfth via located in the pixel region, the orthographic projection of the twelfth via on the substrate at least partially overlapping the orthographic projection of the first via on the substrate, and the pixel electrode is electrically connected to the bridging electrode through the twelfth via.

[0043] According to some exemplary embodiments, the third insulating layer has a thirteenth via located in the pixel region, the orthographic projection of the thirteenth via on the substrate is located within the orthographic projection of the organic insulating layer on the substrate, and the pixel electrode is electrically connected to the bridging electrode through the thirteenth via.

[0044] According to some exemplary embodiments, at least a portion of the third capacitor electrode near the side of the substrate is in contact with the side of the organic insulating layer away from the substrate; or,

[0045] The array substrate further includes a fourth insulating layer, which is located between the third capacitor electrode and the organic insulating layer.

[0046] In another aspect, an array substrate is provided, including a display area and a peripheral area surrounding the display area, wherein the pixel area includes a plurality of pixel areas arranged in an array, and the array substrate includes:

[0047] Substrate;

[0048] A first metal layer is located on the substrate, and the first metal layer includes a first capacitor electrode.

[0049] A first insulating layer is located on the side of the first metal layer away from the substrate, and the first insulating layer has a fourteenth via located in the pixel region, the fourteenth via exposing a portion of the first capacitor electrode;

[0050] The second metal layer is located on the side of the first insulating layer away from the substrate. The second metal layer includes a source electrode, a drain electrode, and a second capacitor electrode located in the pixel region and respectively spaced apart. The drain electrode is electrically connected to the first capacitor electrode through the fourteenth via.

[0051] A second insulating layer is located on the side of the second metal layer away from the substrate, and the second insulating layer has a fifteenth via located in the pixel region, the fifteenth via exposing a portion of the drain electrode;

[0052] An organic insulating layer is located on the side of the second insulating layer away from the substrate.

[0053] A third metal layer is located on the side of the organic insulating layer away from the substrate; and

[0054] A pixel electrode layer is located on the side of the third metal layer away from the substrate. The pixel electrode layer includes a pixel electrode located in the pixel region, and the pixel electrode is electrically connected to the third metal layer.

[0055] The organic insulating layer has a fifth via located in the pixel region. The orthographic projection of the fifth via on the substrate at least partially overlaps with the orthographic projection of the fifteenth via on the substrate, and the orthographic projection of the fifteenth via on the substrate at least partially overlaps with the orthographic projection of the second capacitor electrode on the substrate. The third metal layer is electrically connected to the drain electrode through the fifth and fifteenth vias.

[0056] At least a portion of the third metal layer near the side of the substrate is in contact with the side of the organic insulating layer away from the substrate.

[0057] In another aspect, a display panel is provided, comprising an array substrate as described in any of the preceding claims and an electronic ink layer, the electronic ink layer being located on the side of the pixel electrode layer away from the substrate.

[0058] In another aspect, a display device is provided, including the display panel as described above. Attached Figure Description

[0059] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0060] Figure 1 schematically shows a cross-sectional view of a display panel in the related art.

[0061] Figures 2 and 3 schematically illustrate the principle of crack formation during the manufacturing process of a display panel in the related art.

[0062] Figure 4 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0063] Figure 5 schematically shows a plan view of an array substrate according to some embodiments of the present disclosure.

[0064] Figure 6 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0065] Figure 7 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0066] Figure 8 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0067] Figure 9 schematically shows a planar view of an array substrate located in a pixel region according to some embodiments of the present disclosure.

[0068] Figure 10 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0069] Figure 11 schematically shows a plan view of an array substrate located in a pixel region according to some embodiments of the present disclosure.

[0070] Figure 12 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0071] Figure 13 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0072] Figure 14 schematically shows a plan view of the third and second capacitor electrodes of an array substrate connected in a peripheral region according to some embodiments of the present disclosure.

[0073] Figure 15 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0074] Figure 16 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0075] Figure 17 schematically shows a plan view of an array substrate located in a pixel region according to some embodiments of the present disclosure.

[0076] Figure 18 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0077] Figure 19 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0078] Figure 20 schematically shows a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0079] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0080] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0081] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0082] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements present. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Additionally, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0083] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be named a second element, and similarly, a second element may be named a first element.

[0084] Figure 1 schematically shows a cross-sectional view of a display panel in the related art.

[0085] Referring to FIG1, the display panel includes an array substrate and an electronic ink layer 20' located on the array substrate 10'. The array substrate 10' includes a driving transistor TFT' and a storage capacitor. The storage capacitor includes a first capacitor electrode 210', a second capacitor electrode 220' and a third capacitor electrode 230'. A first storage capacitor Cst1' can be formed between the first capacitor electrode 210' and the second capacitor electrode 220', and a second storage capacitor Cst2' can be formed between the second capacitor electrode 220' and the third capacitor electrode 230'. The array substrate also includes an organic insulating layer ORG' located on the side of the driving transistor TFT' away from the substrate 100' and a pixel electrode layer 400' located on the side of the organic insulating layer ORG' away from the substrate 100'. An organic insulating layer ORG' has a via H. The via H is used to electrically connect the pixel electrode layer 400' to the driving transistor TFT' and to increase the capacitance of the second storage capacitor Cst2' formed between the second capacitor electrode 220' and the third capacitor electrode 230'. The via H has a large area, which will cause the pixel electrode layer 400' to form a recess A0 that is recessed into the substrate 100' at the via H. Because the recess A0 has a large area and a deep depth, there is a risk of film cracking at the location of the recess A0 when other functional film layers are formed on the array substrate later, which may lead to display defects.

[0086] Figures 2 and 3 schematically illustrate the principle of crack formation during the manufacturing process of a display panel in the related art.

[0087] Referring to Figures 1 and 2, when the front-side process is performed on the array substrate 10', that is, other functional film layers, such as electronic ink layer 20', are formed on the side of the pixel electrode layer 400' away from the substrate 100', the process equipment supports the side of the substrate 100' in the array substrate 10'. When there is a foreign object on the table surface of the process equipment supporting the substrate 100', the foreign object will squeeze the recess A0 in the array substrate 10'. After being squeezed, the recess A0 is prone to deformation and stress accumulation, which will cause the film layer at the recess A0 to release stress by cracking at the weak point.

[0088] Referring to Figures 1 and 3, when the back-side process is performed on the array substrate 10', that is, when other functional film layers, such as electromagnetic film layers, are formed on the side of the substrate 100' away from the pixel electrode layer 400', the process equipment applies a downward force to one side of the substrate 100'. When there are foreign objects on the surface of the substrate 100' away from the substrate 10', the foreign objects will squeeze the recess A0 in the array substrate 10'. After being squeezed, the recess A0 is prone to deformation and stress accumulation, which will cause the film layer at the recess A0 to release stress by cracking at the weak point.

[0089] In the process of forming functional film layers on the front or back of the array substrate 10', there is a risk that the film layers in the array substrate 10 may crack, which may result in display defects in the display panel prepared from the array substrate 10.

[0090] The inventors conducted a detailed study and analysis of the shape of the cracks that appeared in the array substrate and found that cracks with regular shapes appeared in the array substrate. These cracks were all located in the vias of the organic insulating layer. Therefore, it was inferred that the generation of the cracks was strongly correlated with the size and depth of the vias of the organic insulating layer.

[0091] Figure 4 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0092] Referring to FIG4, the array substrate 10 includes a substrate 100, a first metal layer M1 located on one side of the substrate 100, a first insulating layer 310 located on the side of the first metal layer M1 away from the substrate 100, an active layer ACT located on the side of the first insulating layer 310 away from the substrate 100, a second metal layer M2 located on the side of the active layer ACT away from the substrate 100, a second insulating layer 320 located on the side of the second metal layer M2 away from the substrate 100, an organic insulating layer ORG located on the side of the second insulating layer 320 away from the substrate 100, a third metal layer M3 located on the side of the organic insulating layer ORG away from the substrate 100, and a pixel electrode layer 400 located on the side of the third metal layer M3 away from the substrate 100.

[0093] Figure 5 schematically shows a plan view of an array substrate according to some embodiments of the present disclosure.

[0094] Referring to Figure 5, the array substrate includes a display area AA and a peripheral area NA located around the display area AA. The array substrate includes multiple data lines L1 spaced apart along the row direction X and extending along the column direction Y, and multiple scan lines L2 spaced apart along the column direction Y and extending along the row direction X. The multiple scan lines L2 and the multiple data lines L1 define multiple pixel areas PA arranged in an array within the display area AA. The multiple pixel areas PA are distributed spaced apart along the row direction X and the column direction Y within the display area AA. Multiple pixel driving circuits are respectively located within the multiple pixel areas PA. The pixel driving circuits include electrically connected driving transistors and storage capacitors.

[0095] Referring to Figures 4 and 5, the first metal layer M1 includes a plurality of gates and a plurality of first capacitor electrodes 210 spaced apart. The gates are located within a plurality of pixel regions PA, and the first capacitor electrodes 210 are located within a plurality of pixel regions PA. The first insulating layer 310 has a fourteenth via V14 located in the pixel region PA, and the fourteenth via V14 exposes a portion of the first capacitor electrodes 210. The orthographic projection of the active layer ACT on the substrate 100 lies within the orthographic projection of the gates on the substrate 100, and the active layer ACT and the gates are spaced apart by the first insulating layer 310.

[0096] The second metal layer M2 includes a plurality of source electrodes S, a plurality of drain electrodes D, and a plurality of second capacitor electrodes 220 spaced apart. The plurality of source electrodes S are located within a plurality of pixel regions PA, the plurality of drain electrodes D are located within a plurality of pixel regions PA, and the plurality of second capacitor electrodes 220 are located within a plurality of pixel regions PA. The source electrodes S and drain electrodes D are respectively connected to the two ends of the active layer ACT, and the drain electrode D is electrically connected to the first capacitor electrode 210 through the fourteenth via V14. The orthographic projection of the second capacitor electrode 220 on the substrate 100 at least partially overlaps with the orthographic projection of the first capacitor electrode 210 on the substrate 100.

[0097] The second insulating layer 320 has a fifteenth via V15 located in the pixel region PA, the fifteenth via V15 exposing a portion of the drain D. The organic insulating layer ORG has a fifth via V05 located in the pixel region PA, the orthographic projection of the fifth via V05 on the substrate 100 at least partially overlapping the orthographic projection of the fifteenth via V15 on the substrate 100, and the orthographic projection of the fifteenth via V15 on the substrate 100 at least partially overlapping the orthographic projection of the drain D on the substrate 100.

[0098] The third metal layer M3 includes a plurality of third capacitor electrodes 230 spaced apart, each located within a plurality of pixel regions PA. The third metal layer M3 is electrically connected to the drain electrode D through a fifth via V05 and a fifteenth via V15. At least a portion of the side of the third metal layer M3 near the substrate 100 is in contact with the side of the organic insulating layer ORG away from the substrate 100. The pixel electrode layer 400 includes a plurality of pixel electrodes 410 spaced apart, each located within a plurality of pixel regions PA. The pixel electrodes 410 are electrically connected to the third capacitor electrodes 230.

[0099] In the array substrate provided in the embodiments of this disclosure, the side of the organic insulating layer ORG away from the substrate 100 includes only the third metal layer M3 and the pixel electrode layer 400, which makes the depth of the sixth recess A6 formed by the pixel electrode layer 400 at the fifth via V05 of the organic insulating layer ORG smaller, which can effectively reduce the risk of cracks in the film layer located at the sixth recess A6 in the array substrate. On the other hand, the inventors discovered through research that the inorganic insulating layer with a higher film-forming temperature has a denser film, resulting in better crack resistance compared to the inorganic insulating layer with a lower film-forming temperature. However, due to the poor high-temperature resistance of the organic insulating layer ORG, the inorganic insulating layer located on the side of the organic insulating layer ORG away from the array substrate can only be formed by a low-temperature film-forming process, resulting in poor crack resistance. In this array substrate, no inorganic insulating layer is provided on the side of the organic insulating layer ORG away from the substrate 100, while the first insulating layer 310 and the second insulating layer 320 on the side of the organic insulating layer ORG close to the substrate 100 are both inorganic insulating layers formed by a high-temperature film-forming process. Therefore, the film layers in this array substrate have better crack resistance.

[0100] It should be noted that the substrate 100 has a first side surface 100a facing the first metal layer M1, and the depth of the recess should be understood as the depth of the recess perpendicular to the first side surface 100a.

[0101] For example, the materials of the first insulating layer 310 and the second insulating layer 320 include inorganic insulating materials, such as silicon oxide and silicon nitride.

[0102] For example, the material of the substrate 100 includes organic polymer materials. The material of the substrate 100 can be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. That is, the substrate 100 can be an organic flexible substrate.

[0103] For example, the material of the substrate 100 may include yellow polyimide, which is a sub-product of polyimide. It refers to polyimide with an imide ring in the main chain and a golden or yellow appearance. Due to its special chemical structure, yellow polyimide has advantages such as good chemical stability, resistance to high / low temperatures, resistance to chemical corrosion, and good mechanical properties.

[0104] According to some exemplary embodiments, referring to Figures 4 and 5, the driving transistor TFT includes a gate, an active layer ACT, a source (S), and a drain (D). The storage capacitor includes a first capacitor electrode 210, a second capacitor electrode 220, and a third capacitor electrode 230. Both the first capacitor electrode 210 and the third capacitor electrode 230 are electrically connected to the drain (D) and are connected to a pixel electrode voltage. The second capacitor electrode 220 is configured to be connected to a common electrode voltage, meaning it is also multiplexed as a common electrode. A first storage capacitor Cst1 is formed between the first capacitor electrode 210 and the second capacitor electrode 220, and a second storage capacitor Cst2 is formed between the second capacitor electrode 220 and the third capacitor electrode 230.

[0105] Figure 6 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0106] Referring to Figures 5 and 6, the organic insulating layer ORG has a first via VO1 and a second via VO2 located in the pixel region PA and spaced apart. The first via VO1 exposes at least a portion of the drain D, and the orthographic projection of the first via VO1 on the substrate 100 is spaced apart from the orthographic projection of the second capacitor electrode 220 on the substrate 100. The orthographic projection of the second via VO2 on the substrate 100 at least partially overlaps with the orthographic projection of the second capacitor electrode 220 on the substrate 1000. The third capacitor electrode 230 is electrically connected to the drain D through the first via VO1 and is also electrically connected to the pixel electrode 410. That is, the first via VO1 serves as a connection via between the pixel electrode 410 and the driving transistor TFT. At the first via VO1, the pixel electrode 410 is electrically connected to the driving transistor TFT through the third capacitor electrode 230. The drain D is electrically connected to the first capacitor electrode 210 through the fourteenth via V14 in the first insulating layer 310. Both the first capacitor electrode 210 and the third capacitor electrode 230 are connected to the pixel electrode voltage. The second capacitor electrode 220 is configured to be connected to the common electrode voltage. A first storage capacitor Cst1 is formed between the first capacitor electrode 210 and the second capacitor electrode 220, and a second storage capacitor Cst2 is formed between the second capacitor electrode 220 and the third capacitor electrode 230. Since a second via VO2 is also provided in the organic insulating layer ORG, only a thin inorganic insulating layer is provided between the portion of the second capacitor electrode 220 exposed by the second via VO2 and the third capacitor electrode 230. This can effectively increase the second storage capacitor Cst2 between the second capacitor electrode 220 and the third capacitor electrode 230, thereby increasing the capacitance value of the storage capacitor in the pixel driving circuit.

[0107] In the array substrate provided in this embodiment, by providing spaced first vias VO1 and second vias VO2 in the organic insulating layer ORG, the first via VO1 enables electrical connection between the pixel electrode 410 and the driving transistor TFT, and the second via VO2 effectively increases the capacitance of the storage capacitor. Furthermore, since the vias in the organic insulating layer ORG used for electrical connection between the pixel electrode 410 and the driving transistor TFT and the vias used to increase the storage capacitor are separated into two independent vias, namely the first via VO1 and the second via VO2, the aperture of a single via in the organic insulating layer ORG can be effectively reduced. This reduces the recessed area of ​​the first recess A1 and the second recess A2 formed in the pixel electrode layer 400 at the first via VO1 and the second via VO2, thereby effectively reducing the risk of film cracking in the array substrate.

[0108] It should be noted that the recessed area should be understood as the area of ​​the orthogonal projection of the recessed portion onto the substrate 100.

[0109] Furthermore, the via mentioned in the embodiments of this disclosure that exposes a part of a structure should be understood as the orthographic projection of the via on the substrate overlapping with the orthographic projection of the structure on the substrate. In actual products, the via is covered by other structures located above it, and the structure located below the via is not in an exposed state.

[0110] According to some exemplary embodiments, referring to FIG6, the first via VO1 is only used to electrically connect the pixel electrode 410 to the driving transistor TFT. Therefore, the first via VO1 can be set to be smaller. The second via VO2 is used to expose at least a portion of the second capacitor electrode 220, so that a larger storage capacitance can be formed between the portion of the second capacitor electrode 220 exposed by the second via VO2 and the third capacitor electrode 230. The larger the area of ​​the portion of the second capacitor electrode 220 exposed by the second via VO2, the more beneficial it is to increase the capacitance value of the second storage capacitance Cst2 between the second capacitor electrode 220 and the third capacitor electrode 230. Therefore, the second via VO2 can be set to be larger. That is to say, the first via VO1 only needs to ensure that the pixel electrode 410 and the driving transistor TFT can be effectively connected. The second via VO2 can be set to be larger according to the capacitance value required. The area of ​​the orthogonal projection of the second via VO2 on the substrate 100 can be larger than the area of ​​the orthogonal projection of the first via VO1 on the substrate 100.

[0111] According to some exemplary embodiments, referring to FIG6, the orthographic projection of the first via VO1 on the substrate 100 and the orthographic projection of the second via VO2 on the substrate 100 are separated by a predetermined distance. This distance should not be set too small. The minimum value of this distance depends on the patterning process precision of the organic insulating layer ORG. For example, the minimum distance can be 3 micrometers to 5 micrometers. In addition, this distance should not be set too large either, as an excessively large distance will reduce the area of ​​the second via VO2, thereby reducing the capacitance value of the storage capacitor. The specific distance is set according to the actual product process requirements.

[0112] According to some exemplary embodiments, referring to FIG6, the array substrate includes a first insulating layer 310 located between a first metal layer M1 and a second metal layer M2, a second insulating layer 320 located between the second metal layer M2 and an organic insulating layer ORG, and a fourth insulating layer 340 located between the organic insulating layer ORG and a third metal layer M3. A first capacitor electrode 210 and a second capacitor electrode 220 are spaced apart by the first insulating layer 310, i.e., the first insulating layer 310 serves as the dielectric between the first capacitor electrode 210 and the second capacitor electrode 220. A second capacitor electrode 220 and a third capacitor electrode 230 are spaced apart by at least one of the second insulating layer 320 and the fourth insulating layer 340, i.e., at least one of the second insulating layer 320 and the fourth insulating layer 340 serves as the dielectric between the second capacitor electrode 220 and the third capacitor electrode 230.

[0113] According to some exemplary embodiments, referring to Figures 5 and 6, the second insulating layer 320 has a sixteenth via V16 located in the pixel region PA. The orthogonal projection of the sixteenth via V16 on the substrate 100 covers the orthogonal projection of the second capacitor electrode 220 on the substrate 100. The fourth insulating layer 340 covers the second capacitor electrode 220. The second capacitor electrode 220 and the third capacitor electrode 230 are spaced apart by the fourth insulating layer 340. The fourth insulating layer 340 serves as the dielectric between the second capacitor electrode 220 and the third capacitor electrode 230.

[0114] According to some exemplary embodiments, referring to Figures 5 and 6, the second insulating layer 320 has a fifteenth via V15 located in the pixel region PA, and the fourth insulating layer 340 has an eighteenth via V18 located in the pixel region PA. The fifteenth via V15 is connected to the first via V01, and the eighteenth via V18 is located within the connected fifteenth via V15 and the first via V01. The third capacitor electrode 230 is electrically connected to the drain electrode D through the eighteenth via V18.

[0115] Figure 7 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0116] According to some exemplary embodiments, referring to Figures 5 and 7, the second insulating layer 320 covers the second capacitor electrode 220, and the fourth insulating layer 340 has a seventeenth via V17 located in the pixel region PA. The orthogonal projection of the seventeenth via V17 on the substrate 100 covers the orthogonal projection of the second capacitor electrode 220 on the substrate 100. The second capacitor electrode 220 and the third capacitor electrode 230 are spaced apart by the second insulating layer 320, and the second insulating layer 320 serves as the dielectric between the second capacitor electrode 220 and the third capacitor electrode 230. With this configuration, only the second insulating layer 320 is retained in the second via V02 of the organic insulating layer ORG as the dielectric between the second capacitor electrode 220 and the third capacitor electrode 230. The second insulating layer 320 is located on the side of the organic insulating layer ORG closer to the substrate 100, that is, the second insulating layer 320 is formed before the organic insulating layer ORG is formed. The second insulating layer 320 can be formed by a high-temperature film deposition process, which gives it better crack resistance.

[0117] According to some exemplary embodiments, referring to FIG7, the orthogonal projection of the second via VO2 on the substrate 100 covers the orthogonal projection of the second capacitor electrode 220 on the substrate 100. The second via VO2 completely exposes the second capacitor electrode 220 so that the second storage capacitance Cst2 between the second capacitor electrode 220 and the third capacitor electrode 230 is as large as possible.

[0118] Figure 8 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 9 schematically shows a plan view of an array substrate located in a pixel region according to some embodiments of the present disclosure, wherein only a portion of the drain, second capacitor electrode, and organic insulating layer is schematically shown in Figure 9.

[0119] According to some exemplary embodiments, referring to Figures 8 and 9, the second capacitor electrode 220 and the drain electrode D are spaced apart. The second metal layer M2 has a first spacing portion G1 that separates the second capacitor electrode 220 and the drain electrode D along the row direction X, that is, the second capacitor electrode 220 and the drain electrode D are respectively located on both sides of the first spacing portion G1 along the row direction X. The second metal layer M2 has a second spacing portion G2 that separates the second capacitor electrode 220 and the drain electrode D along the column direction Y, that is, the second capacitor electrode 220 and the drain electrode D are respectively located on both sides of the second spacing portion G2 along the column direction Y. The orthographic projection of the organic insulating layer ORG on the substrate 100 at least partially overlaps with the orthographic projection of the first spacing portion G1 on the substrate 100, and the orthographic projection of the organic insulating layer ORG on the substrate 100 at least partially overlaps with the orthographic projection of the second spacing portion G2 on the substrate 100. The inventors discovered that the space between the second capacitor electrode 220 and the drain electrode D is more prone to stress accumulation and film cracking than other areas. Therefore, covering the space between the second capacitor electrode 220 and the drain electrode D with an organic insulating layer ORG can effectively reduce the risk of film cracking in this area.

[0120] For example, the orthographic projection of the first via VO1 on the substrate 100 is located within the orthographic projection of the drain electrode D on the substrate 100, and the orthographic projection of the second via VO2 on the substrate 100 is located within the orthographic projection of the second capacitor electrode 220 on the substrate 100. The distance between the edge of the second via VO2 and the edge of the second capacitor electrode 220 should be less than a preset distance, which depends on factors such as the patterning process precision of the organic insulating layer ORG.

[0121] It should be noted that Figure 9 only schematically shows the outline of the organic insulating layer ORG, and does not fill the organic insulating layer ORG with the same pattern shown in Figure 8, so as to more clearly show the structures such as the second capacitor electrode 220 and the drain electrode D.

[0122] Figure 10 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 11 schematically shows a plan view of an array substrate located in a pixel region according to some embodiments of the present disclosure. Figure 10 schematically shows a cross-sectional view taken along line AA' in Figure 11.

[0123] According to some exemplary embodiments, referring to FIG10, the array substrate further includes a third insulating layer 330 located between the third capacitor electrode 230 and the pixel electrode layer 400. The third capacitor electrode 230 and the pixel electrode 410 are spaced apart by the third insulating layer 330. The signals received by the third capacitor electrode 230 and the pixel electrode 410 are different. A third storage capacitor Cst3 can be formed between the third capacitor electrode 230 and the pixel electrode 410. The pixel electrode 410 is also reused as a fourth capacitor electrode of the storage capacitor. In addition, the first capacitor electrode 210 and the second capacitor electrode 220 are spaced apart by the first insulating layer 310. The signals received by the first capacitor electrode 210 and the second capacitor electrode 220 are different. A first storage capacitor Cst1 can be formed between the first capacitor electrode 210 and the second capacitor electrode 220. The storage capacitor is obtained by connecting the first storage capacitor Cst1 and the third storage capacitor Cst3 in parallel.

[0124] According to some exemplary embodiments, referring to FIG10, the first capacitor electrode 210 and the pixel electrode 410 are respectively electrically connected to the drain electrode D, and the first capacitor electrode 210 and the pixel electrode 410 are respectively connected to the pixel electrode voltage. The second capacitor electrode 220 and the third capacitor electrode 230 are electrically connected, and the second capacitor electrode 220 and the third capacitor electrode 230 are respectively connected to the common electrode voltage. The third capacitor electrode 230 is also multiplexed as the common electrode.

[0125] According to some exemplary embodiments, referring to Figures 10 and 11, adjacent third capacitor electrodes 230 along the second direction are electrically connected to each other (Figure 11 schematically shows a third capacitor electrode 230 and the connection structure located on both sides of the third capacitor electrode 230 along the second direction Y). That is, a plurality of third capacitor electrodes 230 arranged in a row are electrically connected in sequence, and at least one end of a row of third capacitor electrodes 230 in the second direction Y can be connected to a common electrode voltage in the peripheral area. Each third capacitor electrode 230 is connected to a common electrode voltage to the second capacitor electrode 220 electrically connected to it.

[0126] According to some exemplary embodiments, referring to Figures 5, 10, and 11, the third metal layer M3 includes a bridging electrode 510 and a third capacitor electrode 230 spaced apart. The bridging electrode 510 is located in the pixel region PA, and its orthographic projection on the substrate 100 at least partially overlaps with the orthographic projection of the first via VO1 on the substrate 100. The second insulating layer 320 has a fifteenth via VO15 located in the pixel region PA, and the third insulating layer 330 has an eighteenth via VO18 located in the pixel region PA. The fifteenth via VO15 and the first via VO1 are connected, and the eighteenth via VO18 is located within the connected fifteenth via VO15 and the first via VO1. The bridging electrode 510 is electrically connected to the drain D through the eighteenth via VO18. The bridging electrode 510 is also electrically connected to the pixel electrode 410 through a via located in the third insulating layer 330, that is, the pixel electrode 410 is electrically connected to the drain D through the bridging electrode 510.

[0127] According to some exemplary embodiments, referring to Figures 5 and 10, the third insulating layer 330 has a twelfth via V12 located in the pixel region PA. The orthographic projection of the twelfth via V12 on the substrate 100 at least partially overlaps with the orthographic projection of the first via V01 on the substrate 100. The pixel electrode 410 is electrically connected to the bridging electrode 510 through the twelfth via V12. For example, the orthographic projection of the twelfth via V12 on the substrate 100 is located at the orthographic projection of the first via V01 on the substrate 100. With this configuration, the recess formed in the pixel electrode 410 at the twelfth via V12 and the recess formed in the pixel electrode 410 at the first via V01 are the same recess. The configuration of the twelfth via V12 does not cause any new recess in the pixel electrode 410, which is beneficial for improving the surface flatness of the array substrate.

[0128] Figure 12 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0129] According to some exemplary embodiments, referring to Figures 5 and 12, the third insulating layer 330 has a thirteenth via V13 located in the pixel region PA. The orthographic projection of the thirteenth via V13 on the substrate 100 lies within the orthographic projection of the organic insulating layer ORG on the substrate 100. The pixel electrode 410 is electrically connected to the bridging electrode 510 through the thirteenth via V13. With this configuration, the depth of the connecting via (i.e., the thirteenth via V13) between the pixel electrode 410 and the bridging electrode 510 is relatively shallow, allowing for better electrical connection between the pixel electrode 410 and the bridging electrode 510 and avoiding poor connection problems between the pixel electrode 410 and the bridging electrode 510.

[0130] According to some exemplary embodiments, referring to Figures 5, 10 and 11, the organic insulating layer ORG has a third via VO3 located in the pixel region PA. The third via VO3 exposes a portion of the second capacitor electrode 220. The third capacitor electrode 230 is electrically connected to the second capacitor electrode 220 through the third via VO3, so that the third capacitor electrode 230 and the second capacitor electrode 220 can both be connected to a common electrode voltage.

[0131] According to some exemplary embodiments, referring to Figures 5 and 10, the second insulating layer 320 has a nineteenth via V19 located in the pixel region PA, and the fourth insulating layer 340 has a twentieth via V20 located in the pixel region PA. The nineteenth via V19 and the third via V03 are connected, and the twentieth via V20 is located in the connected nineteenth via V19 and the third via V03. The third capacitor electrode 230 is electrically connected to the second capacitor electrode 220 through the twentieth via V20.

[0132] According to some exemplary embodiments, referring to Figures 10 and 11, the area of ​​the orthographic projection of the first via VO1 on the substrate 100 and the area of ​​the orthographic projection of the third via VO3 on the substrate 100 are approximately equal.

[0133] According to some exemplary embodiments, referring to Figures 5 and 10, the pixel electrode layer 400 has a first recess A1 located at the first via V01, a third recess A3 located at the third via V03, and a fourth recess A4 located in the area between the bridging electrode 510 and the third capacitor electrode 230 in the display area AA. The recessed areas of the first recess A1, the third recess A3, and the fourth recess A4 are all small, and the recessed depth of the fourth recess A4 is shallow. This results in better surface flatness of the array substrate, which can effectively reduce the risk of film layer cracking in the array substrate.

[0134] According to some exemplary embodiments, referring to Figures 5 and 12, the pixel electrode layer 400 has a first recess A1 located at the first via V01, a third recess A3 located at the third via V03, a fourth recess A4 located in the region between the bridging electrode 510 and the third capacitor electrode 230, and a fifth recess A5 located at the thirteenth via V13 in the third insulating layer 330 in the display area AA. The recessed areas of the first recess A1, the third recess A3, the fourth recess A4, and the fifth recess A5 are all small, and the recessed depths of the fourth recess A4 and the fifth recess A5 are shallow. This results in better surface flatness of the array substrate, which can effectively reduce the risk of film layer cracking in the array substrate.

[0135] Figure 13 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 14 schematically shows a plan view of the third capacitor electrode and the second capacitor electrode of the array substrate according to some embodiments of the present disclosure being connected in the peripheral region.

[0136] According to some exemplary embodiments, referring to Figures 5, 13, and 14, the array substrate further includes a first connection portion 610 and a second connection portion 620 located in the peripheral region NA. The first connection portion 610 and the second capacitor electrode 220 are located on the same layer and are electrically connected. The second connection portion 620 and the third capacitor electrode 230 are located on the same layer and are electrically connected. The third capacitor electrode 230 is electrically connected to the second capacitor electrode 220 through the second connection portion 620 and the first connection portion 610 located in the peripheral region NA. This eliminates the need for vias in the organic insulating layer ORG located in the display region AA to electrically connect the third capacitor electrode 230 and the second capacitor electrode 220. The organic insulating layer ORG only has a first via V01 in the display region AA, thereby further improving the flatness of the array substrate in the display region AA and effectively reducing the risk of film cracking in the display region.

[0137] According to some exemplary embodiments, referring to Figures 5 and 14, in the display area AA, two adjacent second capacitor electrodes 220 along the column direction Y are electrically connected by a second connecting electrode 221. A plurality of second capacitor electrodes 220 located in the same column are sequentially connected into an integral structure and electrically connected to a first connecting portion 610 located in the peripheral area NA. The shape of the first connecting portion 610 can be an annular ring surrounding the display area AA. The two ends of a column of second capacitor electrodes 220 are respectively electrically connected to the first connecting portion 610.

[0138] According to some exemplary embodiments, referring to Figures 5 and 14, in the display area AA, two adjacent third capacitor electrodes 230 along the column direction Y are electrically connected by a third connecting electrode 231. Multiple third capacitor electrodes 230 located in the same column are sequentially connected into an integral structure and electrically connected to a second connecting portion 620 located in the peripheral area NA. The shape of the second connecting portion 620 can be an annular ring surrounding the display area. The two ends of a column of third capacitor electrodes 230 are respectively electrically connected to the second connecting portion 620.

[0139] According to some exemplary embodiments, referring to Figures 5 and 13, the organic insulating layer ORG has a fourth via V04 located in the peripheral region NA, the second insulating layer 320 has a twenty-first via V21 located in the peripheral region NA, and the fourth insulating layer 340 has a twenty-second via V22 located in the peripheral region NA. The twenty-first via V21 and the fourth via V04 are connected, and the twenty-second via V22 is located in the connected twenty-first via V21 and the fourth via V04. The second connecting portion 620 is electrically connected to the first connecting portion 610 through the twenty-second via V22.

[0140] According to some exemplary embodiments, the array substrate may further include a third connection portion located in the peripheral region. The third connection portion is located in the pixel electrode layer and is spaced apart from the pixel electrode. The third connection portion is electrically connected to the first connection portion and the second connection portion respectively. The first connection portion can be electrically connected to the second connection portion through the third connection portion.

[0141] According to some exemplary embodiments, referring to Figures 5 and 13, the array substrate may further include a fourth connection portion 640 located in the peripheral region NA. The first connection portion 610 can be electrically connected to the fourth connection portion 640 through a via located in the first insulating layer 310. The second connection portion 620, the first connection portion 610 and the fourth connection portion 640 are electrically connected in sequence, which can effectively reduce the degree of voltage drop that occurs when the common electrode voltage signal is transmitted in the peripheral region.

[0142] According to some exemplary embodiments, referring to Figures 5 and 13, the third insulating layer 330 may simultaneously provide a twelfth via V12 and a thirteenth via V13 located in the pixel region PA. The pixel electrode 410 is electrically connected to the bridging electrode 510 through the twelfth via V12 and the thirteenth via V13, so that the pixel electrode 410 and the bridging electrode 510 can be better electrically connected.

[0143] According to some exemplary embodiments, referring to Figures 5 and 13, the pixel electrode layer 400 has a first recess A1 located at the first via V01, a fourth recess A4 located in the region between the bridging electrode 510 and the third capacitor electrode 230, and a fifth recess A5 located at the thirteenth via V13 in the third insulating layer 330 in the display area AA. The recessed areas of the first recess A1, the fourth recess A4, and the fifth recess A5 are all small, and the recessed depths of the fourth recess A4 and the fifth recess A5 are shallow. This results in better surface flatness of the array substrate, which can effectively reduce the risk of film layer cracking in the array substrate.

[0144] According to some exemplary embodiments, referring to Figures 10 and 11, the orthographic projection of any one of the first capacitor electrode 210, the second capacitor electrode 220 and the third capacitor electrode 230 on the substrate 100 at least partially overlaps with the orthographic projection of the pixel electrode 410 on the substrate 100.

[0145] For example, the orthographic projection of the first capacitor electrode 210 on the substrate 100 is located within the orthographic projection of the pixel electrode 410 on the substrate 100, the orthographic projection of the second capacitor electrode 220 on the substrate 100 is located within the orthographic projection of the pixel electrode 410 on the substrate 100, and the orthographic projection of the third capacitor electrode 230 on the substrate 100 is located within the orthographic projection of the pixel electrode 410 on the substrate 100.

[0146] It should be noted that this array substrate can serve as the driving backplane for a reflective display panel, such as an electronic paper display panel. Therefore, the capacitor electrodes in the storage capacitor do not need to be positioned to avoid the light-emitting areas in the pixel region. The first capacitor electrode 210, the second capacitor electrode 220, and the third capacitor electrode 230 can be made larger, thereby effectively increasing the capacitance value of the storage capacitor.

[0147] According to some exemplary embodiments, referring to FIG11, the second metal layer M2 includes a scan signal adapter line L3. The scan signal adapter line L3 extends along the column direction Y. The scan signal adapter line L3 may be located between the second capacitor electrode 220 and the data line L1. A scan signal adapter line L3 is electrically connected to a scan line L2 located in the first metal layer through a via located in the first insulating layer (the via is located in the overlapping area of ​​the projection of the scan signal adapter line L3 and the scan line L2). The scan signal adapter line L3 is also electrically connected to the driver chip. The scan signal adapter line L3 is used to input the scan signal to the scan line L2.

[0148] It should be noted that the scan signal adapter line L3 can be omitted depending on the actual process requirements, and the scan signal can be input to each scan line L2 by setting the gate drive circuit.

[0149] Figure 15 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0150] According to some exemplary embodiments, referring to FIG15, a first capacitor electrode 210 and a second capacitor electrode 220 are spaced apart by a first insulating layer 310. The signals received by the first capacitor electrode 210 and the second capacitor electrode 220 are different, and a first storage capacitor Cst1 can be formed between the first capacitor electrode 210 and the second capacitor electrode 220. A second capacitor electrode 220 and a third capacitor electrode 230 are spaced apart by a second insulating layer 320, an organic insulating layer ORG, and a fourth insulating layer 340. The signals received by the second capacitor electrode 220 and the third capacitor electrode 230 are different, and a second storage capacitor Cst2 can be formed between the second capacitor electrode 220 and the third capacitor electrode 230. A third capacitor electrode 230 and a pixel electrode 410 are spaced apart by a third insulating layer 330. The signals received by the third capacitor electrode 230 and the pixel electrode 410 are different, and a third storage capacitor Cst3 can be formed between the third capacitor electrode 230 and the pixel electrode 410. The storage capacitor is obtained by connecting the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 in parallel, which can further increase the capacitance value of the storage capacitor in the array substrate.

[0151] According to some exemplary embodiments, referring to FIG15, the first capacitor electrode 210 and the third capacitor electrode 230 are both connected to a common electrode voltage, and the second capacitor electrode 220 and the pixel electrode 410 are both connected to a pixel electrode voltage.

[0152] According to some exemplary embodiments, referring to FIG15, the second capacitor electrode 220 and the pixel electrode 410 are respectively electrically connected to the drain electrode D, so that both the second capacitor electrode 220 and the pixel electrode 410 are connected to the pixel electrode voltage. The second capacitor electrode 220 and the drain electrode D are both located in the second metal layer M2, and the second capacitor electrode 220 and the drain electrode D are connected to form a conductive functional part 520 with an integral structure. The third metal layer M3 includes a bridging electrode 510, and the pixel electrode 410 is electrically connected to the conductive functional part 520 through the bridging electrode 510.

[0153] For example, the pixel electrode 410 can be electrically connected to the bridging electrode 510 through the twelfth via V12 and the thirteenth via V13 in the third insulating layer 330.

[0154] According to some exemplary embodiments, referring to FIG15, the first capacitor electrode 210 and the third capacitor electrode 230 can be electrically connected through the connection portion located in the peripheral area. The specific connection method can be referred to the connection method of the second capacitor electrode 220 and the third capacitor electrode 230 shown in FIG13 and FIG14.

[0155] According to some exemplary embodiments, referring to Figures 5 and 15, the pixel electrode layer 400 has a first recess A1 located at the first via V01, a fourth recess A4 located in the region between the bridging electrode 510 and the third capacitor electrode 230, and a fifth recess A5 located at the thirteenth via V13 in the third insulating layer 330 in the display area AA. The recessed areas of the first recess A1, the third recess A3, the fourth recess A4, and the fifth recess A5 are all small, and the recessed depths of the fourth recess A4 and the fifth recess A5 are shallow. This results in better surface flatness of the array substrate, which can effectively reduce the risk of film layer cracking in the array substrate.

[0156] Figure 16 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure. Figure 17 schematically shows a plan view of an array substrate located in a pixel region according to some embodiments of the present disclosure. Figure 16 schematically shows a cross-sectional view taken along line BB' in Figure 17.

[0157] According to some exemplary embodiments, referring to Figures 5, 16 and 17, the first capacitor electrode 210 and the third capacitor electrode 230 can be electrically connected through a connection portion located in the peripheral region. The third capacitor electrode 230 is located in the third metal layer M3. The third capacitor electrodes 230 adjacent along the column direction Y and the third capacitor electrodes 230 adjacent along the row direction X are connected into a single structure. That is, multiple third capacitor electrodes 230 located in the display area are connected into a single structure. The third metal layer M3 has an eleventh via V11 located in the pixel region PA. The orthogonal projection of the eleventh via V11 on the substrate 100 covers the orthogonal projection of the first via V01 on the substrate 100. The fourth insulating layer 340 has a twenty-third via V23 located in the pixel region PA, and the third insulating layer 330 has a twenty-fourth via V24. The orthogonal projection of the eleventh via V11 on the substrate 100 covers the orthogonal projections of the twenty-third via V23 and the twenty-fourth via V24 on the substrate 100. The pixel electrode 410 can be electrically connected to the conductive functional part 520 through the twenty-third via V23 and the twenty-fourth via V24.

[0158] Referring to Figure 17, the third metal layer M3 has only an eleventh via V11 in the display area. Except for the area where the eleventh via V11 is provided, the third metal layer M3 is a continuous film layer on the entire surface of the display area. This configuration is beneficial to increasing the overlap area of ​​the third capacitor electrode 230 and the pixel electrode 410, as well as the overlap area of ​​the third capacitor electrode 230 and the second capacitor electrode 220, thereby further increasing the capacitance value of the storage capacitor.

[0159] In the array substrate provided in this embodiment, the twenty-third via V23 in the fourth insulating layer 340 and the twenty-fourth via V24 in the third insulating layer 330 can be formed using a single mask through a single patterning process, thereby simplifying the fabrication process of the array substrate and reducing its manufacturing cost. Furthermore, since the third metal layer M3 no longer has a bridging electrode 510 spaced apart from the third capacitor electrode 230 in the display area, the pixel electrode layer 400 no longer forms a recess located in the area between the bridging electrode and the third capacitor electrode. The pixel electrode layer 400 in this array substrate only has a first recess A1 located at the first via V01 in the display area, which helps to further improve the surface flatness of the array substrate and reduce the risk of film layer cracking in the array substrate.

[0160] It should be noted that since the fourth insulating layer 340 and the third insulating layer 330 are formed through a single patterning process, the vias in the fourth insulating layer 340 and the third insulating layer 330 are formed simultaneously. According to some actual process requirements, the third metal layer M3 can be used to form an etching barrier structure so that some vias in the third insulating layer 330 will not extend further into the fourth insulating layer 340.

[0161] According to some exemplary embodiments, referring to FIG17, a plurality of first capacitor electrodes 210 located in the same row are electrically connected in sequence. Two adjacent first capacitor electrodes 210 along the row direction X are connected into an integral structure through a first connecting electrode 211. The two ends of a row of first capacitor electrodes 210 are electrically connected to the portion of the third metal layer M3 located in the peripheral area, thereby realizing the electrical connection between the third capacitor electrode 230 and the first capacitor electrode 210.

[0162] According to some exemplary embodiments, referring to Figures 16 and 17, since the drain D and the second capacitor electrode 220 are connected as a single structure, the location of the first via V01 used to realize the electrical connection between the pixel electrode 410 and the drain D can be adjusted according to some design requirements. For example, the first via V01 can be located approximately in the central region of the pixel.

[0163] Figure 18 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0164] According to some exemplary embodiments, the structure of the third metal layer M3 illustrated in Figures 16 and 17 can also be applied to the array substrate illustrated in Figures 10, 12, and 13. For example, referring to Figures 5 and 18, the third metal layer M3 has an eleventh via V11 located in the pixel region PA. The pixel electrode 410 is directly connected to the drain D through the eleventh via V11 and the first via V01. Meanwhile, the drain D is electrically connected to the first capacitor electrode 210 through the fourteenth via V14 in the first insulating layer 310. Both the first capacitor electrode 210 and the pixel electrode 410 are connected to the pixel electrode voltage. The second capacitor electrode 220 is electrically connected to the third capacitor electrode 230 through the first connection portion 610 and the second connection portion 620 located in the peripheral region NA. Both the second capacitor electrode 220 and the third capacitor electrode 230 are connected to the common electrode voltage.

[0165] In the array substrate provided in the embodiments of this disclosure, the pixel electrode layer 400 has only a first recess A1 located at the first via V01 in the display area, which is beneficial to further improve the surface flatness of the array substrate and reduce the risk of film layer cracking in the array substrate.

[0166] Figure 19 schematically shows a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0167] Referring to FIG19, at least a portion of the side of the third capacitor electrode 230 near the substrate 100 is in contact with the side of the organic insulating layer ORG away from the substrate 100. No inorganic insulating layer or other film layer structures are provided between the third metal layer M3 and the organic insulating layer ORG, which can further reduce the depth of the first recess A1 formed at the first via V01 of the pixel electrode layer 400, which is beneficial to further improve the surface flatness of the array substrate and reduce the risk of cracking of the film layer in the array substrate.

[0168] It should be noted that in the array substrates shown in Figures 10, 12, 13, 15 and 18, the fourth insulating layer 340 located between the third metal layer M3 and the organic insulating layer ORG can be omitted according to process requirements. This is beneficial to further improve the surface flatness of the array substrate and reduce the risk of film cracking in the array substrate.

[0169] Figure 20 schematically shows a cross-sectional view of a display panel according to some embodiments of the present disclosure.

[0170] Referring to Figure 20, the display panel includes an array substrate 10 and an electronic ink layer 20. The array substrate 10 is the array substrate described above, and the electronic ink layer 20 is located on the side of the pixel electrode layer 400 away from the substrate 100. The electronic ink layer 20 includes charged ink particles, and the distribution of the charged ink particles in the display area is controlled by the electric field formed by the pixel electrodes and the common electrode to achieve the display of a black / white image. Alternatively, color display can be achieved using charged particles of different colors or by using color filters.

[0171] According to some exemplary embodiments, referring to FIG20, the display panel further includes a protective layer 30 located on the side of the electronic ink layer 20 away from the array substrate 10, a front light module 40 located on the side of the protective layer 30 away from the array substrate 10, and a touch panel 50 located on the side of the front light module 40 away from the array substrate 10.

[0172] For example, the material of the protective layer 30 may include an organic polymer material, such as polyethylene terephthalate (PET), and the protective layer 30 covers the surface of the electronic ink layer 20 away from the substrate 100 to encapsulate the electronic ink layer 20.

[0173] For example, the front light module 40 is turned on as a supplementary light source in dim or no light source environments to improve readability in dim or no light source environments. The front light module 40 does not need to be turned on in well-lit environments, and can achieve display simply by reflecting ambient light.

[0174] According to some exemplary embodiments, referring to FIG20, the display panel also includes an electromagnetic film layer 60 located on the side of the array substrate 10 away from the electronic ink layer 20. The electromagnetic film layer 60 can interact with the electromagnetic pen to capture changes in the position and pressure of the pen tip, thereby realizing high-precision handwriting and drawing functions.

[0175] At least some embodiments of this disclosure also provide a display device comprising the display substrate described above. The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0176] It should be understood that the display device according to some exemplary embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be referred to in the above description of the display substrate and will not be repeated here.

[0177] As used herein, the terms “substantially,” “approximately,” “about,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “about” as used herein includes the stated value and indicates that the particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0178] While some embodiments based on the general inventive concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, wherein, The array includes a display area and a peripheral area surrounding the display area. The display area includes a plurality of pixel areas arranged in an array. The array substrate includes: Substrate; Multiple pixel driving circuits are located on the substrate, and the multiple pixel driving circuits are respectively located in the multiple pixel regions. Each pixel driving circuit includes a driving transistor and a storage capacitor. The storage capacitor includes a first capacitor electrode, a second capacitor electrode located on the side of the first capacitor electrode away from the substrate, and a third capacitor electrode located on the side of the second capacitor electrode away from the substrate. An organic insulating layer is located on the side of the driving transistor away from the substrate; and A pixel electrode layer is located on the side of the organic insulating layer away from the substrate. The pixel electrode layer includes a plurality of spaced-apart pixel electrodes, each located within a plurality of pixel regions. The organic insulating layer has a first via located in the pixel region, the first via exposing at least a portion of the driving transistor, and the pixel electrode is electrically connected to the driving transistor through the first via; and The orthographic projection of the first via on the substrate is spaced apart from the orthographic projection of at least one of the first capacitor electrode, the second capacitor electrode, and the third capacitor electrode on the substrate.

2. The array substrate according to claim 1, wherein, The orthographic projection of any one of the first capacitor electrode, the second capacitor electrode, and the third capacitor electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate.

3. The array substrate according to claim 1 or 2, wherein, The first capacitor electrode and the second capacitor electrode are located on the side of the organic insulating layer close to the substrate, and the third capacitor electrode is located between the organic insulating layer and the pixel electrode layer.

4. The array substrate according to claim 3, wherein, The array substrate further includes a first insulating layer located between the first capacitor electrode and the second capacitor electrode, wherein the first capacitor electrode and the second capacitor electrode are spaced apart by the first insulating layer; and The array substrate further includes a second insulating layer located between the second capacitor electrode and the third capacitor electrode, with the second capacitor electrode and the third capacitor electrode spaced apart by the second insulating layer.

5. The array substrate according to claim 3, wherein, The array substrate further includes a first insulating layer located between the first capacitor electrode and the second capacitor electrode, wherein the first capacitor electrode and the second capacitor electrode are spaced apart by the first insulating layer; and The array substrate further includes a second insulating layer located between the second capacitor electrode and the third capacitor electrode, and the second capacitor electrode and the third capacitor electrode are electrically connected.

6. The array substrate according to claim 4 or 5, wherein, The organic insulating layer has a second via located in the pixel region, the second via exposing at least a portion of the second capacitor electrode, and the portion of the second capacitor electrode exposed by the second via being spaced apart from the third capacitor electrode through the second insulating layer.

7. The array substrate according to claim 6, wherein, The area of ​​the second via projected onto the substrate is larger than the area of ​​the first via projected onto the substrate. And / or, The orthographic projection of the second via on the substrate is spaced apart from the orthographic projection of the first via on the substrate by a predetermined distance.

8. The array substrate according to claim 6 or 7, wherein, The orthographic projection of the second capacitor electrode on the substrate is located within the orthographic projection of the second via on the substrate.

9. The array substrate according to claim 6 or 7, wherein, The driving transistor includes a source and a drain, the drain and the second capacitor electrode being located on the same layer; and A first gap is provided between the drain and the second capacitor electrode. The second capacitor electrode and the drain are located on both sides of the first gap along the row direction. The orthographic projection of the organic insulating layer on the substrate overlaps at least partially with the orthographic projection of the first gap on the substrate. And / or, A second gap is provided between the drain electrode and the second capacitor electrode. The second capacitor electrode and the drain electrode are located on opposite sides of the second gap along the column direction. The orthographic projection of the organic insulating layer on the substrate overlaps at least partially with the orthographic projection of the second gap on the substrate.

10. The array substrate according to any one of claims 6-8, wherein, The second insulating layer is located on the side of the organic insulating layer that is close to the substrate.

11. The array substrate according to any one of claims 6-10, wherein, The driving transistor includes a source and a drain, and the third capacitor electrode is electrically connected to the drain through the first via and is also electrically connected to the pixel electrode. The first capacitor electrode is electrically connected to the drain electrode; and The second capacitor electrode is spaced apart from the drain electrode and is configured to be connected to a common electrode voltage.

12. The array substrate according to claim 4 or 5, wherein, The array substrate further includes a third insulating layer located between the third capacitor electrode and the pixel electrode layer, wherein the third capacitor electrode and the pixel electrode layer are spaced apart by the third insulating layer.

13. The array substrate according to claim 12, wherein, The third capacitor electrode is configured to be connected to the common electrode voltage.

14. The array substrate according to claim 13, wherein, The driving transistor includes a source and a drain, the first capacitor electrode and the drain are electrically connected, and the second capacitor electrode and the third capacitor electrode are electrically connected.

15. The array substrate according to claim 14, wherein, The organic insulating layer has a third via located in the pixel region, the third via exposing a portion of the second capacitor electrode, and the third capacitor electrode being electrically connected to the second capacitor electrode through the third via.

16. The array substrate according to claim 14, wherein, The array substrate further includes a first connection portion and a second connection portion located in the peripheral region. The first connection portion and the second capacitor electrode are located on the same layer and are electrically connected. The second connection portion and the third capacitor electrode are located on the same layer and are electrically connected. Furthermore, the first connection portion and the second connection portion are electrically connected.

17. The array substrate according to claim 16, wherein, Multiple second capacitor electrodes located in the same column are sequentially electrically connected to form a single structure and electrically connected to the first connecting portion; and / or, Multiple third capacitor electrodes located in the same column are sequentially electrically connected to form an integral structure and electrically connected to the second connection part.

18. The array substrate according to claim 13, wherein, The driving transistor includes a source and a drain, the second capacitor electrode is electrically connected to the drain, and the first capacitor electrode is electrically connected to the third capacitor electrode.

19. The array substrate according to claim 18, wherein, The second capacitor electrode and the drain electrode are located on the same layer, and the second capacitor electrode and the drain electrode are connected to form a conductive functional part with an integral structure; as well as The first via exposes at least a portion of the conductive functional part, and the pixel electrode is electrically connected to the conductive functional part through the first via.

20. The array substrate according to any one of claims 12-19, wherein, The array substrate includes a third metal layer located between the organic insulating layer and the third insulating layer, the third capacitor electrode is located on the third metal layer, and a plurality of the third capacitor electrodes are connected into an integral structure. as well as The third metal layer has an eleventh via located in the pixel region. The orthographic projection of the first via on the substrate and the orthographic projection of the eleventh via on the substrate at least partially overlap. The pixel electrode is directly connected to the driving transistor through the eleventh via and the first via.

21. The array substrate according to any one of claims 12-19, wherein, The array substrate includes a bridging electrode located in the pixel region, the bridging electrode and the third capacitor electrode being located on the same layer and spaced apart; and The bridging electrode is directly connected to the driving transistor through the first via, and the bridging electrode is electrically connected to the pixel electrode.

22. The array substrate according to claim 21, wherein, The third insulating layer has a twelfth via located in the pixel region. The orthographic projection of the twelfth via on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate. The pixel electrode is electrically connected to the bridging electrode through the twelfth via.

23. The array substrate according to claim 21, wherein, The third insulating layer has a thirteenth via located in the pixel region. The orthographic projection of the thirteenth via on the substrate is located within the orthographic projection of the organic insulating layer on the substrate. The pixel electrode is electrically connected to the bridging electrode through the thirteenth via.

24. The array substrate according to any one of claims 3-23, wherein, At least a portion of the third capacitor electrode near the side of the substrate is in contact with the side of the organic insulating layer away from the substrate; or, The array substrate further includes a fourth insulating layer, which is located between the third capacitor electrode and the organic insulating layer.

25. An array substrate, wherein, The array includes a display area and a peripheral area surrounding the display area. The pixel area includes multiple pixel areas arranged in an array. The array substrate includes: Substrate; A first metal layer is located on the substrate, and the first metal layer includes a first capacitor electrode located in the pixel region; A first insulating layer is located on the side of the first metal layer away from the substrate, and the first insulating layer has a fourteenth via located in the pixel region, the fourteenth via exposing a portion of the first capacitor electrode; The second metal layer is located on the side of the first insulating layer away from the substrate. The second metal layer includes a source electrode, a drain electrode, and a second capacitor electrode located in the pixel region and respectively spaced apart. The drain electrode is electrically connected to the first capacitor electrode through the fourteenth via. A second insulating layer is located on the side of the second metal layer away from the substrate, and the second insulating layer has a fifteenth via located in the pixel region, the fifteenth via exposing a portion of the drain electrode; An organic insulating layer is located on the side of the second insulating layer away from the substrate. A third metal layer is located on the side of the organic insulating layer away from the substrate; and A pixel electrode layer is located on the side of the third metal layer away from the substrate. The pixel electrode layer includes a pixel electrode located in the pixel region, and the pixel electrode is electrically connected to the third metal layer. The organic insulating layer has a fifth via located in the pixel region. The orthographic projection of the fifth via on the substrate at least partially overlaps with the orthographic projection of the fifteenth via on the substrate, and the orthographic projection of the fifteenth via on the substrate at least partially overlaps with the orthographic projection of the second capacitor electrode on the substrate. The third metal layer is electrically connected to the drain electrode through the fifth and fifteenth vias. At least a portion of the third metal layer near the side of the substrate is in contact with the side of the organic insulating layer away from the substrate.

26. A display panel, wherein, The display panel includes an array substrate and an electronic ink layer according to any one of claims 1-25, wherein the electronic ink layer is located on the side of the pixel electrode layer away from the substrate.

27. A display device, wherein, The display device includes the display panel according to claim 26.

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