Display substrate and display apparatus

Abstract

Provided is a display substrate, comprising: a base substrate (100); a driving circuit layer (200) located on the base substrate (100), the driving circuit layer (200) comprising an active layer (ACT); and a first electrode layer (310) located on the side of the driving circuit layer (200) away from the base substrate (100). The display substrate comprises a plurality of scanning lines (L1) and a plurality of data lines (L2), the plurality of scanning lines (L1) extend along a first direction (X) and are arranged along a second direction (Y), the plurality of data lines (L2) extend along the second direction (Y) and are arranged along the first direction (X), and the first direction (X) intersects the second direction (Y); at least one of each scanning line (L1) and each data line (L2) comprises transparent conductive segments (Lx); and the active layer (ACT) comprises a transparent semiconductor material, the first electrode layer (310) comprises a transparent conductive material, and the transparent conductive segments (Lx) are located in at least one of the active layer (ACT) and the first electrode layer (310).

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] Transparent display technology is an emerging display technology that allows users to see both the image on the screen and the objects behind it. This technology has broad application potential in many fields, including commercial displays, museum exhibitions, architecture and interior design, automotive interiors, advertising and display events, and stage and performing arts. Improving the transparency of transparent display panels is one of the key research topics for display product developers.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, comprising:

[0005] Substrate;

[0006] A driving circuit layer, located on the substrate, the driving circuit layer includes an active layer; and

[0007] The first electrode layer is located on the side of the driving circuit layer away from the substrate.

[0008] The display substrate includes multiple scan lines and multiple data lines. The multiple scan lines extend along a first direction and are arranged along a second direction. The multiple data lines extend along the second direction and are arranged along the second direction. The first direction and the second direction intersect.

[0009] At least one of the scan line and the data line includes a transparent conductive segment; and

[0010] The active layer includes a transparent semiconductor material, the first electrode layer includes a transparent conductive material, and the transparent conductive segment is located in at least one of the active layer and the first electrode layer.

[0011] According to some exemplary embodiments, the scan line includes a first transparent conductive segment located in the active layer; and / or,

[0012] The data line includes a second transparent conductive segment located in the first electrode layer.

[0013] According to some exemplary embodiments, the scan line includes a plurality of first transparent conductive segments and a plurality of first metal segments, wherein the plurality of first transparent conductive segments and the plurality of first metal segments are alternately arranged along the first direction and electrically connected sequentially; and / or,

[0014] The data line includes multiple second transparent conductive segments and multiple second metal segments, which are arranged alternately along the second direction and electrically connected in sequence.

[0015] According to some exemplary embodiments, the first metal segment is located in the driving circuit layer, and / or the second metal segment is located in the driving circuit layer.

[0016] According to some exemplary embodiments, the driving circuit layer includes a light-shielding layer on the substrate, a buffer layer on the side of the light-shielding layer away from the substrate, an active layer on the side of the buffer layer away from the substrate, a gate insulating layer on the side of the active layer away from the substrate, a gate metal layer on the side of the gate insulating layer away from the substrate, an interlayer dielectric layer on the side of the gate metal layer away from the substrate, and a source / drain metal layer on the side of the interlayer dielectric layer away from the substrate.

[0017] The first metal segment is located in the light-shielding layer, and / or the second metal segment is located in the source / drain metal layer.

[0018] According to some exemplary embodiments, the scan line further includes a connection segment located in the source / drain metal layer, and adjacent first transparent conductive segments and first metal segments are electrically connected through the connection segment.

[0019] According to some exemplary embodiments, the display substrate further includes a passivation layer located on the side of the source / drain metal layer away from the substrate and a planarization layer located between the passivation layer and the first electrode layer;

[0020] The passivation layer has a first via, the first via exposing a portion of the second metal segment, and both ends of the second transparent conductive segment respectively overlap with two adjacent second metal segments through at least two of the first vias; and

[0021] The planarization layer has a first opening, and the orthographic projection of the second transparent conductive segment on the substrate is located within the orthographic projection of the first opening on the substrate.

[0022] According to some exemplary embodiments, the orthographic projection of the first metal segment on the substrate partially overlaps with the orthographic projection of the second transparent conductive segment on the substrate; and / or,

[0023] The orthographic projection of the first transparent conductive segment on the substrate is spaced apart from the orthographic projection of the second metal segment on the substrate.

[0024] According to some exemplary embodiments, the orthographic projection of the first metal segment on the substrate is spaced apart from the orthographic projection of the second metal segment on the substrate; and / or,

[0025] The orthographic projection of the first transparent conductive segment on the substrate is spaced apart from the orthographic projection of the second transparent conductive segment on the substrate.

[0026] According to some exemplary embodiments, the length of the first metal segment along the first direction is greater than or equal to the length of the first transparent conductive segment along the first direction; and / or,

[0027] The length of the second metal segment along the second direction is greater than or equal to the length of the second transparent conductive segment along the second direction.

[0028] According to some exemplary embodiments, the display substrate includes a display area, which includes a transparent area and a sub-pixel area;

[0029] In at least one first transparent conductive segment adjacent to the transparent region, the first transparent conductive segment includes a first main segment and a first auxiliary segment, the first main segment and the first auxiliary segment are located in the same layer, the first main segment is located between two adjacent first metal segments, the first auxiliary segment is connected to the first main segment along the second direction and is located in the transparent region; and / or,

[0030] In at least one second transparent conductive segment adjacent to the transparent region, the second transparent conductive segment includes a second main segment and a second auxiliary segment, the second main segment and the second auxiliary segment are located in the same layer, the second main segment is located between two adjacent second metal segments, the second auxiliary segment is connected to the second main segment along the first direction and the second auxiliary segment is located in the transparent region.

[0031] According to some exemplary embodiments, the length of the first transparent conductive segment along the first direction is less than the dimension of the sub-pixel region along the first direction, and the length of the first metal segment along the first direction is less than the dimension of the sub-pixel region along the first direction; and / or

[0032] The length of the second transparent conductive segment along the second direction is less than the size of the sub-pixel region along the second direction, and the length of the second metal segment along the second direction is less than the size of the sub-pixel region along the second direction.

[0033] According to some exemplary embodiments, the active layer includes an active portion, the active portion includes a channel portion and conductor portions located on both sides of the channel portion, and the sheet resistance of the first transparent conductive segment is less than or equal to the sheet resistance of the conductor portion.

[0034] According to some exemplary embodiments, the first electrode layer includes a first electrode, and the sheet resistance of the second transparent conductive segment is less than or equal to the sheet resistance of the first electrode.

[0035] In another aspect, a display device is provided, the display device comprising the display substrate as described above. Attached Figure Description

[0036] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0037] Figure 1 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0038] Figure 2 schematically shows an enlarged view of the display sub-area in Figure 1.

[0039] Figure 3 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0040] Figure 4 schematically shows a plan view of scan lines and data lines of a display substrate according to some embodiments of the present disclosure.

[0041] Figure 5 schematically shows a plan view of scan lines and data lines of a display substrate according to some embodiments of the present disclosure.

[0042] Figures 6A-6C schematically illustrate the fabrication process of a display substrate provided according to some embodiments of the present disclosure.

[0043] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0044] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0045] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0046] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements present. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Additionally, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0047] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be named a second element, and similarly, a second element may be named a first element.

[0048] Figure 1 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure. Figure 2 schematically shows an enlarged view of the display sub-region in Figure 1.

[0049] Referring to Figures 1 and 2, the display substrate includes a display area AA, which includes multiple display sub-areas AA1 arranged along a first direction X and a second direction Y. Each display sub-area AA1 includes a pixel area PXA and a transparent area TA. The pixel area PXA is the area used to emit light for display. The transparent area TA does not contain any opaque structures, and the portion of the display substrate located in the transparent area TA has high light transmittance, thereby achieving a transparent display effect.

[0050] Referring again to Figure 2, the pixel region PXA includes multiple sub-pixel regions PXAx, such as a first sub-pixel region PXA1, a second sub-pixel region PXA2, a third sub-pixel region PXA3, and a fourth sub-pixel region PXA4. The first and second sub-pixel regions PXA1 and PXA2 are arranged along a first direction X, as are the third and fourth sub-pixel regions PXA3 and PXA4. The third sub-pixel region PXA3 is located on one side of the first sub-pixel region PXA1 along a second direction Y, and the fourth sub-pixel region PXA4 is located on one side of the second sub-pixel region PXA2 along a second direction Y. A transparent region TA can be located on one side of the pixel region PXA along the first direction X. The pixel region PXA may include two transparent regions TA: one transparent region TA is located on the side of the first sub-pixel region PXA1 away from the second sub-pixel region PXA2, and the other transparent region TA is located on the side of the third sub-pixel region PXA3 away from the fourth sub-pixel region PXA4. In other words, a pixel region PXA can include four sub-pixel regions PXA and two transparent regions TA.

[0051] For example, the first sub-pixel region PXA1 is the region that emits red light, the second sub-pixel region PXA2 is the region that emits green light, the third sub-pixel region PXA3 is the region that emits blue light, and the fourth sub-pixel region PXA4 is the region that emits white light.

[0052] It should be noted that Figure 2 only schematically shows one planar structure of the display sub-area AA1. According to the actual display requirements, the shape and arrangement of the pixel area PXA and the transparent area TA in the display sub-area AA1, as well as the shape and arrangement of the sub-pixels in the pixel area PXA, can be adjusted. This disclosure does not limit this aspect.

[0053] Figure 3 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure, wherein Figure 3 schematically shows a cross-sectional view of the display substrate taken along line AA' in Figure 2.

[0054] Referring to FIG3, the display substrate includes a substrate 100, a driving circuit layer 200 located on the substrate 100, and a light-emitting device layer 300 located on the side of the driving circuit layer 200 away from the substrate 100. The driving circuit layer 200 includes a plurality of pixel driving circuits, and the light-emitting device layer 300 includes a plurality of light-emitting devices. The plurality of light-emitting devices are electrically connected to the plurality of pixel driving circuits, and the plurality of light-emitting devices and the plurality of pixel driving circuits are respectively located in a plurality of sub-pixel regions.

[0055] The driving circuit layer 200 may include a light-shielding layer LS located on the substrate 100, a buffer layer BUF located on the side of the light-shielding layer LS away from the substrate 100, an active layer ACT located on the side of the buffer layer BUF away from the substrate 100, a gate insulating layer GI located on the side of the active layer ACT away from the substrate 100, a gate metal layer Gate located on the side of the gate insulating layer GI away from the substrate 100, an interlayer dielectric layer ILD located on the side of the gate metal layer Gate away from the substrate 100, and a source / drain metal layer SD located on the side of the interlayer dielectric layer ILD away from the substrate 100. The light-shielding layer LS includes a light-shielding portion 210, and the active layer ACT includes an active portion 220. The active portion 220 includes a channel portion 221 and a conductive portion 222 connected to both sides of the channel portion 221. The orthographic projection of the channel portion 221 on the substrate 100 is located within the orthographic projection of the light-shielding portion 210 on the substrate 100. The gate metal layer includes a gate 230, the orthographic projection of the gate 230 on the substrate 100 substantially coincides with the orthographic projection of the channel portion 221 on the substrate 100. The source and drain metal layers SD include a source 241 and a drain 242 spaced apart, the source 241 and the drain 242 respectively connecting to the two conductive portions 222 of the active portion 220 through vias located in the interlayer dielectric layer ILD.

[0056] The light-emitting device layer 300 includes a first electrode layer 310 located in the driving circuit layer 200 away from the substrate 100, a pixel defining layer PDL located on the side of the first electrode layer 310 away from the substrate 100, a light-emitting layer 320 located on the side of the pixel defining layer PDL away from the substrate 100, and a second electrode layer 330 located on the side of the light-emitting layer 320 away from the substrate 100. The pixel defining layer PDL has a plurality of second openings KK2, and the light-emitting layer 320 contacts the first electrode layer 310 through the plurality of second openings KK2. A passivation layer PVX and a planarization layer PLN located between the first electrode layer 310 and the source / drain metal layer SD may also be disposed between the first electrode layer 310 and the source / drain metal layer SD. The first electrode layer 310 includes a plurality of first electrodes 311, and the first electrodes 311 can be electrically connected to the driving circuit layer 200 through vias located in the planarization layer PLN and the passivation layer PVX.

[0057] Figure 4 schematically illustrates a plan view of scan lines and data lines of a display substrate according to some embodiments of the present disclosure, wherein Figure 4 schematically illustrates a plan view of data lines and scan lines located around a transparent area.

[0058] Referring to Figures 3 and 4, the display substrate includes multiple scan lines L1 and multiple data lines L2. Scan lines L1 are used to input scan signals to the pixel driving circuit, and data lines L2 are used to input data signals to the pixel driving circuit. The multiple scan lines L1 extend along a first direction X and are arranged along a second direction Y, while the multiple data lines L2 extend along the second direction Y and are arranged along the first direction X. The first direction X and the second direction Y intersect. At least one of the scan lines L1 and data lines L2 includes a transparent conductive segment Lx. The active layer ACT includes a transparent semiconductor material, and the first electrode layer 310 includes a transparent conductive material. The transparent conductive segment Lx is located in at least one of the active layer ACT and the first electrode layer 310.

[0059] In the display substrate provided in this embodiment, at least a portion of the data line L2 or scan line L1 is made transparent, which can effectively improve the transparency of the display substrate and thus improve the transparent display effect. At the same time, the transparent conductive segment Lx is located in at least one of the active layer ACT and the first electrode layer 310. That is to say, the transparent conductive segment Lx is formed at the same time as the active layer ACT and the first electrode layer 310 are formed, without the need for additional display substrate manufacturing processes.

[0060] It should be noted that the filling pattern of some structures in Figure 4 is different from the filling pattern of the same structure in Figure 3. This difference is only to make the structure of scan line L1 and data line L2 more clearly shown in Figure 4. The structures marked by the same reference numerals in Figure 4 and Figure 3 are the same structures.

[0061] According to some exemplary embodiments, referring to FIG3, the material of the active layer ACT may include indium gallium zinc oxide, and the material of the first electrode layer 310 may include indium tin oxide.

[0062] It should be noted that the boundaries between the sub-pixel region PXA and the transparent region TA are defined by multiple scan lines L1 and multiple data lines L2 arranged in an interlaced manner. For example, referring to Figure 4, the transparent region TA can be defined by two data lines L2 and two scan lines L1.

[0063] According to some exemplary embodiments, referring to Figures 3 and 4, the scan line L1 includes a first transparent conductive segment L11 located in the active layer ACT.

[0064] According to some exemplary embodiments, referring to Figures 3 and 4, the data line L2 includes a second transparent conductive segment L21, which is located in the first electrode layer 310. The second transparent conductive segment L21 for transmitting data signals and the first transparent conductive segment L11 for transmitting scan signals are located in different layers, which can effectively avoid the problem of mutual interference between data signals and scan signals.

[0065] According to some exemplary embodiments, referring to FIG4, the scan line L1 includes multiple first transparent conductive segments L11 and multiple first metal segments L12. The multiple first transparent conductive segments L11 and multiple first metal segments L12 are alternately arranged along the first direction X and electrically connected in sequence. That is, the scan line L1 is formed by alternating connection of light-transmitting first transparent conductive segments L11 and first metal segments L12 with low resistance. While improving the transparent display effect, it can ensure that the scan line L1 has a low trace resistance.

[0066] According to some exemplary embodiments, referring to FIG4, the data line L2 includes multiple second transparent conductive segments L21 and multiple second metal segments L22. The multiple second transparent conductive segments L21 and multiple second metal segments L22 are alternately arranged along the second direction Y and electrically connected in sequence. That is, the data line L2 is formed by alternating connection of light-transmitting second transparent conductive segments L21 and second metal segments L21 with low resistance. While improving the transparent display effect, it can ensure that the data line L2 has a low trace resistance.

[0067] According to some exemplary embodiments, referring to FIG3, the first metal segment L12 and the second metal segment L22 may both be located in the driving circuit layer 200.

[0068] According to some exemplary embodiments, referring to FIG3, the first metal segment L12 and the second metal segment L22 are located on different layers, which can effectively avoid the problem of mutual interference between data signals and scanning signals.

[0069] According to some exemplary embodiments, referring to FIG3, the film layer with metal material in the driving circuit layer 200 includes a light-shielding layer LS, a gate metal layer Gate, and a source / drain metal layer SD. Therefore, the first metal segment L12 can be located in any one of the light-shielding layer LS, the gate metal layer Gate, and the source / drain metal layer SD, and the second metal segment L22 can be located in any one of the remaining two layers.

[0070] For example, the first metal segment L12 is located in the light-shielding layer LS, and the second metal segment L22 is located in the gate metal layer. As another example, the first metal segment L12 is located in the gate metal layer, and the second metal segment L22 is located in the source / drain metal layer SD. Yet another example, the first metal segment L12 is located in the light-shielding layer LS, and the second metal segment L22 is located in the source / drain metal layer SD.

[0071] The inventors discovered that when the first metal segment L12 is located in the light-shielding layer LS and the second metal segment L22 is located in the source / drain metal layer SD (i.e., the situation shown in Figure 3), there are at least two insulating layers, a buffer layer BUF and an interlayer dielectric layer ILD, between the first metal segment L12 and the second metal segment L22, which can more effectively avoid the problem of mutual interference between data signals and scan signals.

[0072] According to some exemplary embodiments, referring to Figures 3 and 4, the scan line L1 further includes a connection segment L13 located in the source / drain metal layer SD. Adjacent first transparent conductive segments L11 and first metal segments L12 are electrically connected through the connection segment L13. The interlayer dielectric layer (ILD) has a second via VO2, and the interlayer dielectric layer (ILD) and buffer layer (BUF) have a third via VO3. The second via VO2 exposes a portion of the first transparent conductive segment L11, and the third via VO3 exposes a portion of the first metal segment L12. The two ends of the connection segment L13 are electrically connected to the first transparent conductive segment L11 and the first metal segment L12 respectively through the second via VO2 and the third via VO3, thereby achieving electrical connection between the first transparent conductive segment L11 and the first metal segment L12. With this connection method, both the second via VO2 and the third via VO3 are formed during the patterning process of the interlayer dielectric layer (ILD), while the buffer layer (BUF) does not require a mask for patterning, which simplifies the fabrication process of the display substrate.

[0073] According to some exemplary embodiments, referring to FIG3, the gate 230 is located in the gate metal layer Gate, and the scan line L1 is located in the light-shielding layer LS and the active layer ACT. The gate 230 and the scan line L1 are not directly connected. The scan line L1 and the gate 230 can be electrically connected through a connection structure located in the source-drain metal layer SD. For example, one end of the connection structure is electrically connected to the gate 230 through a via located in the interlayer dielectric layer ILD, and the other end is electrically connected to the first transparent conductive segment L11 through a via located in the interlayer dielectric layer ILD. As another example, one end of the connection structure is electrically connected to the gate 230 through a via located in the interlayer dielectric layer ILD, and the other end is electrically connected to the first metal segment L12 through a via located in the interlayer dielectric layer ILD and the buffer layer BUF.

[0074] According to some exemplary embodiments, referring to FIG3, the passivation layer PVX has a first via VO1, which exposes a portion of the second metal segment L22. The two ends of the second transparent conductive segment L21 are respectively connected to two adjacent second metal segments L22 through at least two first vias VO1. The planarization layer PLN has a first opening KK1, and the orthographic projection of the second transparent conductive segment L21 on the substrate 100 lies within the orthographic projection of the first opening KK1 onto the substrate 100. By setting a large first opening KK1 in the planarization layer PLN, the second transparent conductive segment L21 can be completely placed within the first opening KK1. The first via V01 connecting the second transparent conductive segment L21 and the second metal segment L22 is located only in the passivation layer PVX. The depth of the first via V01 is relatively shallow, which allows the second transparent conductive segment L21 and the second metal segment L22 to be better connected. This improves the connection reliability between the second transparent conductive segment L21 and the second metal segment L22 and reduces the contact resistance between the second transparent conductive segment L21 and the second metal segment L22.

[0075] According to some exemplary embodiments, referring to FIG4, the orthographic projection of the first metal segment L12 on the substrate 100 overlaps with the orthographic projection of the second transparent conductive segment L21 on the substrate 100. Since the scan line L1 extending along the first direction X and the data line L2 extending along the second direction Y will inevitably overlap, there is a risk of signal interference at the overlap. By overlapping the first metal segment L12 in the scan line L1 and the second transparent conductive segment L21 in the data line L2, at least three insulating layers—a buffer layer BUF, an interlayer dielectric layer ILD, and a passivation layer PVX—are provided between the first metal segment L12 and the second transparent conductive segment L21. The total thickness of the insulating layer between the first metal segment L12 and the second transparent conductive segment L21 is relatively thick, thereby more effectively avoiding the problem of mutual interference between the data signal and the scan signal.

[0076] According to some exemplary embodiments, referring to FIG4, the orthographic projection of the first transparent conductive segment L11 on the substrate 100 and the orthographic projection of the second metal segment L22 on the substrate 100 are spaced apart. Based on the overlap of the orthographic projection of the first metal segment L12 on the substrate 100 and the orthographic projection of the second transparent conductive segment L21 on the substrate 100, the first transparent conductive segment L11 and the second metal segment L22 are set to be projected separately, thereby further reducing the mutual interference between data signals and scanning signals.

[0077] According to some exemplary embodiments, referring to FIG4, the orthographic projection of the first metal segment L12 on the substrate 100 and the orthographic projection of the second metal segment L22 on the substrate 100 are spaced apart. Based on the overlap of the orthographic projection of the first metal segment L12 on the substrate 100 and the orthographic projection of the second transparent conductive segment L21 on the substrate 100, the first metal segment L12 and the second metal segment L22 are set to be projected separately, thereby further reducing the mutual interference between data signals and scanning signals.

[0078] According to some exemplary embodiments, referring to FIG4, the orthographic projection of the first transparent conductive segment L11 on the substrate 100 and the orthographic projection of the second transparent conductive segment L21 on the substrate 100 are spaced apart. Based on the overlap of the orthographic projection of the first metal segment L12 on the substrate 100 and the orthographic projection of the second transparent conductive segment L21 on the substrate 100, the first transparent conductive segment L11 and the second transparent conductive segment L21 are set to be projected separately, thereby further reducing the mutual interference between data signals and scanning signals.

[0079] According to some exemplary embodiments, referring to FIG4, the length of the first metal segment L12 along the first direction X is greater than or equal to the length of the first transparent conductive segment L11 along the first direction X. That is, in the scan line L1, more of the portion is composed of the first metal segment L12, thereby ensuring that the scan line L1 has a lower trace resistance. For example, the ratio of the length of the first metal segment L12 along the first direction X to the length of the first transparent conductive segment L11 along the first direction X is greater than or equal to 5.

[0080] According to some exemplary embodiments, the length of the second metal segment L22 along the second direction Y is greater than or equal to the length of the second transparent conductive segment L21 along the second direction Y. That is, in the data line L2, a larger portion is composed of the second metal segment L22, thereby ensuring that the data line L2 has a lower trace resistance. For example, the ratio of the length of the second metal segment L22 along the second direction Y to the length of the second transparent conductive segment L21 along the second direction Y is greater than or equal to 5.

[0081] According to some exemplary embodiments, referring to FIG4, in the scan line L1, the width of the first metal segment L12 along the second direction Y is substantially equal to the width of the first transparent conductive segment L11 along the second direction Y. The scan line L1 can be set as a uniform width trace with substantially the same width everywhere.

[0082] According to some exemplary embodiments, referring to FIG4, in scan line L1, the width of connecting segment L13 along the second direction Y is substantially equal to the width of first metal segment L12 along the second direction Y.

[0083] According to some exemplary embodiments, referring to FIG4, in the data line L2, the width of the second metal segment L22 along the first direction X is substantially equal to the width of the second transparent conductive segment L21 along the first direction X, and the data line L2 can be set as a uniform width trace with substantially the same width everywhere.

[0084] Figure 5 schematically shows a plan view of scan lines and data lines of a display substrate according to some embodiments of the present disclosure.

[0085] According to some exemplary embodiments, referring to Figures 2 and 5, at least a portion of the first transparent conductive segment L11 in the scan line L1 is disposed adjacent to the transparent region TA. In at least one first transparent conductive segment L11 adjacent to the transparent region TA, the first transparent conductive segment L11 includes a first main segment L111 and a first auxiliary segment L112. Both the first main segment L111 and the first auxiliary segment L112 are located in the active layer ACT. The first main segment L111 is located between two adjacent first metal segments L12. The first auxiliary segment L112 is connected to the first main segment L111 along the second direction Y to form an integral structure, and the first auxiliary segment L112 is located in the transparent region TA. With this setting, the width of the scan line L1 is increased at the position adjacent to the transparent area TA, which can reduce the trace resistance of the scan line L1 to a certain extent. At the same time, the first auxiliary segment L112 is located in the active layer ACT. Setting the first auxiliary segment L112 in the transparent area TA will not affect the transparency of the display substrate. In addition, since the first auxiliary segment L112 is located outside the pixel area PXA, it will not occupy the arrangement space of related structures within the pixel area PXA.

[0086] It should be noted that the first main body segment L111 and the first auxiliary segment L112 are connected as a single structure. The portion of the first metal segment L12 with the same width is considered the first main body segment L111, and the portion protruding in the second direction Y relative to the adjacent first metal segment L12 is considered the first auxiliary segment L112. When the scan line L1 includes the first auxiliary segment L112, the boundary of the transparent region TA should be understood as being defined by the portion of the scan line L1 excluding the first auxiliary segment L112 (i.e., including the first main body segment L111, the first metal segment L12, and the connecting segment L13) and the data line L2.

[0087] According to some exemplary embodiments, referring to FIG5, in at least one first transparent conductive segment L11, the dimension of the first main segment L111 along the first direction X is equal to the dimension of the first auxiliary segment L112 along the first direction X. Optionally, the dimension of the first auxiliary segment L112 along the first direction X may be larger than the dimension of the first main segment L111 along the first direction X.

[0088] According to some exemplary embodiments, referring to Figures 2 and 5, at least a portion of the second transparent conductive segment L21 in the data line L2 can be disposed adjacent to the transparent region TA. In at least one second transparent conductive segment L21 adjacent to the transparent region TA, the second transparent conductive segment L21 includes a second main segment L211 and a second auxiliary segment L212. Both the second main segment L211 and the second auxiliary segment L212 are located in the first electrode layer 310. The second main segment L211 is located between two adjacent second metal segments L22. The second auxiliary segment L212 is connected to the second main segment L211 along the first direction X to form an integral structure, and the second auxiliary segment L212 is located in the transparent region TA. With this setting, the width of the data line L2 is increased at the position adjacent to the transparent area TA, which can reduce the trace resistance of the data line L2 to a certain extent. At the same time, the second auxiliary segment L212 is located in the first electrode layer 310. Setting the second auxiliary segment L212 in the transparent area TA will not affect the transparency of the display substrate. In addition, since the second auxiliary segment L212 is located outside the pixel area PXA, it will not occupy the arrangement space of related structures within the pixel area PXA.

[0089] It should be noted that the second main segment L211 and the second auxiliary segment L212 are connected as a single structure. The portion of the second main segment L211 that is the same width as the adjacent second metal segment L22 is considered the second main segment L211, and the portion that protrudes in the first direction X relative to the adjacent second metal segment L22 is considered the second auxiliary segment L212. When the scan line L1 includes the second auxiliary segment L212, the boundary of the transparent region TA should be understood as being defined by the portion of the data line L2 excluding the second auxiliary segment L212 (i.e., including the second main segment L211 and the first metal segment L12) and the scan line L1.

[0090] According to some exemplary embodiments, referring to FIG5, the orthographic projection of the first auxiliary segment L112 on the substrate and the orthographic projection of the second auxiliary segment L212 on the substrate are spaced apart, thereby effectively avoiding the problem of mutual interference between the scanning signal transmitted in the first auxiliary segment L112 and the data signal transmitted in the second auxiliary segment L212.

[0091] According to some exemplary embodiments, referring to FIG5, in at least one second transparent conductive segment L21, the dimension of the second main segment L211 along the second direction Y is equal to the dimension of the second auxiliary segment L212 along the second direction Y. Optionally, the dimension of the second auxiliary segment L212 along the second direction Y may be greater than the dimension of the second main segment L211 along the second direction Y.

[0092] According to some exemplary embodiments, referring to Figures 2 and 4, the length of the first transparent conductive segment L11 along the first direction X is less than the size of the sub-pixel region PXAx along the first direction X, and the length of the first metal segment L12 along the first direction X is less than the size of the sub-pixel region PXAx along the first direction X. This results in alternating first transparent conductive segments L11 and first metal segments L12 around a sub-pixel region PXAx, avoiding the problem of poor display uniformity caused by some sub-pixel regions PXAx having only transparent first transparent conductive segments L11 around them, while other sub-pixel regions PXAx have only opaque first metal segments L12 around them.

[0093] According to some exemplary embodiments, referring to Figures 2 and 4, the length of the second transparent conductive segment L21 along the second direction Y is less than or equal to the size of the sub-pixel region PXAx along the second direction Y, and the length of the second metal segment L22 along the second direction Y is less than or equal to the size of the sub-pixel region PXAx along the second direction Y. This ensures that alternating second transparent conductive segments L21 and second metal segments L22 exist simultaneously around a sub-pixel region PXAx, avoiding the problem of poor display uniformity caused by some sub-pixel regions PXAx having only transparent second transparent conductive segments L21 around their periphery, while other sub-pixel regions PXAx have only opaque second metal segments L22 around their periphery.

[0094] According to some exemplary embodiments, referring to FIG3, the active layer ACT includes an active portion 220, which includes a channel portion 221 and conductive portions 222 located on both sides of the channel portion 221. The sheet resistance of the first transparent conductive segment L11 is less than or equal to the sheet resistance of the conductive portion 222. That is, during the formation of the active layer ACT, the sheet resistance of the first transparent conductive segment L11 can be reduced by increasing the conductive time of the first transparent conductive segment L11, thereby further reducing the resistance of the scan line L1. In addition, the conductive time of the conductive portion 222 remains unchanged, avoiding the problem of device performance deviation of the transistor.

[0095] According to some exemplary embodiments, referring to FIG3, the first electrode layer 310 includes a first electrode 311, and the sheet resistance of the second transparent conductive segment L21 is less than or equal to the sheet resistance of the first electrode 311. That is, during the formation of the first electrode layer 310, the second transparent conductive segment L21 can be additionally conductiveized, thereby reducing the sheet resistance of the second transparent conductive segment L21. In addition, the first electrode 311 does not need to be conductiveized, thus avoiding affecting the performance of the light-emitting device.

[0096] Figures 6A-6C schematically illustrate the fabrication process of a display substrate provided according to some embodiments of the present disclosure.

[0097] At least some embodiments of this disclosure also provide a method for preparing a display substrate, which will be described below with reference to Figures 6A-6C.

[0098] Referring to FIG6A, a driving circuit layer 200 is formed on a substrate 100. The formation of the driving circuit layer 200 may include forming a light-shielding layer LS on the substrate 100, forming a buffer layer BUF on the side of the light-shielding layer LS away from the substrate 100, forming an active layer ACT on the side of the buffer layer BUF away from the substrate 100, forming a gate insulating layer GI on the side of the active layer ACT away from the substrate 100, forming a gate metal layer Gate on the side of the gate insulating layer GI away from the substrate 100, forming an interlayer dielectric layer ILD on the side of the gate metal layer Gate away from the substrate 100, and forming a source / drain metal layer SD on the side of the interlayer dielectric layer ILD away from the substrate 100.

[0099] The formation of the light-shielding layer LS includes forming a light-shielding portion 210 and a first metal segment L12 that are spaced apart. The material of the light-shielding layer LS may include copper, and the thickness of the light-shielding layer LS may be greater than or equal to 5500 angstroms.

[0100] Forming an active layer ACT may include forming an active portion 220 and a first transparent conductive segment L11 spaced apart. The active portion 220 includes a channel portion 221 and a conductive portion 222 connected to both sides of the channel portion 221. During the formation of the active layer ACT, it is necessary to perform conductive treatment on the conductive portion 222 and the first transparent conductive segment L11 while shielding the channel portion 221. For example, a dry etching process can be used to reduce the oxygen content in the conductive portion 222 and the first transparent conductive segment L11 by plasma bombardment to increase their conductivity. At the same time, the sheet resistance of the first transparent conductive segment L11 can be further reduced by extending the conductive time of the first transparent conductive segment L11.

[0101] Forming a gate metal layer includes forming a gate 230, the orthographic projection of the gate 230 on the substrate 100 substantially coincides with the orthographic projection of the channel portion 221 on the substrate 100.

[0102] The source-drain metal layer SD includes forming a source electrode 241, a drain electrode 242, a second metal segment L22, and a connecting segment L13 spaced apart. The source electrode 241 and the drain electrode 242 are respectively connected to the two conductive segments 222 of the active part 220 through vias located in the interlayer dielectric layer ILD. The two ends of the connecting segment L13 are electrically connected to the first transparent conductive segment L11 and the first metal segment L12 through the second via V02 and the third via V03, respectively. The multiple first transparent conductive segments L11, the multiple first metal segments L12, and the multiple connecting segments L13 connected in sequence constitute a scan line L1 for transmitting scan signals.

[0103] For example, the material of the source / drain metal layer SD can include copper, and the thickness of the source / drain metal layer SD can be greater than or equal to 5500 angstroms.

[0104] Referring to FIG6B, a passivation layer PVX is formed on the side of the driving circuit layer 200 away from the substrate 100, a planarization layer PLN is formed on the side of the passivation layer PVX away from the substrate 100, and a first electrode layer 310 is formed on the side of the planarization layer PLN away from the substrate 100. The first electrode layer 310 includes a first electrode 311 and a second transparent conductive segment L21 disposed at intervals. The first electrode 311 is electrically connected to the drain 242 through vias located in the planarization layer PLN and the passivation layer PVX. The second transparent conductive segment L21 is located in the first opening KK1 of the planarization layer PLN. The two ends of the second transparent conductive segment L21 are respectively connected to two adjacent second metal segments L22 through at least two first vias V01 in the passivation layer PVX. The plurality of second transparent conductive segments L21 and the plurality of second metal segments L22 connected in sequence constitute a data line L2 for transmitting data signals.

[0105] For example, during the formation of the first electrode layer 310, while the first electrode 311 is still shielded, the second transparent conductive segment L21 is subjected to a conductor-enhancing process, thereby further improving the conductivity of the second transparent conductive segment L21. Exemplarily, the second transparent conductive segment L21 can be further conductor-enhanced by bombarding it with plasma using a dry etching process. Furthermore, since the first electrode 311 is shielded during the conductor-enhancing process of the second transparent conductive segment L21, the first electrode 311 does not undergo additional conductor-enhancing treatment, thus ensuring the relevant performance of the light-emitting device.

[0106] Referring to FIG6C, a pixel defining layer PDL is formed on the side of the first metal layer away from the substrate 100, a light-emitting layer 320 is formed on the side of the pixel defining layer PDL away from the substrate 100, and a second electrode layer 330 is formed on the side of the light-emitting layer 320 away from the substrate 100. The pixel defining layer PDL has a second opening KK2, and the light-emitting layer 320 contacts the first electrode 311 through the second opening KK2.

[0107] At least some embodiments of this disclosure also provide a display device comprising the display substrate described above. The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, window with integrated display functionality, billboard, and building curtain wall, etc.

[0108] It should be understood that the display device according to some exemplary embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be referred to in the above description of the display substrate and will not be repeated here.

[0109] As used herein, the terms “substantially,” “approximately,” “about,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “about” as used herein includes the stated value and indicates that the particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0110] While some embodiments based on the general inventive concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate includes: Substrate; A driving circuit layer, located on the substrate, the driving circuit layer includes an active layer; and The first electrode layer is located on the side of the driving circuit layer away from the substrate. The display substrate includes multiple scan lines and multiple data lines. The multiple scan lines extend along a first direction and are arranged along a second direction. The multiple data lines extend along the second direction and are arranged along the second direction. The first direction and the second direction intersect. At least one of the scan line and the data line includes a transparent conductive segment; and The active layer includes a transparent semiconductor material, the first electrode layer includes a transparent conductive material, and the transparent conductive segment is located in at least one of the active layer and the first electrode layer.

2. The display substrate according to claim 1, wherein, The scan line includes a first transparent conductive segment, the first transparent conductive segment being located in the active layer; and / or, The data line includes a second transparent conductive segment located in the first electrode layer.

3. The display substrate according to claim 2, wherein, The scan line includes multiple first transparent conductive segments and multiple first metal segments, wherein the multiple first transparent conductive segments and the multiple first metal segments are alternately arranged along the first direction and electrically connected sequentially; and / or, The data line includes multiple second transparent conductive segments and multiple second metal segments, which are arranged alternately along the second direction and electrically connected in sequence.

4. The display substrate according to claim 3, wherein, The first metal segment is located in the driving circuit layer, and / or the second metal segment is located in the driving circuit layer.

5. The display substrate according to claim 4, wherein, The driving circuit layer includes a light-shielding layer on the substrate, a buffer layer on the side of the light-shielding layer away from the substrate, an active layer on the side of the buffer layer away from the substrate, a gate insulating layer on the side of the active layer away from the substrate, a gate metal layer on the side of the gate insulating layer away from the substrate, an interlayer dielectric layer on the side of the gate metal layer away from the substrate, and a source / drain metal layer on the side of the interlayer dielectric layer away from the substrate. The first metal segment is located in the light-shielding layer, and / or the second metal segment is located in the source / drain metal layer.

6. The display substrate according to claim 5, wherein, The scan line also includes a connection segment located in the source / drain metal layer, and adjacent first transparent conductive segments and first metal segments are electrically connected through the connection segment.

7. The display substrate according to claim 5 or 6, wherein, The display substrate further includes a passivation layer located on the side of the source / drain metal layer away from the substrate and a planarization layer located between the passivation layer and the first electrode layer; The passivation layer has a first via that exposes a portion of the second metal segment, and the two ends of the second transparent conductive segment are respectively connected to two adjacent second metal segments through at least two of the first vias; as well as The planarization layer has a first opening, and the orthographic projection of the second transparent conductive segment on the substrate is located within the orthographic projection of the first opening on the substrate.

8. The display substrate according to any one of claims 5-7, wherein, The orthographic projection of the first metal segment on the substrate overlaps with the orthographic projection of the second transparent conductive segment on the substrate. And / or, The orthographic projection of the first transparent conductive segment on the substrate is spaced apart from the orthographic projection of the second metal segment on the substrate.

9. The display substrate according to claim 8, wherein, The orthographic projection of the first metal segment on the substrate is spaced apart from the orthographic projection of the second metal segment on the substrate; And / or, The orthographic projection of the first transparent conductive segment on the substrate is spaced apart from the orthographic projection of the second transparent conductive segment on the substrate.

10. [Amendment to Rule 26, 24.10.2025] The display substrate according to any one of claims 3-9, wherein, The length of the first metal segment along the first direction is greater than or equal to the length of the first transparent conductive segment along the first direction; and / or, The length of the second metal segment along the second direction is greater than or equal to the length of the second transparent conductive segment along the second direction.

11. The display substrate according to any one of claims 3-10, wherein, The display substrate includes a display area, which includes a transparent area and a sub-pixel area; In at least one first transparent conductive segment adjacent to the transparent region, the first transparent conductive segment includes a first main segment and a first auxiliary segment, the first main segment and the first auxiliary segment are located in the same layer, the first main segment is located between two adjacent first metal segments, the first auxiliary segment is connected to the first main segment along the second direction and is located in the transparent region; and / or, In at least one second transparent conductive segment adjacent to the transparent region, the second transparent conductive segment includes a second main segment and a second auxiliary segment, the second main segment and the second auxiliary segment are located in the same layer, the second main segment is located between two adjacent second metal segments, the second auxiliary segment is connected to the second main segment along the first direction and the second auxiliary segment is located in the transparent region.

12. The display substrate according to claim 11, wherein, The length of the first transparent conductive segment along the first direction is less than the dimension of the sub-pixel region along the first direction; the length of the first metal segment along the first direction is less than the dimension of the sub-pixel region along the first direction; and / or The length of the second transparent conductive segment along the second direction is less than the size of the sub-pixel region along the second direction, and the length of the second metal segment along the second direction is less than the size of the sub-pixel region along the second direction.

13. The display substrate according to any one of claims 2-12, wherein, The active layer includes an active portion, which includes a channel portion and conductor portions located on both sides of the channel portion. The sheet resistance of the first transparent conductive segment is less than or equal to the sheet resistance of the conductor portion.

14. The display substrate according to any one of claims 2-13, wherein, The first electrode layer includes a first electrode, and the sheet resistance of the second transparent conductive segment is less than or equal to the sheet resistance of the first electrode.

15. A display device, wherein, The display device includes a display substrate according to any one of claims 1-14.

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