Andreev level qubit device and manufacturing method therefor

Abstract

According to one embodiment of the present invention, an Andreev level qubit device is provided, the device comprising: a structure including an upper insulating layer, a lower insulating layer and multilayer graphene, which is positioned between the upper insulating layer and the lower insulating layer and has a conductor length (L); first and second superconductor layers that are in contact with both sides of the multilayer graphene and have a superconductor coherence length (ξ); an insulating deposition layer deposited on the upper insulating layer and the first and second superconductor layers; and a gate electrode formed on the insulating deposition layer at at least a portion of a region under which the multilayer graphene is positioned, wherein an energy gap (ΔE) of an Andreev level is adjusted by a gate voltage applied to the gate electrode.

Description

Andrev level qubit device and method for manufacturing the same

[0001] Embodiments of the present invention relate to an Andreve level qubit device and a method for manufacturing the same, and more specifically, to an Andreve level qubit device capable of controlling the energy gap using only an electric field without using a magnetic field and a method for manufacturing the same.

[0002]

[0003] An Andreev-level qubit is a type of superconductor-based qubit. Similar to another superconductor-based qubit, the Transmon qubit, it utilizes a specialized component called a Josephson junction. A Josephson junction is fabricated by inserting a very short length of non-superconducting material, such as an ordinary conductor or insulator, between two superconducting electrodes; this inserted material is called a "weak link" and acts as a medium through which a very small amount of supercurrent can flow. The Andreev level is a quantized energy state formed in a Josephson junction using an ordinary conductor. The Andreev level possesses energy states symmetric with respect to energy zero. When the ordinary conductor is sufficiently short, an Andreev-level qubit has a pair of energy levels and a ground state (E<0) - ) and the excited state (excited state, E>0) + ) can be thought of as 0 and 1, respectively, like bits in a classical computer. In this case, the transition between the 0 and 1 states is the energy gap between the two energy states ΔE = E + -E - An amount of energy is induced by applying external sources such as microwaves. The frequency of these microwaves is called the qubit frequency, which can control the superconducting qubit. It has the relationship where h is Planck's constant. This energy gap is directly linked to the performance of the qubit, as it is associated with coherence time and signal-to-noise ratio, which are the most fundamental elements in qubit control. For the efficient operation of a quantum computer, the ability to change this energy gap as desired is essential.

[0004]

[0005] The energy of the Andreev level depends on various parameters of the Josephson junction. The typical Andreev level can vary depending on the phase difference φ between the two superconductors, the electron permeability t of the junction, and the correlation between the length L of the ordinary conductor and the coherence length ξ of the superconductor.

[0006] Andreev level qubit devices realized in previous research results have a constant ratio of L to ξ. Since this ratio is determined by the physical elements of the device, it is very difficult to change once the device is fabricated. Conventional Andreev level qubits control the energy gap ΔE by fabricating a superconducting ring-shaped device similar to an RF SQUID (superconducting quantum interference device) and applying a magnetic field to adjust the energy gap ΔE. However, applying a magnetic field is generally more difficult to implement and control than applying an electric field, and the applied external magnetic field generally affects the control and performance of the RF device.

[0007]

[0008] Embodiments of the present invention are intended to provide an Andreev level qubit device capable of controlling the energy gap by applying an electric field instead of a magnetic field affecting the device, and a method for manufacturing the same.

[0009]

[0010] According to one embodiment of the present invention, an Andreev level qubit device is provided, comprising: a structure including an upper insulating layer, a lower insulating layer, and a double-layered graphene having a conductor length (L) located between the upper insulating layer and the lower insulating layer; first and second superconducting layers having a superconducting coherence length (ξ) in contact with both sides of the double-layered graphene; an insulating deposit layer deposited on the upper insulating layer and the first and second superconducting layers; and a gate electrode formed on at least a portion of the lower portion of the double-layered graphene located on the insulating deposit layer; wherein the energy gap (ΔE) of the Andreev level is controlled by a gate voltage applied to the gate electrode.

[0011]

[0012] The upper insulating layer and the lower insulating layer may include boron nitride.

[0013]

[0014] The above boron nitride may be hexagonal boron nitride.

[0015]

[0016] The thickness of the above structure may be 10 to 50 nm.

[0017]

[0018] The cross-section of the above structure may be a trapezoid with a narrow top.

[0019]

[0020] The first and second superconducting layers may include one selected from aluminum (Al), niobium (Nb), molybdenum rhenium (MoRe), and niobium nitride (NbN).

[0021]

[0022] The above insulating deposition layer may include aluminum(III) oxide (Al2O3).

[0023]

[0024] The gate electrode may include gold (Au).

[0025]

[0026] When a gate voltage is applied to the gate electrode, the ratio (L / ξ) of the conductor length (L) and the superconductor coherence length (ξ) is controlled, and the energy gap (ΔE) of the Andreev level can be controlled.

[0027]

[0028] According to another embodiment of the present invention, a method for manufacturing an Andreev level qubit device is provided, comprising the steps of: stacking a lower insulating layer, a double-layer graphene, and an upper insulating layer on a substrate, and forming a structure through lithography such that the double-layer graphene has a conductor length (L); forming first and second superconducting layers having a superconducting coherence length (ξ) on both sides of the structure; depositing an insulating deposition layer on the upper insulating layer and the first and second superconducting layers; and forming a gate electrode on at least a portion of the area where the double-layer graphene is located on the insulating deposition layer.

[0029]

[0030] The energy gap (ΔE) of the Andreev level can be controlled by the gate voltage applied to the gate electrode.

[0031]

[0032] The upper insulating layer and the lower insulating layer may include boron nitride.

[0033]

[0034] The above boron nitride may be hexagonal boron nitride.

[0035]

[0036] The thickness of the above structure may be 10 to 50 nm.

[0037]

[0038] The cross-section of the above structure may be a trapezoid with a narrow top.

[0039]

[0040] The first and second superconducting layers may include one selected from aluminum (Al), niobium (Nb), molybdenum rhenium (MoRe), and niobium nitride (NbN).

[0041]

[0042] The above insulating deposition layer may include aluminum(III) oxide (Al2O3).

[0043]

[0044] The gate electrode may include gold (Au).

[0045]

[0046] According to another embodiment of the present invention, a method of operating an Andreev level qubit device is provided, comprising: a structure including an upper insulating layer, a lower insulating layer, and a double-layered graphene having a conductor length (L) located between the upper insulating layer and the lower insulating layer; first and second superconducting layers having a superconducting coherence length (ξ) in contact with both sides of the double-layered graphene; an insulating deposition layer deposited on the upper insulating layer and the first and second superconducting layers; and a gate electrode formed on at least a portion of the lower portion of the insulating deposition layer where the double-layered graphene is located; wherein the energy gap (ΔE) of the Andreev level is controlled by applying a gate voltage to the gate electrode to control the ratio (L / ξ) of the conductor length (L) and the superconducting coherence length (ξ).

[0047]

[0048] When a gate voltage is applied to the gate electrode, the Fermi velocity of electrons in the double-layered graphene changes, and the superconductor coherence length (ξ) can change.

[0049]

[0050] According to embodiments of the present invention, an Andreev level qubit device capable of controlling the energy gap by applying an electric field instead of a magnetic field affecting the device, and a method for manufacturing the same are provided.

[0051]

[0052] FIG. 1 is a cross-sectional view showing an Andreev level qubit element according to an embodiment of the present invention.

[0053] Figure 2 shows the wavenumber of electrons (k) in double-layered graphene. F A graph showing the relationship between ) and energy (E).

[0054] Figure 3 shows the gate voltage (V) of double-layered graphene. g ) and Fermi velocity (v F A graph representing the relationship between )

[0055] Figure 4 shows the gate voltage (V) for each type of superconductor. g Graph showing the change in L / ξ values ​​according to the change

[0056] Figure 5 is a graph showing the change in Andreev levels according to the L / ξ value.

[0057] FIG. 6 is a flowchart illustrating a method for manufacturing an Andreev level qubit element according to an embodiment of the present invention.

[0058]

[0059] Specific embodiments will be described below with reference to the drawings. The following detailed description is provided to facilitate a comprehensive understanding of the methods, apparatuses, and / or systems described herein. However, this is merely illustrative and the disclosed embodiments are not limited thereto.

[0060] In describing the embodiments, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions could unnecessarily obscure the essence of the disclosed embodiments. Furthermore, terms described below are defined in consideration of their functions in the disclosed embodiments, and these may vary depending on the intent or practice of the user or operator. Therefore, such definitions should be based on the content throughout this specification. Terms used in the detailed description are intended merely to describe the embodiments and should not be limiting. Unless explicitly stated otherwise, expressions in the singular form include the meaning of the plural form. In this description, expressions such as "include" or "comprise" are intended to refer to certain characteristics, numbers, steps, actions, elements, parts thereof, or combinations thereof, and should not be interpreted to exclude the existence or possibility of one or more other characteristics, numbers, steps, actions, elements, parts thereof, or combinations thereof other than those described.

[0061]

[0062] FIG. 1 is a cross-sectional view showing an Andreev Level qubit element (10) according to one embodiment of the present invention.

[0063]

[0064] Referring to FIG. 1, an Andreev level qubit device (10) according to one embodiment of the present invention may include a structure (200) comprising an upper insulating layer (210b), a lower insulating layer (210a), and a double-layered graphene (250) located between the upper insulating layer (210b) and the lower insulating layer (210a); first and second superconducting layers (300a, 300b) in contact with both sides of the double-layered graphene (250) of the structure (200); an insulating deposition layer (400) deposited on the upper insulating layer (210b) and the first and second superconducting layers (300a, 300b); and a gate electrode (500) formed on at least a portion of the insulating deposition layer (400) where the double-layered graphene (250) is located below it. Here, the stacked graphene has a conductor length (L), and the first and second superconducting layers (300a, 300b) may have a superconducting coherence length (ξ). In one embodiment of the present invention, the conductor length (L) and the superconducting coherence length (ξ) are conditions for controlling the energy gap (ΔE) of the Andreev level, and the superconducting coherence length (ξ) is a gate voltage (V) applied to the gate electrode (500). g It can be changed by ).

[0065]

[0066] The upper insulating layer (210b) and the lower insulating layer (210a) may comprise boron nitride. The boron nitride may be hexagonal boron nitride. Hexagonal boron nitride is an insulator that can be peeled into multiple layers and can be used to protect the double-layered graphene (250) against external mechanical and chemical defects. The thickness of the structure (200) comprising the upper insulating layer (210b), the double-layered graphene (250), and the lower insulating layer (210a) may be 10 to 50 nm, which may be for ease of manufacturing. The structure (200) may be formed into a trapezoidal shape with a cross-section that is narrower at the top than at the bottom through a lithography process. In order to stack the structure (200) and apply the lithography process, the structure (200) may be formed on a substrate (100). The substrate (100) may be a silicon substrate.

[0067]

[0068] Additionally, the first and second superconducting layers (300a, 300b) may include one selected from aluminum (Al), niobium (Nb), molybdenum rhenium (MoRe), and niobium nitride (NbN). The first and second superconducting layers (300a, 300b) and the stacked graphene (250) located between them may form a Josephson junction. In order to control the ratio (L / ξ) of the conductor length (L) and the superconducting coherence length (ξ) in the Josephson junction, the width of the stacked graphene (250) and the type of the first and second superconducting layers (300a, 300b) in the structure (200) may be determined. Through this, the range of the ratio (L / ξ) of the conductor length (L) and the superconductor coherence length (ξ), which can be varied through the gate voltage, can be determined, thereby allowing the energy gap (ΔE) of the Andreev level, which will be explained later, to be controlled.

[0069] And, by forming the structure (200) in a trapezoidal shape, a Josephson junction can be properly formed between the double-layered graphene (250) exposed at the edge of the structure (200) and the first and second superconducting layers (300a, 300b).

[0070]

[0071] The insulating deposition layer (400) deposited on the upper insulating layer (210b) and the first and second superconducting layers (300a, 300b) may include aluminum oxide (III) (Al2O3). The gate electrode (500) is located on the region where the double-layered graphene (250) is located, and the material of the gate electrode (500) may be gold (Au), a metal with good conductivity. A voltage biasing device (600) is connected to the gate electrode (500) to obtain a gate voltage (V g ) can be authorized.

[0072]

[0073] In one embodiment of the present invention, the ratio (L / ξ) of the length (L) of the general conductor forming the Josephson junction of the Andreev level qubit element (10) and the superconducting coherence length (ξ) of the superconducting layer is closely related to the energy gap (ΔE) by Equation 1, and can be controlled in real time through the gate voltage.

[0074]

[0075] [Equation 1]

[0076]

[0077] Here, describes the additional phase obtained due to the transmission (t) and reflection (r) of electrons by a scatterer present at a longitudinal position a (0≤x≤L) of a general conductor, where N = ±1, ±2, ±3,…

[0078]

[0079] FIG. 2 shows the wavenumber (k) of electrons in double-layered graphene (250). F This is a graph showing the relationship between ) and energy (E).

[0080] Referring to FIG. 2, the double-layer graphene (250) is a structure in which two layers of monolayer graphene, a two-dimensional material in which carbon atoms are bonded in a hexagonal structure, are stacked vertically. As shown in FIG. 2, the electron wave number (k) of the double-layer graphene F , wave number) and energy (E) have a non-linear relationship.

[0081]

[0082] FIG. 3 shows the gate voltage (V) of the double-layered graphene (250). g ) and Fermi velocity (v F It is a graph representing the relationship between ).

[0083] Referring to FIG. 3, the wavenumber (k) of the stacked graphene (250) F ) is charge density (n) and It has the relationship. At this time, the gate voltage (V) on the double-layered graphene g By applying a vertical electric field by ) , the charge density (n) of the stacked graphene can be changed according to the same principle as a FET (field effect transistor), and therefore the wavenumber (k F ) also changes. In this case, the electron's Fermi velocity is Therefore, the gate voltage (V) to the double-layered graphene (250) g By applying ), the Fermi velocity (v) F It becomes possible to control ).

[0084]

[0085] Figure 4 shows the gate voltage (V) for each type of superconductor. g This is a graph showing the change in L / ξ values ​​according to the change.

[0086] Referring to FIG. 4, when the stacked graphene (250) is sufficiently clean so that the electronic conduction has ballisticity, the superconducting coherence length is It has the relationship . Here, Δ is the superconducting gap energy. Therefore, assuming the conduction channel length of a general conductor is L=1μm, the gate voltage (V g Depending on ), the L / ξ value changes as shown in FIG. 4 as superconductors such as aluminum (Al), niobium (Nb), molybdenum rhenium (MoRe), and niobium nitride (NbN) are used. Here, the charge density change efficiency per voltage of the gate voltage is ~6.4×10⁻¹⁰, taking into account the characteristics of the dielectric forming the insulating deposition layer (400) between the double-layered graphene (250) and the gate electrode (500). 14 m -2 Assume / V.

[0087]

[0088] Figure 5 is a graph showing the change in Andreev levels according to the L / ξ value.

[0089] Referring to Fig. 5, for example, when the L / ξ value is adjusted from 0.5 to 3, such as at t=0.9, it can be observed that the Andreev energy gap (ΔE) changes as shown in Fig. 5. At this time, the temperature of the device is A sufficiently low temperature must be maintained to satisfy [the condition].

[0090]

[0091] The operation method of an Andreve level qubit element according to one embodiment of the present invention is as follows.

[0092] A gate voltage (V) to the gate electrode (500) of the Andrev level qubit element (10) shown in FIG. 1 g When a vertical electric field is formed in the double-layered graphene (250) by applying ) the charge density (n) of the double-layered graphene (250) changes according to the same principle as a field effect transistor, and the wave number (k) of the electrons F ) can be changed. As a result, the Fermi velocity (v) of electrons in the double-layered graphene (250) can be changed. FAs ) changes, the superconducting coherence length (ξ) is Since it has the relationship equation, the superconducting coherence length (ξ) can be controlled. Accordingly, the ratio (L / ξ) of the conductor length (L) and the superconducting coherence length (ξ) is adjusted, and the energy gap (ΔE) of the Andreev level can be controlled by [Equation 1], and the qubit frequency (f) of the Andreev level qubit element (10) q ) can be controlled according to the energy gap (ΔE) by the following relationship.

[0093]

[0094] [Equation 2]

[0095]

[0096] (h is Planck's constant)

[0097]

[0098] FIG. 6 is a flowchart illustrating a method for manufacturing an Andreev level qubit element according to one embodiment of the present invention.

[0099]

[0100] Referring to FIG. 6, a method for manufacturing an Andreev level qubit device comprises the steps of: stacking a lower insulating layer (210a), a double-layered graphene (250), and an upper insulating layer (210b) on a substrate (100), and forming a structure (200) through lithography such that the double-layered graphene (250) has a conductor length (L) (S10); forming first and second superconducting layers (300a, 300b) having a superconducting coherence length (ξ) on both sides of the structure (200) (S20); depositing an insulating deposition layer (400) on the upper insulating layer (210b) and the first and second superconducting layers (300a, 300b) (S30); and forming a gate electrode (500) on at least a portion of the area where the double-layered graphene (250) is located on the insulating deposition layer (400). It may include step (S40).

[0101]

[0102] In forming the structure (200), a thin and transparent material, which is a polymer material having sufficient adhesion at a certain temperature or higher, can be used. And, as previously described, the structure (200) can be formed to have a thickness of about 10 to 50 nm using a lithography process. More specifically, after stacking the lower insulating layer (210a), the double-layered graphene (250), and the upper insulating layer (210b) in sequence, if the double-layered graphene (250) is made to have a conductor length (L) using reactive ion etching, the structure (200) becomes a trapezoidal shape with the upper part narrower than the lower part, and carbon atoms located at both edges of the double-layered graphene (250) can be exposed. Through this, when the first and second superconducting layers (300a, 300b) are formed, a Josephson junction can be formed between the double-layered graphene (250) and the first and second superconducting layers (300a, 300b).

[0103]

[0104] Then, after forming the first and second superconducting layers (300a, 300b) on both sides of the structure (200) through deposition (S20), an insulating deposition layer (400) can be formed on the upper insulating layer (210b) and the first and second superconducting layers (300a, 300b) using an atomic layer deposition (ALD) process (S30). Then, a gate electrode (500) can be deposited on at least a portion of the area where the double-layered graphene (250) is located using a highly conductive metal (S40). Here, the highly conductive metal may be gold (Au), but is not limited thereto.

[0105]

[0106] And, a voltage biasing device (600) is connected to the gate electrode (500) to obtain a gate voltage (V g ) can be authorized.

[0107]

[0108] Although representative embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications can be made to the above-described embodiments without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims set forth below as well as equivalents thereof.

[0109]

[0110] [Explanation of the symbol]

[0111] 10: Andreev level qubit element

[0112] 100 : Substrate

[0113] 200 : Structure

[0114] 210a: Lower insulation layer

[0115] 210b: Upper insulation layer

[0116] 250 : Layered graphene

[0117] 300a: First superconducting layer

[0118] 300b: Second superconducting layer

[0119] 400 : Insulating deposition layer

[0120] 500 : Gate electrode

[0121] 600: Voltage biasing device

Claims

1. A structure comprising an upper insulating layer, a lower insulating layer, and a double-layered graphene located between the upper insulating layer and the lower insulating layer and having a conductor length (L); First and second superconducting layers having a superconducting coherence length (ξ) and in contact with both sides of the above-mentioned stacked graphene; An insulating layer deposited on the upper insulating layer and the first and second superconducting layers; and A gate electrode formed on at least a portion of the area where the double-layered graphene is located on the lower part of the insulating deposition layer; comprising An Andreev level qubit device in which the energy gap (ΔE) of the Andreev level is controlled by the gate voltage applied to the gate electrode.

2. In Claim 1, An Andreev level qubit device in which the upper insulating layer and the lower insulating layer comprise boron nitride.

3. In Claim 2, The above boron nitride is a hexagonal boron nitride, an Andreev level qubit element.

4. In Claim 1, An Andreev level qubit device having a thickness of 10 to 50 nm of the above structure.

5. In Claim 1, An Andreev level qubit element, the cross-section of the above structure is a trapezoid in which the upper part is narrower than the lower part.

6. In Claim 1, The first and second superconducting layers mentioned above are, Andrev level qubit element comprising one selected from aluminum (Al), niobium (Nb), molybdenum rhenium (MoRe) and niobium nitride (NbN).

7. In Claim 1, The above insulating deposition layer comprises aluminum(III) oxide (Al2O3), and is an Andrev level qubit device.

8. In Claim 1, The above gate electrode is an Andreev level qubit element comprising gold (Au).

9. In Claim 1, An Andreev level qubit device in which, when a gate voltage is applied to the gate electrode, the ratio (L / ξ) of the conductor length (L) and the superconductor coherence length (ξ) is controlled, and the energy gap (ΔE) of the Andreev level is controlled.

10. A step of stacking a lower insulating layer, a double-layered graphene, and an upper insulating layer on a substrate, and forming a structure through lithography such that the double-layered graphene has a conductor length (L); A step of forming first and second superconducting layers having a superconducting coherence length (ξ) on both sides of the above structure; A step of depositing an insulating deposition layer on the upper insulating layer and the first and second superconducting layers; and A method for manufacturing an Andreev level qubit device, comprising the step of forming a gate electrode on at least a portion of the area where the double-layered graphene is located on the insulating deposition layer.

11. In Claim 10, A method for manufacturing an Andreve level qubit device in which the energy gap (ΔE) of the Andreve level is controlled by the gate voltage applied to the gate electrode.

12. In Claim 10, A method for manufacturing an Andreve level qubit device, wherein the upper insulating layer and the lower insulating layer comprise boron nitride.

13. In Claim 12, A method for manufacturing an Andreev level qubit device, wherein the boron nitride is hexagonal boron nitride.

14. In Claim 10, A method for manufacturing an Andreev level qubit device, wherein the thickness of the above structure is 10 to 50 nm.

15. In Claim 10, A method for manufacturing an Andreev level qubit element, wherein the cross-section of the above structure is a trapezoid with a narrow top.

16. In Claim 10, The first and second superconducting layers mentioned above are, A method for manufacturing an Andreb level qubit device comprising one selected from aluminum (Al), niobium (Nb), molybdenum rhenium (MoRe) and niobium nitride (NbN).

17. In Claim 10, A method for manufacturing an Andreev level qubit device, wherein the insulating deposition layer comprises aluminum(III) oxide (Al2O3).

18. In Claim 10, A method for manufacturing an Andreve level qubit device, wherein the gate electrode comprises gold (Au).

19. A structure comprising an upper insulating layer, a lower insulating layer, and a double-layered graphene having a conductor length (L) located between the upper insulating layer and the lower insulating layer; first and second superconducting layers having a superconducting coherence length (ξ) in contact with both sides of the double-layered graphene; an insulating deposit layer deposited on the upper insulating layer and the first and second superconducting layers; and a gate electrode formed on at least a portion of the lower portion of the double-layered graphene located on the insulating deposit layer; wherein A method of operation of an Andreev level qubit device in which the energy gap (ΔE) of the Andreev level is controlled by applying a gate voltage to the gate electrode to control the ratio (L / ξ) of the conductor length (L) and the superconductor coherence length (ξ).

20. In Claim 19, A method of operation of an Andreev level qubit device in which, when a gate voltage is applied to the gate electrode, the Fermi velocity of electrons in the double-layered graphene changes and the superconductor coherence length (ξ) changes.

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