Driving method for display panel, and display apparatus

Abstract

A driving method for a display panel (DP), and a display apparatus. The driving method comprises: on the basis of the current shutter duration (t) and a target refresh frequency (f), adjusting a light-emitting control signal (EM) outputted to each row of sub-pixels (100), so that the current shutter duration (t) is a positive integer multiple of the period of the light-emitting control signal (EM), and light-emitting elements (102) in each row of sub-pixels (100) have the same cumulative light-emitting duration during exposure of an image acquisition device, thereby preventing scanning stripes from appearing when the image acquisition device acquires an image displayed on the display panel (DP).

Description

Display panel driving method and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving method and display device for a display panel. Background Technology

[0002] Typically, a display panel is used to display the image. When an image acquisition device is used to capture the image displayed on the display panel, there will be differences in brightness in the image captured by the image acquisition device, which will affect the shooting effect.

[0003] Summary of the Invention

[0004] This disclosure provides a driving method for a display panel, the display panel including a plurality of sub-pixels arranged in an array and a light-emitting driving circuit electrically connected to each row of sub-pixels, the sub-pixels including a pixel circuit and a light-emitting element connected to the pixel circuit;

[0005] The driving method includes:

[0006] Determine the current shutter speed of the image acquisition device and the target refresh rate of the display panel; the image acquisition device is used to acquire the image displayed on the display panel.

[0007] Based on the current shutter speed and the target refresh rate, the light emission control signal output by the light emission driving circuit to each row of sub-pixels is adjusted. The adjusted light emission control signal controls the operation of the pixel circuit so as to control the cumulative light emission duration of the light emission elements in each row of sub-pixels to be the same within the current shutter speed.

[0008] In some possible implementations, the reciprocal of the target refresh rate divided by the current shutter duration is a positive integer.

[0009] In some possible implementations, the pixel circuit includes: a first light-emitting control transistor, a driving circuit, and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving circuit, and the second light-emitting control transistor are connected between a first power supply terminal and the light-emitting element;

[0010] The light-emitting driving circuit is connected to the control terminal of the first light-emitting control transistor and the control terminal of the second light-emitting control transistor in each row of sub-pixels.

[0011] The adjustment of the light emission control signal output by the light emission driving circuit to each row of sub-pixels includes:

[0012] The light emission control signal output by the light emission driving circuit to each row of sub-pixels is adjusted to a periodic signal with alternating active and inactive levels, and the current shutter duration is made a positive integer multiple of the period of the light emission control signal.

[0013] In some possible implementations, the period duration is 2h*x, where x is an integer greater than or equal to 2, and h is the scanning time required for one row of sub-pixel input data signals.

[0014] In some possible implementations, the duration of the invalid level in each cycle of the light emission control signal is greater than or equal to 2 hours.

[0015] In some possible implementations, a target light emission control trigger signal is output to the light emission driving circuit, the target light emission control trigger signal being a periodic signal that alternates between valid and invalid levels.

[0016] In some possible implementations, for the upper and lower row sub-pixels in two adjacent rows of sub-pixels, the light emission control signal output to the lower row sub-pixel is delayed by a first set phase difference compared to the light emission control signal output to the upper row sub-pixel; the first set phase difference is the scan time required for the input data signal of a row of sub-pixels.

[0017] In some possible implementations, the pixel circuit includes: a first light-emitting control transistor, a driving circuit, and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving circuit, and the second light-emitting control transistor are connected between a first power supply terminal and the light-emitting element;

[0018] The light-emitting driving circuit is connected to the control terminal of the first light-emitting control transistor in each row of sub-pixels;

[0019] The control terminal of the second light-emitting control transistor in each row of sub-pixels is used to receive the global light-emitting control signal;

[0020] The adjustment of the light emission control signal output by the light emission driving circuit to each row of sub-pixels includes:

[0021] The global illumination control signal is controlled as a periodic signal with alternating active and inactive levels. The illumination control signal output by the illumination driving circuit to each row of sub-pixels has an active level and an inactive level. The current shutter duration is a positive integer multiple of the period of the global illumination control signal, and during the duration of the global illumination control signal being active, the illumination control signal output by the illumination driving circuit to each row of sub-pixels is always active.

[0022] In some possible implementations, during the duration during which the global illumination control signal is at an invalid level, the illumination control signal output by the illumination driving circuit to one or more rows of sub-pixels is at an invalid level.

[0023] In some possible implementations, during the duration during which the global light emission control signal is at an invalid level, when the light emission control signal output by the light emission driving circuit to the multi-row sub-pixels is at an invalid level, the invalid level of the light emission control signal of the multi-row sub-pixels is sequentially delayed by a second predetermined phase difference.

[0024] In some possible implementations, the invalid levels of the light emission control signals of any two rows of sub-pixels in the multi-row sub-pixel light emission control signals do not overlap in duration.

[0025] In some possible implementations, the pixel circuit further includes a first reset transistor, a second reset transistor, and a scan transistor, wherein the first reset transistor is connected between a second power supply terminal and a first node, the second reset transistor is connected between the second power supply terminal and the light-emitting element, and the scan transistor is connected between a data signal terminal and the first node;

[0026] For each row of sub-pixels, the control terminal of the first reset transistor is used to receive a first reset control signal, the control terminal of the second reset transistor is used to receive a second reset control signal, and the control terminal of the scan transistor is used to receive a scan control signal.

[0027] The driving method further includes:

[0028] During the duration when the light emission control signal is at an invalid level, the first reset control signal, the second reset control signal, and the scan control signal output to each row of sub-pixels sequentially become valid.

[0029] In some possible implementations, during the duration of the effective level of the light emission control signal, the second reset control signal output to each row of sub-pixels sequentially appears at multiple effective levels at intervals, and when the global light emission control signal appears at an invalid level, the second reset control signal output to each row of sub-pixels appears at an invalid level.

[0030] In some possible implementations, the display panel has multiple refresh rates;

[0031] Determining the target refresh rate of the display panel includes:

[0032] Obtain the current refresh rate of the display panel; the current refresh rate is one of the plurality of refresh rates;

[0033] When the reciprocal of the current refresh rate divided by the current shutter length is a positive integer, the current refresh rate is taken as the target refresh rate;

[0034] When the reciprocal of the current refresh rate divided by the current shutter length is not a positive integer, a new refresh rate is determined from the plurality of refresh rates as the target refresh rate; wherein the reciprocal of the new refresh rate divided by the current shutter length is a positive integer.

[0035] In some possible implementations, the refresh frequencies other than the current refresh frequency among the plurality of refresh frequencies have a plurality of alternative refresh frequencies, and the reciprocal of each alternative refresh frequency divided by the current shutter length is a positive integer.

[0036] The new refresh frequency is any one of the plurality of alternative refresh frequencies, or the maximum value of the plurality of alternative refresh frequencies, or the minimum value of the plurality of alternative refresh frequencies.

[0037] This disclosure also provides a display device, including:

[0038] The display panel includes a plurality of sub-pixels arranged in an array and a light-emitting driving circuit electrically connected to each row of sub-pixels. The sub-pixels include a pixel circuit and a light-emitting element connected to the pixel circuit.

[0039] A timing controller, connected to the light-emitting driving circuit, is used to determine the current shutter speed of the image acquisition device and the target refresh rate of the display panel; based on the current shutter speed and the target refresh rate, the timing controller adjusts the light-emitting control signal output by the light-emitting driving circuit to each row of sub-pixels, and controls the operation of the pixel circuit through the adjusted light-emitting control signal to ensure that the cumulative light-emitting duration of the light-emitting elements in each row of sub-pixels is the same within the current shutter speed; the image acquisition device is used to acquire the image displayed on the display panel.

[0040] In some possible implementations, the pixel circuit includes: a first light-emitting control transistor, a driving circuit, and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving circuit, and the second light-emitting control transistor are connected between a first power supply terminal and the light-emitting element;

[0041] The light-emitting driving circuit is connected to the control terminal of the first light-emitting control transistor and the control terminal of the second light-emitting control transistor in each row of sub-pixels.

[0042] In some possible implementations, the pixel circuit includes: a first light-emitting control transistor, a driving circuit, and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving circuit, and the second light-emitting control transistor are connected between a first power supply terminal and the light-emitting element;

[0043] The light-emitting driving circuit is connected to the control terminal of the first light-emitting control transistor in each row of sub-pixels;

[0044] The display panel also includes a global light emission control signal terminal, the control terminal of the second light emission control transistor in each row of sub-pixels is connected to the global light emission control signal terminal, and the timing controller is also connected to the global light emission control signal terminal for outputting a global light emission control signal to the global light emission control signal terminal. Attached Figure Description

[0045] Figure 1 is a schematic diagram of the pixel circuit in an embodiment of this disclosure;

[0046] Figure 2 is a signal timing diagram of the pixel circuit in an embodiment of this disclosure;

[0047] Figure 3 is a timing diagram of the light emission control signal output by the light emission driving circuit in the embodiment of this disclosure;

[0048] Figure 4 is a schematic diagram of the structure of the display panel in an embodiment of this disclosure;

[0049] Figure 5 is a schematic diagram of the structure of the light-emitting driving circuit in an embodiment of this disclosure;

[0050] Figure 6 is a flowchart of some of the driving methods for the display panel in the embodiments of this disclosure;

[0051] Figure 7 is a flowchart of the method for determining the target refresh rate of the display panel in an embodiment of this disclosure;

[0052] Figure 8 shows some timing diagrams of the light emission control signals in the embodiments of this disclosure;

[0053] Figure 9 is a schematic diagram of the shift register unit of the light-emitting driving circuit in an embodiment of this disclosure;

[0054] Figure 10 is a schematic diagram of some of the structures of the display panel in the embodiments of this disclosure;

[0055] Figure 11 is a schematic diagram of some of the structures of the display panel in the embodiments of this disclosure;

[0056] Figure 12 is another timing diagram of the light emission control signal in the embodiments of this disclosure;

[0057] Figure 13 is a timing diagram of some signals of the light-emitting driving circuit in an embodiment of this disclosure;

[0058] Figure 14 is a schematic diagram of some of the pixel circuits in the embodiments of this disclosure;

[0059] Figure 15 is a timing diagram of some more signals of the pixel circuit in the embodiments of this disclosure;

[0060] Figure 16 is a flowchart of a method for determining the target refresh rate of a display panel in an embodiment of this disclosure;

[0061] Figure 17 is a schematic diagram of the structure of the display device in an embodiment of this disclosure. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0063] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0064] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0065] Typically, a display panel may include multiple sub-pixels, each sub-pixel including pixel circuitry and a light-emitting element connected to the pixel circuitry. For example, the pixel circuitry may include transistors and capacitors, and the interaction between the transistors and capacitors drives the connected light-emitting element to emit light.

[0066] For example, the light-emitting element may include: organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED), micro light-emitting diode (Micro LED), and mini light-emitting diode (Mini LED).

[0067] For example, as shown in Figure 1, the pixel circuit may include a 7T1C circuit, specifically including: a first reset transistor M1, a scan transistor M2, a drive transistor M3, a scan transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a second reset transistor M7, and a storage capacitor Cs. The cathode of the light-emitting element is coupled to the second power supply terminal VSS. For example, the first terminal of the first reset transistor M1 is coupled to the second power supply terminal Vinit, the second terminal is coupled to the Dnode node (first node), and the control terminal is coupled to the reset signal terminal RST_A. For example, the first reset transistor M1 is turned on under the control of the effective level of the reset control signal at the reset signal terminal RST_A, and turned off under the control of the ineffective level of the reset control signal. Optionally, as shown in Figure 1, the first reset transistor M1 can be set as a P-type transistor, in which case the effective level of the reset control signal is low and the ineffective level is high. Of course, the first reset transistor M1 can also be set as an N-type transistor, in which case the effective level of the reset control signal is high and the ineffective level is low.

[0068] For example, the first terminal of the scanning transistor M2 is coupled to the Dnode node, the second terminal is coupled to the N2 node, and the control terminal is coupled to the scan signal terminal Gate. For example, the scanning transistor M2 is turned on under the control of the active level of the scan control signal at the scan signal terminal Gate, and turned off under the control of the inactive level of the scan control signal. Optionally, as shown in Figure 1, the scanning transistor M2 can be configured as a P-type transistor, in which case the active level of the scan control signal is low and the inactive level is high. Of course, the scanning transistor M2 can also be configured as an N-type transistor, in which case the active level of the scan control signal is high and the inactive level is low.

[0069] For example, the first terminal of the driving transistor M3 is coupled to node N3, the second terminal is coupled to node N2, and the control terminal is coupled to node Dnode. For example, the driving transistor M3 is turned on under the control of the active level of the signal at node Dnode and turned off under the control of the inactive level of the signal at node Dnode. Optionally, as shown in Figure 1, the driving transistor M3 can be configured as a P-type transistor, in which case the active level of the signal at node Dnode is low and the inactive level is high. Of course, the driving transistor M3 can also be configured as an N-type transistor, in which case the active level of the signal at node Dnode is high and the inactive level is low.

[0070] For example, the first terminal of the scanning transistor M4 is coupled to the data signal terminal Data, the second terminal is coupled to the N3 node, and the control terminal is coupled to the scanning signal terminal Gate. For example, the scanning transistor M4 is turned on under the control of the active level of the scanning control signal at the scanning signal terminal Gate, and turned off under the control of the inactive level of the scanning control signal. Optionally, as shown in Figure 1, the scanning transistor M4 can be configured as a P-type transistor, in which case the active level of the scanning control signal is low and the inactive level is high. Of course, the driving transistor M3 can also be configured as an N-type transistor, in which case the active level of the scanning control signal is high and the inactive level is low.

[0071] For example, the first terminal of the first light-emitting control transistor M5 is coupled to the first power supply terminal VDD, the second terminal is coupled to the N3 node, and the control terminal is coupled to the light-emitting control signal terminal EM. For example, the first light-emitting control transistor M5 is turned on under the control of the effective level of the light-emitting control signal at the light-emitting control signal terminal EM, and turned off under the control of the ineffective level of the light-emitting control signal. Optionally, as shown in FIG1, the first light-emitting control transistor M5 can be configured as a P-type transistor, in which case the effective level of the light-emitting control signal is low and the ineffective level is high. Of course, the first light-emitting control transistor M5 can also be configured as an N-type transistor, in which case the effective level of the light-emitting control signal is high and the ineffective level is low.

[0072] For example, the first terminal of the second light-emitting control transistor M6 is coupled to the N2 node, the second terminal is coupled to the anode of the light-emitting element, and the control terminal is coupled to the light-emitting control signal terminal EM. For example, the second light-emitting control transistor M6 is turned on under the control of the effective level of the light-emitting control signal at the light-emitting control signal terminal EM, and turned off under the control of the ineffective level of the light-emitting control signal. Optionally, as shown in FIG1, the second light-emitting control transistor M6 can be configured as a P-type transistor, in which case the effective level of the light-emitting control signal is low and the ineffective level is high. Of course, the second light-emitting control transistor M6 can also be configured as an N-type transistor, in which case the effective level of the light-emitting control signal is high and the ineffective level is low.

[0073] For example, the first terminal of the second reset transistor M7 is electrically connected to the second power supply terminal Vinit, the second terminal is electrically connected to the anode of the light-emitting element, and the control terminal is coupled to the reset signal terminal RST_A. For example, the second reset transistor M7 is turned on under the control of the effective level of the reset control signal at the reset signal terminal RST_A, and turned off under the control of the ineffective level of the reset control signal. Optionally, as shown in FIG1, the second reset transistor M7 can be configured as a P-type transistor, in which case the effective level of the reset control signal is low and the ineffective level is high. Of course, the second reset transistor M7 can also be configured as an N-type transistor, in which case the effective level of the reset control signal is high and the ineffective level is low.

[0074] The first plate of the storage capacitor Cs is coupled to the Dnode node, and the second plate is coupled to the first power supply terminal VDD.

[0075] In some embodiments of this disclosure, the first power supply terminal VDD can be configured to apply a constant first power supply voltage, which is generally positive. The third power supply terminal VSS can apply a constant second power supply voltage, which is generally ground voltage or a negative value. In practical applications, the specific values ​​of the first and second power supply voltages can be designed and determined according to the actual application environment, and are not limited herein.

[0076] In some embodiments of this disclosure, the first terminal of the transistor can be used as its source and the second terminal as its drain, depending on the type of the transistor and the signal at its control terminal; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. This can be designed and determined according to the actual application environment, and no specific distinction is made here.

[0077] The above are merely examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this disclosure and are not specifically limited here.

[0078] For example, the structure of the pixel circuit shown in Figure 1 corresponds to the signal timing diagram shown in Figure 2. Here, em represents the light-emitting control signal applied to the control terminals M5 and M6 of the first and second light-emitting control transistors, rst_a represents the reset control signal applied to the control terminals M1 and M7 of the first and second reset transistors, and gate represents the scan control signal applied to the scan transistors M2 and M4. Furthermore, the working process of Figure 2, combined with that of Figure 1, is essentially the same as that in the prior art, and will not be elaborated upon here. It should be noted that Figure 2 is only for illustrative purposes. In practical applications, the signal timing diagram corresponding to the pixel circuit provided in this embodiment can also be other forms of signal timing diagrams, which are not limited here.

[0079] As shown in Figure 4, a light-emitting driving circuit is also installed in the display panel to input em signals to the first and second light-emitting control transistors. The control terminals of the first and second light-emitting control transistors are coupled to the light-emitting driving circuit.

[0080] For example, the light-emitting driving circuit may include multiple cascaded shift register units, as shown in Figure 5. The input signal terminal INPUT of the first-stage shift register unit is connected to the frame trigger signal terminal, and the signal output terminal OUTPUT is connected to the input signal terminal INPUT of the second-stage shift register unit. The signal output terminal OUTPUT of the (n-1)th-stage shift register unit is connected to the input signal terminal INPUT of the nth-stage shift register unit. The first clock signal terminal CK of each odd-numbered-stage shift register unit is provided by the same clock signal terminal, i.e., the first clock signal terminal ck, and the second clock signal terminal CB is provided by the same clock signal terminal, i.e., the second clock signal terminal cb. The first clock signal terminal CK of each even-numbered-stage shift register unit is provided by the same clock signal terminal, i.e., the second clock signal terminal cb, and the second clock signal terminal CB is provided by the same clock signal terminal, i.e., the first clock signal terminal ck. One shift register unit corresponds to one row of pixel circuit.

[0081] As shown in Figure 3, during operation, a frame trigger signal ESTV is input to the first-level shift register unit to trigger its operation. The remaining shift register units output illumination control signals sequentially. For example, the signal output terminal of the first-level shift register unit is connected to the control terminals of the first and second illumination control transistors in the pixel circuit of the first row of sub-pixels, and is configured to provide illumination control signal Eout1 to the first and second illumination control transistors in the first row of sub-pixels; the signal output terminal of the second-level shift register unit is connected to the control terminals of the first and second illumination control transistors in the pixel circuit of the second row of sub-pixels, and is configured to provide illumination control signals Eout2…; the signal output terminal of the m-th level shift register unit is connected to the control terminals of the first and second illumination control transistors in the pixel circuit of the m-th row of sub-pixels, and is configured to provide illumination control signal Eoutm to the first and second illumination control transistors in the m-th row of sub-pixels. Based on this, under the excitation of the frame trigger signal, the light-emitting driving circuit generates light-emitting control signals Eout1, Eout2...Eoutm in sequence with their timing shifted sequentially by each shift register unit.

[0082] For example, the display panel may include x rows and y columns of sub-pixels. The scanning time required for the input data signal of one row of sub-pixels, i.e., the time for the gate signal to be at an effective level (e.g., low level), is h (typically 5-20µs). The time required to scan from the first row of sub-pixels to the nth row of sub-pixels is n*h. Assume that the current shutter speed t of the image acquisition device is n*h. Assume that when scanning to the mth row of sub-pixels, the image acquisition device starts exposure and captures the image displayed on the display panel. During the exposure period of the image acquisition device, the sub-pixels from the mth row to the (m+n)th row of sub-pixels are scanned sequentially. The light emission control signal undergoes a process of being turned off and then on again (i.e., the light emission element undergoes a process of being turned off and then on again). The sub-pixels from the mth row to the (m+n)th row of sub-pixels will briefly stop emitting light for a period of time during the exposure period of the image acquisition device. The brightness is reduced compared to the other rows of sub-pixels. The sensor of the image acquisition device will capture this brightness difference of the display panel, which is reflected in the final captured image as scan lines.

[0083] For example, as shown in Figure 3, Eout1 represents the light emission control signal input to the control terminals of the first and second light emission control transistors in the first row of sub-pixels, Eout2 represents the light emission control signal input to the control terminals of the first and second light emission control transistors in the second row of sub-pixels, and so on, Eoutm represents the light emission control signal input to the control terminals of the first and second light emission control transistors in the m-th row of sub-pixels. During one frame of display time, assuming the exposure start time of the image acquisition device coincides with the start time of the high level of Eout1, then within the shutter duration, the sub-pixels in rows 1 to 4 have completed the reset and write phases, and the light emission control signals Eout1 to Eout4 have completed the "off-on" process, causing the light emission elements in the sub-pixels in rows 1 to 4 to start emitting light again; the sub-pixels in rows 5 to 7 are undergoing the reset and write phase after the light emission control signal is turned off, and the light emission elements are still in an off state; the light emission elements in the sub-pixels in rows 8 to m are always in the light emission phase. Because the light emission control signals received by each row of sub-pixels during the exposure period of the image acquisition device are not switched on and off at the same time, the light emission time of the light-emitting element is also different. As a result, the image acquisition device will capture the difference in brightness of the display panel, resulting in a scanning pattern.

[0084] To address the aforementioned problems, this disclosure provides a driving method for a display panel, as shown in FIG6. The driving method may include the following steps:

[0085] Step S100: Determine the current shutter speed of the image acquisition device and the target refresh rate of the display panel; the image acquisition device is used to acquire the image displayed on the display panel.

[0086] For example, when the display panel is used in scenarios such as physical shooting or virtual shooting, and an image acquisition device is used to capture the virtual scene image displayed on the display panel, the current shutter speed of the image acquisition device is obtained.

[0087] For example, the current shutter speed of the image acquisition device can be obtained in the following two ways:

[0088] Method 1: You can manually input the current shutter speed of the image acquisition device on the user interface of the display panel. For example, you can directly input the current shutter speed of the image acquisition device on the user interface of the display panel, or select the current shutter speed of the image acquisition device through the options on the user interface.

[0089] Method 2: Data interaction can be performed between the display panel and the image acquisition device to obtain the current shutter speed of the image acquisition device. For example, the display panel can obtain the shutter speed of the image acquisition device via wired or wireless means. Users can manually report the current shutter speed of the image acquisition device to the display panel, or the display panel can periodically obtain the current shutter speed of the image acquisition device, or the image acquisition device can automatically report its current shutter speed to the display panel according to a set period.

[0090] In practical applications, the display panel can operate at multiple refresh rates, such as 60Hz, 90Hz and 120Hz.

[0091] When the display panel operates at multiple refresh rates, the method for determining the target refresh rate of the display panel, as shown in Figure 7, may include the following steps:

[0092] Step S11: Receive the current shutter speed t reported by the image acquisition device according to the set period.

[0093] Step S12: Obtain the current refresh rate f of the display panel, and determine whether 1 / ft is a positive integer. If yes, proceed to step S16; otherwise, proceed to step S13.

[0094] Step S13: Determine whether the display panel is working at multiple refresh rates. If yes, proceed to step S14; otherwise, the process ends.

[0095] For example, if the reciprocal of the current refresh rate divided by the current shutter duration is not a positive integer, and the display panel is not operating at multiple refresh rates, a light emission control signal can be output to each row of sub-pixels of the display panel according to relevant technical methods.

[0096] Step S14: Obtain the refresh frequencies other than the current refresh frequency among the multiple refresh frequencies of the display panel, calculate the reciprocal of the remaining refresh frequencies divided by the current shutter duration, and select the corresponding refresh frequency with a positive integer value as the candidate refresh frequency.

[0097] Step S15: Determine the target refresh frequency based on the alternative refresh frequencies.

[0098] For example, there may be multiple alternative refresh frequencies. When there are multiple alternative refresh frequencies, one can be selected as the target refresh frequency, or the refresh frequency with the largest refresh frequency value can be selected as the target refresh frequency, or the refresh frequency with the smallest refresh frequency value can be selected as the target refresh frequency.

[0099] Step S16: Use the current refresh rate as the target refresh rate.

[0100] Step S200: Based on the current shutter speed and target refresh rate, adjust the light emission control signal output by the light emission driving circuit to each row of sub-pixels. Control the pixel circuit to work through the adjusted light emission control signal so that the cumulative light emission time of the light emission element in each row of sub-pixels is the same within the current shutter speed.

[0101] It should be noted that the cumulative duration of light emission of the light-emitting elements in each row of sub-pixels is the same within the current shutter speed. This can be understood as the duration of the effective level of the light emission control signal input to each row of sub-pixels being the same within the current shutter speed.

[0102] The driving method for the display panel provided in this embodiment of the present disclosure can make the cumulative light emission duration of the light-emitting elements in each row of sub-pixels the same during the exposure of the image acquisition device by adjusting the light emission control signal output to each row of sub-pixels. This can make the brightness difference of the entire display area of ​​the display panel consistent, thereby avoiding the appearance of scanning lines on the acquired image when the image is acquired by the image acquisition device.

[0103] In some embodiments of this disclosure, the reciprocal of the target refresh rate divided by the current shutter duration is a positive integer.

[0104] For example, if the target refresh rate f is 60Hz and the current shutter speed t is 333.34us, then 1 / ft is 50.

[0105] In some embodiments of this disclosure, as shown in FIG4, the pixel circuit 101 includes: a first light-emitting control transistor M5, a driving circuit M3, and a second light-emitting control transistor M6. The first light-emitting control transistor M5, the driving circuit M3, and the second light-emitting control transistor M6 are connected between the first power supply terminal VDD and the light-emitting element 102. The light-emitting driving circuit 200 is connected to the control terminals of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 in each row of sub-pixels 100. Based on this, step S200, adjusting the light-emitting control signal output by the light-emitting driving circuit to each row of sub-pixels, may include the following steps: adjusting the light-emitting control signal EM output by the light-emitting driving circuit to each row of sub-pixels to a periodic signal with alternating active and inactive levels, and making the current shutter duration a positive integer multiple of the period of the light-emitting control signal.

[0106] It should be noted that, as shown in Figure 3, the light emission control signal output by the light emission driving circuit to each row of sub-pixels has only one invalid level before adjustment within one frame display time.

[0107] For example, as shown in Figure 8, ESTV represents the light emission control trigger signal, Eout1 represents the light emission control signal output by the light emission driving circuit to the control terminals of the first and second light emission control transistors in the first row of sub-pixels, Eout2 represents the light emission control signal output by the light emission driving circuit to the control terminals of the first and second light emission control transistors in the second row of sub-pixels, and so on, Eoutm represents the light emission control signal output by the light emission driving circuit to the control terminals of the first and second light emission control transistors in the m-th row of sub-pixels. The period of the light emission control signal can be equal to the current shutter speed. The light emission control signal can include one active level and one inactive level within each period. The duration of a single active level and a single inactive level of the light emission control signal can be the same, i.e., the duty cycle of the light emission control signal is 50%. Of course, the duration of a single active level and a single inactive level of the light emission control signal can also be different.

[0108] For example, the current shutter speed is t, and the period of the light emission control signal is T, where t equals mT, and m can be a natural number such as 1, 2, or 3. For example, if the current shutter speed t is 333.34 μs, and m is 1, then the period T of the light emission control signal is 333.4 μs; if m is 2, then the period T of the light emission control signal is 166.7 μs.

[0109] In some embodiments of this disclosure, the period of the light emission control signal is 2h*x, where x is an integer greater than or equal to 2, and h is the scanning time required for a row of sub-pixel input data signals.

[0110] For example, if h is 23.81 μs and x is 7, then the period T of the light emission control signal is 333.34 μs.

[0111] For example, taking the light-emitting driving circuit shown in Figure 9 and the clock signals ck and cb output to the light-emitting driving circuit with a period of 2h as an example, the light-emitting driving circuit can output the light-emitting control signal normally when the period of the light-emitting control signal is greater than or equal to 4h.

[0112] In some embodiments of this disclosure, the duration of the invalid level in each cycle of the light emission control signal is greater than or equal to 2 hours.

[0113] In some embodiments of this disclosure, a target light emission control trigger signal ESTV is output to the light emission driving circuit 200. The target light emission control trigger signal ESTV is a periodic signal that alternates between valid and invalid levels.

[0114] For example, as shown in Figure 8, the period of the target illumination control trigger signal can be the same as the current shutter speed, and each period can include one active level and one inactive level. For example, the duration of a single active level and a single inactive level of the target illumination control trigger signal can be the same, that is, the duty cycle of the target illumination control trigger signal is 50%. Of course, the duration of a single active level and a single inactive level of the target illumination control trigger signal can also be different.

[0115] For example, as shown in Figure 10, the timing controller 300 adjusts the period of the light emission control trigger signal to output the target light emission control trigger signal ESTV to the light emission driving circuit 200. The light emission driving circuit 200 outputs light emission control signals Eout1 to Eoutm with the same period as the target light emission control trigger signal ESTV to the corresponding sub-pixel rows through each shift register unit, as shown in Figure 8.

[0116] For example, if the current shutter duration is 6 hours, the duty cycle of the target light emission control trigger signal ESTV is 50%, and the duration of a single invalid level is 3 hours, then the target light emission control trigger signal ESTV output by the timing controller 300 to the light emission driving circuit 200 is a periodic signal with a period duration of 6 hours and a duration of a single valid level of 3 hours. At this time, the output of the light emission control signals Eout at each level is as shown in Figure 8. The output waveforms of Eout1 and Eout7 are consistent, and the output waveforms of Eout2 and Eout8 are consistent. That is, the Eout output every 6 rows is consistent, which can make the first row of sub-pixels and the last row of sub-pixels of the display panel, as well as the frame start of the next display frame and the frame end of the previous display frame in two adjacent display frames, connect without producing other display abnormalities.

[0117] In some embodiments of this disclosure, for the upper and lower row sub-pixels in two adjacent rows of sub-pixels, the light emission control signal output to the lower row sub-pixel is delayed by a first set phase difference compared to the light emission control signal output to the upper row sub-pixel; the first set phase difference is the scanning time required for the input data signal of a row of sub-pixels.

[0118] For example, as shown in FIG8, within the current shutter duration, the start time of the invalid level (e.g., high level) of the light emission control signal Eout2 input to the second row of sub-pixels is delayed by 1 hour compared to the start time of the invalid level of the light emission control signal Eout1 input to the first row of sub-pixels, the start time of the invalid level (e.g., high level) of the light emission control signal Eout3 input to the third row of sub-pixels is delayed by 1 hour compared to the start time of the invalid level of the light emission control signal Eout2 input to the second row of sub-pixels, and so on, the start time of the invalid level of the light emission control signal Eoutm input to the m-th row of sub-pixels is delayed by 1 hour compared to the start time of the invalid level of the light emission control signal Eoutm-1 input to the (m-1)-th row of sub-pixels.

[0119] This application embodiment also provides another pixel circuit. For example, as shown in FIG11, pixel circuit 101 may include: a first light-emitting control transistor M5, a driving transistor M3, and a second light-emitting control transistor M6. The pixel circuit shown in FIG11 is a variation of the pixel circuit shown in FIG1. ​​The similarities will not be described again. The difference is that the control terminal of the second light-emitting control transistor M6 is connected to the global light-emitting control signal terminal and is used to receive the global light-emitting control signal provided by the global light-emitting control signal terminal. Based on this, the above step S200, which adjusts the light-emitting control signal output by the light-emitting driving circuit to each row of sub-pixels, may include the following steps: controlling the global light-emitting control signal to be a periodic signal with alternating valid and invalid levels, and the light-emitting control signal output by the light-emitting driving circuit to each row of sub-pixels having a valid level and an invalid level; wherein, the current shutter duration is a positive integer multiple of the period of the global light-emitting control signal, and during the duration of the global light-emitting control signal being at a valid level, the light-emitting control signal output by the light-emitting driving circuit to each row of sub-pixels is at a valid level.

[0120] For example, as shown in FIG11, the global light emission control signal HF can be a signal with a fixed duty cycle that is mesh-like in the plane, and the second light emission control transistor M6 in each pixel circuit 200 is connected to the global light emission control signal HF through a gate line.

[0121] For example, as shown in Figure 12, HF represents the global light emission control signal input to the control terminal of the second light emission control transistor in each row of sub-pixels, Eout1 represents the light emission control signal input to the control terminal of the first light emission control transistor in the first row of sub-pixels, Eout2 represents the light emission control signal input to the control terminal of the first light emission control transistor in the second row of sub-pixels, ..., Eoutm represents the light emission control signal input to the control terminal of the first light emission control transistor in the m-th row of sub-pixels. The light emission control signals Eout1 to Eoutm have one invalid level (e.g., a high level) and at least one valid level within one frame of display time. For example, the light emission control signal Eout1 input to the first row of sub-pixels has one valid level and one invalid level, while Eout2 to Eoutm each have two valid levels and one invalid level. That is, the light emission control signal input to the first light emission control transistor is not adjusted in any way; the method in related technologies is still used, and only the light emission control signal input to the second light emission control transistor is adjusted.

[0122] For example, as shown in Figure 12, the period of the global illumination control signal can be equal to the current shutter duration. The global illumination control signal can include one active level and one inactive level within each period. Each active level of the global illumination control signal overlaps with the active levels of the illumination control signals input to each row of sub-pixels for a certain duration.

[0123] For example, as shown in FIG11, the first light-emitting control transistor M4, the driving circuit M5, and the second light-emitting control transistor M6 are P-type transistors. When the light-emitting control signal received by the first light-emitting control transistor M5 is low, the signal of the Dnode node coupled to the driving circuit M3 is low, and the global light-emitting control signal received by the second light-emitting control transistor is low, the first light-emitting control transistor M5, the driving circuit M3, and the second light-emitting control transistor M6 are simultaneously turned on, providing the first power supply voltage of the first power supply terminal VDD to the light-emitting element 102, and controlling the light-emitting element 102 to emit light.

[0124] For example, if the current refresh rate of the display panel is 60Hz, the current shutter speed of the image acquisition device is 333.34µs, and the scanning time required for one line of sub-pixel input data signal is 23.81µs, then the period of the global illumination control signal HF can be (333.34 / n)µs, where n can be a natural number such as 1, 2, 3, or 4. When n is 1, it means that one global illumination control signal cycle can be executed within one current shutter speed; when n is 2, it means that two global illumination control signal cycles can be executed within one current shutter speed.

[0125] The display panel driving method provided in this embodiment adjusts the light emission control signal of the second light emission control transistor output to each row of pixel circuits to a global light emission control signal, so that the light emission elements in each row of sub-pixels can emit light at least once simultaneously during the exposure of the image acquisition device. This makes the brightness difference of the entire display area of ​​the display panel consistent, thereby avoiding the appearance of scanning lines on the acquired image when the image is acquired by the image acquisition device.

[0126] In some embodiments of this disclosure, during the duration of the global light emission control signal being at an invalid level, the light emission control signal output by the light emission driving circuit to one or more rows of sub-pixels is at an invalid level.

[0127] For example, as shown in Figure 12, during the current shutter duration of the image acquisition device, Eout1 and Eout2 have invalid levels during the duration of the invalid level (high level) of the global illumination control signal HF; during the duration of the second invalid level (high level) of the global illumination control signal HF, Eout3 and Eout4 have invalid levels; that is, during the duration of the invalid level of each cycle of the global illumination control signal, there are two adjacent rows of Eout with invalid levels.

[0128] In some embodiments of this disclosure, during the duration of the global light emission control signal being at an invalid level, when the light emission control signal output by the light emission driving circuit to the multi-row sub-pixels is at an invalid level, the invalid level of the light emission control signal of the multi-row sub-pixels is sequentially delayed by a second predetermined phase difference.

[0129] For example, as shown in FIG12, the second set phase difference can be the sum of the duration of a single invalid level of the light emission control signal and the duration of a single valid level of the global light emission control signal. Of course, the second set phase difference can also be greater than the sum of the duration of an invalid level of the light emission control signal and the duration of a valid level of the global light emission control signal.

[0130] For example, as shown in Figure 9, the shift register unit of the light-emitting driving circuit and the signal timing diagram shown in Figure 12, between two adjacent effective levels of the global light-emitting control signal, the waveforms of the ck and cb signals input to the shift register unit can be controlled. For example, as shown in Figure 13, the light-emitting control signal output by the light-emitting driving circuit 200 can be interspersed between the global light-emitting control signals. For example, after every two rows of sub-pixels input an invalid level of the light-emitting control signal, an effective level of the global light-emitting control signal is output to each row of sub-pixels. This ensures that the light-emitting control signal input to the sub-pixels does not affect the global light-emitting control signal.

[0131] In some embodiments of this disclosure, the invalid levels of the light emission control signals of any two rows of sub-pixels in the light emission control signals of the multi-row sub-pixels do not overlap in duration.

[0132] For example, as shown in Figure 12, the invalid level (high level) of the light emission control signal of any row of sub-pixels does not overlap with the invalid level of the light emission control signal of other rows of sub-pixels.

[0133] In some embodiments of this disclosure, as shown in FIG14, the pixel circuit 101 further includes a first reset transistor M1, a second reset transistor M7, and scan transistors M2 and M4. The first reset transistor M1 is connected between the second power supply terminal Vinit and the first node Dnode. The second reset transistor M7 is connected between the second power supply terminal VSS and the light-emitting element 102. The scan transistors M2 and M4 are connected between the data signal terminal Data and the first node Dnode.

[0134] For each row of sub-pixels, the control terminal of the first reset transistor M1 is used to receive the first reset control signal rst_a, the control terminal of the second reset transistor M7 is used to receive the second reset control signal rst_b, and the control terminals of the scan transistors M2 and M4 are used to receive the scan control signal gate.

[0135] The driving method may also include the following steps:

[0136] During the duration when the light emission control signal is at an invalid level, the first reset control signal, the second reset control signal, and the scan control signal output to each row of sub-pixels sequentially become valid.

[0137] For example, as shown in Figure 14, the first reset transistor M1 is an N-type transistor, and the other transistors in the pixel circuit are P-type transistors. As shown in the signal timing diagram in Figure 15, Eout represents the light emission control signal, rst_a represents the first reset control signal, rst_b represents the second reset control signal, gate represents the scan control signal, and HF represents the global light emission control signal. The duration of a single invalid level of the light emission control signal Eout1 can be equal to the sum of the durations of a single valid level of the first reset control signal rst_a1, the second reset control signal rst_b1, and the scan control signal gate1. That is, the rising edge of the first reset control signal rst_a1 is aligned with the rising edge of the light emission control signal Eout1, the falling edge of the second reset control signal rst_b1 is aligned with the falling edge of the first reset control signal rst_a1, and the falling edge of the scan control signal gate1 is aligned with the rising edge of the second reset control signal rst_b1.

[0138] In some embodiments of this disclosure, during the duration of the light emission control signal being at an effective level, the second reset control signal output to each row of sub-pixels sequentially appears at multiple effective levels at intervals, and when the global light emission control signal appears at an invalid level, the second reset control signal output to each row of sub-pixels appears at an invalid level.

[0139] For example, as shown in Figure 15, during the effective duration of the light emission control signal Eout1 (e.g., low level), the second reset control signal rst_b1 has multiple effective levels; the invalid level of the global light emission control signal HF and the invalid level of the second reset control signal input to each row of sub-pixels have overlapping durations.

[0140] It should be noted that by resetting the anode of the light-emitting element before each emission of light from the light-emitting element in each row of sub-pixels, the uniformity of the display panel can be guaranteed.

[0141] Transistors that typically use metal-oxide-semiconductor (MODS) materials as their active layers generally have lower leakage current. Therefore, to reduce leakage current, in some embodiments of this disclosure, the active layer material of each transistor in the first reset transistor M1 of the pixel circuit can be set to a MODS material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other MODS materials can also be used, and this is not limited here. This allows the transistors to be set as oxide thin-film transistors, thereby reducing the leakage current of the pixel circuit and preventing the potential difference between the start and end of the frame caused by leakage current in the first reset transistor at the first node of the pixel circuit.

[0142] In some embodiments of this disclosure, the display panel has multiple refresh rates.

[0143] As shown in Figure 16, determining the target refresh rate of the display panel may include the following steps:

[0144] Step S21: Obtain the current refresh rate of the display panel; the current refresh rate is one of multiple refresh rates.

[0145] Step S22: Determine whether the reciprocal of the current refresh rate divided by the current shutter speed is a positive integer. If yes, proceed to step S23; otherwise, proceed to step S24.

[0146] Step S23: Use the current refresh rate as the target refresh rate.

[0147] Step S24: Determine a new refresh rate as the target refresh rate from multiple refresh rates; wherein the reciprocal of the new refresh rate divided by the current shutter speed is a positive integer.

[0148] In some embodiments of this disclosure, the refresh frequencies other than the current refresh frequency among a plurality of refresh frequencies have a plurality of alternative refresh frequencies, and the reciprocal of each alternative refresh frequency divided by the current shutter duration is a positive integer.

[0149] The new refresh rate is any one of the multiple alternative refresh rates, or the maximum value of the multiple alternative refresh rates, or the minimum value of the multiple alternative refresh rates.

[0150] For example, if the display panel has multiple refresh rates of 60, 120, 180, and 240Hz, and the current shutter speed is 333.34µs, then the reciprocal of the refresh rate divided by the current shutter speed are 50, 25, 16.67, and 12.5, respectively. 60 and 120Hz are then selected as alternative refresh rates. Either the alternative refresh rates of 60 and 120Hz can be selected as the target refresh rate. Alternatively, the refresh rate with the highest value of 120Hz can be selected as the target refresh rate, or the refresh rate with the lowest value of 60Hz can be selected as the target refresh rate.

[0151] This disclosure also provides a display device, as shown in FIG17, including a display panel DP and a timing controller 300.

[0152] The display panel DP includes a plurality of sub-pixels 100 arranged in an array and a light-emitting driving circuit 200 electrically connected to each row of sub-pixels 100. Sub-pixels 100 include pixel circuits 101 and light-emitting elements 102 connected to the pixel circuits 101.

[0153] The timing controller 300 is connected to the light-emitting drive circuit 200. The timing controller 300 is used to determine the current shutter length of the image acquisition device and the target refresh rate of the display panel DP. According to the current shutter length and the target refresh rate, the light-emitting control signal EM output by the light-emitting drive circuit 200 to each row of sub-pixels 100 is adjusted. The adjusted light-emitting control signal EM controls the pixel circuit 101 to work, so as to control the cumulative light-emitting duration of the light-emitting element 102 in each row of sub-pixels 100 to be the same within the current shutter length. The image acquisition device is used to acquire the image displayed on the display panel.

[0154] In some embodiments of this disclosure, the display panel DP further includes a global illumination control signal terminal 400, and the timing controller 300 is also connected to the global illumination control signal terminal 400 for outputting a global illumination control signal HF to the global illumination control signal terminal 400.

[0155] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0156] This disclosure provides a driving method and display device for a display panel. By adjusting the light emission control signal output to each row of sub-pixels, the cumulative light emission duration of the light-emitting elements in each row of sub-pixels during the exposure of the image acquisition device can be made the brightness difference of the entire display area of ​​the display panel is consistent. Therefore, when the image displayed on the display panel is acquired by the image acquisition device, no scanning lines will appear on the acquired image.

[0157] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0158] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0159] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0160] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0161] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0162] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A method for driving a display panel, wherein, The display panel includes a plurality of sub-pixels arranged in an array and a light-emitting driving circuit electrically connected to each row of sub-pixels. The sub-pixel includes a pixel circuit and a light-emitting element connected to the pixel circuit. The driving method includes: Determine the current shutter speed of the image acquisition device and the target refresh rate of the display panel; the image acquisition device is used to acquire the image displayed on the display panel. Based on the current shutter speed and the target refresh rate, the light emission control signal output by the light emission driving circuit to each row of sub-pixels is adjusted. The adjusted light emission control signal controls the operation of the pixel circuit so as to control the cumulative light emission duration of the light emission elements in each row of sub-pixels to be the same within the current shutter speed.

2. The driving method as described in claim 1, wherein, The reciprocal of the target refresh rate divided by the current shutter duration is a positive integer.

3. The driving method as described in claim 2, wherein, The pixel circuit includes: a first light-emitting control transistor, a driving circuit, and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving circuit, and the second light-emitting control transistor are connected between a first power supply terminal and the light-emitting element; The light-emitting driving circuit is connected to the control terminal of the first light-emitting control transistor and the control terminal of the second light-emitting control transistor in each row of sub-pixels. The adjustment of the light emission control signal output by the light emission driving circuit to each row of sub-pixels includes: The light emission control signal output by the light emission driving circuit to each row of sub-pixels is adjusted to a periodic signal with alternating active and inactive levels, and the current shutter duration is made a positive integer multiple of the period of the light emission control signal.

4. The driving method as described in claim 3, wherein, The cycle duration is 2h*x, where x is an integer greater than or equal to 2, and h is the scanning time required for one row of sub-pixel input data signals.

5. The driving method as described in claim 4, wherein, The duration of the invalid level in each cycle of the light emission control signal is greater than or equal to 2 hours.

6. The driving method as described in claim 5, wherein, The target light emission control trigger signal is output to the light emission driving circuit. The target light emission control trigger signal is a periodic signal that alternates between valid and invalid levels.

7. The driving method as described in claim 6, wherein, For the upper and lower row sub-pixels in two adjacent rows of sub-pixels, the light emission control signal output to the lower row sub-pixel is delayed by a first set phase difference compared to the light emission control signal output to the upper row sub-pixel; the first set phase difference is the scanning time required for the input data signal of a row of sub-pixels.

8. The driving method as described in claim 2, wherein, The pixel circuit includes: a first light-emitting control transistor, a driving circuit, and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving circuit, and the second light-emitting control transistor are connected between a first power supply terminal and the light-emitting element; The light-emitting driving circuit is connected to the control terminal of the first light-emitting control transistor in each row of sub-pixels; The control terminal of the second light-emitting control transistor in each row of sub-pixels is used to receive the global light-emitting control signal; The adjustment of the light emission control signal output by the light emission driving circuit to each row of sub-pixels includes: The global illumination control signal is controlled as a periodic signal with alternating active and inactive levels. The illumination control signal output by the illumination driving circuit to each row of sub-pixels has an active level and an inactive level. The current shutter duration is a positive integer multiple of the period of the global illumination control signal, and during the duration of the global illumination control signal being active, the illumination control signal output by the illumination driving circuit to each row of sub-pixels is always active.

9. The driving method as described in claim 8, wherein during the duration during which the global light emission control signal is at an invalid level, the light emission control signal output by the light emission driving circuit to one or more rows of sub-pixels is at an invalid level.

10. In the driving method as described in claim 9, during the duration of the global light emission control signal being at an invalid level, when the light emission control signal output by the light emission driving circuit to the multi-row sub-pixels is at an invalid level, the invalid level of the light emission control signal of the multi-row sub-pixels is sequentially delayed by a second predetermined phase difference.

11. The driving method as described in claim 10, wherein the invalid levels of the light emission control signals of any two rows of sub-pixels in the multi-row sub-pixel light emission control signals do not overlap for any duration.

12. The driving method as described in claim 11, wherein, The pixel circuit further includes a first reset transistor, a second reset transistor, and a scan transistor. The first reset transistor is connected between the second power supply terminal and the first node, the second reset transistor is connected between the second power supply terminal and the light-emitting element, and the scan transistor is connected between the data signal terminal and the first node. For each row of sub-pixels, the control terminal of the first reset transistor is used to receive a first reset control signal, the control terminal of the second reset transistor is used to receive a second reset control signal, and the control terminal of the scan transistor is used to receive a scan control signal. The driving method further includes: During the duration when the light emission control signal is at an invalid level, the first reset control signal, the second reset control signal, and the scan control signal output to each row of sub-pixels sequentially become valid.

13. The driving method as described in claim 12, wherein, During the duration of the effective level of the light emission control signal, the second reset control signal output to each row of sub-pixels sequentially appears at multiple effective levels. Furthermore, when the global light emission control signal appears at an invalid level, the second reset control signal output to each row of sub-pixels appears at an invalid level.

14. The driving method according to any one of claims 2-13, wherein, The display panel has multiple refresh rates; Determining the target refresh rate of the display panel includes: Obtain the current refresh rate of the display panel; the current refresh rate is one of the plurality of refresh rates; When the reciprocal of the current refresh rate divided by the current shutter length is a positive integer, the current refresh rate is taken as the target refresh rate; When the reciprocal of the current refresh rate divided by the current shutter length is not a positive integer, a new refresh rate is determined from the plurality of refresh rates as the target refresh rate; wherein the reciprocal of the new refresh rate divided by the current shutter length is a positive integer.

15. The driving method as described in claim 14, wherein, The refresh frequencies other than the current refresh frequency have multiple candidate refresh frequencies, and the reciprocal of each candidate refresh frequency divided by the current shutter duration is a positive integer. The new refresh frequency is any one of the plurality of alternative refresh frequencies, or the maximum value of the plurality of alternative refresh frequencies, or the minimum value of the plurality of alternative refresh frequencies.

16. A display device, wherein, include: The display panel includes a plurality of sub-pixels arranged in an array and a light-emitting driving circuit electrically connected to each row of sub-pixels. The sub-pixels include a pixel circuit and a light-emitting element connected to the pixel circuit. A timing controller, connected to the light-emitting driving circuit, is used to determine the current shutter duration of the image acquisition device and the target refresh rate of the display panel; Based on the current shutter speed and the target refresh rate, the light emission control signal output by the light emission driving circuit to each row of sub-pixels is adjusted. The adjusted light emission control signal controls the operation of the pixel circuit to ensure that the cumulative light emission duration of the light emission elements in each row of sub-pixels is the same within the current shutter speed. The image acquisition device is used to acquire the image displayed on the display panel.

17. The display device as claimed in claim 16, wherein, The pixel circuit includes: a first light-emitting control transistor, a driving circuit, and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving circuit, and the second light-emitting control transistor are connected between a first power supply terminal and the light-emitting element; The light-emitting driving circuit is connected to the control terminal of the first light-emitting control transistor and the control terminal of the second light-emitting control transistor in each row of sub-pixels.

18. The display device as claimed in claim 16, wherein, The pixel circuit includes: a first light-emitting control transistor, a driving circuit, and a second light-emitting control transistor, wherein the first light-emitting control transistor, the driving circuit, and the second light-emitting control transistor are connected between a first power supply terminal and the light-emitting element; The light-emitting driving circuit is connected to the control terminal of the first light-emitting control transistor in each row of sub-pixels; The display panel also includes a global light emission control signal terminal, and a second light emission control terminal in each row of sub-pixels. The control terminal of the transistor is connected to the global light emission control signal terminal, and the timing controller is also connected to the global light emission control signal terminal to output a global light emission control signal to the global light emission control signal terminal.

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