Array substrate, array substrate mother substrate and display apparatus

Abstract

An array substrate, an array substrate mother substrate and a display apparatus. The array substrate comprises a display region and a non-display region, the array substrate having a first edge line and a second edge line arranged opposite to each other in a first direction. The array substrate comprises: a base substrate; a plurality of connection pads (CT Pads), which are provided on one side of the base substrate, located in the non-display region and sequentially arranged in the first direction, the plurality of connection pads (CT Pads) forming a first pad group (CT PadZ1) and a second pad group (CT PadZ2), an input level of the first pad group (CT PadZ1) being different from an input level of the second pad group (CT PadZ2), and the number of the connection pads (CT Pads) comprised in the first pad group (CT PadZ1) being greater than the number of the connection pads (CT Pads) comprised in the second pad group (CT PadZ2); a plurality of display lines (XSLs), which are provided on one side of the base substrate and located in the non-display region, the display lines (XSLs) being connected at one end to the connection pads (CT Pads); an insulating layer group, which is provided on the side of the connection pads (CT Pads) and the display lines (XSLs) facing away from the base substrate; and a plurality of connection portions (LJBs), which are provided on the side of the insulating layer group facing away from the base substrate and are located in the non-display region, the connection portions (LJBs) being connected at one end to the connection pads (CT Pads). The first pad group (CT PadZ1) and the second pad group (CT PadZ2) are arranged closer to the first edge line than to the second edge line, the first pad group (CT PadZ1) being arranged on the side of the second pad group (CT PadZ2) close to the first edge line. At least some of the display lines (XSLs) extend in the first direction towards the side away from the first edge line. The orthographic projecti

Description

Array substrate, array substrate motherboard and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate, an array substrate motherboard, and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are widely used in various display fields, such as homes, public places, offices, and personal electronic products. After the array substrate fabrication process is completed, the thin-film transistors and other structures formed on the array substrate motherboard need to be inspected and tested; this is generally called array testing. Array testing can detect defects in the early stages, preventing the continued production of products with existing problems in subsequent processes.

[0003] Array testing typically involves forming test traces (AT traces) on the array substrate motherboard. One end of the test trace is connected to the test terminal (AT pad), and the other end is connected to the connection pad (CT pad) of each array substrate on the array substrate motherboard. The connection pad is connected to the gate lines and data lines in the display area, thereby realizing the connection between the test terminal and the sub-pixels of the array substrate and detecting the structure of the sub-pixels of the array substrate.

[0004] However, in the current array substrate, high and low level signals in the connecting pads are prone to short circuit failure.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0006] Summary of the Invention

[0007] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate, an array substrate motherboard, and a display device.

[0008] According to one aspect of this disclosure, an array substrate is provided, including a display area and a non-display area, the array substrate having a first edge line and a second edge line disposed opposite to each other in a first direction, wherein the array substrate includes:

[0009] Substrate;

[0010] Multiple connecting pads are disposed on one side of the substrate and located in the non-display area, and are arranged sequentially along the first direction; the multiple connecting pads form a first pad group and a second pad group, the input level of the first pad group is different from the input level of the second pad group, and the number of connecting pads included in the first pad group is greater than the number of connecting pads included in the second pad group.

[0011] Multiple display traces are disposed on one side of the substrate and located in the non-display area, with one end of each display trace connected to the connecting pad.

[0012] An insulating layer assembly is disposed on the side of the connecting pad and the display trace away from the substrate.

[0013] Multiple connecting portions are provided on the side of the insulating layer group away from the substrate and located in the non-display area, with one end of each connecting portion connected to the connecting pad.

[0014] Wherein, the first pad group and the second pad group are disposed closer to the first edge line than the second edge line, and the first pad group is disposed on the side of the second pad group closer to the first edge line. At least a portion of the display traces extend away from the first edge line along the first direction. At least a portion of the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection of the display traces extending from the side closer to the first edge line on the substrate.

[0015] And / or, the first pad group and the second pad group are disposed closer to the second edge line than the first edge line, and the first pad group is disposed on the side of the second pad group closer to the second edge line, at least a portion of the display traces extend away from the second edge line along the first direction, and at least a portion of the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection of the display traces extending from the side closer to the second edge line on the substrate.

[0016] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0017] Multiple test traces are located in the non-display area and on the side of the connecting pad away from the display area. The multiple test traces extend along the first direction, with at least some of the test traces introduced from the first edge line and / or at least some of the test traces introduced from the second edge line. The connecting pad near the first edge line is connected to the test trace introduced from the first edge line, and the connecting pad near the second edge line is connected to the test trace introduced from the second edge line.

[0018] In an exemplary embodiment of this disclosure, multiple test traces are sequentially connected to multiple connecting pads; the tail end of each test trace is located on the side of the connecting pad connected to it that is away from the display area; the spacing between each test trace introduced from the first edge line and each connecting pad in the second direction decreases as the spacing between the connecting pad and the first edge line in the first direction increases, and / or, the spacing between each test trace introduced from the second edge line and each connecting pad in the second direction decreases as the spacing between the connecting pad and the second edge line in the first direction increases; the second direction intersects the first direction.

[0019] In one exemplary embodiment of this disclosure, the ends of the multiple test traces that are connected to the corresponding connecting pads are arranged collinearly.

[0020] In an exemplary embodiment of this disclosure, the connecting portion is connected between the connecting pad and the test trace, and the end of the connecting portion connected to the test trace is a first end. The edge lines of the first ends of the plurality of connecting portions extending along the first direction are collinear.

[0021] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0022] A driving circuit layer assembly is disposed on one side of the substrate, and the driving circuit layer assembly includes the connection pads and the test traces disposed at intervals.

[0023] A first electrode layer is disposed on the side of the driving circuit layer group opposite to the substrate, and the first electrode layer includes a first electrode;

[0024] A protective layer is disposed on the side of the first electrode layer opposite to the substrate.

[0025] The second electrode layer is disposed on the side of the protective layer opposite to the substrate, and the second electrode layer includes a second electrode and the connection portion.

[0026] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0027] Multiple first support portions are arranged in an array on the side of the protective layer away from the substrate and on the side of the multiple connecting portions away from the display area. The orthographic projection of a portion of the first support portions on the substrate overlaps with the orthographic projection of the test traces on the substrate.

[0028] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0029] A driving circuit layer group is disposed on one side of the substrate; the driving circuit layer group includes the display traces and the connection pads, or, when the array substrate includes test traces, the driving circuit layer group includes the display traces, the connection pads and the test traces;

[0030] A first electrode layer is disposed on the side of the driving circuit layer group away from the substrate. The first electrode layer includes a first electrode and the connection portion. The other end of the connection portion is used to connect the test trace.

[0031] A protective layer is disposed on the side of the first electrode layer opposite to the substrate.

[0032] A second electrode layer is disposed on the side of the protective layer opposite to the substrate, and the second electrode layer includes a second electrode.

[0033] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0034] Multiple first support portions are arranged in an array on the side of the protective layer away from the substrate. The orthographic projection of a portion of the first support portions on the substrate overlaps with the orthographic projection of the connecting portion on the substrate, and the orthographic projection of a portion of the first support portions on the substrate overlaps with the orthographic projection of the test trace on the substrate.

[0035] In one exemplary embodiment of this disclosure, the driving circuit layer group includes:

[0036] A gate layer is disposed on one side of the substrate. The gate layer includes the connection pad and the display trace, or the gate layer includes the display trace, the connection pad and the test trace.

[0037] A gate insulating layer is disposed on the side of the gate layer opposite to the substrate.

[0038] A source / drain layer is disposed on the side of the gate insulating layer opposite to the substrate. The source / drain layer includes a first auxiliary conductive portion, a second auxiliary conductive portion, and a third auxiliary conductive portion. The first auxiliary conductive portion is connected to the connection pad through a first via on the gate insulating layer. The second auxiliary conductive portion is connected to the display trace through a second via on the gate insulating layer. The third auxiliary conductive portion is connected to the test trace through a third via on the gate insulating layer.

[0039] A buffer layer is disposed on the side of the source / drain layer opposite to the substrate.

[0040] An organic layer is disposed on the side of the buffer layer opposite to the substrate, and the orthographic projection of the organic layer on the substrate covers the display traces.

[0041] In one exemplary embodiment of this disclosure, the connecting pad is located between the display trace and the test trace.

[0042] In one exemplary embodiment of this disclosure, the input level of the first pad group is higher than the input level of the second pad group.

[0043] In an exemplary embodiment of this disclosure, on the side near the first edge line, the first pad group includes a frame start signal connection pad and a plurality of clock signal connection pads arranged sequentially in a direction away from the first edge line, and the second pad group includes a gate drive low level connection pad and a low level signal arranged sequentially in a direction away from the first edge line.

[0044] And / or, on the side near the second edge line, the first pad group includes a frame start signal connection pad and a plurality of clock signal connection pads arranged sequentially in a direction away from the second edge line, and the second pad group includes a gate drive low level connection pad and a low level signal arranged sequentially in a direction away from the second edge line.

[0045] According to another aspect of this disclosure, an array substrate mother plate is provided, comprising:

[0046] The array substrate mother plate is provided with a cutting line, which divides the array substrate mother plate into multiple array substrates, wherein the array substrate is any of the array substrates described above; the cutting line includes:

[0047] The first cutting line extends along the first direction;

[0048] The second cutting line extends along the second direction;

[0049] Wherein, a first cutting line is provided between two adjacent array substrates in the second direction, and two second cutting lines are provided between two adjacent array substrates in the first direction; or, two first cutting lines are provided between two adjacent array substrates in the second direction, and one second cutting line is provided between two adjacent array substrates in the first direction.

[0050] According to another aspect of this disclosure, a display device is provided, comprising: an array substrate, which is the array substrate described in any of the preceding claims.

[0051] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0052] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0053] Figure 1 is a schematic diagram of the structure of a first example embodiment of the array substrate disclosed herein.

[0054] Figure 2 is a schematic diagram of the structure of a second exemplary embodiment of the array substrate disclosed herein.

[0055] Figure 3 is a cross-sectional view of the area shown in Figures 1 and 2.

[0056] Figure 4 is a schematic diagram of the specific structure of the part indicated by H in Figure 1.

[0057] Figure 5 is a schematic diagram of the specific structure of the part indicated by I in Figure 1.

[0058] Figure 6 is a schematic diagram of the structure after the first support part is added based on Figure 4.

[0059] Figure 7 is a schematic cross-sectional view of the section cut according to the MM section in Figure 6.

[0060] Figure 8 is a schematic cross-sectional view of the data binding side of a third exemplary embodiment of the array substrate of this disclosure.

[0061] Figure 9 is a schematic cross-sectional view of the data binding side of a fourth exemplary embodiment of the array substrate of this disclosure.

[0062] Figure 10 is a top view of the array substrate in Figure 9.

[0063] Figure 11 is a partial top view of the data binding side of another exemplary embodiment of the array substrate of this disclosure.

[0064] Figure 12 is a partial top view of the data binding side of another exemplary embodiment of the array substrate of this disclosure.

[0065] Figure 13 is a schematic diagram of the structure of the array substrate motherboard in the related technology.

[0066] Figure 14 is a schematic diagram of the structure after the array substrate mother plate in Figure 13 is cut to form the array substrate and polyimide (PI) liquid and sealing glue are applied.

[0067] Figure 15 is a schematic diagram of the structure of the first support portion and the second support portion provided in the non-display area after the array substrate and the color filter substrate of this disclosure are aligned.

[0068] Figure 16 is a schematic diagram of an example embodiment of the array substrate motherboard of this disclosure.

[0069] Figure 17 is a schematic diagram of another example embodiment of the array substrate motherboard of this disclosure.

[0070] Explanation of reference numerals in the attached figures:

[0071] 1. Substrate;

[0072] 2. Driver circuit layer group; 21. Gate layer; 211. Gate; 212. Gate line;

[0073] 22. Gate insulation layer; 221. First via; 222. Second via; 223. Third via;

[0074] 23. Active layer; 231. First conductive connection portion; 232. Channel portion; 233. Second conductive connection portion; 24. Source-drain layer; 241. Data line; 242. Source; 243. Drain; 244. First auxiliary conductive portion; 245. Second auxiliary conductive portion; 246. Third auxiliary conductive portion; 25. Buffer layer; 26. Organic layer;

[0075] 3. First electrode layer; 31. First electrode;

[0076] 4. Protective layer;

[0077] 5. Second electrode layer; 51. Second electrode;

[0078] 6. Sealing adhesive;

[0079] 10. Array substrate; 101. Groove; 20. Color filter substrate;

[0080] CT PadZ1, first pad group; CT PadZ2, second pad group; CT Pad, connecting pad; CT Pad1, first connecting pad; CT Pad2, second connecting pad; CT Pad3, third connecting pad; CT Pad4, fourth connecting pad; AT Pad, detection terminal;

[0081] ATL, Test Trace; ATL1, First Test Trace; ATL2, Second Test Trace; ATL21, First Section; ATL22, Second Section; ATL23, Third Section; ATL3, Third Test Trace; ATL31, Fourth Section; ATL32, Fifth Section; ATL33, Sixth Section; ATL34, Seventh Section; ATL35, Eighth Section; ATL4, Fourth Test Trace;

[0082] LJB, connecting part; LJB1, first connecting part; LJB2, second connecting part;

[0083] PSA, first support section; PSF, second support section;

[0084] XSL, display trace; XSL1, first display trace; XSL2, second display trace;

[0085] AA, Display area; NAA, Non-display area; DP, Data bonding side; DPO, Data bonding opposite side; GPL, Left side of gate signal output; GPR, Right side of gate signal output;

[0086] L1, first edge line; L2, second edge line;

[0087] CL, cutting line; CL1, first cutting line; CL2, second cutting line;

[0088] X, the first direction; Y, the second direction. Detailed Implementation

[0089] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0090] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0091] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0092] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0093] This disclosure provides an array substrate, as shown in Figures 1-12. The array substrate may include a display area AA and a non-display area NAA. The array substrate has a first edge line L1 and a second edge line L2 disposed opposite each other in a first direction X. The array substrate may also include a substrate 1, a plurality of connection pads CT Pads, a plurality of display traces XSL, an insulating layer group, and a plurality of connection portions LJB. The plurality of connection pads CT Pads are disposed on one side of the substrate 1, located in the non-display area NAA, and arranged sequentially along the first direction X. The plurality of connection pads CT Pads can form a first pad group CT Pad Z1 and a second pad group CT Pad Z2. The input level of the first pad group CT Pad Z1 is different from the input level of the second pad group CT Pad Z2. The number of connection pads CT Pads included in the first pad group CT Pad Z1 is greater than the number of connection pads CT Pads included in the second pad group CT Pad Z2. The number of Pads; multiple display traces XSL are disposed on one side of the substrate 1 and located in the non-display area NAA, with one end of the display traces XSL connected to the connecting pad CT Pad; an insulating layer group is disposed on the side of the connecting pad CT Pad and the display traces XSL away from the substrate 1; multiple connecting portions LJB are disposed on the side of the insulating layer group away from the substrate 1 and located in the non-display area NAA, with one end of the connecting portion LJB connected to the connecting pad CT Pad; the first pad group CT Pad Z1 and the second pad group CT Pad Z2 are disposed closer to the first edge line L1 than the second edge line L2, and the first pad group CT Pad Z1 is disposed on the second pad group CT Pad Z2. PadZ2 is located near the first edge line L1, and at least a portion of the display trace XSL extends along the first direction X toward the side away from the first edge line L1. At least a portion of the connection portion LJB's orthographic projection on the substrate 1 overlaps with the orthographic projection of the display trace XSL extending from its side near the first edge line L1 on the substrate 1. And / or, the first pad group CT PadZ1 and the second pad group CT PadZ2 are disposed closer to the second edge line L2 than the first edge line L1, and the first pad group CT PadZ1 is disposed on the side of the second pad group CT PadZ2 near the second edge line L2. At least a portion of the display trace XSL extends along the first direction X toward the side away from the second edge line L2, and at least a portion of the connection portion LJB's orthographic projection on the substrate 1 overlaps with the orthographic projection of the display trace XSL extending from its side near the second edge line L2 on the substrate 1.

[0094] In the array substrate disclosed herein, the display trace XSL connected to the first pad group CT PadZ1 is the first display trace XSL1, the connection portion LJB connected to the first pad group CT PadZ1 is the first connection portion LJB1, the display trace XSL connected to the second pad group CT PadZ2 is the second display trace XSL2, and the connection portion LJB connected to the second pad group CT PadZ2 is the second connection portion LJB2. The first pad group CT PadZ1 is disposed on the side of the second pad group CT PadZ2 near the first edge line L1, or the first pad group CT PadZ1 is disposed on the side of the second pad group CT PadZ2 near the second edge line L2. Although the first display trace XSL1 overlaps with the second connection portion LJB2, the number of connecting pads CT Pad in the second pad group CT PadZ2 is less than the number of connecting pads CT Pad in the first pad group CT PadZ1. The number of pads results in a shorter overlap length between the first display trace XSL1 and the second connection LJB2, thereby reducing the probability of a short circuit between the first display trace XSL1 and the second connection LJB2.

[0095] Referring to Figures 1 and 2, the array substrate may include a display area AA (Active Area) and a non-display area NAA. Specifically, the non-display area NAA may surround the outer periphery of the display area AA. The array substrate may be rectangular, and the display area AA may be rectangular, such that the non-display area NAA is a rectangular frame.

[0096] The non-display area (NAA) may include a data pad (DP), a data pad opposite (DPO), a gate pad left (GPL), and a gate pad left (GPR). The data pad (DP) may contain circuit bonding pads and source drive circuitry; the data pad (DP) typically corresponds to the area covered by the bottom bezel. The data pad (DP) and the data pad opposite (DPO) are positioned opposite each other in the second direction (Y), and the data pad opposite (DPO) typically corresponds to the area covered by the top bezel. Gate drive on array (GOA) circuitry is provided on the gate pad left (GPL) and the gate drive on ...

[0097] Referring to FIG3, the array substrate 10 may include a substrate 1, a driving circuit layer group 2, a first electrode layer 3, a protective layer 4, and a second electrode layer 5. The material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layer material may be any of the aforementioned materials. Of course, the substrate 1 may also be a single layer, and may be any of the aforementioned materials.

[0098] The driving circuit layer group 2 may include multiple transistors arranged in an array. Specifically, referring to FIG3, the driving circuit layer group 2 may include a gate layer 21, a gate insulating layer 22, an active layer 23, a source-drain layer 24, a buffer layer 25, and an organic layer 26. The gate layer 21 is disposed on one side of the substrate 1. The gate layer 21 may include a gate 211 and a gate line 212. The gate line 212 is connected to the gate 211, or a portion of the gate line 212 may be reused as the gate 211. The gate line 212 may extend along the second direction Y. The gate layer 21 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate layer 21 may be a single-layer film or a multilayer film.

[0099] A gate insulating layer 22 is disposed on the side of the gate layer 21 facing away from the substrate 1. The gate insulating layer 22 may include silicon compounds, metal oxides, or the like. For example, the gate insulating layer 22 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These can be used individually or in combination. The gate insulating layer 22 may be a single-layer film or a multilayer film, wherein the multilayer film is formed as a stacked structure of different materials. The gate insulating layer 22 may be disposed only on the side of the gate layer 21 facing away from the substrate 1; of course, the gate insulating layer 22 may also be disposed over the entire surface of the substrate 1.

[0100] An active layer 23 is disposed on the side of the gate insulating layer 22 facing away from the substrate 1. The active layer 23 may include polycrystalline silicon. However, this disclosure is not limited thereto, and the active layer 23 may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor, etc. The active layer 23 may include a first conductive connection portion 231, a channel portion 232, and a second conductive connection portion 233 connected in sequence. For example, the first conductive connection portion 231 and the second conductive connection portion 233 are connected to opposite ends of the channel portion 232.

[0101] The source / drain layer 24 is disposed on the side of the active layer 23 facing away from the substrate 1. The source / drain layer 24 may include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The source / drain layer 24 may be a single-layer film or a multilayer film. For example, the source / drain layer 24 may be formed as a stacked structure having Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu. The source / drain layer 24 may include a data line 241, a source 242, and a drain 243. The source 242 may be part of the data line 241, or the source 242 may be connected to the data line 241. The source electrode 242 is connected to the first conductive connection portion 231, and the drain electrode 243 is connected to the second conductive connection portion 233.

[0102] A buffer layer 25 is disposed on the side of the source / drain layer 24 facing away from the substrate 1. The buffer layer 25 can be made of an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The thickness of the buffer layer 25 is greater than or equal to 2500 angstroms. An organic layer 26 is disposed on the side of the buffer layer 25 facing away from the substrate 1. The organic layer 26 can be made of an organic material, such as polyimide (PI), polycarbonate, polyacrylate, polyetherimide, etc. The thickness of the organic layer 26 is greater than or equal to 25000 angstroms.

[0103] The channel 232, gate 211, source 242 and drain 243 constitute a thin-film transistor (TFT).

[0104] It should be noted that the thin-film transistor TFT described in this specification is a bottom-gate thin-film transistor TFT. In other exemplary embodiments of this disclosure, the thin-film transistor TFT can also be a top-gate type or a dual-gate type (two gates 211), and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistor TFTs with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source 242" and the "drain 243" are sometimes interchanged. Therefore, in this specification, the "source 242" and the "drain 243" can be interchanged.

[0105] Referring to FIG3, a first electrode layer 3 is disposed on the side of the driving circuit layer group 2 facing away from the substrate 1. Specifically, the first electrode layer 3 is disposed on the side of the organic layer 26 facing away from the substrate 1. The material of the first electrode layer 3 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first electrode layer 3 may include a first electrode 31, which may be a pixel electrode. The first electrode 31 can be connected to the drain 243 through vias on the buffer layer 25 and the organic layer 26. Display driving signals can be input to the first electrode 31 through the drain 243.

[0106] A protective layer 4 is provided on the side of the first electrode layer 3 facing away from the substrate 1. The protective layer 4 can be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The thickness of the protective layer 4 is greater than or equal to 1500 angstroms.

[0107] A second electrode layer 5 is disposed on the side of the protective layer 4 facing away from the substrate 1. The material of the second electrode layer 5 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The second electrode layer 5 may include a second electrode 51, which may be a common electrode.

[0108] Of course, in some other example embodiments of this disclosure, the first electrode 31 may be a common electrode and the second electrode 51 may be a pixel electrode. In this case, the second electrode 51 may be connected to the drain 243 through vias on the buffer layer 25, vias on the organic layer 26 and vias on the protective layer 4. Display driving signals may be input to the second electrode 51 through the drain 243, while the first electrode 31 may not be connected to the drain 243.

[0109] Referring to Figures 1 and 2, the array substrate 10 has a first edge line L1 and a second edge line L2 disposed opposite to each other in a first direction X; the first edge line L1 can be the left edge line, that is, the first edge line L1 can be the edge line of the left side of the gate signal output GPL away from the display area AA; the second edge line L2 can be the right edge line, that is, the second edge line L2 can be the edge line of the right side of the gate signal output GPR away from the display area AA.

[0110] The array substrate 10 may include a plurality of connection pads CT Pads, which are disposed in the non-display area NAA. Specifically, the plurality of connection pads CT Pads are disposed on the data binding side DP. The plurality of connection pads CT Pads are arranged sequentially along the first direction X, that is, the plurality of connection pads CT Pads are arranged sequentially along the first direction X on the data binding side DP.

[0111] Multiple connecting pad CT pads can form a first pad group CT PadZ1 and a second pad group CT PadZ2. The input level of the first pad group CT PadZ1 is different from the input level of the second pad group CT PadZ2. The first pad group CT PadZ1 may include at least two connecting pad CT pads. For example, the first pad group CT PadZ1 may include multiple clock signal connecting pads CLK, frame start signal connecting pads STV1 / STV2, data signal connecting pads Data, etc.

[0112] The second pad group CT PadZ2 may include at least two connected pads CT Pad. For example, the second pad group CT PadZ2 may include a gate drive low level connected pad VGL, a low level signal connected pad LVGL, etc.

[0113] The first pad group CT PadZ1 and the second pad group CT PadZ2 are positioned closer to the first edge line L1 than the second edge line L2. That is, the first pad group CT PadZ1 and the second pad group CT PadZ2 are positioned on a portion of the data binding side DP near the first edge line L1. The first pad group CT PadZ1 is positioned on the side of the second pad group CT PadZ2 near the first edge line L1. That is, the first pad group CT PadZ1 with a higher input level is positioned closer to the first edge line L1.

[0114] Referring to FIG4, the first pad group CT PadZ1 may include a frame start signal connection pad STV1 and a plurality of clock signal connection pads CLK arranged sequentially along the direction away from the first edge line L1. Specifically, the first pad group CT PadZ1 may include a frame start signal connection pad STV1, a first clock signal connection pad CLK1, a third clock signal connection pad CLK3, a fifth clock signal connection pad CLK5 and a seventh clock signal connection pad CLK7 arranged sequentially along the direction away from the first edge line L1.

[0115] The second pad group CT PadZ2 may include a gate drive low-level connection pad VGL and a low-level signal connection pad LVGL arranged sequentially along a direction away from the first edge line L1.

[0116] Specifically, the multiple connection pads CT Pad can be arranged sequentially along the direction away from the first edge line L1 as follows: red data signal connection pad DR, green data signal connection pad DG, frame start signal connection pad STV1, first clock signal connection pad CLK1, third clock signal connection pad CLK3, fifth clock signal connection pad CLK5, seventh clock signal connection pad CLK7, gate drive low level connection pad VGL, low level signal connection pad LVGL, reset signal connection pad RST, first noise reduction signal connection pad VDDO, second noise reduction signal connection pad VDDE, and common signal connection pad VCOM (not shown in the last four figures).

[0117] Multiple display traces (XSLs) are located in the non-display area (NAA). One end of each display trace (XSL) is connected to a connecting pad (CT Pad). The display traces (XSLs) connected to the connecting pads (CT Pads) near the first edge line (L1) extend along the first direction (X) away from the first edge line (L1). Each connecting pad (CT Pad) needs to be connected to a flexible printed circuit board (FPC) or a chip-on-film (COF) via a display trace (XSL). Display signals are input to the connecting pads (CT Pads) through the FPC or COF, and then input to the display area (AA) through the connecting pads (CT Pads) to achieve image display. After exiting the connecting pads (CT Pads), the display traces (XSLs) extend along the first direction (X) away from the first edge line (L1) to achieve connection with the FPC or COF.

[0118] In this example embodiment, referring to FIG7, the gate layer 21 may include a plurality of connection pads CT Pad and a plurality of display traces XSL, that is, the plurality of connection pads CT Pad and the plurality of display traces XSL are disposed on the gate layer 21. The plurality of connection pads CT Pad and the plurality of display traces XSL can be directly connected without the need for a bridging structure.

[0119] A first auxiliary conductive part 244 and a second auxiliary conductive part 245 can be provided in the source-drain layer 24. The first auxiliary conductive part 244 can be connected to the connection pad CT Pad through the first via 221 on the gate insulating layer 22 to reduce the impedance of the connection pad CT Pad. The second auxiliary conductive part 245 can be connected to the display trace XSL through the second via 222 on the gate insulating layer 22 to reduce the impedance of the display trace XSL.

[0120] Of course, in some other exemplary embodiments of this disclosure, multiple connecting pads CT Pad and multiple display traces XSL can be disposed in the source-drain layer 24, while the first auxiliary conductive part 244 and the second auxiliary conductive part 245 can be disposed in the gate layer 21; or the first auxiliary conductive part 244 and the second auxiliary conductive part 245 can be omitted.

[0121] An insulating layer group is provided on the side of the connecting pad CT Pad and the display trace XSL facing away from the substrate 1. For example, the insulating layer group may include a gate insulating layer 22, a buffer layer 25, an organic layer 26, and a protective layer. Depending on the location of the connecting pad CT Pad and the display trace XSL and the location of the connecting part LJB, the film layers included in the insulating layer group are different. As long as an insulating film layer is provided between the connecting pad CT Pad and the display trace XSL and the connecting part LJB, it is within the scope of protection of this disclosure. Therefore, it will not be described in detail here.

[0122] Multiple connection portions LJB are disposed on the side of the insulating layer group away from the substrate 1 and located in the non-display area NAA. One end of the connection portion LJB is connected to the connection pad CT Pad. Specifically, one end of the connection portion LJB is connected to the connection pad CT Pad through a via on the insulating layer group. Each connection pad CT Pad needs to be connected to the test trace ATL through the connection portion LJB, and then connected to the detection terminal AT Pad through the test trace ATL to complete the detection of the sub-pixel structure of the array substrate.

[0123] The orthographic projection of the portion of the connection LJB connected to the connection pad CT Pad near the first edge line L1 on the substrate 1 overlaps with the orthographic projection of the display trace XSL extending from the side of the connection LJB near the first edge line L1 on the substrate 1. That is, the orthographic projection of the nth connection LJB on the substrate 1 overlaps with the orthographic projection of the display trace XSL extending from the side of the nth connection LJB near the first edge line L1 on the substrate 1.

[0124] For ease of explanation, the display trace XSL connected to the first pad group CT PadZ1 is defined as the first display trace XSL1, the connecting part LJB connected to the first pad group CT PadZ1 is defined as the first connecting part LJB1, the display trace XSL connected to the second pad group CT PadZ2 is defined as the second display trace XSL2, and the connecting part LJB connected to the second pad group CT PadZ2 is defined as the second connecting part LJB2.

[0125] Because the number of connecting CT Pads in the first pad group CT PadZ1 is greater than the number of connecting CT Pads in the second pad group CT PadZ2, if the multiple connecting CT Pads are not arranged according to the above structure, the second display trace XSL2 will overlap with the first connection part LJB1, and the overlap length is relatively long. If the insulating film layer between the second display trace XSL2 and the first connection part LJB1 is thin or damaged, the transfer of electrons from the high-level signal of the first connection part LJB1 to the low-level signal of the second display trace XSL2 will cause electrons to break down the damaged or thin insulating film layer, resulting in a short circuit between the two sets of signals. With the first support part PSA provided, the pressure exerted by the first support part PSA on the insulating film layer is greater, making the aforementioned short circuit more likely to occur.

[0126] The first pad group CT PadZ1 is placed on the side of the second pad group CT PadZ2 near the first edge line L1. Although the first display trace XSL1 will overlap with the second connection part LJB2, the number of connecting pads CT Pad in the second pad group CT PadZ2 is less than the number of connecting pads CT Pad in the first pad group CT PadZ1. This results in a shorter overlap length between the first display trace XSL1 and the second connection part LJB2, thereby reducing the probability of a short circuit between the first display trace XSL1 and the second connection part LJB2.

[0127] Optionally, the input level of the first pad group CT PadZ1 is higher than the input level of the second pad group CT PadZ2, resulting in a higher level on the first display trace XSL and a lower level on the second connection LJB. Even if the first display trace XSL extends along the first direction X and overlaps with the second connection LJB, due to the lower input level on the second connection LJB and the smaller area of ​​the first display trace XSL, there are fewer paths for electrons of the high-level signal on the first display trace XSL to transfer to the low-level second connection LJB. This reduces or even avoids the transfer of electrons breaking down the already damaged or thin insulating film layer, thereby preventing a short circuit between the two sets of signals.

[0128] Of course, when the first pad group CT PadZ1 and the second pad group CT PadZ2 are set closer to the second edge line L2 relative to the first edge line L1, that is, when the first pad group CT PadZ1 and the second pad group CT PadZ2 are set on a part of the data binding side DP near the second edge line L2; when the first pad group CT PadZ1 is set on the side of the second pad group CT PadZ2 near the second edge line L2, that is, the first pad group CT PadZ1 with a higher input level is set closer to the second edge line L2.

[0129] Referring to FIG5, the first pad group CT PadZ1 may include a frame start signal connection pad STV2 and a plurality of clock signal connection pads CLK arranged sequentially along the direction away from the second edge line L2. Specifically, the first pad group CT PadZ1 may include a frame start signal connection pad STV2, a second clock signal connection pad CLK2, a fourth clock signal connection pad CLK4, a sixth clock signal connection pad CLK6 and an eighth clock signal connection pad CLK8 arranged sequentially along the direction away from the second edge line L2.

[0130] The second pad group CT PadZ2 may include gate drive low-level connection pads VGL and low-level signal connection pads LVGL arranged sequentially along a direction away from the second edge line L2.

[0131] Specifically, the multiple connection pads CT Pad can be arranged sequentially along the direction away from the second edge line L2 as follows: blue data signal connection pad DB, switch data signal connection pad DS, frame start signal connection pad STV2, second clock signal connection pad CLK2, fourth clock signal connection pad CLK4, sixth clock signal connection pad CLK6 and eighth clock signal connection pad CLK8, gate drive low level connection pad VGL, low level signal connection pad LVGL, reset signal connection pad RST, first noise reduction signal connection pad VDDO, second noise reduction signal connection pad VDDE and common signal connection pad VCOM (not shown in the last four figures).

[0132] In this case, the portion of the connecting pad CT Pad connected to the second edge line L2 shows the trace XSL extending along the first direction X toward the side away from the second edge line L2.

[0133] The orthographic projection of the portion of the connection LJB connected to the connection pad CT Pad near the second edge line L2 on the substrate 1 overlaps with the orthographic projection of the display trace XSL extending from the side of the connection LJB near the second edge line L2 on the substrate 1. That is, the orthographic projection of the nth connection LJB on the substrate 1 overlaps with the orthographic projection of the display trace XSL extending from the side of the nth connection LJB near the second edge line L2 on the substrate 1.

[0134] Similarly, by placing the first pad group CT PadZ1 on the side of the second pad group CT PadZ2 near the second edge line L2, although the first display trace XSL1 will overlap with the second connection part LJB2, the number of connecting pads CT Pad in the second pad group CT PadZ2 is less than the number of connecting pads CT Pad in the first pad group CT PadZ1, resulting in a shorter overlap length between the first display trace XSL1 and the second connection part LJB2, thereby reducing the probability of a short circuit between the first display trace XSL1 and the second connection part LJB2.

[0135] Optionally, the input level of the first pad group CT PadZ1 is higher than the input level of the second pad group CT PadZ2, resulting in a higher level on the first test trace ATL and a lower level on the second connection LJB. Even if the first test trace ATL extends along the first direction X and overlaps with the second connection LJB, the lower level on the second connection LJB and the smaller area of ​​the first test trace ATL mean that there are fewer paths for electrons from the high-level signal on the first test trace ATL to transfer to the low-level second connection LJB. This reduces or even avoids the transfer of electrons breaking down the already damaged or thin insulating film layer, thereby preventing a short circuit between the two sets of signals.

[0136] Of course, in some other exemplary embodiments of this disclosure, the first pad group CT PadZ1 and the second pad group CT PadZ2 may be provided only in a portion of the data binding side DP near the first edge line L1. In this case, all display traces XSL extend along the first direction X toward the side away from the first edge line L1, and the orthographic projection of all connection portions LJB on the substrate 1 overlaps with the orthographic projection of the display traces XSL extending from the side near the first edge line L1 on the substrate 1. Alternatively, the first pad group CT PadZ1 and the second pad group CT PadZ2 may be provided only in a portion of the data binding side DP near the second edge line L2. In this case, all display traces XSL extend along the first direction X toward the side away from the second edge line L2, and the orthographic projection of all connection portions LJB on the substrate 1 overlaps with the orthographic projection of the display traces XSL extending from the side near the second edge line L2 on the substrate 1.

[0137] In some exemplary embodiments of this disclosure, referring to Figures 4 and 5, the array substrate may further include multiple test traces ATL, which extend along a first direction X and are arranged substantially parallel to each other; the multiple test traces ATL are located in the non-display area NAA, specifically, the multiple test traces ATL are located on the data bonding side DP, and the multiple test traces ATL are located on the side of the multiple connection pads CT Pad away from the display area AA.

[0138] A portion of the test traces ATL can be introduced from the first edge line L1, that is, one end of a portion of the test traces ATL extends to the first edge line L1; the connecting pads CT Pad are connected to the test traces ATL. Specifically, the connecting pads CT Pad near the first edge line L1 are connected to the test traces ATL introduced from the first edge line L1, and the first pad group CT PadZ1 and the second pad group CT PadZ2 near the first edge line L1 are connected to the test traces ATL introduced from the first edge line L1.

[0139] Another portion of the test traces ATL can be introduced from the second edge line L2, that is, one end of a portion of the test traces ATL extends to the second edge line L2; the connecting pad CT Pad is connected to the test traces ATL. Specifically, the connecting pad CT Pad near the second edge line L2 is connected to the test traces ATL introduced from the second edge line L2, and the first pad group CT PadZ1 and the second pad group CT PadZ2 near the second edge line L2 are connected to the test traces ATL introduced from the second edge line L2.

[0140] In related technologies, referring to Figures 13 and 14, the test trace ATL bypasses the data bonding opposite side DPO of the adjacent array substrate. That is, before the array substrate motherboard is cut, part of the test trace ATL is set on the data bonding side DP of one array substrate, and another part is set on the data bonding opposite side DPO of another adjacent array substrate. Specifically, the test trace ATL is introduced from one corner of the data bonding opposite side DPO of the lower array substrate, then crosses the first cut line CL1 with zero cut edge to connect to the data bonding side DP of the upper array substrate, and connects to the connection pad CT Pad of the data bonding side DP. Then (about 1 / 20 of the array substrate), it crosses the first cut line CL1 with zero cut edge again to connect to the data bonding opposite side DPO of the lower array substrate, and extends to the connection pad CT Pad on the opposite side. The first cut line CL1 with zero cut edge crosses the first cut line with zero cut edge for the third time to connect to the data bonding side DP of the upper array substrate, and connects to the connection pad CT Pad of the data bonding side DP. The Pad is connected, and then the first cutting line CL1, which crosses the zero edge for the fourth time, is connected to the data binding opposite side DPO of the lower array substrate, and is led out from the other corner of the data binding opposite side DPO of the lower array substrate.

[0141] After the array substrate motherboard is cut to form multiple array substrates, test traces ATL are also provided on the DPO opposite to the data bonding of the array substrate. Moreover, the ends of the test traces ATL are exposed on the cutting line. The connection pad CT Pad and the exposed test traces ATL can be insulated by adhesive insulating glue.

[0142] The array substrate and color filter substrate can be made of polyimide (PI) liquid, sealant 6 and liquid crystal (LC) cell. For example, the polyimide liquid can be coated on the area to be covered on the array substrate by rotating the roller. After the polyimide liquid is cured, it forms an alignment film.

[0143] Referring to Figure 14, due to the requirements of the narrow bezel setting, the distance between the edge line of the display area AA and the data bonding opposite side DPO of the array substrate, the edge line of the gate signal output left side GPL, and the edge line of the gate signal output right side GPR is usually less than or equal to 2mm. The distance K1 between the display area AA on the data bonding opposite side DPO and the edge of the polyimide liquid is greater than or equal to 1.2mm, the width K2 of the sealant 6 is greater than or equal to 750μm and less than or equal to 950μm, and there is overlap between the sealant 6 and the polyimide liquid. Furthermore, considering that the distance K3 between the test trace ATL and the first cutting line CL1 is greater than or equal to 250μm, the distance between the test trace ATL and the polyimide liquid is extremely limited and may even overlap. The polyimide liquid will seep out of the sealant 6 along the test trace ATL and then diffuse at the first cutting line CL1 (the edge of the DPO on the data binding side of the array substrate). Since the polyimide liquid is hygroscopic, under the PCT (high pressure cooking) test (2atm & 121℃ & 100% humidity) environment, external moisture enters the display device through the first cutting line CL1 where the adhesion is weak, which macroscopically manifests as Bubble defects.

[0144] In this example embodiment, the test traces ATL can be almost entirely retained on the data bonding side DP. Compared to the structure in related technologies, the test traces ATL on the data bonding opposite side DPO of the array substrate are completely removed. That is, no test traces ATL are set on the data bonding opposite side DPO of the array substrate. In other words, no test traces ATL are set in the non-display area NAA opposite to the setting of the connection pad CT Pad. This effectively avoids the panel bubble caused by water absorption at the cutting line due to the polyimide liquid seeping out along the test traces ATL to the cutting line and spreading at the cutting line.

[0145] Of course, in some other exemplary embodiments of this disclosure, when the first pad group CT PadZ1 and the second pad group CT PadZ2 are only located in a portion of the data binding side DP near the first edge line L1, all test traces ATL can be introduced from the first edge line L1, that is, one end of all test traces ATL extends to the first edge line L1; when the first pad group CT PadZ1 and the second pad group CT PadZ2 are only located in a portion of the data binding side DP near the second edge line L2, all test traces ATL can be introduced from the second edge line L2, that is, one end of all test traces ATL extends to the second edge line L2.

[0146] In some example embodiments of this disclosure, multiple test traces (ATLs) are sequentially connected to multiple connection pads (CT Pads) in a one-to-one correspondence.

[0147] For example, multiple test traces ATL are sequentially arranged along the direction furthest from the display area AA, that is, multiple test traces ATL are sequentially arranged along the second direction Y, in the direction furthest from the display area AA. For example, the test trace ATL closest to the display area AA is the first test trace ATL1, and in the direction furthest from the display area AA, they are the second test trace ATL2, the third test trace ATL3, the fourth test trace ATL4, and so on.

[0148] Multiple connecting pads CT Pads close to the first edge line L1 are sequentially arranged in a direction away from the first edge line L1. That is, multiple connecting pads CT Pads close to the first edge line L1 are sequentially arranged in a direction away from the first edge line L1 in the first direction X. For example, the connecting pad CT Pad closest to the first edge line L1 is the first connecting pad CT Pad1, and in the direction away from the first edge line L1, they are sequentially the second connecting pad CT Pad2, the third connecting pad CT Pad3, the fourth connecting pad CT Pad4, and so on.

[0149] Test traces (ATLs) can be connected to connection pads (CT Pads) with the same serial number. For example, the first test trace (ATL1) is connected to the first connection pad (CT Pad1), the second test trace (ATL2) is connected to the second connection pad (CT Pad2), the third test trace (ATL3) is connected to the third connection pad (CT Pad3), and the fourth test trace (ATL4) is connected to the fourth connection pad (CT Pad4). Alternatively, one connection pad (CT Pad) may not be connected to a test trace (ATL) (e.g., the third connection pad (CT Pad) in Figures 4 and 5). In this case, after the connection pad (CT Pad) not connected to a test trace (ATL), the nth connection pad (CT Pad) is connected to the (n-1)th test trace (ATL). Of course, in other exemplary embodiments of this disclosure, two or more connection pads (CT Pads) may not be connected to test traces (ATLs).

[0150] Of course, it should be noted that the connecting pad CT Pad near the first edge line L1 is connected to the test trace ATL introduced from the first edge line L1.

[0151] Multiple connecting pads CT Pads close to the second edge line L2 are sequentially arranged in a direction away from the second edge line L2. That is, multiple connecting pads CT Pads close to the second edge line L2 are sequentially arranged in a first direction X in a direction away from the second edge line L2. For example, the connecting pad CT Pad closest to the second edge line L2 is the first connecting pad CT Pad1, and in the direction away from the second edge line L2, they are sequentially the second connecting pad CT Pad2, the third connecting pad CT Pad3, the fourth connecting pad CT Pad4, and so on.

[0152] Test traces ATL are connected to connection pads CT Pad with the same serial number. For example, the first test trace ATL1 is connected to the first connection pad CT Pad1, the second test trace ATL2 is connected to the second connection pad CT Pad2, the third test trace ATL3 is connected to the third connection pad CT Pad3, and the fourth test trace ATL4 is connected to the fourth connection pad CT Pad4. Alternatively, one connection pad CT Pad may not be connected to a test trace ATL, meaning that after the connection pad CT Pad not connected to a test trace ATL, the nth connection pad CT Pad is connected to the (n-1)th test trace ATL. Of course, in other exemplary embodiments of this disclosure, two or more connection pads CT Pad may not be connected to a test trace ATL.

[0153] Therefore, connecting multiple test traces (ATLs) to multiple connection pads (CT Pads) in a one-to-one correspondence means that multiple test traces (ATLs) and multiple connection pads (CT Pads) are connected in sequence, with intervals allowed, but they cannot be interleaved.

[0154] Similarly, it should be noted that the connecting pad CT Pad near the second edge line L2 is connected to the test trace ATL introduced from the second edge line L2.

[0155] Alternatively, the end of the test trace ATL is located on the side of the connecting pad CT Pad that it is connected to, away from the display area AA. That is, the test trace ATL does not run through the entire data bonding side DP, but only occupies a part of the data bonding side DP. The main function of the test trace ATL is to connect the connecting pad CT Pad to the detection terminal AT Pad. Therefore, the end of the test trace ATL is located on the side of the connecting pad CT Pad that it is connected to, away from the display area AA, so that the test trace ATL can be connected to the connecting pad CT Pad. Specifically, the edge of the end of the test trace ATL in the first direction X is collinear with the edge of the connecting pad CT Pad that is perpendicular to the first direction X. Alternatively, the edge of the end of the test trace ATL in the first direction X protrudes slightly beyond the edge of the connecting pad CT Pad that is perpendicular to the first direction X.

[0156] Since the first test trace ATL1 only extends to the side of the first connecting pad CT Pad1 away from the display area AA, the first test trace ATL1 is not set on the side of the second connecting pad CT Pad2, the third connecting pad CT Pad3, and subsequent connecting pad CT Pads away from the display area AA, thus creating a vacant position.

[0157] The spacing between each test trace (ATL) introduced from the first edge line L1 and each connecting pad (CT Pad) in the second direction Y decreases as the spacing between the connecting pad (CT Pad) and the first edge line L1 in the first direction X increases. Each decrease is greater than or equal to 28 micrometers and less than or equal to 40 micrometers; for example, each decrease could be 30 micrometers, 32 micrometers, 35 micrometers, 37 micrometers, etc.

[0158] The spacing between each test trace (ATL) introduced from the second edge line L2 and each connecting pad (CT Pad) in the second direction Y decreases as the spacing between the connecting pad (CT Pad) and the second edge line L2 in the first direction X increases. Each decrease is greater than or equal to 28 micrometers and less than or equal to 40 micrometers; for example, each decrease could be 30 micrometers, 32 micrometers, 35 micrometers, 37 micrometers, etc.

[0159] Specifically, starting at least from the second test trace ATL2, the test trace ATL is bent towards the connecting pad CT Pad at a position opposite to the connecting pad CT Pad to form a step line. Since the first test trace ATL1 is directly connected to the first connecting pad CT Pad1, the first test trace ATL1 does not need to be bent to form a step line. For example, the second test trace ATL2 bends and offsets towards the second connecting pad CT Pad2 at a position opposite to the second connecting pad CT Pad2, forming a stepped line with two bends. Specifically, the second test trace ATL2 may include a first part ATL21, a second part ATL22, and a third part ATL23 that are connected in a smooth transition. The second part ATL22 may extend along the second direction Y, while the first part ATL21 and the third part ATL23 may extend along the first direction X. The third part ATL23 is closer to the connecting pad CT Pad in the second direction Y than the first part ATL21. The third part ATL23 is the tail end of the second test trace ATL2. The third part ATL23 is connected to the second connecting pad CT Pad2. The third part ATL23 is basically collinear with the first test trace ATL1, so that the ends of multiple test traces ATL and the corresponding connecting pad CT Pad are collinear.

[0160] The offset distance of the third part ATL23 is the sum of the width of a test trace ATL and the spacing between two adjacent test trace ATLs. Alternatively, the length of the second part ATL22 in the second direction Y is the sum of the width of a test trace ATL and the spacing between two adjacent test trace ATLs. For example, the offset distance of the third part ATL23 is greater than or equal to 28 micrometers and less than or equal to 40 micrometers. For example, the offset distance of the third part ATL23 can be 30 micrometers, 32 micrometers, 35 micrometers, 37 micrometers, etc.

[0161] For the third test trace ATL3, it bends and shifts towards the second connecting pad CT Pad2 at a position opposite to the second connecting pad CT Pad2, and bends and shifts towards the third connecting pad CT Pad3 at a position opposite to the third connecting pad CT Pad3, forming a stepped line with four bends. Specifically, the third test trace ATL3 may include a fourth part ATL31, a fifth part ATL32, a sixth part ATL33, a seventh part ATL34, and an eighth part ATL35 that are connected smoothly in sequence. The fifth part ATL32 and the seventh part ATL34 can extend along the second direction Y, and the fourth part ATL31, the sixth part ATL33, and the eighth part ATL35 can extend along the first direction X. The sixth part ATL33 is closer to the connecting pad CT Pad in the second direction Y than the fourth part ATL31, and the eighth part ATL35 is closer to the connecting pad CT in the second direction Y than the sixth part ATL33. Pad; Part 8 ATL35 is the tail end of the third test trace ATL3. Part 8 ATL35 is connected to the third connecting pad CT Pad3. Part 8 ATL35, Part 3 ATL23 and the first test trace ATL1 are basically collinear, so that the ends of multiple test traces ATL and the corresponding connecting pad CT Pad are collinear.

[0162] The offset distance of the sixth part ATL33 and the eighth part ATL35 is the sum of the width of a test trace ATL and the spacing between two adjacent test trace ATLs. Alternatively, the length of the fifth part ATL32 and the seventh part ATL34 in the second direction Y is the sum of the width of a test trace ATL and the spacing between two adjacent test trace ATLs. For example, the offset distance of the sixth part ATL33 and the eighth part ATL35 is greater than or equal to 28 micrometers and less than or equal to 40 micrometers. For example, the offset distance of the sixth part ATL33 and the eighth part can be 30 micrometers, 32 micrometers, 35 micrometers, 37 micrometers, etc.

[0163] Of course, for the fourth test trace ATL4, it bends and shifts towards the second connecting pad CT Pad2 at the position opposite to the second connecting pad CT Pad2, bends and shifts towards the third connecting pad CT Pad3 at the position opposite to the third connecting pad CT Pad3, and bends and shifts towards the fourth connecting pad CT Pad4 at the position opposite to the fourth connecting pad CT Pad4, forming a stepped line with six bends. The bending and shifting methods of subsequent test traces ATL are similar, and will not be described in detail here.

[0164] It should be noted that the second direction Y intersects with the first direction X, for example, the second direction Y is perpendicular to the first direction X; moreover, both the second direction Y and the first direction X are parallel to the substrate 1.

[0165] Alternatively, if the array substrate also includes multiple test traces ATL, the connection portion LJB is connected between the connection pad CT Pad and the test trace ATL. Specifically, multiple connection portions LJB are connected one-to-one between multiple connection pads CT Pad and multiple test traces ATL, and the connection between the connection pad CT Pad and the test trace ATL is an indirect connection formed through the connection portion LJB.

[0166] Because the ends of multiple test traces (ATLs) and the corresponding connecting pads (CT Pads) are collinear, and the end of the connecting part (LJB) connected to the test trace (ATL) is the first end, and the edges of the first ends of multiple connecting parts (LJBs) extending along the first direction X are collinear, a one-to-one connection between multiple connecting parts (LJBs) and multiple test traces (ATLs) can be achieved. This arrangement ensures that the connecting part (LJB) only overlaps with the test trace (ATL) it connects to; that is, connecting parts (LJBs) transmitting the same signal overlap with test traces (ATLs). However, connecting parts (LJBs) do not overlap with test traces (ATLs) that are not connected to them, and connecting parts (LJBs) transmitting different signals do not overlap with test traces (ATLs). This prevents electrons from high-level signals on the test trace (ATL) from transferring to low-level connecting parts (LJBs), and avoids the transferred electrons from breaking down damaged or thin insulating layers, thus preventing short circuits between the two sets of signals. Furthermore, it reduces the area of ​​the connecting part (LJB), facilitating the subsequent installation of the first support part (PSA).

[0167] It should be noted that "collinear setup" not only includes completely collinear setup, but can also have a certain degree of error. The error range varies depending on the equipment and preparation process. Therefore, if the error range of the equipment and preparation process is within the range of error, it is considered to be a collinear setup.

[0168] In some exemplary embodiments of this disclosure, referring to FIG7, the gate layer 21 may include multiple test traces ATL, that is, multiple test traces ATL are disposed in the gate layer 21. A third auxiliary conductive portion 246 may be disposed in the source-drain layer 24. The third auxiliary conductive portion 246 may be connected to the test traces ATL through a third via 223 on the gate insulating layer 22 to reduce the impedance of the test traces ATL.

[0169] Of course, in some other exemplary embodiments of this disclosure, multiple test traces ATL can be disposed in the source-drain layer 24, while the third auxiliary conductive part 246 can be disposed in the gate layer 21; or the third auxiliary conductive part 246 can be omitted.

[0170] The second electrode layer 5 may include a connecting portion LJB, that is, the connecting portion LJB is disposed on the side of the protective layer 4 away from the substrate 1.

[0171] Referring to Figure 15, a first support portion PSA is provided on the array substrate 10, and a second support portion PSF is provided on the color filter substrate 20. The first support portion PSA and the second support portion PSF are arranged opposite each other to provide support for the liquid crystal layer. In order to balance the gap difference between the display area AA and the non-display area NAA, the non-display area NAA is also designed with a first support portion PSA and a second support portion PSF, and the first support portion PSA and the second support portion PSF are periodically arranged. However, in related technologies, because the lengths of the multiple connecting portions LJB are different, and the first support portion PSA cannot be set above the connecting portion LJB, the first support portion PSA cannot be set above the display trace XSL and the test trace ATL on the side of the connecting pad CT Pad near the edge line. Only the second support portion PSF is set on the color filter substrate 20. This results in insufficient support of the support portion in the area where the connecting pad CT Pad is set, which leads to uneven stress during subsequent cell assembly, resulting in gap differences and the risk of yellowing around the edges.

[0172] Referring to Figures 6 and 7, the array substrate may further include multiple first support portions PSA, which are arranged in an array on the side of the multiple connecting portions LJB away from the display area AA. Specifically, the first support portions PSA can be disposed on the uppermost side of the array substrate. For example, the first support portions PSA can be disposed on the side of the protective layer 4 away from the substrate 1. The first support portions PSA are used to support the color filter substrate, so that a gap for accommodating the liquid crystal layer is formed between the array substrate and the color filter substrate. The orthographic projection of a portion of the first support portions PSA on the substrate 1 overlaps with the orthographic projection of the test trace ATL on the substrate 1, while the orthographic projection of another portion of the first support portions PSA on the substrate 1 does not overlap with the orthographic projection of the test trace ATL on the substrate 1. That is, the first support portions PSA can be disposed on the side of the test trace ATL away from the substrate 1, increasing the placement area of ​​the first support portions PSA, thereby reducing the difference in the gap for accommodating the liquid crystal layer formed by the non-display area NAA and the display area AA of the array substrate, which is beneficial for preventing yellowing defects around the display device.

[0173] In this case, since the first support PSA is made of an organic material, specifically a resin material that easily absorbs moisture, if the first support PSA is connected to the connecting part LJB, the moisture absorbed by the first support PSA will cause the connecting part LJB to be corroded by the moisture. Therefore, the connecting part LJB and the first support PSA cannot be connected. Furthermore, the first safety distance 'a' between the connecting part LJB and the first support PSA needs to be greater than or equal to 50 micrometers.

[0174] The second safety distance b between the first support PSA and the third edge line needs to be greater than or equal to 250 micrometers. The third edge line is the edge line of the data binding side DP away from the display area AA.

[0175] The first support PSA for the array arrangement can be set in the region c between the first and second safety distances.

[0176] This configuration allows the corners of the array substrate to also have a first support PSA, thereby reducing the difference in the gap between the corners of the array substrate and other areas that accommodate the liquid crystal layer, which helps prevent yellowing defects around the display device.

[0177] In some other exemplary embodiments of this disclosure, referring to FIG8, the first electrode layer 3 may include a first electrode 31 and a connection portion LJB, that is, the connection portion LJB is disposed between the organic layer 26 and the protective layer 4, and the connection portion LJB is connected between the connection pad CT Pad and the test trace ATL. Specifically, one end of the connection portion LJB is connected to the connection pad CT Pad through the buffer layer 25 and the via on the organic layer 26, and the other end of the connection portion LJB is connected to the test trace ATL through the buffer layer 25 and the organic layer 26.

[0178] In this case, since the connecting portion LJB is covered by the protective layer 4, a portion of the orthographic projection of the first support portion PSA on the substrate 1 can overlap with the orthographic projection of the connecting portion LJB on the substrate 1. That is, the first support portion PSA can be positioned above the connecting portion LJB. Even if the first support portion PSA absorbs moisture, it will be blocked by the protective layer 4, preventing moisture from penetrating the connecting portion LJB and causing corrosion. This further increases the area of ​​the first support portion PSA and further reduces the difference in gap between the corners of the array substrate and other areas forming the liquid crystal layer, which helps prevent yellowing defects around the display device.

[0179] Since the test trace ATL is also covered by the protective layer 4, a portion of the orthographic projection of the first support PSA on the substrate 1 can overlap with the orthographic projection of the test trace ATL on the substrate 1. That is, the first support PSA can be positioned above the test trace ATL. Even if the first support PSA absorbs moisture, it will be blocked by the protective layer 4, preventing moisture from penetrating the test trace ATL and causing corrosion. This further increases the area of ​​the first support PSA and further reduces the difference in gap between the corners of the array substrate and other areas forming the liquid crystal layer, which helps prevent yellowing defects around the display device.

[0180] Since the display trace XSL is also covered by the protective layer 4, a portion of the orthographic projection of the first support portion PSA on the substrate 1 can overlap with the orthographic projection of the display trace XSL on the substrate 1. That is, the first support portion PSA can be positioned above the display trace XSL. Even if the first support portion PSA absorbs moisture, it will be blocked by the protective layer 4, preventing moisture from penetrating the display trace XSL and causing corrosion. This further increases the area of ​​the first support portion PSA and further reduces the difference in gap between the corners of the array substrate and other areas forming the liquid crystal layer, which helps prevent yellowing defects around the display device.

[0181] The second auxiliary conductive part 245 is connected to the display trace XSL through the second via 222 on the gate insulating layer 22. The distance D between the side of the display trace XSL close to the substrate 1 and the side of the second auxiliary conductive part 245 away from the substrate 1 is greater than or equal to 5000 angstroms and less than or equal to 7000 angstroms, resulting in the formation of multiple protrusions and recesses at the display trace XSL. The orthographic projection of the organic layer 26 on the substrate 1 covers the display trace XSL. The organic layer 26 can fill the recesses, avoiding the breakage caused by the subsequent connection part LJB at the protrusions and recesses due to the ramp. Moreover, it can avoid the short circuit caused by the connection part LJB and the display trace XSL due to the thinness of the buffer layer 25.

[0182] In the above example embodiment, referring to Figures 1, 4-8, and 16, during the cutting of the array substrate motherboard, there is a zero cut between the data bonding side DP and the data bonding counterpart DPO, meaning a first cutting line CL1 is provided between the data bonding side DP and the data bonding counterpart DPO. There is a non-zero cut between the left side GPL of the gate signal output and the right side GPR of the gate signal output, meaning two second cutting lines CL2 are provided between the left side GPL of the gate signal output and the right side GPR of the gate signal output. The two second cutting lines CL2 are separated by a gap greater than or equal to 2.5 mm. In this case, the test trace ATL located on the data bonding side DP of the array substrate is not cut away and is retained in the array substrate product.

[0183] In other exemplary embodiments of this disclosure, referring to Figures 2, 9, 10, and 17, during the cutting of the array substrate motherboard, there is a non-zero cut between the data bonding side DP and the data bonding counterpart side DPO. That is, two first cutting lines CL1 are provided between the data bonding side DP and the data bonding counterpart side DPO, and the two first cutting lines CL1 are separated by a gap greater than or equal to 2.5 mm. There is a zero cut between the left side GPL of the gate signal output and the right side GPR of the gate signal output. That is, a second cutting line CL2 is provided between the left side GPL of the gate signal output and the right side GPR of the gate signal output. In the array substrate formed under this condition, the test trace ATL located on the data bonding side DP can be cut off and is not retained in the array substrate product; the end of the connector LJB that connects to the test trace ATL is also cut off and only the end of the connector LJB that connects to the connector pad CT Pad is retained, so that one end of the connector LJB is connected to the connector pad CT Pad, and the other end of the connector LJB is used to connect to the test trace ATL.

[0184] In this case, the gate insulation layer 22, the buffer layer 25 and the organic layer 26 need to be removed at the first cutting line CL1 to form a groove 101 at the first cutting line CL1, which facilitates subsequent cutting.

[0185] Furthermore, referring to Figure 10, the second electrode layer 5 extends into the non-display area NAA. Considering the safety distance H1 between the second electrode layer 5 and the first support PSA, which is greater than or equal to 150 micrometers, and the safety distance H2 between the first support PSA and the first cutting line CL1, which is greater than or equal to 250 micrometers, the remaining area H3 can be entirely used to house the first support PSA. This ensures a difference in gap between the corners of the array substrate and other areas, which helps prevent yellowing defects around the display device.

[0186] In the above example implementation, as shown in Figures 4-6, the XSL trace can be located between the connecting pad CT Pad and the test trace ATL.

[0187] In some other exemplary embodiments of this disclosure, referring to Figures 11 and 12, the connecting pad CT Pad can be located between the display trace XSL and the test trace ATL. The display trace XSL, the connecting pad CT Pad, and the test trace ATL can be connected by the connecting part LJB. The other end of the display trace XSL is connected to the display driver chip.

[0188] Since the LJB connector is located on the top surface of the array substrate and is exposed, it is easy for the LJB to come into contact with external conductive materials and become conductive, which can easily lead to short circuits between different signal lines. Therefore, insulating adhesive (e.g., photosensitive adhesive) can be applied to the LJB connector of the array substrate for insulation treatment, and then fixing tape (cell tape) can be applied. The control precision of the insulating adhesive is greater than or equal to 400μm. After the array substrate and the color filter substrate are assembled to form a display device, the edge line of the color filter substrate is located inside the array substrate, that is, the array substrate protrudes from the edge line of the color filter substrate. The insulating adhesive must not overlap with the color filter substrate. If the insulating adhesive overlaps with the color filter substrate, the color filter substrate will be placed on the side of the insulating adhesive away from the array substrate. The insulating adhesive will support the color filter substrate, which will cause the thickness of the display device to exceed the specification and is prone to light leakage. Therefore, the distance between the edge line of the connecting pad CT Pad near the color filter substrate and the edge line of the color filter substrate near the connecting pad CT Pad must also be greater than or equal to 400μm. This is not conducive to the setting of a narrow bezel and affects the yield of the array substrate.

[0189] The CT Pad is placed between the display trace XSL and the test trace ATL, so that the CT Pad is far away from the edge of the color filter substrate. This effectively prevents the insulation adhesive from overlapping with the color filter substrate, which would cause the thickness to exceed the standard, and also prevents light leakage defects.

[0190] It should be noted that, as shown in FIG11, the structure in which the connecting pad CT Pad is placed between the display trace XSL and the test trace ATL can be combined with the structure in which the test trace ATL is set as a stepped line as described above; as shown in FIG12, the structure in which the connecting pad CT Pad is placed between the display trace XSL and the test trace ATL can also be combined with the structure in which the test trace ATL is set as a straight line.

[0191] Based on the same inventive concept, this disclosure provides an array substrate mother plate. Referring to Figures 16 and 17, the array substrate mother plate is provided with dicing lines CL, which divide the array substrate mother plate into multiple array substrates. The array substrates are any of the array substrates described above. The specific structure of the array substrates has been described in detail above, and therefore will not be repeated here. The dicing lines CL may include a first dicing line CL1 and a second dicing line CL2; the first dicing line CL1 extends along a first direction X; and the second dicing line CL2 extends along a second direction Y.

[0192] In some exemplary embodiments of this disclosure, referring to FIG16, a first cutting line CL1 is provided between two adjacent array substrates in the second direction Y, and two second cutting lines CL2 are provided between two adjacent array substrates in the first direction X, forming the array substrate shown in FIG1 after cutting.

[0193] In some other exemplary embodiments of this disclosure, referring to FIG17, two first cutting lines CL1 are provided between two adjacent array substrates in the second direction Y, and a second cutting line CL2 is provided between two adjacent array substrates in the first direction X, forming the array substrate shown in FIG2 after cutting.

[0194] Based on the same inventive concept, this disclosure provides a display device that may include the array substrate described in any of the above-described embodiments. The specific structure of the array substrate has been described in detail above, and therefore will not be repeated here.

[0195] The display device can be a liquid crystal display panel, an OLED (Organic Electroluminescence Display) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, and so on.

[0196] If the display device can be a liquid crystal display panel, the display device may also include a color filter substrate 15, which is bonded to the array substrate by a frame 14.

[0197] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0198] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0199] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0200] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, comprising a display area and a non-display area, the array substrate having a first edge line and a second edge line disposed opposite to each other in a first direction, wherein, The array substrate includes: Substrate; Multiple connecting pads are disposed on one side of the substrate and located in the non-display area, and are arranged sequentially along the first direction; the multiple connecting pads form a first pad group and a second pad group, the input level of the first pad group is different from the input level of the second pad group, and the number of connecting pads included in the first pad group is greater than the number of connecting pads included in the second pad group. Multiple display traces are disposed on one side of the substrate and located in the non-display area, with one end of each display trace connected to the connecting pad. An insulating layer assembly is disposed on the side of the connecting pad and the display trace away from the substrate. Multiple connecting portions are provided on the side of the insulating layer group away from the substrate and located in the non-display area, with one end of each connecting portion connected to the connecting pad. Wherein, the first pad group and the second pad group are disposed closer to the first edge line than the second edge line, and the first pad group is disposed on the side of the second pad group closer to the first edge line. At least a portion of the display traces extend away from the first edge line along the first direction. At least a portion of the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection of the display traces extending from the side closer to the first edge line on the substrate. And / or, the first pad group and the second pad group are disposed closer to the second edge line than the first edge line, and the first pad group is disposed on the side of the second pad group closer to the second edge line, at least a portion of the display traces extend away from the second edge line along the first direction, and at least a portion of the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection of the display traces extending from the side closer to the second edge line on the substrate.

2. The array substrate according to claim 1, wherein, The array substrate further includes: Multiple test traces are located in the non-display area and on the side of the connecting pad away from the display area. The multiple test traces extend along the first direction, with at least some of the test traces introduced from the first edge line and / or at least some of the test traces introduced from the second edge line. The connecting pad near the first edge line is connected to the test trace introduced from the first edge line, and the connecting pad near the second edge line is connected to the test trace introduced from the second edge line.

3. The array substrate according to claim 2, wherein, Multiple test traces are sequentially connected to multiple connecting pads; the tail end of each test trace is located on the side of the connecting pad connected to it that is away from the display area; the spacing between each test trace introduced from the first edge line and each connecting pad in the second direction decreases as the spacing between the connecting pad and the first edge line in the first direction increases, and / or, the spacing between each test trace introduced from the second edge line and each connecting pad in the second direction decreases as the spacing between the connecting pad and the second edge line in the first direction increases; the second direction intersects the first direction.

4. The array substrate according to claim 3, wherein, The ends of the multiple test traces and the corresponding connecting pads are arranged collinearly.

5. The array substrate according to claim 4, wherein, The connecting part is connected between the connecting pad and the test trace. The end of the connecting part connected to the test trace is the first end. The edge lines of the first ends of the plurality of connecting parts extending along the first direction are collinear.

6. The array substrate according to any one of claims 2 to 5, wherein, The array substrate further includes: A driving circuit layer assembly is disposed on one side of the substrate, and the driving circuit layer assembly includes the connection pads and the test traces disposed at intervals. A first electrode layer is disposed on the side of the driving circuit layer group opposite to the substrate, and the first electrode layer includes a first electrode; A protective layer is disposed on the side of the first electrode layer opposite to the substrate. The second electrode layer is disposed on the side of the protective layer away from the substrate, and the second electrode layer includes a second electrode and the connection portion.

7. The array substrate according to claim 6, wherein, The array substrate further includes: Multiple first support portions are arranged in an array on the side of the protective layer away from the substrate and on the side of the multiple connecting portions away from the display area. The orthographic projection of a portion of the first support portions on the substrate overlaps with the orthographic projection of the test traces on the substrate.

8. The array substrate according to any one of claims 1 to 5, wherein, The array substrate further includes: A driving circuit layer group is disposed on one side of the substrate; the driving circuit layer group includes the display traces and the connection pads, or, when the array substrate includes test traces, the driving circuit layer group includes the display traces, the connection pads and the test traces; A first electrode layer is disposed on the side of the driving circuit layer group away from the substrate. The first electrode layer includes a first electrode and the connection portion. The other end of the connection portion is used to connect the test trace. A protective layer is disposed on the side of the first electrode layer opposite to the substrate. A second electrode layer is disposed on the side of the protective layer opposite to the substrate, and the second electrode layer includes a second electrode.

9. The array substrate according to claim 8, wherein, The array substrate further includes: Multiple first support portions are arranged in an array on the side of the protective layer away from the substrate. The orthographic projection of a portion of the first support portions on the substrate overlaps with the orthographic projection of the connecting portion on the substrate, and the orthographic projection of a portion of the first support portions on the substrate overlaps with the orthographic projection of the test trace on the substrate.

10. The array substrate according to claim 8, wherein, The driving circuit layer group includes: A gate layer is disposed on one side of the substrate. The gate layer includes the connection pad and the display trace, or the gate layer includes the display trace, the connection pad and the test trace. A gate insulating layer is disposed on the side of the gate layer opposite to the substrate. A source / drain layer is disposed on the side of the gate insulating layer opposite to the substrate. The source / drain layer includes a first auxiliary conductive portion, a second auxiliary conductive portion, and a third auxiliary conductive portion. The first auxiliary conductive portion is connected to the connection pad through a first via on the gate insulating layer. The second auxiliary conductive portion is connected to the display trace through a second via on the gate insulating layer. The third auxiliary conductive portion is connected to the test trace through a third via on the gate insulating layer. A buffer layer is disposed on the side of the source / drain layer opposite to the substrate. An organic layer is disposed on the side of the buffer layer opposite to the substrate, and the orthographic projection of the organic layer on the substrate covers the display traces.

11. The array substrate according to any one of claims 2 to 5, wherein, The connecting pad is located between the display trace and the test trace.

12. The array substrate according to any one of claims 1 to 5, wherein, The input level of the first pad group is higher than the input level of the second pad group.

13. The array substrate according to claim 12, wherein, On the side near the first edge line, the first pad group includes a frame start signal connection pad and a plurality of clock signal connection pads arranged sequentially in a direction away from the first edge line, and the second pad group includes a gate drive low level connection pad and a low level signal arranged sequentially in a direction away from the first edge line. And / or, on the side near the second edge line, the first pad group includes a frame start signal connection pad and a plurality of clock signal connection pads arranged sequentially in a direction away from the second edge line, and the second pad group includes a gate drive low level connection pad and a low level signal arranged sequentially in a direction away from the second edge line.

14. An array substrate mother plate, wherein, include: The array substrate mother plate is provided with a cutting line, which divides the array substrate mother plate into multiple array substrates, and the array substrate is the array substrate according to any one of claims 1 to 13. The cutting line includes: The first cutting line extends along the first direction; The second cutting line extends along the second direction; Wherein, a first cutting line is provided between two adjacent array substrates in the second direction, and two second cutting lines are provided between two adjacent array substrates in the first direction; or, two first cutting lines are provided between two adjacent array substrates in the second direction, and one second cutting line is provided between two adjacent array substrates in the first direction.

15. A display device, wherein, include: The array substrate is the array substrate as described in any one of claims 1 to 13.

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