Manufacturing method for solar cell, and solar cell

Abstract

The present application relates to a manufacturing method for a solar cell and a solar cell. The manufacturing method for a solar cell of the present application comprises the following steps: preparing a tunnel oxide layer and an intrinsic silicon material layer, that are sequentially stacked, on the back surface of a substrate; and doping the intrinsic silicon material layer by laser processing so as to respectively obtain a first doped silicon material layer and a second doped silicon material layer, and simultaneously forming a groove located between the first doped silicon material layer and the second doped silicon material layer and used for separating the first doped silicon material layer from the second doped silicon material layer, wherein the groove runs through the intrinsic silicon material layer and the tunnel oxide layer in a thickness direction of the substrate.

Description

Methods for fabricating solar cells, solar cells

[0001] This application claims priority to Chinese Patent Application No. 202411525050.1, filed on October 29, 2024, entitled "Method for Preparing Solar Cells, Solar Cells", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Technology

[0003] Back-contact solar cells are a type of solar cell structure used to improve cell efficiency. Their core design involves placing all the metal electrodes of the solar cell on the back of the cell, thereby ensuring that the front of the cell is not blocked by the metal grid lines. This increases the area of ​​the cell that absorbs sunlight, reduces optical losses, and improves photoelectric conversion efficiency.

[0004] In back-contact solar cells, the emitters are all located on the back of the cell and are composed of two different types of doped regions, which makes the fabrication process of back-contact solar cells more complex.

[0005] Summary of the Invention

[0006] Therefore, it is necessary to provide a method for fabricating a solar cell and a solar cell itself. The method for fabricating a solar cell in this application can achieve good fabrication results for back-contact solar cells with fewer process steps.

[0007] In a first aspect, this application provides a method for fabricating a solar cell, comprising the following steps:

[0008] A substrate is provided, the substrate having a front side and a back side disposed opposite to each other;

[0009] A tunneling oxide layer and an intrinsic silicon material layer are sequentially stacked on the back side of the substrate;

[0010] The intrinsic silicon material layer is doped by laser processing to obtain a first doped silicon material layer and a second doped silicon material layer with opposite doping types. At the same time, a groove is formed between the first doped silicon material layer and the second doped silicon material layer to separate the first doped silicon material layer and the second doped silicon material layer. The groove penetrates the intrinsic silicon material layer and the tunneling oxide layer along the thickness direction of the substrate.

[0011] In some embodiments, doping the intrinsic silicon material layer by laser processing includes the following steps:

[0012] A first paste and a second paste are respectively disposed at different positions at intervals on the surface of the intrinsic silicon material layer. The first paste includes a first doping element, and the second paste includes a second doping element. The doping types of the first doping element and the second doping element are opposite.

[0013] The intrinsic silicon material layer is doped by laser processing using the first slurry and the second slurry.

[0014] In some embodiments, the laser power of the laser processing is 30W to 80W.

[0015] In some embodiments, the maximum width of the laser-processed spot is 100 μm to 300 μm.

[0016] In some embodiments, the laser processing spot overlap rate is less than 80%.

[0017] In some embodiments, the laser treatment further includes the following step: annealing the laser-treated sample in a nitrogen or oxygen atmosphere.

[0018] In some embodiments, the annealing process takes 5 to 20 minutes.

[0019] In some embodiments, the annealing temperature is 200°C to 1000°C.

[0020] In some embodiments, before forming a tunneling oxide layer and an intrinsic silicon material layer that are sequentially stacked on the surface of the substrate, the method further includes the following step: forming a recess on the back side of the substrate, wherein the recess and the back side of the substrate have a height difference along the thickness direction of the substrate.

[0021] In some embodiments, forming a recess on the surface of the substrate includes the following steps:

[0022] A mask layer is formed on the back side of the substrate;

[0023] Part of the mask layer is removed by laser;

[0024] The recess is formed by etching the back side of the substrate exposed in the mask layer using an alkaline solution.

[0025] In some embodiments, the height difference between the recess and the back side of the substrate along the thickness direction of the substrate is greater than 1 μm.

[0026] In some embodiments, the thickness of the tunneling oxide layer is 1 nm to 3 nm.

[0027] In some embodiments, the thickness of the intrinsic silicon material layer is 80 nm to 300 nm.

[0028] Secondly, this application provides a solar cell prepared by any of the methods described above.

[0029] In some embodiments, the solar cell includes a substrate having a front side and a back side disposed opposite to each other, the front side of the substrate having a textured structure and having a first passivation antireflection layer disposed thereon;

[0030] The substrate has a recess on its back side, and there is a height difference between the recess and the back side of the substrate along the thickness direction of the substrate. A tunneling oxide layer, a first doped silicon material layer and a second passivation antireflection layer are sequentially stacked on the recess.

[0031] A tunneling oxide layer, a second doped silicon material layer, and a second passivation antireflection layer are sequentially stacked on the back side of the substrate and the recessed portion, which are offset from each other; the first doped silicon material layer and the second doped silicon material layer have opposite doping types; a groove is formed between the first doped silicon material layer and the second doped silicon material layer, and the groove penetrates the tunneling oxide layer along the thickness direction of the substrate; the bottom and walls of the groove are provided with the second passivation antireflection layer;

[0032] The solar cell further includes a first electrode and a second electrode disposed on the second passivation antireflection layer, wherein the first electrode is electrically in contact with the first doped silicon material layer, and the second electrode is electrically in contact with the second doped silicon material layer.

[0033] In the aforementioned method for fabricating solar cells, the intrinsic silicon material layer is doped using laser processing to obtain a first doped silicon material layer and a second doped silicon material layer. Simultaneously, a groove is formed between the first and second doped silicon material layers to separate them. This groove penetrates the intrinsic silicon material layer and the tunneling oxide layer along the thickness direction of the substrate. In other words, laser processing not only enables the fabrication of doped silicon material layers with different doping types on the back side of the solar cell but also forms a groove to isolate different types of emitters, reducing the number of production steps for back-contact solar cells. Furthermore, the laser-processed doping method improves the accuracy of the doped region fabrication, resulting in higher photoelectric conversion efficiency. The solar cell fabrication method of this application achieves good back-contact solar cell fabrication results with fewer process steps. Attached Figure Description

[0034] Figure 1 is a schematic diagram of the structure of forming a mask layer on the back side of the substrate;

[0035] Figure 2 is a schematic diagram of the structure with part of the mask layer removed from the structure shown in Figure 1;

[0036] Figure 3 is a schematic diagram of a structure in which a recess is formed and the mask layer is removed based on the structure shown in Figure 2.

[0037] Figure 4 is a schematic diagram of the structure in which a tunneling oxide layer and an intrinsic silicon material layer are formed on the basis of the structure shown in Figure 3;

[0038] Figure 5 is a schematic diagram of the structure for forming the first slurry and the second slurry based on the structure shown in Figure 4;

[0039] Figure 6 is a schematic diagram of the structure of the first doped silicon material layer, the second doped silicon material layer and the groove prepared based on the structure shown in Figure 5;

[0040] Figure 7 is a schematic diagram of the structure after texturing based on the structure shown in Figure 6;

[0041] Figure 8 is a schematic diagram of the structure in which the first passivation anti-reflection layer and the second passivation anti-reflection layer are formed based on the structure shown in Figure 7;

[0042] Figure 9 is a schematic diagram of the structure in which the first electrode and the second electrode are formed based on the structure shown in Figure 8.

[0043] Explanation of reference numerals in the attached figures: 10, substrate; 20, mask layer; 30, recess; 40, tunneling oxide layer; 50, intrinsic silicon material layer; 61, first paste; 62, second paste; 71, first doped silicon material layer; 72, second doped silicon material layer; 80, trench; 91, first passivation antireflection layer; 92, second passivation antireflection layer; 101, first electrode; 102, second electrode. Detailed Implementation

[0044] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0048] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0049] Referring to Figures 1 to 9, one embodiment of this application provides a method for fabricating a solar cell, comprising the following steps:

[0050] A substrate 10 is provided, the substrate 10 having a front side and a back side disposed opposite to each other;

[0051] A tunneling oxide layer 40 and an intrinsic silicon material layer 50 are sequentially stacked on the back side of the substrate 10.

[0052] The intrinsic silicon material layer 50 is doped by laser processing to obtain a first doped silicon material layer 71 and a second doped silicon material layer 72 with opposite doping types. At the same time, a groove 80 is formed between the first doped silicon material layer 71 and the second doped silicon material layer 72 to separate the first doped silicon material layer 71 and the second doped silicon material layer 72. The groove 80 penetrates the intrinsic silicon material layer 50 and the tunnel oxide layer 40 along the thickness direction of the substrate 10.

[0053] In the aforementioned method for fabricating solar cells, the intrinsic silicon material layer 50 is doped using laser processing to obtain a first doped silicon material layer 71 and a second doped silicon material layer 72. Simultaneously, a groove 80 is formed between the first and second doped silicon material layers 71 and 72 to separate them. The groove 80 penetrates the intrinsic silicon material layer 50 and the tunneling oxide layer 40 along the thickness direction of the substrate 10. In other words, laser processing not only enables the fabrication of doped silicon material layers with different doping types on the back side of the solar cell but also forms the groove 80 to isolate different types of emitters, reducing the number of production steps for back-contact solar cells. Furthermore, the laser-processed doping method improves the accuracy of the doped region fabrication, resulting in higher photoelectric conversion efficiency. The solar cell fabrication method of this application achieves good back-contact solar cell fabrication results with fewer process steps.

[0054] In some embodiments, the method for fabricating a solar cell includes the following steps:

[0055] S10: Provide a substrate 10, which has a front side and a back side disposed opposite to each other; a recess 30 is formed on the back side of the substrate 10, and there is a height difference between the recess 30 and the back side of the substrate 10 along the thickness direction of the substrate 10.

[0056] In some embodiments, forming a recess 30 on the back side of the substrate 10 includes the following steps:

[0057] A mask layer 20 is formed on the back side of the substrate 10;

[0058] Part of the mask layer 20 is removed by laser;

[0059] An alkaline solution is used to etch the back side of the substrate 10 exposed to the mask layer 20 to form a recess 30.

[0060] Forming a recess 30 on the back side allows for a certain height difference between the recess 30 and the back side of the substrate 10. By using this height difference in conjunction with the thickness of each film layer, it is convenient to achieve isolation between doped silicon material layers of different doping types.

[0061] Referring to Figures 1 to 3, Figure 1 is a schematic diagram of a structure in which a mask layer 20 is formed on the back side of a substrate 10; Figure 2 is a schematic diagram of a structure in which part of the mask layer 20 is removed from the structure shown in Figure 1; and Figure 3 is a schematic diagram of a structure in which a recessed portion 30 is formed and the mask layer 20 is removed from the structure shown in Figure 2.

[0062] In some embodiments, the height difference between the recess 30 and the back surface of the substrate 10 along the thickness direction of the substrate 10 is more than 1 μm.

[0063] In some embodiments, the material of the mask layer 20 includes silicon oxide.

[0064] In some embodiments, the mask preparation method includes at least one of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition, and atomic layer deposition.

[0065] In some embodiments, a portion of the mask layer 20 is removed by laser. The laser wavelength is 532nm, the laser power is 30W to 80W, the laser spot size is a square spot of 100μm to 300μm, and the horizontal spot overlap rate is controlled to be below 80%.

[0066] In some embodiments, the alkaline solution comprises an alkaline solution and water in a volume ratio of 1:10.

[0067] In some embodiments, the alkaline solution includes at least one of NaOH and KOH.

[0068] In some embodiments, the concentration of the alkaline solution is 45 wt% to 55 wt%.

[0069] Optionally, the concentration of the alkaline solution is 45wt%, 46wt%, 47wt%, 48wt%, 49wt%, 50wt%, 51wt%, 52wt%, 53wt%, 54wt%, or 55wt%, or the concentration of the alkaline solution may be within the range of any two of the above concentrations.

[0070] In some embodiments, the temperature at which the back side of the substrate 10 exposed to the mask layer 20 is etched using an alkaline solution is 65°C to 90°C.

[0071] Optionally, the etching temperature for the back side of the substrate 10 exposed to the mask layer 20 using alkaline solution is 65°C, 70°C, 75°C, 80°C, 85°C or 90°C, or the etching temperature for the back side of the substrate 10 exposed to the mask layer 20 using alkaline solution can also be within the range of any two of the above temperatures.

[0072] In some embodiments, the etching time of the back side of the substrate 10 exposed to the mask layer 20 using an alkaline solution is 180s to 420s.

[0073] Optionally, the etching time for the back side of the substrate 10 exposed to the mask layer 20 using alkaline solution is 180s, 200s, 220s, 250s, 280s, 300s, 320s, 350s, 380s, 400s, or 420s. Alternatively, the etching time for the back side of the substrate 10 exposed to the mask layer 20 using alkaline solution can also be within any two of the above-mentioned time ranges.

[0074] Within the range of process parameters for etching the back side of the substrate 10 exposed to the mask layer 20 using alkaline solution, a better preparation effect of the recess 30 can be achieved.

[0075] In some embodiments, after forming the recess 30, the following steps are further included:

[0076] Use acid to remove the remaining mask layer 20.

[0077] In some embodiments, the acid solution comprises a hydrofluoric acid solution and water in a volume ratio of 1:20.

[0078] In some embodiments, the concentration of the hydrofluoric acid solution is 45 wt% to 50 wt%.

[0079] Optionally, the concentration of the hydrofluoric acid solution is 45 wt%, 46 wt%, 47 wt%, 48 wt%, 49 wt%, or 50 wt%, or the concentration of the hydrofluoric acid solution may be within any two of the above concentrations.

[0080] In some embodiments, the remaining mask layer 20 is removed using acid at room temperature.

[0081] In some embodiments, the time for removing the remaining mask layer 20 with acid is 60s to 240s.

[0082] Optionally, the time for removing the remaining mask layer 20 with acid is 60s, 80s, 100s, 120s, 140s, 160s, 180s, 200s, 220s or 240s, or the time for removing the remaining mask layer 20 with acid can be within any two of the above times.

[0083] S20: A tunneling oxide layer 40 and an intrinsic silicon material layer 50 are sequentially stacked on the back side of the substrate 10.

[0084] Referring to Figure 4, which is a schematic diagram of a structure in which a tunneling oxide layer 40 and an intrinsic silicon material layer 50 are formed based on the structure shown in Figure 3. It can be understood that the tunneling oxide layer 40 and the intrinsic silicon material layer 50 are sequentially stacked on the back side of the substrate 10, meaning that the back side of the substrate 10 and the recessed portion 30 are both provided with sequentially stacked tunneling oxide layers 40 and intrinsic silicon material layers 50.

[0085] In some embodiments, the material of the tunneling oxide layer 40 includes silicon oxide.

[0086] In some embodiments, the thickness of the tunneling oxide layer 40 is 1 nm to 3 nm.

[0087] Optionally, the thickness of the tunneling oxide layer 40 is 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm or 3 nm, or the thickness of the tunneling oxide layer 40 may be within any two of the above thicknesses.

[0088] In some embodiments, the tunneling oxide layer 40 is prepared by low-pressure chemical vapor deposition.

[0089] In some embodiments, the deposition temperature of the tunnel oxide layer 40 is 500°C to 800°C.

[0090] Optionally, the deposition temperature of the tunneling oxide layer 40 is 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, or 800°C, or the deposition temperature of the tunneling oxide layer 40 may be within the range of any two of the above deposition temperatures.

[0091] In some embodiments, the thickness of the intrinsic silicon material layer 50 is 80 nm to 300 nm.

[0092] Optionally, the thickness of the intrinsic silicon material layer 50 is 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, 220nm, 250nm, 280nm or 300nm, or the thickness of the intrinsic silicon material layer 50 may be within any two of the above thicknesses.

[0093] In some embodiments, the intrinsic silicon material layer 50 is an intrinsic polycrystalline silicon layer.

[0094] In some embodiments, the intrinsic silicon material layer 50 is prepared by low-pressure chemical vapor deposition.

[0095] In some embodiments, the silane flow rate is 300 sccm to 1000 sccm during the preparation of the intrinsic silicon material layer 50.

[0096] Optionally, in the preparation of the intrinsic silicon material layer 50, the silane flow rate is 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm or 1000 sccm, or the silane flow rate can be within the range of any two of the above flow rates.

[0097] In some embodiments, the deposition temperature of the intrinsic silicon material layer 50 is 500°C to 900°C.

[0098] Optionally, the deposition temperature of the intrinsic silicon material layer 50 is 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, or 900°C, or the deposition temperature of the intrinsic silicon material layer 50 may be within the range of any two of the above temperatures.

[0099] S30: A first paste 61 and a second paste 62 are respectively disposed at different positions on the surface of the intrinsic silicon material layer 50. The first paste 61 includes a first doping element, and the second paste 62 includes a second doping element. The doping types of the first doping element and the second doping element are opposite.

[0100] Referring to Figure 5, Figure 5 is a structural schematic diagram of forming the first slurry 61 and the second slurry 62 based on the structure shown in Figure 4.

[0101] In some embodiments, the following steps are included before the intrinsic silicon material layer 50 is doped with the first slurry 61 and the second slurry 62 by laser processing:

[0102] The first slurry 61 and the second slurry 62 are dried and cured.

[0103] In some embodiments, the first slurry 61 and the second slurry 62 are boron slurry and phosphorus slurry, respectively.

[0104] In some embodiments, the printing width of the phosphate paste is 300 μm to 500 μm.

[0105] Optionally, the printing width of the phosphate paste is 300μm, 350μm, 400μm, 450μm or 500μm, or the printing width of the phosphate paste may be within the range of any two of the above widths.

[0106] In some embodiments, the solid content of the phosphate paste is 15% to 35%.

[0107] Optionally, the solid content of the phosphate syrup is 15%, 20%, 25%, 30%, or 35%, or the solid content of the phosphate syrup may be within the range of any two of the above solid contents.

[0108] In some embodiments, the viscosity of the phosphate paste is 20 Pa·s to 50 Pa·s.

[0109] Optionally, the viscosity of the phosphate paste is 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s or 50 Pa·s, or the viscosity of the phosphate paste may be within the range of any two of the above viscosity values.

[0110] In some embodiments, the printing width of the boron paste is 500 μm to 700 μm.

[0111] Optionally, the printing width of the boron paste is 500μm, 550μm, 600μm, 650μm or 700μm, or the printing width of the boron paste may be within any two of the above widths.

[0112] In some embodiments, the solid content of the boron paste is 20% to 55%.

[0113] Optionally, the solid content of the boron paste is 20%, 25%, 30%, 35%, 40%, 45%, 50%, or 55%, or the solid content of the boron paste may be within the range of any two of the above solid contents.

[0114] In some embodiments, the viscosity of the boron paste is 20 Pa·s to 50 Pa·s.

[0115] Optionally, the viscosity of the boron paste is 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s, or 50 Pa·s, or the viscosity of the boron paste may be within any two of the above viscosity ranges.

[0116] Within the parameter ranges of the aforementioned phosphate paste and boron paste, a good printing effect of the paste on the intrinsic silicon material layer 50 can be achieved, thereby achieving a more uniform doping effect through laser processing.

[0117] S40: The intrinsic silicon material layer 50 is doped by laser processing with the first paste 61 and the second paste 62 to obtain the first doped silicon material layer 71 and the second doped silicon material layer 72 respectively. At the same time, a groove 80 is formed between the first doped silicon material layer 71 and the second doped silicon material layer 72 to separate the first doped silicon material layer 71 and the second doped silicon material layer 72. The groove 80 penetrates the intrinsic silicon material layer 50 and the tunnel oxide layer 40 along the thickness direction of the substrate 10.

[0118] Referring to Figure 6, which is a schematic diagram of the structure of the first doped silicon material layer 71, the second doped silicon material layer 72, and the groove 80 prepared based on the structure shown in Figure 5, it can be understood that the groove 80 can be prepared by laser processing in the area between the area where the first paste 61 is printed and the area where the second paste 62 is printed, thereby achieving the isolation of the first doped silicon material layer 71 and the second doped silicon material layer 72.

[0119] In some embodiments, the laser power for laser processing is 30W to 80W.

[0120] Optionally, the laser power for laser processing is 30W, 40W, 50W, 60W, 70W or 80W, or the laser power for laser processing can be within the range of any two of the above powers.

[0121] In some embodiments, the maximum width of the laser-processed spot is 100 μm to 300 μm.

[0122] Optionally, the maximum width of the laser-processed spot is 100μm, 150μm, 200μm, 250μm or 300μm, or the maximum width of the laser-processed spot can be within any two of the above widths.

[0123] In some of these embodiments, the overlap rate of the laser-processed spot is less than 80%.

[0124] In some embodiments, the laser-processed spot is a square spot.

[0125] In some embodiments, the laser processing scans the area of ​​the printed boron paste with a width of 300 μm to 800 μm.

[0126] Optionally, the scanning width of the area of ​​the printed boron paste by laser processing is 300μm, 400μm, 500μm, 600μm, 700μm or 800μm, or the scanning width of the area of ​​the printed boron paste by laser processing can also be within the range of any two of the above widths.

[0127] In some embodiments, the laser processing scans the area of ​​the printed phosphate paste with a width of 200 μm to 600 μm.

[0128] Optionally, the scanning width of the area of ​​the printed phosphate paste by laser processing is 200μm, 300μm, 400μm, 500μm or 600μm, or the scanning width of the area of ​​the printed phosphate paste by laser processing can also be within the range of any two of the above widths.

[0129] Within the range of parameters for the aforementioned laser processing, a good doping effect can be achieved on the intrinsic silicon material layer 50 through the slurry.

[0130] In some embodiments, the width of the groove 80 is 100 μm to 200 μm.

[0131] Optionally, the width of the groove 80 is 100μm, 120μm, 140μm, 160μm, 180μm or 200μm, or the width of the groove 80 may be within any two of the above widths.

[0132] In some embodiments, the laser treatment further includes the following step: annealing the laser-treated sample in a nitrogen or oxygen atmosphere.

[0133] In some embodiments, the annealing process takes 5 to 20 minutes.

[0134] Optionally, the annealing time can be 5 min, 8 min, 10 min, 12 min, 15 min, 18 min or 20 min, or the annealing time can be within any two of the above times.

[0135] In some embodiments, the annealing temperature is 200°C to 1000°C.

[0136] Optionally, the annealing temperature is 200°C, 400°C, 600°C, 800°C, or 1000°C, or the annealing temperature may be within any two of the above temperatures.

[0137] S50: Texturing the sample after preparing the groove 80.

[0138] Referring to Figure 7, which is a schematic diagram of the structure after texturing based on the structure shown in Figure 6, it can be understood that texturing the sample after preparing the groove 80 can form a textured surface structure on the front side of the substrate 10 and the bottom of the groove 80.

[0139] In some of these embodiments, an alkaline solution is used to texturize the sample.

[0140] In some embodiments, the texturing temperature is 70°C to 85°C.

[0141] Optionally, the flocking temperature is 70°C, 72°C, 75°C, 78°C, 80°C, 82°C or 85°C, or the flocking temperature may be within any two of the above temperatures.

[0142] In some embodiments, the texturing time is 300s to 420s.

[0143] Optionally, the fabrication time can be 300s, 320s, 340s, 360s, 380s, 400s, or 420s, or the fabrication time can be within any two of the above times.

[0144] S60: A first passivation antireflection layer 91 and a second passivation antireflection layer 92 are respectively prepared on the front and back sides of the substrate 10.

[0145] Referring to Figure 8, which is a schematic diagram of a structure in which a first passivation antireflection layer 91 and a second passivation antireflection layer 92 are formed based on the structure shown in Figure 7. It can be understood that the first passivation antireflection layer 91 covers the front side of the substrate 10, and the second passivation antireflection layer 92 covers the back side of the substrate 10, as well as the bottom and walls of the groove 80.

[0146] In some embodiments, the first passivation antireflection layer 91 includes a first passivation film and a first antireflection film stacked together, with the first antireflection film disposed on the surface of the first passivation film away from the substrate 10.

[0147] In some embodiments, the material of the first passivation film includes aluminum oxide.

[0148] In some embodiments, the thickness of the first passivation film is 3 nm to 10 nm.

[0149] Optionally, the thickness of the first passivation film is 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, or the thickness of the first passivation film may be within any two of the above thicknesses.

[0150] In some of these embodiments, the first passivation film is prepared by atomic layer deposition.

[0151] In some embodiments, the material of the first antireflective film includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0152] In some embodiments, the thickness of the first antireflective film is 70 nm to 110 nm.

[0153] Optionally, the thickness of the first antireflective film is 70nm, 80nm, 90nm, 100nm or 110nm, or the thickness of the first antireflective film may be within any two of the above thicknesses.

[0154] In some embodiments, the refractive index of the first antireflective coating is 2 to 2.4.

[0155] Optionally, the refractive index of the first antireflective coating is 2, 2.1, 2.2, 2.3 or 2.4, or the refractive index of the first antireflective coating may be within the range of any two of the above reflectivities.

[0156] In some embodiments, the first antireflective film is prepared by plasma-enhanced chemical vapor deposition.

[0157] In some embodiments, the second passivation antireflection layer 92 includes a second passivation film and a second antireflection film stacked together, with the second antireflection film disposed on the surface of the second passivation film away from the substrate 10.

[0158] In some of these embodiments, the material of the second passivation film includes aluminum oxide.

[0159] In some embodiments, the thickness of the second passivation film is 3 nm to 10 nm.

[0160] Optionally, the thickness of the second passivation film is 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, or the thickness of the second passivation film can be within any two of the above thicknesses.

[0161] In some embodiments, the second passivation film is prepared by atomic layer deposition.

[0162] In some embodiments, the material of the second antireflective film includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0163] In some embodiments, the thickness of the second antireflective film is 70 nm to 110 nm.

[0164] Optionally, the thickness of the second antireflective film is 70nm, 80nm, 90nm, 100nm or 110nm, or the thickness of the second antireflective film may be within any two of the above thicknesses.

[0165] In some embodiments, the refractive index of the second antireflective coating is 2 to 2.4.

[0166] Optionally, the refractive index of the second antireflective coating is 2, 2.1, 2.2, 2.3 or 2.4, or the refractive index of the second antireflective coating may be within the range of any two of the above reflectivities.

[0167] In some embodiments, the first antireflective film is prepared by plasma-enhanced chemical vapor deposition.

[0168] S70: A first electrode 101 and a second electrode 102 are prepared on the surface of the second passivation antireflection layer 92. The first electrode 101 is in electrical contact with the first doped silicon material layer 71, and the second electrode 102 is in electrical contact with the second doped silicon material layer 72.

[0169] Referring to Figure 9, which is a schematic diagram of a structure in which a first electrode 101 and a second electrode 102 are formed based on the structure shown in Figure 8.

[0170] In some embodiments, the first electrode 10191 and the second electrode 10292 are prepared by silver paste sintering.

[0171] In some of these embodiments, the sintering temperature is 700°C to 900°C.

[0172] Optionally, the sintering temperature is 700°C, 750°C, 800°C, 850°C or 900°C, or the sintering temperature may be within the range of any two of the above temperatures.

[0173] Another embodiment of this application provides a solar cell prepared by any of the above-described methods.

[0174] Referring again to FIG9, in some embodiments, the solar cell includes a substrate 10 having a front side and a back side disposed opposite to each other, the front side of the substrate 10 having a textured structure and having a first passivation antireflection layer 91 disposed thereon.

[0175] The back side of the substrate 10 has a recess 30, and there is a height difference between the recess 30 and the back side of the substrate 10 along the thickness direction of the substrate 10. A tunneling oxide layer 40, a first doped silicon material layer 71 and a second passivation antireflection layer 92 are sequentially stacked on the recess 30.

[0176] A tunneling oxide layer 40, a second doped silicon material layer 72, and a second passivation antireflection layer 92 are sequentially stacked on the back side of the substrate 10 and the recessed portion 30, which are staggered. The doping types of the first doped silicon material layer 71 and the second doped silicon material layer 72 are opposite. A groove 80 is formed between the first doped silicon material layer 71 and the second doped silicon material layer 72, and the groove 80 penetrates the tunneling oxide layer 40 along the thickness direction of the substrate 10. The second passivation antireflection layer 92 is provided on the bottom and walls of the groove 80.

[0177] The solar cell also includes a first electrode 101 and a second electrode 102 disposed on the second passivation antireflection layer 92. The first electrode 101 is in electrical contact with the first doped silicon material layer 71, and the second electrode 102 is in electrical contact with the second doped silicon material layer 72.

[0178] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0179] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A method for fabricating a solar cell, comprising the following steps: A substrate is provided, the substrate having a front side and a back side disposed opposite to each other; A tunneling oxide layer and an intrinsic silicon material layer are sequentially stacked on the back side of the substrate; The intrinsic silicon material layer is doped by laser processing to obtain a first doped silicon material layer and a second doped silicon material layer with opposite doping types. At the same time, a groove is formed between the first doped silicon material layer and the second doped silicon material layer to separate the first doped silicon material layer and the second doped silicon material layer. The groove penetrates the intrinsic silicon material layer and the tunneling oxide layer along the thickness direction of the substrate.

2. The method for preparing a solar cell according to claim 1, wherein, Doping the intrinsic silicon material layer by laser processing includes the following steps: A first paste and a second paste are respectively disposed at different positions at intervals on the surface of the intrinsic silicon material layer. The first paste includes a first doping element, and the second paste includes a second doping element. The doping types of the first doping element and the second doping element are opposite. The intrinsic silicon material layer is doped by laser processing using the first slurry and the second slurry.

3. The method for preparing a solar cell according to any one of claims 1 to 2, wherein, The laser power of the laser processing is 30W to 80W.

4. The method for preparing a solar cell according to any one of claims 1 to 3, wherein, The maximum width of the laser-processed spot is 100μm to 300μm.

5. The method for preparing a solar cell according to any one of claims 1 to 4, wherein, The overlap rate of the laser-processed spot is below 80%.

6. The method for preparing a solar cell according to any one of claims 1 to 5, wherein, The laser treatment process further includes the following step: annealing the laser-treated sample in a nitrogen or oxygen atmosphere.

7. The method for preparing a solar cell according to claim 6, wherein, The annealing process takes 5 to 20 minutes.

8. The method for preparing a solar cell according to any one of claims 6 to 7, wherein, The annealing temperature is 200℃~1000℃.

9. The method for preparing a solar cell according to any one of claims 1 to 8, wherein, Before preparing a tunneling oxide layer and an intrinsic silicon material layer that are sequentially stacked on the surface of the substrate, the method further includes the following step: preparing a recess on the back side of the substrate, wherein the recess and the back side of the substrate have a height difference along the thickness direction of the substrate.

10. The method for preparing a solar cell according to claim 9, wherein, The process of creating a recess on the surface of the substrate includes the following steps: A mask layer is formed on the back side of the substrate; Part of the mask layer is removed by laser; The recess is formed by etching the back side of the substrate exposed in the mask layer using an alkaline solution.

11. The method for preparing a solar cell according to claim 10, wherein, The height difference between the recess and the back side of the substrate along the thickness direction of the substrate is more than 1 μm.

12. The method for preparing a solar cell according to any one of claims 10-11, wherein, The thickness of the tunneling oxide layer is 1 nm to 3 nm.

13. The method for preparing a solar cell according to any one of claims 10 to 12, wherein, The thickness of the intrinsic silicon material layer is 80 nm to 300 nm.

14. A solar cell, prepared by the method of any one of claims 1 to 13.

15. The solar cell according to claim 14, wherein, It includes a substrate having a front side and a back side arranged opposite to each other, wherein the front side of the substrate has a textured structure and is provided with a first passivation antireflection layer; The substrate has a recess on its back side, and there is a height difference between the recess and the back side of the substrate along the thickness direction of the substrate. A tunneling oxide layer, a first doped silicon material layer and a second passivation antireflection layer are sequentially stacked on the recess. A tunneling oxide layer, a second doped silicon material layer, and a second passivation antireflection layer are sequentially stacked on the back side of the substrate and the recessed portion, which are offset from each other; the first doped silicon material layer and the second doped silicon material layer have opposite doping types; a groove is formed between the first doped silicon material layer and the second doped silicon material layer, and the groove penetrates the tunneling oxide layer along the thickness direction of the substrate; the bottom and walls of the groove are provided with the second passivation antireflection layer; The solar cell further includes a first electrode and a second electrode disposed on the second passivation antireflection layer, wherein the first electrode is electrically in contact with the first doped silicon material layer, and the second electrode is electrically in contact with the second doped silicon material layer.

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