Embedded substrate, method for manufacturing embedded substrate, power supply apparatus, and electronic device

Abstract

An embedded substrate, a method for manufacturing the embedded substrate, a power supply apparatus, and an electronic device. The embedded substrate comprises a core holder and a chip embedded in the core holder. A front build up layer of the embedded substrate comprises a first front build up layer covering a first surface of the core holder. A front surface of the chip is disposed facing the first surface of the core holder. The front surface of the chip comprises a pad and an inorganic film layer located on the surface of the chip. A first conduction structure is provided between a circuit layer of the first front build up layer and the pad. One end of the first conduction structure passes through a dielectric layer of the first front build up layer and is electrically connected to the circuit layer, and the other end thereof passes through the inorganic film layer and is electrically connected to the pad. An outer peripheral surface of the first conduction structure is bonded to the dielectric layer of the first front build up layer and the inorganic film layer, respectively. The inorganic film layer can prevent oxidation of the pad. The first conduction structure is formed by fully utilizing the size of the chip pad, thereby improving current carrying capability while achieving good thermal conductivity, and mitigating the effects of parasitics.

Description

Embedded substrate, method for manufacturing embedded substrate, power supply device and electronic device

[0001] This application claims priority to Chinese Patent Application No. 202411515932.X, filed on October 28, 2024, entitled "Embedded Substrate, Method for Manufacturing Embedded Substrate, Power Supply Device and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic component packaging technology, and in particular to an embedded substrate, a method for manufacturing the embedded substrate, a power supply device, and an electronic device. Background Technology

[0003] Embedded substrate technology embeds electronic components, such as but not limited to chips, resistors, capacitors, and inductors, within a substrate. These components are interconnected and fan-out via external circuitry, forming highly integrated, high-density functional modules. Embedded substrate technology can be used in various application scenarios. As product functions continue to evolve, achieving high current, high heat dissipation, and high reliability has become the core requirements for embedded substrates.

[0004] A typical power chip packaging module embeds components such as chips within a core board structure. Add-on layers are stacked on the core board surface to achieve highly integrated circuitry for interconnection. Typically, a redistribution layer (RDL) is formed on the front side of the chip, with RDL pads exposed through openings in the polyimide (PI) layer. Blind vias are formed through the add-on layers adjacent to the chip, establishing electrical connections between the chip side and the add-on layer side. The cross-sectional dimensions of these blind vias are related to the dimensions of the polyimide open (PIO) and the relative positional accuracy of the blind via and the PIO. This limits the cross-sectional dimensions of the blind vias, making it impossible to meet performance requirements such as high current, high heat dissipation, low parasitics, and high reliability. Summary of the Invention

[0005] This application provides an embedded substrate, a method for manufacturing the embedded substrate, a power supply device, and an electronic device. By optimizing the embedded substrate structure, high current, high heat dissipation, low parasitics, and high reliability are achieved.

[0006] The first aspect of this application provides an embedded substrate, which includes a core retainer, a front augmentation layer, and a chip embedded in the core retainer. The core retainer includes a first surface and a second surface. The front augmentation layer includes a first front augmentation layer covering the first surface and is bonded to the front surface of the chip. The front surface of the chip is disposed facing the first surface of the core retainer and includes pads and an inorganic film layer located on the surface of the chip. The first front augmentation layer includes a dielectric layer and a circuit layer stacked together. A first conductive structure is disposed between the circuit layer of the first front augmentation layer and the pads. One end of the first conductive structure passes through the dielectric layer of the first front augmentation layer and is electrically connected to the circuit layer, and the other end passes through the inorganic film layer and is electrically connected to the pads. The outer peripheral surface of the first conductive structure is respectively bonded to the dielectric layer and the inorganic film layer of the first front augmentation layer.

[0007] This configuration, through the formation of a dense passivation layer using an inorganic film covering the chip surface, effectively blocks the diffusion of moisture and mobile ions, preventing chip pad oxidation and effectively avoiding interface delamination problems between the first conductive structure and the pads, and between the dielectric layer and the pads caused by pad oxidation. This overcomes the potential adverse effects of environmental factors on chip performance. Simultaneously, the first conductive structure, electrically connected between the add-on circuit layer and the pads, passes through and adheres to the inorganic film layer, maximizing the utilization of the chip pad size to construct the first conductive structure. This results in a first conductive structure with a large current-carrying cross-section, effectively improving current carrying capacity while also providing good thermal conductivity. Here, "current-carrying cross-section" refers to the cross-section perpendicular to the embedded substrate where the corresponding conductive structure intersects. In addition to improving chip current carrying capacity, it also reduces the resistance value along the current-carrying path, effectively mitigating the effects of parasitic generation.

[0008] Furthermore, the inorganic film can form chemical bonds with the build-up dielectric layer and the pads, thereby achieving high bonding strength, improving interfacial bonding strength and reliability, and providing a solid technical guarantee for the stable operation of the chip. For the non-iso-network pads of the chip, the inorganic film effectively blocks the diffusion of water vapor and mobile ions, avoiding the influence of water vapor and ion migration, and providing reliable electrical isolation between non-iso-networks. Overall, it exhibits good reliability.

[0009] Furthermore, based on the high adhesion between the inorganic film layer and the substrate dielectric layer and pads, holes can be directly formed on the dielectric layer and inorganic film layer, such as, but not limited to, laser drilling, to construct the first conductive structure. Compared to the traditional method of creating holes by opening windows in the PI layer on the front side of the chip, this solution can further reduce the difficulty of the hole-forming process and provide better manufacturability.

[0010] For example, the core retainer may be a core board, or the core retainer may be a filler layer made of filler material.

[0011] Based on the first aspect, this application also provides a first implementation of the first aspect: the material of the inorganic film layer is alumina, silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, aluminum nitride, titanium nitride, silicon nitride, or tantalum nitride; or, the material of the inorganic film layer is at least two of alumina, silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, aluminum nitride, titanium nitride, silicon nitride, and tantalum nitride. Based on the above inorganic materials, the inorganic film layer covering the front side of the chip can be realized using atomic layer deposition (ALD) technology. Through the layer-by-layer growth of single-atom films, the atoms of the inorganic material are deposited layer by layer on the front side of the chip, thereby forming an inorganic film layer with high adhesion and good density. In other practical applications, the inorganic film layer can also be realized using chemical vapor deposition (CVD) technology to obtain an inorganic film layer with good density, low residual stress, and excellent adhesion.

[0012] Based on the first aspect, or the first embodiment of the first aspect, this application also provides a second embodiment of the first aspect: the thickness of the inorganic film layer is 1nm to 500nm. With this configuration, while protecting the chip from environmental factors, the thinner inorganic film layer has better hole-forming processability, which can further improve the yield of directly forming holes on the inorganic film layer.

[0013] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, this application also provides a third embodiment of the first aspect: the material of the dielectric layer of the first frontal reinforcement layer is an organic material, such as, but not limited to, Ajinomoto film or prepreg. In this way, a dielectric layer with excellent insulation properties and mechanical strength can be obtained through vacuum molding and thermosetting / hot pressing processes, further enhancing the adhesion to the inorganic film layer and improving the interfacial bonding strength and reliability.

[0014] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, this application also provides a fourth implementation of the first aspect: the pad is electrically connected to a plurality of first conductive structures, and the plurality of first conductive structures are spaced apart. That is, each pad can be respectively provided with a plurality of first conductive structures, and except for the local position where the first conductive structure contacts the pad, there is no inorganic film layer, the dielectric layer and the pad can maintain good adhesion through the inorganic film layer, thereby enhancing the interface bonding strength and reliability.

[0015] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, this application also provides a fifth implementation of the first aspect: the shape of the current-carrying cross-section of the first conductive structure is the same as the shape of the corresponding pad. In this way, the size of the chip pad can be fully utilized to configure the first conductive structure, and a current-carrying cross-section that approximates the shape and size of the pad can be constructed to maximize the conductive current-carrying cross-section.

[0016] In practical applications, the current-carrying cross-section of the first conductive structure can be circular, elliptical, polygonal, or strip-shaped. For example, corresponding to a rectangular pad, the current-carrying cross-section of the first conductive structure can be rectangular; corresponding to a hexagonal pad, the current-carrying cross-section of the first conductive structure can be hexagonal.

[0017] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, this application also provides a sixth embodiment of the first aspect: the embedded substrate further includes a back-side enhancement layer covering the second side of the core retainer. In this way, interconnection between components and connection to external circuits can be realized according to product functional requirements, exhibiting good adaptability and designability.

[0018] In practical applications, the embedded substrate may also include multiple electronic components embedded in the core retainer, at least one of which is a capacitor or a resistor.

[0019] A second aspect of this application provides a method for manufacturing an embedded substrate, comprising the following steps: forming an inorganic film layer on the front side of a chip, the inorganic film layer covering the chip body and its surface pads; preparing a core holder to form an embedded frame; embedding the chip within the embedded groove of the core holder and performing back-side filling and pressing; performing front-side filling and pressing to form a first front-side uplayer dielectric layer; creating openings in the dielectric layer corresponding to the pads and removing the inorganic film layer at the bottom of the openings; depositing copper to form a first conductive structure and electroplating to form a first front-side uplayer circuit layer, wherein the outer peripheral surface of the first conductive structure is respectively bonded to the dielectric layer of the first front-side uplayer and the inorganic film layer. This allows for the maximum utilization of the chip pad size to construct the first conductive structure, resulting in a first conductive structure with a large current-carrying cross-section, effectively improving current carrying capacity and providing good thermal conductivity. Furthermore, the inorganic film layer has high bonding strength with both the uplayer dielectric layer and the pads, improving interface bonding strength and reliability.

[0020] In practical applications, lasers or mechanical processing can be used to create holes in the dielectric layer corresponding to the pads, and the inorganic film layer at the bottom of the holes can be removed.

[0021] Based on the second aspect, this application also provides a first implementation method for the second aspect: the inorganic film layer is formed by atomic layer deposition or chemical vapor deposition. Based on inorganic materials, ALD technology can form an inorganic film layer with high adhesion on the front side of the chip, while CVD technology can obtain an inorganic film layer with good density, low residual stress, and excellent adhesion.

[0022] Based on the second aspect, or the first implementation of the second aspect, this application also provides a second implementation of the second aspect: while forming the dielectric layer of the first front-side enhancement layer, a circuit layer copper is also formed; correspondingly, the circuit layer copper is patterned before the corresponding pads are opened in the dielectric layer. Overall, it has good processability.

[0023] A third aspect of this application provides a power supply device including a chip and an inductor. The chip is embedded in a package using an embedded substrate as described above, and the inductor is surface-mounted on the embedded substrate. A dense passivation layer is formed based on an inorganic film covering the chip surface, effectively avoiding interface delamination problems between the pads and the first conductive structure, and between the dielectric layer and the pads caused by pad oxidation. Simultaneously, the first conductive structure passes through and adheres to the inorganic film layer, maximizing the utilization of the chip pad size to construct the first conductive structure, resulting in a first conductive structure with a large current-carrying cross-section, effectively improving current carrying capacity and providing good thermal conductivity. In addition to improving the chip's current carrying capacity, the resistance value along the current-carrying path can be reduced, effectively mitigating the effects of parasitic generation and providing good reliability.

[0024] For example, the inductor is surface-mounted on the front or back of the embedded substrate.

[0025] A fourth aspect of this application provides an electronic device, which includes a system board and a power supply device, wherein the power supply device is disposed on the system board and is the power supply device as described above.

[0026] In practical applications, this electronic device can be a server, computer, or high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, this electronic device can also be a switch, router, or edge device, etc. Attached Figure Description

[0027] Figure 1 is a cross-sectional view of an embedded substrate provided in an embodiment of this application;

[0028] Figure 2 is an enlarged schematic diagram of part C in Figure 1;

[0029] Figure 3 is a cross-sectional view of DD in Figure 2;

[0030] Figure 4 is a cross-sectional view of another embedded substrate structure provided in an embodiment of this application;

[0031] Figure 5 is an enlarged schematic diagram of part E in Figure 4;

[0032] Figure 6 is a cross-sectional view of FF in Figure 4;

[0033] Figure 7 is a schematic diagram of the flow passage cross section of another first conductive structure provided in an embodiment of this application;

[0034] Figure 8 is a schematic diagram of the process of an embedded substrate provided in an embodiment of this application;

[0035] Figure 9 is a schematic diagram of an application scenario of a power supply device provided in an embodiment of this application;

[0036] Figure 10 is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0037] This application provides an embedded substrate implementation scheme that can achieve high current, high heat dissipation, low parasitics and high reliability, so as to be applied to different high integration and high density application scenarios.

[0038] Embedded substrate technology is used to embed electronic components inside a substrate, which can shorten the connection path between components, reduce transmission loss, improve product integration, and reduce the size of the module. Taking the embedded substrate of a power chip packaging module as an example, a typical embedded substrate architecture embeds components such as chips, capacitors, and / or resistors in a core board, and then stacks add-on layers on the surface of the core board to realize interconnection between components and connection with external circuits.

[0039] In this structure, the pads on the front side of the chip are exposed through circular or elliptical openings in the PI layer. Correspondingly, laser-cut vias are used on the add-on layer to form blind vias corresponding to the chip pads, establishing electrical connections between the chip side and the add-on layer's circuitry. The PI layer openings on the front side of the chip are formed using a patterning process, and their dimensions must meet certain geometric tolerances; that is, the opening size should be smaller than the pad size. Simultaneously, there is a certain annular width between the blind vias and the openings. The determination of this annular width needs to consider the chip mounting positioning accuracy and the accuracy of the laser-cut vias; that is, the blind via size should be smaller than the opening size. This structural relationship restricts the cross-sectional size of the blind vias, thus affecting the current carrying capacity and heat dissipation performance on the front side of the chip. Furthermore, due to the differences in the coefficients of thermal expansion (CTE) between the PI layer, the chip dielectric material, and the pads, a high-risk area for strain delamination forms between the PI layer and the chip.

[0040] Based on this, this application provides an embedded substrate, which includes a core retainer, an augmentation layer, and a chip embedded in the core retainer. The front side of the chip includes pads and an inorganic film layer on the chip surface. The augmentation layer includes a front augmentation layer covering a first side of the core retainer. This front augmentation layer includes a first front augmentation layer bonded to the first side of the core retainer and bonded to the front side of the chip. The first front augmentation layer includes a dielectric layer and a circuit layer stacked together. A first conductive structure is provided between the circuit layer and the pads of the first front augmentation layer. One end of the first conductive structure passes through the dielectric layer and is electrically connected to the circuit layer, and the other end passes through the inorganic film layer and is electrically connected to the pads. The outer peripheral surface of the first conductive structure is bonded to both the dielectric layer and the inorganic film layer.

[0041] This configuration, through the formation of a dense passivation layer using an inorganic film covering the chip surface, effectively blocks the diffusion of moisture and mobile ions, and prevents chip pad oxidation. It effectively avoids interface delamination problems between the first conductive structure and the pads, and between the dielectric layer and the pads, caused by pad oxidation, thus overcoming the potential adverse effects of environmental factors on chip performance. Simultaneously, the first conductive structure, electrically connected between the add-on circuit layer and the pads, passes through and adheres to the inorganic film layer, maximizing the utilization of the chip pad size to construct the first conductive structure. This results in a first conductive structure with a large current-carrying cross-section, effectively improving current carrying capacity while also providing good thermal conductivity. In addition to improving chip current carrying capacity, it also reduces the resistance value along this current-carrying path, effectively mitigating the effects of parasitic generation.

[0042] Furthermore, this inorganic film layer can form chemical bonds with both the build-up dielectric layer and the pads, achieving high bonding strength. This improves interfacial bonding strength and reliability, providing a strong technical guarantee for the stable operation of the chip. Overall, it exhibits good reliability.

[0043] Furthermore, based on the high adhesion between the inorganic film layer and the substrate dielectric layer and pads, holes can be directly formed on the dielectric layer and inorganic film layer, such as, but not limited to, laser drilling, to construct the first conductive structure. Compared to the traditional method of creating holes by opening windows in the PI layer on the front side of the chip, this solution can further reduce the difficulty of the hole-forming process and provide better manufacturability.

[0044] To better understand the technical solutions and effects of this application, without loss of generality, specific embodiments will be described in detail below with reference to the accompanying drawings. Please refer to Figure 1, which is a cross-sectional view of an embedded substrate architecture provided in an embodiment of this application.

[0045] As shown in Figure 1, the core retainer 1 of the embedded substrate 10 can be made of a core board. A chip 2 and electronic components 3 are embedded in the core retainer 1. For clarity of the basic architecture of the embedded substrate, two chips 2 and two electronic components 3 are illustrated in the figure, by way of example.

[0046] In specific implementations, the number of chips 2 and electronic components 3 can be determined according to the overall product design requirements. For example, but not limited to, electronic components 3 can be capacitors and / or resistors to construct corresponding functional circuits. The electronic components 3 in the core holder 1 are optional components; that is, only chip 2 can be embedded in the embedded substrate 10. This application does not limit the specific implementation.

[0047] In this configuration, the front side of chip 2 faces the first surface 1A of the core holder 1, and correspondingly, the back side of chip 2 faces the second surface 1B of the core holder 1. Please refer to Figures 2 and 3 together, where Figure 2 is an enlarged schematic diagram of part C in Figure 1, and Figure 3 is a cross-sectional view of DD in Figure 2.

[0048] The front side of chip 2 includes an inorganic film layer 21 covering its surface. The inorganic film layer 21 can be made of alumina, silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, aluminum nitride, titanium nitride, silicon nitride, or tantalum nitride. Specifically, the inorganic film layer 21 can be made of any of the above-mentioned inorganic materials, or at least two of them, for example, but not limited to, a composite of alumina and silicon oxide, to obtain high strength and toughness properties.

[0049] Here, the inorganic film layer 21 covering the front side of chip 2 can be achieved using ALD technology. Through a single-atom film layer-by-layer growth method, inorganic material atoms are deposited layer by layer onto the front side of chip 2, resulting in better density. Simultaneously, the thickness of the inorganic film layer 21 can be precisely controlled, effectively reducing the potential impact of stress. In other specific implementations, the inorganic film layer 21 can also be achieved using CVD technology, obtaining an inorganic film layer 21 with good density, low residual stress, and excellent adhesion. In cases where two or more inorganic materials are used to form the inorganic film layer 21, the inorganic film layers 21 can be sequentially stacked based on the ALD process. For example, an aluminum oxide film can be formed first, followed by a silicon oxide film. CVD based on the ALD process can form a composite inorganic film layer 21. The embodiments in this application are not limited to this.

[0050] In specific implementations, the thickness of the inorganic film layer 21 can range from 1 nm to 500 nm. It is understood that the thickness of the inorganic film layer 21 can be determined based on the overall product design requirements. This application does not impose such limitations.

[0051] In this embodiment, both sides of the core retainer 1 of the embedded substrate 10 are covered with augmentation layers. The circuit layers of the augmentation layers are connected to the devices embedded in the core retainer 1 to achieve more complex circuit connections and functions. Specifically, the first side 1A of the core retainer 1 is covered with a front augmentation layer T, and the second side 1B of the core retainer 1 is covered with a back augmentation layer B, which enables double-sided interconnection and heat dissipation.

[0052] For example, both the front-side add-on layer T and the back-side add-on layer B comprise three layers stacked sequentially, formed by a dielectric layer 42 and a circuit layer 41 stacked sequentially from both sides of the core retainer 1. In other possible implementations, the number of layers on the front-side add-on layer T and the back-side add-on layer B is not limited to the three layers shown in the figure, and can be determined according to the product function. In one scenario, the front-side add-on layer T (not shown in the figure) may only be covered on the first surface 1A of the core retainer 1. This application does not limit the scope of the implementation.

[0053] The front-side enhancement layer T includes a first front-side enhancement layer T1 located on the inner layer. This first front-side enhancement layer T1 is bonded to the first surface 1A of the core holder 1 and the inorganic film layer 21 on the front side of the chip 2. The first conductive structure electrically connecting the pad 22 of the chip 2 and the circuit layer 41 of the first front-side enhancement layer T1 is a blind via 5, that is, the first conductive structure has a circular current-passing cross-section. Correspondingly, the circuit layers 41 of the two side enhancement layers can be electrically connected through a second conductive structure 6, which can also be a blind via; this embodiment of the application is not limited to this.

[0054] The dielectric layer 42 of the first front-side addition layer T1 is stacked on the circuit layer 41 of the core holder 1 and the inorganic film layer 21 on the front side of the chip 2. The circuit layer 41 of the first front-side addition layer T1 is stacked on the dielectric layer 42 of the first front-side addition layer T1. In a specific implementation, the material of the dielectric layer 42 of the first front-side addition layer T1 can be Ajinomoto Build-up Film (ABF) or Prepreg (PP). It can be obtained through vacuum lamination and thermosetting / hot pressing processes to achieve excellent insulation performance and mechanical strength.

[0055] Please also refer to Figure 2, which is a CC cross-sectional view of Figure 1. To clearly show the connection relationship between the blind via 5 (first conductive structure) and the inorganic film layer 21 on the side of chip 2, chip 2 is illustrated in the figure with two pads 22 and the corresponding blind via 5.

[0056] In this embodiment, one end of the blind via 5 passes through the dielectric layer 42 of the first front-side add-on layer T1 and is electrically connected to its circuit layer 41, while the other end passes through the inorganic film layer 21 and is electrically connected to the pad 22. The outer peripheral surface of the blind via 5 is respectively bonded to the dielectric layer 42 and the inorganic film layer 21. In a specific implementation, based on the chemical bonds formed between the inorganic film layer 21 and the dielectric layer 42 and the pad 22, a high bonding force is achieved, allowing direct hole formation on the dielectric layer 42 and the inorganic film layer 21, so that the pad 22 is exposed to form the corresponding blind via 5. This fully utilizes the size of the chip pad 22 to construct a blind via 5 with a large current-carrying cross-section.

[0057] For the non-same network pads of chip 2, the inorganic film layer 21 can effectively block the diffusion of water vapor and mobile ions, avoid the influence of water vapor and ion migration, and provide reliable electrical isolation between non-same networks.

[0058] Of course, different blind vias 5 with different adaptable structures can be used for a single pad 22. Please refer to Figure 3, which is a DD cross-sectional view of Figure 1. As shown in the figure, multiple blind vias 5 are respectively provided for the two pads 22, and the blind vias 5 are spaced apart. Except for the local position where the blind via 5 contacts the pad 22, where there is no inorganic film layer 21, the dielectric layer 42 and the pad 22 maintain good adhesion through the inorganic film layer 21, thereby improving the interface bonding strength and reliability.

[0059] It should be noted that the number of blind vias 5 corresponding to pad 22 is not limited to the four shown in the figure. In other specific implementations, it can be determined according to actual needs. This application embodiment does not limit this.

[0060] In the aforementioned embodiment, the first conductive structure is a blind via structure. In other specific implementations, the first conductive structure electrically connected between the pad 22 of chip 2 and the circuit layer 41 of the first front-side addition layer T1 may also have a strip-shaped current-carrying cross section. Please refer to Figures 4, 5, and 6 together. Figure 4 is a cross-sectional view of another embedded substrate architecture provided in this application embodiment, Figure 5 is an enlarged schematic diagram of part E in Figure 4, and Figure 6 is a cross-sectional view of part FF in Figure 4. To clearly illustrate the differences and connections between this embodiment and the embodiment described in Figure 1, the same functional components and structures are indicated by the same reference numerals in the figures.

[0061] Compared with the scheme described in Figure 1, the difference of the embedded substrate architecture shown in Figure 4 is that its first conductive structure is a copper strip 5a extending inside the surface of the embedded substrate 10. That is to say, the first conductive structure in this embodiment has a strip-shaped flow passage cross section.

[0062] As shown in Figure 2, one end of the copper strip 5a passes through the dielectric layer 42 of the first front-side add-on layer T1 and is electrically connected to its circuit layer 41, while the other end passes through the inorganic film layer 21 and is electrically connected to the pad 22. The outer peripheral surface of the copper strip 5a is bonded to both the dielectric layer 42 and the inorganic film layer 21. Similarly, holes can be directly formed in the dielectric layer 42 and the inorganic film layer 21 to expose the pad 22 and form the copper strip 5a. In this embodiment, the copper strip 5a and the pad 22 are arranged in a one-to-one correspondence, which fully utilizes the size of the chip pad 22 to configure the length and width of the copper strip 5a, thus forming a copper strip 5a with a larger current-carrying cross-section.

[0063] The other functional components and structures of this implementation scheme can be implemented in the same way as those described in Figure 1. They will not be elaborated further here.

[0064] To maximize the current-carrying cross-section, the shape of the current-carrying cross-section of the first conductive structure is the same as that of the chip pad 22. This allows for the construction of a current-carrying cross-section that approximates the shape and size of the pad 22. In specific implementations, besides the strip-shaped and circular current-carrying cross-sections described in the preceding embodiments, the first conductive structure can also have other shapes of current-carrying cross-sections. Please refer to Figure 7, which is a schematic diagram of the current-carrying cross-section of another first conductive structure provided in this application embodiment. To clearly illustrate the differences and connections between this embodiment and the preceding embodiments, the same functional components and structures are indicated by the same reference numerals in the figure.

[0065] As shown in Figure 7, the pads 22 on the chip side include rectangular pads 22b and hexagonal pads 22c. Corresponding to the rectangular pad 22b, the current-carrying cross section of the first conductive structure 5b is rectangular, and corresponding to the hexagonal pad 22c, the current-carrying cross section of the first conductive structure 5c is hexagonal.

[0066] In other possible implementations, the current-carrying cross-section of the matching pad and the first conductive structure can also be other shapes (not shown in the figure), such as, but not limited to, elliptical, as long as the current-carrying cross-section of the first conductive structure is close to the shape and size of the pad 22. This application does not limit the embodiments.

[0067] The process of the embedded substrate 10 described in the embodiments of this application is briefly explained below with reference to Figure 8.

[0068] Step S801: The front-side RDL of chip 2 is processed to form pads 22. In a specific implementation, the pads on the RDL surface can be patterned.

[0069] In step S802, an inorganic film layer 21 is formed on the front side of the chip 2. This inorganic film layer 21 can be deposited on the surface of the chip body and the pads 22 using ALD, CVD or PVD (Physical Vapor Deposition) techniques.

[0070] In a specific implementation, the inorganic film layer 21 can be made of aluminum oxide, silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, aluminum nitride, titanium nitride, silicon nitride, or tantalum nitride. Specifically, the inorganic film layer 21 can be made of any of the above-mentioned inorganic materials, or it can be made of a composite of at least two of the above-mentioned inorganic materials. The thickness of the inorganic film layer 21 can be from 1 nm to 500 nm.

[0071] Here, steps S801 and S802 can be implemented through pre-preparation, in other words, they can be performed independently of the preparation and embedding of the core holder 1.

[0072] Step S803: Prepare the core retainer 1, form an embedded frame, and apply an adhesive film.

[0073] An embedding groove 1-1 is formed on the core holder 1. In specific implementations, the groove can be formed using a UV laser, a CO2 laser, or other machining processes. Then, an adhesive film 1-2 is attached to the first surface 1A of the core holder 1.

[0074] It is understood that steps S801 and S802 are not executed in the order shown in Figure 8. In practice, step S803 may be executed before or simultaneously with steps S801 and S802, and this embodiment of the application does not impose any limitations on this.

[0075] Step S804: Mount the chip and electronic components, fill and press the back side to prepare the first back side layer.

[0076] Specifically, chip 2 and electronic component 3 are embedded in a buried groove and mounted on adhesive film 1-2. Here, electronic component 3 can be a capacitor, resistor, or inductor. In specific implementations, the buried filler material 1-3 can be ABF, or selected according to actual process conditions. Here, while laminating and filling the gaps between the devices and between the devices and the buried groove, the buried filler material 1-3 also forms a dielectric layer bonded to the second surface 1B side of the core holder 1. At the same time, the surface copper of the first additional layer of the circuit layer 41 on the back can also be formed.

[0077] The first back layer here is the back layer structure that is joined to the second surface of the core retainer 1.

[0078] Step S805: Remove the adhesive film.

[0079] Step S806: Front-side filling and lamination to prepare the first front-side enhancement layer. While the embedded filler materials 1-3 are laminating and filling the gaps between the devices and between the devices and the embedded trenches, a dielectric layer bonded to the first side of the core holder 1 is also formed. Simultaneously, the surface copper of the circuit layer 41 of the first front-side enhancement layer can also be formed.

[0080] The first front layer here is the layer structure in which the front layer is joined to the first surface of the core retainer 1.

[0081] Step S807: Patterning of copper on surface 41 of the circuit layer. In practice, films 1-4 can be laminated onto the copper on surface 41 of the circuit layer, and patterning can be achieved through exposure, development, and etching processes.

[0082] Step S808: Peel off the film.

[0083] Step S809: Open holes 1-5 and remove adhesive. These openings 1-5 correspond to the pin pads of chip 2 and electronic component 3, and the through-holes on the core retainer 1, respectively. In practice, UV laser, CO2 laser, or other machining processes can be used to open the holes.

[0084] Step S810: Remove the inorganic film layer. Specifically, remove the inorganic film layer 21 at the bottom of the openings 1-5 corresponding to the pads 22 of chip 2. This can also be done using UV laser, CO2 laser, or other mechanical processing techniques.

[0085] Step S811: Electroless copper plating and full-board electroplating are performed to form the first conductive structure and other conductive structures, as well as the first front-side added circuit layer 41.

[0086] In a specific implementation, copper plating forms a first conductive structure, which can be a blind via 5 or a copper strip 5a. Further, a first front-side enhancement layer 41 is electroplated.

[0087] Step S812, patterning of circuit layer 41. In a specific implementation, films 1-4 can be laminated on circuit layer 41, and the circuit layer 41 can be patterned through processes such as exposure, development, etching and stripping.

[0088] Step S813: The front and back layers are prepared, and an outer solder resist layer is formed, and the surface of the outer metal is treated.

[0089] In specific implementations, surface metal treatments include, but are not limited to, ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold), ENIG (Electroless Nickel / Immersion Gold), OSP (Organic Solderability Preservative), or SOP processes.

[0090] In other possible implementation schemes, the number of layers for each outer layer can be determined according to the overall product design requirements, and corresponding manufacturing processes can be established. This application does not limit the specific implementation.

[0091] The aforementioned implementation uses a core board as the core retainer 1. In other specific implementations, a filler material can also be used to form the core retainer. That is, a core-free frame structure, which is simple in process and can reasonably control manufacturing costs.

[0092] Furthermore, the embedded substrates described in the foregoing embodiments all include a front-side uplift layer T and a back-side uplift layer B. In other possible implementations, the back-side uplift layer B may be selectively provided, and this application does not limit this.

[0093] The embedded substrate architecture schemes described in the foregoing embodiments can be widely applied to the packaging structures of different functional modules. In practical applications, the above-mentioned technical advantages are particularly significant in power module architecture scenarios. Please refer to Figure 9, which is a schematic diagram of an application scenario of a power supply device provided by an embodiment of this application.

[0094] As shown in Figure 9, the power supply device 100 includes a chip 2, an inductor 20, and multiple electronic components. The electronic components 3 can be capacitors and / or resistors to form corresponding functional circuits. The chip 2 is embedded in a package using the embedded substrate 10 architecture described in Figure 1 or Figure 7; the inductor 20 can be surface-mounted to the back of the embedded substrate 10, that is, the surface of the second side of the embedded substrate 10 near the core holder 1. The front side of the embedded substrate 10 is mounted on one side of the system board 200, and the processor 300 is mounted on the other side of the system board 200. For example, but not limited to, the processor can be an XPU.

[0095] In a specific implementation, some of the multiple electronic components can be embedded together with the chip 2 in the embedded substrate 10, while other electronic components can be surface-mounted together with the inductor 20 on the back side of the embedded substrate 10. This application does not limit the scope of the embodiments.

[0096] In use, the high-speed transmission channels formed vertically and within the board surface based on the internal structure of the embedded substrate can reduce the resistance of the entire link between the power chip 2, system board 200 and processor 300 chip, as well as between the power chip 2 and inductor 20, thereby improving the current carrying capacity. At the same time, it can reasonably control link parasitics and take into account good thermal conductivity and reliability.

[0097] In other implementations, the inductor 20 can be surface-mounted on the front side of the embedded substrate 10 (not shown in the figure). Correspondingly, the back side of the embedded substrate 10 is mounted on one side of the system board 200, and the processor 300 is mounted on the other side of the system board 200. Specific options can be selected as needed, and this application embodiment does not limit the choice.

[0098] It should be understood that the other functions of the power supply device are not the core inventive points of this application, and can be implemented by those skilled in the art based on existing technology, so they will not be described in detail here.

[0099] In addition to the aforementioned embedded substrate, this embodiment also provides an electronic device. Please refer to Figure 10, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0100] As shown in Figure 10, the electronic device 1000 includes a housing 400 and a system board 200 disposed within the housing 400. The system board 200 is provided with a power supply device 100 as described in the foregoing embodiments. A processor (not shown in the figure) may be disposed on the system board 200. Based on the excellent high current carrying capacity, low parasitics, high thermal conductivity and high reliability of the power supply device 100, it can be widely used in various high-density application scenarios.

[0101] In specific implementations, the electronic device can be a server, a computer, or a high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, the electronic device can also be a switch, a router, or an edge device, etc., which are not limited in the embodiments of this application.

[0102] It should be understood that other functions of the electronic device are not the core inventive points of this application, and can be implemented by those skilled in the art based on existing technology, so they will not be described in detail here.

[0103] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An embedded substrate, characterized in that, The embedded substrate includes a core retainer, a front augmentation layer, and a chip embedded in the core retainer. The core retainer includes a first surface and a second surface. The front augmentation layer includes a first front augmentation layer covering the first surface, and the first front augmentation layer is bonded to the front surface of the chip. The front side of the chip is disposed facing the first side of the core holder. The front side of the chip includes pads and an inorganic film layer located on the surface of the chip. The first augmentation layer on the front side includes a dielectric layer and a circuit layer stacked together. A first conductive structure is disposed between the circuit layer of the first augmentation layer on the front side and the pads. One end of the first conductive structure passes through the dielectric layer of the first augmentation layer on the front side and is electrically connected to the circuit layer, and the other end passes through the inorganic film layer and is electrically connected to the pads. The outer peripheral surface of the first conductive structure is respectively attached to the dielectric layer and the inorganic film layer of the first augmentation layer on the front side.

2. The embedded substrate according to claim 1, characterized in that, The inorganic film is made of aluminum oxide, silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, aluminum nitride, titanium nitride, silicon nitride, or tantalum nitride.

3. The embedded substrate according to claim 1, characterized in that, The inorganic film is made of at least two of the following materials: aluminum oxide, silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, aluminum nitride, titanium nitride, silicon nitride, and tantalum nitride.

4. The embedded substrate according to any one of claims 1 to 3, characterized in that, The thickness of the inorganic film is 1 nm to 500 nm.

5. The embedded substrate according to any one of claims 1 to 4, characterized in that, The dielectric layer of the first frontal enhancement layer is made of organic material.

6. The embedded substrate according to any one of claims 1 to 5, characterized in that, The pads are electrically connected to a plurality of the first conductive structures, and the plurality of the first conductive structures are spaced apart.

7. The embedded substrate according to any one of claims 1 to 5, characterized in that, The shape of the current-carrying cross section of the first conductive structure is the same as the shape of the corresponding pad.

8. The embedded substrate according to any one of claims 1 to 7, characterized in that, The current-carrying cross section of the first conductive structure is circular, elliptical, polygonal, or strip-shaped.

9. The embedded substrate according to any one of claims 1 to 8, characterized in that, The embedded substrate also includes a back-side reinforcement layer covering the second side of the core retainer.

10. The embedded substrate according to any one of claims 1 to 9, characterized in that, The embedded substrate also includes a plurality of electronic components embedded in the core retainer, at least one of the plurality of electronic components being a capacitor or a resistor.

11. The embedded substrate according to any one of claims 1 to 10, characterized in that, The core retainer is a core board or a filling medium layer made of filling medium material.

12. A method for manufacturing an embedded substrate, characterized in that, The manufacturing method includes the following steps: An inorganic film layer is formed on the front side of the chip, and the inorganic film layer covers the chip body and the pads on its surface. Prepare a core retainer to form an embedded framework; The chip is embedded in the embedding groove of the core retainer and then backfilled and pressed. Perform front-side filling and lamination to form the first front-side additive layer of the dielectric layer; A hole is made in the dielectric layer corresponding to the pad, and the inorganic film layer at the bottom of the hole is removed; A first conductive structure is formed by copper plating, and a first front-side enhancement layer is formed by electroplating. The outer peripheral surface of the first conductive structure is bonded to the dielectric layer and the inorganic film layer of the first front-side enhancement layer, respectively.

13. The method for manufacturing an embedded substrate according to claim 12, characterized in that, The inorganic film layer is formed by atomic layer deposition or chemical vapor deposition.

14. The method for manufacturing an embedded substrate according to claim 12 or 13, characterized in that, While forming the dielectric layer of the first front-side enhancement layer, the copper circuit layer of the first front-side enhancement layer is also formed; correspondingly, the copper circuit layer is patterned before the pads are made in the dielectric layer.

15. The method for manufacturing an embedded substrate according to any one of claims 12 to 14, characterized in that, A laser or mechanical processing method is used to create a hole in the dielectric layer corresponding to the pad, and the inorganic film layer at the bottom of the hole is removed.

16. A power supply device, characterized in that, The device includes a chip and an inductor, wherein the chip is formed into an embedded package using an embedded substrate as described in any one of claims 1 to 11, and the inductor is surface-mounted on the embedded substrate.

17. The power supply device according to claim 16, characterized in that, The inductor is surface-mounted on the front or back of the embedded substrate.

18. An electronic device, characterized in that, It includes a system board and a power supply unit, the power supply unit being disposed on the system board, and the power supply unit being the power supply unit as described in claim 16 or 17.

Images