Decoding method and storage device

Abstract

The present invention provides a decoding method and a storage device. The method comprises: reading first data, the first data comprising multiple bits; executing a decoding operation on the first data to obtain first guide data and second guide data, the first guide data reflecting an attractive force for bit flipping for each of the bits, and the second guide data reflecting a repulsive force for bit flipping for each of the bits; generating third guide data on the basis of the first guide data and the second guide data; performing bit flipping on at least one of the multiple bits on the basis of the third guide data, and obtaining a flipping result; and executing a second decoding operation on the flipping result. Thus, decoding efficiency can be improved.

Description

Decoding method and storage device Technical Field This invention relates to the field of storage technology, and more particularly to a decoding method and storage device. Background Technology Generally, to ensure the correctness of data read from a memory module, the data must be decoded. In the decoding process, low-density parity-check (LDPC) codes are commonly used for error correction to correct erroneous bits in the data. Bit-flipping decoders are widely used in practice for error correction, especially in the decoding of LDPC codes. A bit-flipping decoder is a hard-decision decoding method that attempts to correct errors by flipping erroneous bits. However, for data containing a large number of erroneous bits, bit-flipping algorithms also suffer from decoding degradation. Therefore, how to effectively improve the decoding efficiency of the data being read without increasing the complexity of the decoding operation as much as possible is an urgent problem to be solved. Summary of the Invention The present invention provides a decoding method and a storage device that can improve the above-mentioned problems, thereby effectively improving the decoding efficiency of the decoding operation for reading data without increasing the complexity of the decoding operation as much as possible. An embodiment of the present invention provides a decoding method for a storage device, the decoding method comprising: reading first data, wherein the first data includes a plurality of bits; performing a first decoding operation on the first data to obtain first guide data and second guide data, wherein the first guide data reflects an attractive force for bit flipping each of the bits, and the second guide data reflects a repulsive force for bit flipping each of the bits; generating third guide data based on the first guide data and the second guide data; performing bit flipping on at least one of the plurality of bits based on the third guide data to obtain a flipping result; and performing a second decoding operation on the flipping result. An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: read first data from the memory module, wherein the first data includes a plurality of bits; perform a first decoding operation on the first data to obtain first boot data and second boot data, wherein the first boot data reflects the attraction of bit flipping each of the bits, and the second boot data reflects the repulsion of bit flipping each of the bits; generate third boot data based on the first boot data and the second boot data; perform bit flipping on at least one of the plurality of bits based on the third boot data to obtain a flipping result; and perform a second decoding operation on the flipping result. Based on the above, after reading first data containing multiple bits from the first entity unit, the first data can be decoded to obtain first guide data and second guide data. The first guide data reflects the attractive force for bit flipping of the multiple bits. The second guide data reflects the repulsive force for bit flipping of the multiple bits. Based on the first guide data and the second guide data, third guide data can be generated and used to flip at least one of the multiple bits. Thus, the decoding efficiency of the decoded operation for the read data is effectively improved without increasing the complexity of the decoding operation as much as possible. Attached Figure Description Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention; Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention; Figure 3 is a schematic diagram of a memory management module according to an embodiment of the present invention; Figure 4 is a schematic diagram illustrating the acquisition of first state information according to an embodiment of the present invention; Figures 5 and 6 are schematic diagrams illustrating multiple iterative decoding of first data according to an embodiment of the present invention; Figures 7 and 8 are schematic diagrams of force field information used to guide bit flipping during decoding operations, according to embodiments of the present invention. Figure 9 is a flowchart of a decoding method according to an embodiment of the present invention. Detailed Implementation Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts. Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Referring to Figure 1, the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (e.g., vehicle, aircraft, or ship), and the type of host system 11 is not limited thereto. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage devices. Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121. Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics. Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller. The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences. Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention. Referring to Figures 1 and 2, the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to a host system 11 via the connection interface 121 for communication with the host system 11. The memory interface 22 is used to connect to a memory module 122 for access to the memory module 122. Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123. In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention. Figure 3 is a schematic diagram of a memory management module according to an embodiment of the present invention. Referring to Figures 1 to 3, the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of storage cells for non-volatile storage of data. In one embodiment, an entity unit may include one or more entity programming units. In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors contained in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be considered as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto. In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell. In one embodiment, a physical erase unit may include multiple physical programmed units. The multiple physical programmed units in a physical erase unit can be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to the multiple physical programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these physical programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, the memory control circuit 23 can logically associate entity units 301(1) to 301(A) and 301(A+1) to 301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1) to 301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1) to 301(B) in the idle area 32 do not store any data (e.g., valid data). In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool. In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32. In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1) to 302(C) to map physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units. In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data. In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table). In one embodiment, the memory control circuit 23 can read data (also referred to as first data) from at least one physical unit (also referred to as a first physical unit) in the memory module 122. For example, the first physical unit can be at least one of physical units 301(1) to 301(B). The first data includes a plurality of bits. For example, the memory control circuit 23 can send a read instruction sequence to the memory module 122. The memory module 122 can perform a read operation on the first physical unit according to this read instruction sequence. The memory module 122 can return the first data to the memory control circuit 23 according to the read result of this read operation. In one embodiment, after acquiring the first data, the decoding circuit 25 may perform a decoding operation (also referred to as a first decoding operation) on the first data to obtain various types of boot data. Then, the decoding circuit 25 may perform bit flipping on at least one bit in the first data according to the various types of boot data. In one embodiment, the guide data includes first guide data and second guide data. The first guide data reflects the attractive force for bit flipping of a plurality of bits in the first data. The second guide data reflects the repulsive force for bit flipping of a plurality of bits in the first data. In one embodiment, the gravity can be used to increase the probability of bit flipping at least one of the plurality of bits. That is, the greater the gravity reflected by the first bootstrap data, the higher the probability that at least one bit in the first data will be flipped (e.g., flipped from "1" to "0" or from "0" to "1") in the first decoding operation. In one embodiment, the repulsive force can be used to reduce the probability of bit flipping at least one of the plurality of bits. That is, the greater the repulsive force reflected in the second bootstrap data, the lower the probability that at least one bit in the first data is flipped (e.g., flipped from "1" to "0" or from "0" to "1") in the first decoding operation. In one embodiment, the memory control circuit 23 can generate another boot data (also referred to as third boot data) based on the first boot data and the second boot data. The decoding circuit 25 can perform bit flipping on at least one bit in the first data based on the third boot data. For example, the decoding circuit 25 can flip at least one bit (also referred to as the first bit) in the first data from "1" to "0" and / or flip at least one bit (also referred to as the second bit) in the first data from "0" to "1" based on the third boot data. In one embodiment, during the first decoding operation, the memory control circuit 23 can acquire status information (also referred to as first status information) related to multiple bits in the first data. The first status information can reflect the current status of the multiple bits. For example, the first status information can reflect that some bits in the first data are error bits and / or some bits in the first data are not error bits. Figure 4 is a schematic diagram illustrating the acquisition of first state information according to an embodiment of the present invention. Referring to Figure 4, in one embodiment, it is assumed that the first data includes codeword 42, and codeword 42 includes bits b(1) to b(n). In one embodiment, during the first decoding operation, the decoding circuit 25 can obtain vector 43 (i.e., first state information) based on the parity check matrix 41 (also called the H matrix) and the codeword 42. For example, the decoding circuit 25 can perform matrix multiplication on the parity check matrix 41 and the codeword 42, and obtain vector 43 based on the result of the matrix multiplication. In one embodiment, vector 43 is also called vector y. Vector 43 (i.e., first state information) can reflect the current state of codeword 42 (i.e., first data). Specifically, the size of the first data read by each variable node (B node) before each verification depends mainly on the following factors: 1. Number of variable nodes: Each check node (C node) needs to read data from all the variable nodes it connects to. In the check matrix H, the number of rows indicates the number of check nodes (C nodes). Each row represents multiple variable nodes connected to a check node, and the number of connections is determined by the number of columns with a value of 1 in that row. 2. Data amount sent by each variable node: Typically, each variable node sends one bit (0 or 1) to the connected check node C, representing the current bit state. Therefore, each check node receives 1 bit of data from each connected variable node. For example, suppose the parity check matrix H has the following structure: Therefore, the number of check nodes (C nodes) in H above is 3, and the number of variable nodes (B nodes) connected to it is 6. The nodes of the check matrix H are assigned as C1, C2, and C3 by row. Before each verification: C1 reads the following data from the connected B node: b1, b3, b4, with a data size of 3 bits (3 0s or 1s); C2 (verification node 2) reads the following data from the connected B node: b2, b4, b5, with a data size of 3 bits (3 0s or 1s); C3 (verification node 3) reads the following data from the connected B node: b1, b2, b5, b6, with a data size of 4 bits (4 0s or 1s). The amount of data read by each check node is equal to the number of variable nodes it is connected to multiplied by the data size sent by each variable node (usually 1 bit). Correspondingly, the total amount of data read by all check nodes is: if there are m check nodes and n variable nodes, then the total amount of data read is the total number of variable nodes connected to all check nodes. (For example, if each check node is connected to d1, d2, ..., dm, then the total amount of data is d1 + d2 + ... + dm). m Bit. In the example above, the total amount of data read is 3 + 3 + 4 = 10 bits. Therefore, the total amount of data read before each check is determined by the number of connections in the check matrix. The amount of data read by each check node is the number of variable nodes it is connected to, and each connected variable node transmits 1 bit of data. It should be noted that in existing solutions, if the 10-bit bit flipping process is performed as shown in the example above, 10 iterations are required (i.e., a judgment is made before flipping the selected target bit each time). However, the method proposed in this application only requires selecting at least one bit for flipping based on the calculation result each time, thereby improving encoding efficiency. Furthermore, the size of the data read each time in this application can be determined based on the dimension of the parity check matrix, or it can be a preset size of data, including but not limited to: 8 bits, 16 bits, 1KB, etc., without specific limitations here. In one embodiment, vector 43 includes bits s(1) to s(n). Each of bits s(1) to s(n) is also called a checksum. In particular, the value of bit s(i) reflects whether bit b(i) in codeword 42 is an error bit. For example, if bit s(i) is "1", it means that bit b(i) in codeword 42 has a high probability of being an error bit. Conversely, if bit s(i) is "0", it means that bit b(i) in codeword 42 has a high probability of not being an error bit. In one embodiment, if bits s(1) to s(n) are all "0", it means that there are no error bits in codeword 42. If there are no error bits in codeword 42, the decoding circuit 25 can output successfully decoded data and stop decoding. It should be noted that, according to the parity check matrix 41, the values ​​of multiple bits in vector 43 may be affected by the same bit in codeword 42. Therefore, it is not possible to accurately locate the erroneous bit in codeword 42 based solely on vector 43. Traditionally, to determine the bit to be flipped in the current decoding operation (i.e., the error bit), the memory control circuit 23 can refer to the parity check matrix 41 to obtain the syndrome sum corresponding to each bit in the codeword 42. Then, the memory control circuit 23 can identify the bit in the codeword 42 corresponding to the largest syndrome sum as the error bit and flip this bit (e.g., flipping it from "1" to "0" or from "0" to "1"). By flipping a small number of bits one by one in multiple iterations, all errors in the codeword 42 can be attempted to be corrected. However, the drawback of this error correction method is also obvious: it can only flip a very small number of bits each time. If the total number of bits flipped in a certain iteration is too large, the flips performed in that iteration have a high probability of being invalid, and may even lead to error divergence. Therefore, it is necessary to propose further improvements to effectively improve the decoding efficiency of the decoded data without increasing the complexity of the decoding operation as much as possible. In one embodiment, during the first decoding operation, the memory control circuit 23 may also acquire another state information (also called second state information) related to multiple bits in the first data. The second state information may reflect the target state of the multiple bits. For example, in one embodiment, the second state information may include a vector x, in which multiple bits of vector x are all "0". In other words, the target state of the multiple bits reflected by the second state information is the expected final state of vector y in Figure 4. Once the bits s(1) to s(n) in vector y are all "0", it indicates that there are no error bits in the codeword 42 (i.e., the first data) during decoding. It should be noted that a target state is set here (e.g.:

[0000] Error correction (OCR) is an assumption that the data received by the receiver should be in a known ideal state without errors. For example, in some coding schemes, the target state may be all zeros (as is set in the construction of error-correcting codes), so the goal of the algorithm is to flip the bits to be as close as possible to this assumed target state. In reality, the receiving end only knows the state y of the currently read data, but not whether it is correct. The read data may contain errors, but the receiving end does not know the specific location of the errors. Therefore, the goal of the error correction process is to gradually correct these errors. It does not know what the ideal target state is, but only uses an assumed target state to guide error correction. The algorithm iterates continuously, performing bit flipping based on the verification results and rules, to make the received signal conform as closely as possible to the preset target state. In practical applications, the target state is unknown. Error correction algorithms (such as the bit-flipping algorithm) are used, employing redundant information provided by check nodes (C nodes) to detect and correct received erroneous bits. This process does not depend on a definite target state; the target state is merely an assumption used to guide the flip direction. In one embodiment, the memory control circuit 23 can obtain distance information (also referred to as first distance information) based on first state information and second state information. The first distance information can reflect the Euclidean distance (also referred to as Euclidean distance) between the current state and the target state. For example, the memory control circuit 23 can obtain the first distance information according to the following formula (1.1). D(1)=||yx|| (1.1) In formula (1.1), vector x represents the target state of multiple bits in the first data, vector y represents the current state of the multiple bits, and D(1) is the first distance information. Then, the memory control circuit 23 can obtain the first guidance data according to the first distance information. In one embodiment, the memory control circuit 23 can obtain gravitational potential field information corresponding to the first data based on the first distance information. In particular, the gravitational potential field information can be used to simulate the gravitational potential field used to pull multiple bits in the first data from the current state to the target state. For example, the memory control circuit 23 can obtain the gravitational potential field information according to the following formula (1.2). In formula (1.2), k(1) is the attraction constant, and U1(y) is the gravitational potential field information. In particular, k(1) can be used to control the strength of the gravitational potential field. For example, the value of k(1) is positively correlated with the strength of the gravitational potential field. In one embodiment, setting k(1) to a larger value can accelerate the movement of multiple bits in the first data from the current state to the target state, but may also lead to overcorrection. In one embodiment, setting k(1) to a smaller value can slow down the movement of multiple bits in the first data from the current state to the target state, but may also lead to an increase in the number of iterations. In one embodiment, the value of k(1) can be set empirically and can be dynamically adjusted. Then, the memory control circuit 23 can obtain the first guiding data based on the gravitational potential field information. In one embodiment, the memory control circuit 23 can obtain gravitational field gradient information based on the gravitational potential field information. In particular, the gravitational field gradient information can be used to simulate the gradient of the gravitational potential field. For example, the memory control circuit 23 can obtain the gravitational field gradient information according to the following formula (1.3). In formula (1.3), The information provided is the gravitational field gradient. Then, the memory control circuit 23 can obtain the first guidance data based on the gravitational field gradient information. For example, the first guidance data may include the gravitational field gradient information. In one embodiment, during the first decoding operation, the memory control circuit 23 may also acquire another state information (also referred to as third state information) related to multiple bits in the first data. The third state information may reflect the rejection state of the multiple bits in the first data. For example, in one embodiment, the third state information may include a vector z. The multiple bits in vector z may all be "1". In other words, the rejection state of the multiple bits reflected by the third state information is the reverse state of vector x. In one embodiment, the memory control circuit 23 can obtain distance information (also referred to as second distance information) based on the first state information and the third state information. The second distance information can reflect the Euclidean distance (i.e., Euclidean distance) between the current state and the repulsive state. For example, the memory control circuit 23 can obtain the second distance information according to the following formula (2.1). D(2)=||yz|| (2.1) In formula (1.1), vector z represents the exclusion state of multiple bits in the first data, and D(2) is the second distance information. Then, the memory control circuit 23 can obtain the second guiding data according to the second distance information. In one embodiment, the memory control circuit 23 can obtain repulsive potential field information corresponding to the first data based on the second distance information. In particular, the repulsive potential field information can be used to simulate a repulsive potential field to resist pulling the plurality of bits in the first data from the current state to the target state. For example, the memory control circuit 23 can obtain the repulsive potential field information according to the following formulas (2.2) and (2.3). U2(y)=0, if D(2)>d (2.3) In formulas (2.2) and (2.3), k(2) is the repulsive force constant, d is the distance threshold value, and U2(y) is the repulsive potential field information. Specifically, k(2) can be used to control the strength of the repulsive potential field. For example, the value of k(2) is positively correlated with the strength of the repulsive potential field. In one embodiment, setting k(2) to a larger value can increase the resistance of the repulsive potential field to the gravitational potential field. In another embodiment, setting k(2) to a smaller value can decrease the resistance of the repulsive potential field to the gravitational potential field. In one embodiment, the value of k(2) can be set empirically and can be dynamically adjusted. Then, the memory control circuit 23 can obtain the second guidance data based on the repulsive potential field information. In one embodiment, the memory control circuit 23 can obtain repulsive field gradient information based on the repulsive potential field information. In particular, the repulsive field gradient information can be used to simulate the gradient of the repulsive potential field. For example, the memory control circuit 23 can obtain the repulsive field gradient information according to the following formulas (2.4) and (2.5). In formulas (2.4) and (2.5), The repulsive field gradient information is then used. The memory control circuit 23 can then obtain the second guidance data based on the repulsive field gradient information. For example, the second guidance data may include the repulsive field gradient information. In one embodiment, the memory control circuit 23 can obtain synthetic gradient data based on first guide data and second guide data. Specifically, the synthetic gradient data can be used to simulate the gradient of a synthetic potential field corresponding to the first data, and the synthetic potential field consists of an attractive potential field and a repulsive potential field. For example, the memory control circuit 23 can obtain the synthetic gradient data according to the following formula (3.1). In formula (3.1), F(y) represents the synthesized gradient data. The memory control circuit 23 can then generate the third guiding data based on the synthesized gradient data. For example, the third guiding data may include the synthesized gradient data. In one embodiment, the memory control circuit 23 can obtain multiple gradient information corresponding to the multiple bits in the first data according to the third bootstrap data. The memory control circuit 23 can compare the multiple gradient information to obtain a comparison result. Then, the memory control circuit 23 can flip at least one of the multiple bits according to the comparison result. In one embodiment, F(y) includes f(1) to f(n) (i.e., gradient information). f(1) to f(n) correspond to the plurality of bits in the first data, respectively. For example, f(i) may reflect the gradient corresponding to the i-th bit in the first data. In one embodiment, the memory control circuit 23 may compare f(1) to f(n). Then, the memory control circuit 23 may determine the bit to be flipped in the first data based on the largest of f(1) to f(n). For example, assuming that the largest of f(1) to f(n) is f(i), in the first decoding operation, the decoding circuit 25 may perform bit flipping on the i-th bit in the first data, for example, flipping the i-th bit in the first data from "1" to "0" or from "0" to "1". In addition, the number of bits flipped in each iteration may be one or more, which is not limited by the present invention. It should be noted that all the above formulas can be adjusted according to practical needs, which is not limited by the present invention. It should be noted that when selecting the target bit for the flipping operation based on the result of each iteration, in extreme cases, all bits may have the same gradient information. In this case, directly performing the flipping operation on all bits may lead to non-convergence. Conversely, failing to perform the flipping operation on any bit will obviously result in a deadlock where iteration cannot continue. Therefore, in practical scenarios, to avoid this situation, the following solution can be adopted: 1. Introduce random perturbations: When the net force is the same, a small random perturbation can be introduced (i.e., randomly select to flip or not flip). This can break the balance and avoid getting stuck in an infinite loop or flipping all bits. For example, for all gradient information bits, randomly select one or a few as target bits to flip. This strategy ensures that not too many bits are flipped in a single iteration, thus maintaining a gradual approach to the target state. 2. Selection based on historical information: Record the flipping history of each bit in previous iterations and combine it with the current gradient information to determine the flipping order. For example, select bits that have been flipped less in the previous iterations for flipping. This ensures a more even selection with each flip, reducing the likelihood of repeatedly switching back and forth between the same states. 3. Prioritize the most sensitive bits: By analyzing the impact of each bit on the overall potential field, select the bits most sensitive to changes in the potential field for flipping. For example, calculate the local potential field change for each bit, i.e., calculate the change in the overall potential field caused by flipping that bit; prioritize flipping those bits that contribute the most to the change in the potential field. 4. Introduce a dynamic adjustment mechanism: A dynamic adjustment mechanism is introduced into the flipping strategy to adjust the flipping strategy according to the changes in the potential field during the iteration process. For example, in the early stage of iteration, more bits can be flipped to quickly approach the target state; as convergence approaches, the number of flipped bits in each iteration is reduced to improve stability and convergence speed. Specifically, single-point flipping (or a few flipping) strategies ensure relatively small state changes each time, helping to gradually approach the target state. History-based or sensitivity-based strategies can reduce unnecessary flips and prevent switching back and forth between the same states. Dynamically adjusting strategies make the algorithm more flexible, adaptively adjusting the flipping strategy according to the current state, improving convergence speed and reliability. Figures 5 and 6 are schematic diagrams illustrating multiple iterations of decoding for first data according to an embodiment of the present invention. Referring to Figure 5, in one embodiment, it is assumed that the codewords in the first data are represented by a vector v. For example, vector v includes bits b(1) to b(6). For example, vector v = [b(1), b(2), b(3), b(4), b(5), b(6)]. In the first iteration of decoding vector v (i.e., [b(1), b(2), b(3), b(4), b(5), b(6)]), decoding circuit 25 can obtain vector x (i.e., second state information) and vector y (i.e., first state information). Vector x can reflect the individual target states of bits b(1) to b(6) in vector v. For example, vector x = [0, 0, 0, 0, 0, 0]. In addition, vector y can reflect the individual current states of bits b(1) to b(6) in vector v. For example, vector y = [1, 0, 1, 0, 1, 1]. In one embodiment, the memory control circuit 23 can obtain vector g(1) (i.e., first guidance information) according to formulas (1.1) to (1.3), and obtain vector g(2) (i.e., second guidance information) according to formulas (2.1) to (2.5). Then, the memory control circuit 23 can obtain vector g(3) (i.e., third guidance information) according to vector g(1) and g(2). According to the third guidance information, the memory control circuit 23 (or decoding circuit 25) can perform bit flipping on bits b(1) and b(3) in vector v. For example, the memory control circuit 23 (or decoding circuit 25) can flip bits b(1) and b(3) in vector v to b(1)' and b(3)' respectively. At this time, the result of the first iteration decoding of vector v is to update vector v to [b(1)', b(2), b(3)', b(4), b(5), b(6)]. Based on the updated vector v, the decoding circuit 25 can obtain the updated vector y (i.e., y(1)). For example, vector y(1) = [0, 0, 0, 0, 1, 1]. Compared to vector y, vector y(1) reflects that bits b(1) and b(3) in vector v, which were originally erroneous bits, have been corrected (i.e., bits b(1) to b(4) in vector v are no longer erroneous bits). However, vector y(1) is different from vector x. Therefore, the memory control circuit 23 and the decoding circuit 25 can perform a second iteration of decoding on vector v. Referring to Figure 6, continuing from the embodiment in Figure 5, in the second iteration of decoding for vector v (i.e., [b(1)', b(2), b(3)', b(4), b(5), b(6)]), the memory control circuit 23 can again obtain vector g(1) (i.e., the first guiding information) according to formulas (1.1) to (1.3), and obtain vector g(2) (i.e., the second guiding information) according to formulas (2.1) to (2.5). Then, the memory control circuit 23 can obtain vector g(3) (i.e., the third guiding information) according to vectors g(1) and g(2). According to the third guiding information, the memory control circuit 23 (or the decoding circuit 25) can perform bit flipping on bits b(5) and b(6) in vector v. For example, the memory control circuit 23 (or the decoding circuit 25) can flip bits b(5) and b(6) in vector v to b(5)' and b(6)' respectively. At this point, the result of the second iteration of decoding for vector v is to update vector v to [b(1)', b(2), b(3)', b(4), b(5)', b(6)']. Based on the updated vector v, the decoding circuit 25 can obtain the updated vector y (i.e., y(2)). For example, vector y(2) = [0, 0, 0, 0, 0, 0]. Compared to vector y(1), vector y(2) reflects that bits b(5) and b(6) in vector v, which were originally erroneous bits, have been corrected (i.e., bits b(1) to b(6) in vector v are no longer erroneous bits). Thus, vector y(2) is the same as vector x. Therefore, the memory control circuit 23 and the decoding circuit 25 can determine that the decoding of the first data (i.e., vector v) is successful and output the decoded first data. Figures 7 and 8 are schematic diagrams of force field information used to guide bit flipping during decoding operations, as shown in an embodiment of the present invention. Referring to Figure 7, curves 71, 72, and 73 can be shown respectively. In the embodiment of Figure 5, vector g(1) (i.e., the first guiding information), vector g(2) (i.e., the second guiding information), and vector g(3) (i.e., the third guiding information) correspond to the force field information of multiple bits b(1) to b(6) in the first data (i.e., vector v). Specifically, the force field information presented by curve 71 is used to simulate the gravitational potential field that pulls bits b(1) to b(6) from the current state to the target state. The force field information presented by curve 72 is used to simulate the repulsive potential field that resists pulling bits b(1) to b(6) from the current state to the target state. In addition, the force field information presented by curve 73 is used to simulate the combined force field formed by the gravitational potential field and the repulsive potential field. According to the extreme value position of curve 73, bits b(1) and b(3) in the first data (i.e., vector v) can be flipped. Please refer to Figure 8. Curves 81, 82 and 83 can be presented respectively. In the embodiment of Figure 6, vector g(1) (i.e., the first guiding information), vector g(2) (i.e., the second guiding information) and vector g(3) (i.e., the third guiding information) correspond to the force field information of multiple bits b(1)', b(2), b(3)', b(4) to b(6) in the first data (i.e., vector v). Specifically, the force field information presented by curve 81 is used to simulate the gravitational potential field that pulls bits b(1)', b(2), b(3)', b(4)~b(6) from the current state to the target state. The force field information presented by curve 82 is used to simulate the repulsive potential field that resists pulling bits b(1)', b(2), b(3)', b(4)~b(6) from the current state to the target state. In addition, the force field information presented by curve 83 is used to simulate the combined force field formed by the gravitational potential field and the repulsive potential field. According to the extreme position of curve 83, bits b(5) and b(6) in the first data (i.e. vector v) can be flipped. It should be noted that, for the embodiment shown in Figure 5, if a traditional bit-flipping algorithm is used to determine the bits to be flipped in each iteration, it may require four or more iterations of decoding to completely correct all errors in the first data (i.e., vector v). However, in the embodiments shown in Figures 5 and 6 (in conjunction with Figures 7 and 8), only two iterations of decoding are needed to completely correct all errors in the first data (i.e., vector v). Therefore, the decoding efficiency for the read data can be effectively improved without significantly increasing the complexity of the decoding operation. Figure 9 is a flowchart illustrating a decoding method according to an embodiment of the present invention. Specifically, please refer to the steps shown in Figure 9 as follows: In step S901, first data is read from the first entity unit, wherein the first data includes multiple bits. In step S902, a decoding operation is performed on the first data to obtain first guide data and second guide data, wherein the first guide data reflects (or provides) the attraction of bit flipping of the plurality of bits, and the second guide data reflects (or provides) the repulsion of bit flipping of the plurality of bits. In step S903, third guidance data is generated based on the first guidance data and the second guidance data. In step S904, at least one of the plurality of bits is bit-flipped according to the third guiding data. However, since each step in Figure 9 has been described in detail above, it will not be repeated here. It is worth noting that each step in Figure 9 can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, the method in Figure 9 can be used in conjunction with the above exemplary embodiments, or it can be used alone, and this invention is not limited thereto. In summary, the decoding method and storage device proposed in this invention can simulate the attraction and repulsion forces acting on each bit in the data to be decoded. Specifically, the attraction pulls each bit in the data to be decoded toward the target decoding state, while the repulsion resists pulling each bit in the data to be decoded toward the target state. Based on the simulation results of the attraction and repulsion forces, at least some bits in the data to be decoded can be flipped. Therefore, the decoding efficiency for read data can be effectively improved without significantly increasing the complexity of the decoding operation. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A decoding method, characterized in that, For a storage device, the decoding method includes: Read first data, wherein the first data includes multiple bits; A first decoding operation is performed on the first data to obtain first guide data and second guide data, wherein the first guide data reflects the attraction of bit flipping each bit, and the second guide data reflects the repulsion of bit flipping each bit. Based on the first boot data and the second boot data, third boot data is generated; and Based on the third guiding data, at least one of the plurality of bits is flipped to obtain a flipped result; and Perform a second decoding operation on the flipped result.

2. The decoding method according to claim 1, wherein the attraction is used to increase the probability of performing the bit flip on at least one of the plurality of bits, and the repulsion is used to reduce the probability of performing the bit flip on at least one of the plurality of bits.

3. The decoding method according to claim 1, wherein the step of performing the first decoding operation on the first data to obtain the first boot data includes: Based on the first data, first state information is determined, wherein the first state information reflects the current state of the plurality of bits; Based on the first state information and the target state information, first distance information is obtained, wherein the target state information is used to reflect the target state that the flipping result is expected to eventually reach, and the first distance information reflects the Euclidean distance between the current state and the target state. as well as Based on the first distance information, the first guidance data is obtained.

4. The decoding method according to claim 3, wherein the step of obtaining the first guidance data based on the first distance information includes: Based on the first distance information, gravitational potential field information corresponding to the first data is obtained, wherein the gravitational potential field information is used to simulate the gravitational potential field that flips the plurality of bits from the current state to the target state; and The first guidance data is obtained based on the gravitational potential field information.

5. The decoding method according to claim 4, wherein the step of obtaining the first guiding data based on the gravitational potential field information includes: Based on the gravitational potential field information, gravitational field gradient information is obtained, wherein the gravitational field gradient information is used to simulate the gradient of the gravitational potential field; as well as The first guidance data is obtained based on the gravitational field gradient information.

6. The decoding method according to claim 1, wherein the step of performing the first decoding operation on the first data to obtain the second boot data includes: Obtain first state information of the plurality of bits, wherein the first state information reflects the current state of the plurality of bits; Obtain third state information of the plurality of bits, wherein the third state information reflects the exclusion state of the plurality of bits; Based on the first state information and the third state information, a second distance information is obtained, wherein the second distance information reflects the Euclidean distance between the current state and the repulsion state; as well as Based on the second distance information, the second guidance data is obtained.

7. The decoding method according to claim 6, wherein the step of obtaining the second guiding data based on the second distance information includes: Based on the second distance information, repulsive potential field information corresponding to the first data is obtained, wherein the repulsive potential field information is used to simulate a repulsive potential field to resist pulling the plurality of bits from the current state to the target state; and The second guidance data is obtained based on the repulsive potential field information.

8. The decoding method according to claim 7, wherein the step of obtaining the second guiding data based on the repulsive potential field information includes: Based on the repulsive potential field information, the repulsive field gradient information is obtained, wherein the repulsive field gradient information is used to simulate the gradient of the repulsive potential field; as well as The second guidance data is obtained based on the repulsive field gradient information.

9. The decoding method according to claim 1, wherein the step of generating the third boot data based on the first boot data and the second boot data includes: Based on the first guidance data and the second guidance data, synthetic gradient data is obtained, wherein the synthetic gradient data is used to simulate the gradient of the synthetic potential field corresponding to the first data, and the synthetic potential field consists of an attractive potential field and a repulsive potential field; and The third guiding data is generated based on the synthesized gradient data.

10. The decoding method according to claim 1, wherein the step of performing the bit flipping on at least one of the plurality of bits according to the third bootstrap data comprises: Based on the third guiding data, obtain multiple gradient information corresponding to the multiple bits respectively; The multiple gradient information are compared to obtain a comparison result; as well as Based on the comparison result, at least one of the plurality of bits is flipped.

11. A storage device, characterized in that, include: A connection interface used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to: Read first data from the memory module, wherein the first data includes multiple bits; A first decoding operation is performed on the first data to obtain first guide data and second guide data, wherein the first guide data reflects the attraction of bit flipping each bit, and the second guide data reflects the repulsion of bit flipping each bit. Based on the first boot data and the second boot data, third boot data is generated; Based on the third guiding data, at least one of the plurality of bits is flipped to obtain a flipping result; as well as Perform a second decoding operation on the flipped result.

12. The storage device of claim 11, wherein the attraction is used to increase the probability of performing the bit flip on at least one of the plurality of bits, and the repulsion is used to decrease the probability of performing the bit flip on at least one of the plurality of bits.

13. The storage device of claim 11, wherein the operation of the memory controller performing the first decoding operation on the first data to obtain the first boot data includes: Based on the first data, first state information is determined, wherein the first state information reflects the current state of the plurality of bits; Based on the first state information and the target state information, first distance information is obtained, wherein the target state information is used to reflect the target state that the flipping result is expected to eventually reach, and the first distance information reflects the Euclidean distance between the current state and the target state. as well as Based on the first distance information, the first guidance data is obtained.

14. The storage device of claim 13, wherein the operation of the memory controller obtaining the first boot data based on the first distance information includes: Based on the first distance information, gravitational potential field information corresponding to the first data is obtained, wherein the gravitational potential field information is used to simulate the gravitational potential field that flips the plurality of bits from the current state to the target state; and The first guidance data is obtained based on the gravitational potential field information.

15. The storage device of claim 14, wherein the operation of the memory controller acquiring the first guidance data based on the gravitational potential field information includes: Based on the gravitational potential field information, gravitational field gradient information is obtained, wherein the gravitational field gradient information is used to simulate the gradient of the gravitational potential field; as well as The first guidance data is obtained based on the gravitational field gradient information.

16. The storage device of claim 11, wherein the operation of the memory controller performing the first decoding operation on the first data to obtain the second boot data includes: Obtain first state information of the plurality of bits, wherein the first state information reflects the current state of the plurality of bits; Obtain third state information of the plurality of bits, wherein the third state information reflects the exclusion state of the plurality of bits; Based on the first state information and the third state information, a second distance information is obtained, wherein the second distance information reflects the Euclidean distance between the current state and the repulsion state; as well as Based on the second distance information, the second guidance data is obtained.

17. The storage device of claim 16, wherein the operation of the memory controller obtaining the second boot data based on the second distance information includes: Based on the second distance information, repulsive potential field information corresponding to the first data is obtained, wherein the repulsive potential field information is used to simulate a repulsive potential field to resist pulling the plurality of bits from the current state to the target state; and The second guidance data is obtained based on the repulsive potential field information.

18. The storage device of claim 17, wherein the operation of the memory controller obtaining the second guidance data based on the repulsive potential field information includes: Based on the repulsive potential field information, the repulsive field gradient information is obtained, wherein the repulsive field gradient information is used to simulate the gradient of the repulsive potential field; as well as The second guidance data is obtained based on the repulsive field gradient information.

19. The storage device of claim 11, wherein the operation of the memory controller generating the third boot data based on the first boot data and the second boot data includes: Based on the first guidance data and the second guidance data, synthetic gradient data is obtained, wherein the synthetic gradient data is used to simulate the gradient of the synthetic potential field corresponding to the first data, and the synthetic potential field consists of an attractive potential field and a repulsive potential field; and The third guiding data is generated based on the synthesized gradient data.

20. The storage device of claim 11, wherein the operation of the memory controller performing the bit flipping on at least one of the plurality of bits according to the third boot data comprises: Based on the third guiding data, obtain multiple gradient information corresponding to the multiple bits respectively; The multiple gradient information are compared to obtain a comparison result; as well as Based on the comparison result, at least one of the plurality of bits is flipped.

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