Display substrate, manufacturing method, and display device

Abstract

A display substrate, a manufacturing method, and a display device. The display substrate comprises a base, and a driving module, a first voltage line (V1), a second voltage line (V2), and a third voltage line (V3) which are arranged on the base. The driving module comprises a multi-stage driving circuit. The driving circuit comprises an output node control circuit (11), a cascade output circuit (12), and a driving output circuit (13). The orthographic projection of at least part of a transistor comprised in the driving output circuit (13) on the base is arranged between the orthographic projection of the first voltage line (V1) on the base and the orthographic projection of the third voltage line (V3) on the base, facilitating saving of the lateral space occupied by the driving module, and achieving a narrow bezel.

Description

Display substrate, manufacturing method and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411514162.7, filed in China on October 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method, and a display device. Background Technology

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly widespread, and people's requirements for the display quality of display products are getting higher and higher. In order to better realize narrow bezel display products, GOA (Gate On Array) technology is adopted in display products. That is, the gate driving circuit is directly fabricated on the array substrate. The sub-pixel rows of the display area are driven by the shift registers of each level included in the gate driving circuit, thereby realizing the display function of the display product. However, the existing shift register structure is complex, includes a large number of transistors, and still occupies a large layout space, which is not conducive to further narrowing the bezel of display products. Summary of the Invention

[0005] In one aspect, embodiments of this disclosure provide a display substrate, including a substrate and a driving module, a first voltage line, a second voltage line and a third voltage line disposed on the substrate, wherein the driving module includes a multi-stage driving circuit;

[0006] The driving circuit includes an output node control circuit, a cascaded output circuit, and a driving output circuit.

[0007] The output node control circuit is electrically connected to the input terminal, the first output node, the second output node and the first clock signal terminal respectively, and is used to control the potential of the first output node and the potential of the second output node under the control of the input signal provided by the input terminal and the first clock signal provided by the first clock signal terminal.

[0008] The cascaded output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal terminal, and the cascaded output terminal, respectively. It is used to control the output of the cascaded output signal through the cascaded output terminal under the control of the potential of the first output node and the potential of the second output node, according to the first voltage signal provided by the first voltage line and the second clock signal provided by the second clock signal terminal.

[0009] The drive output circuit is electrically connected to the cascaded output terminal, the second voltage line, the third voltage line and the drive output terminal respectively, and is used to control the drive signal to be provided through the drive output terminal under the control of the cascaded output signal, according to the second voltage signal provided by the second voltage line and the third voltage signal provided by the third voltage line;

[0010] The orthographic projection of at least a portion of the transistors included in the drive output circuit onto the substrate is disposed between the orthographic projection of the first voltage line onto the substrate and the orthographic projection of the third voltage line onto the substrate.

[0011] Optionally, the orthographic projection of the transistors in the drive output circuit onto the substrate and the orthographic projection of the third voltage line onto the substrate at least partially overlap.

[0012] Optionally, the display substrate includes a display area and a peripheral area; the first voltage line, the second voltage line, the third voltage line, and the driving module are disposed in the peripheral area;

[0013] The orthographic projections of the third voltage line on the substrate, the first voltage line on the substrate, and the second voltage line on the substrate are arranged sequentially along a direction away from the display area.

[0014] Optionally, the orthographic projection of at least a portion of the transistors in the cascaded output circuit onto the substrate is positioned between the orthographic projection of the second voltage line onto the substrate and the orthographic projection of the first voltage line onto the substrate.

[0015] Optionally, the cascaded output circuit includes at least two transistors, which are arranged along a first direction.

[0016] Optionally, the driving circuit further includes a first energy storage circuit and a second energy storage circuit;

[0017] The first terminal of the first energy storage circuit is electrically connected to the second output node, and the second terminal of the first energy storage circuit is electrically connected to the cascaded output terminal.

[0018] The first terminal of the second energy storage circuit is electrically connected to the first output node, and the second terminal of the second energy storage circuit is electrically connected to the first voltage line.

[0019] The orthographic projection of the capacitor included in the first energy storage circuit onto the substrate at least partially overlaps with the first voltage line;

[0020] The orthogonal projection of the capacitor included in the second energy storage circuit onto the substrate at least partially overlaps with the first voltage line.

[0021] Optionally, the orthographic projection of the capacitor included in the second energy storage circuit onto the substrate and the orthographic projection of the capacitor included in the first energy storage circuit onto the substrate are arranged along a first direction.

[0022] The display substrate described in at least one embodiment of this disclosure further includes a fourth voltage line disposed on the substrate; the output node control circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, and a second output node control circuit;

[0023] The first node control circuit is electrically connected to the input terminal, the first voltage line, the second voltage line and the first node respectively, and is used to control the connection or disconnection between the first node and the first voltage line, and the connection or disconnection between the first node and the second voltage line under the control of the input signal provided by the input terminal;

[0024] The second node control circuit is electrically connected to the first clock signal terminal, the input terminal, and the second node, respectively, and is used to write the input signal into the second node under the control of the first clock signal provided by the first clock signal terminal;

[0025] The first output node control circuit is electrically connected to the first clock signal terminal, the first node and the first output node respectively, and is used to control the connection or disconnection between the first node and the first output node under the control of the first clock signal.

[0026] The second output node control circuit is electrically connected to the fourth voltage line, the second node, and the second output node, respectively, and is used to control the connection or disconnection between the second node and the second output node under the control of the fourth voltage signal provided by the fourth voltage line.

[0027] Optionally, the orthographic projection of the transistors in the second output node control circuit onto the substrate at least partially overlaps with the orthographic projection of the second voltage line onto the substrate.

[0028] Optionally, the orthographic projection of the second voltage line on the substrate and the orthographic projection of the fourth voltage line on the substrate are aligned along a direction away from the display area;

[0029] The orthographic projection of the transistors included in the second node control circuit onto the substrate, and the orthographic projection of the transistors included in the first output node control circuit onto the substrate, are disposed between the orthographic projection of the second voltage line onto the substrate and the orthographic projection of the fourth voltage line onto the substrate.

[0030] The display substrate described in at least one embodiment of this disclosure further includes a starting voltage line disposed on the substrate;

[0031] The orthographic projection of the transistors in the first output node control circuit onto the substrate at least partially overlaps with the orthographic projection of the starting voltage line onto the substrate.

[0032] The display substrate described in at least one embodiment of this disclosure further includes a plurality of clock signal lines disposed on the substrate;

[0033] The orthographic projection of at least some of the transistors in the second node control circuit onto the substrate at least partially overlaps with the orthographic projection of at least one of the clock signal lines onto the substrate.

[0034] The display substrate described in at least one embodiment of this disclosure further includes a plurality of clock signal lines disposed on the substrate;

[0035] The orthographic projection of the clock signal line on the substrate is positioned between the orthographic projection of the second voltage line on the substrate and the orthographic projection of the fourth voltage line on the substrate;

[0036] The first node control circuit includes at least a portion of the transistors whose orthogonal projections on the substrate are disposed between the orthogonal projections of the fourth voltage line on the substrate and the orthogonal projections of the clock signal line on the substrate.

[0037] Optionally, the first node control circuit includes at least two transistors, which are arranged sequentially along a first direction.

[0038] Optionally, the first node control circuit includes a first transistor and a second transistor;

[0039] The first transistor is an oxide transistor, and the second transistor is a low-temperature polysilicon transistor;

[0040] The first transistor includes a first gate and a second gate;

[0041] The first gate of the first transistor is electrically connected to the input terminal, the second gate of the first transistor is electrically connected to the fourth voltage line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node.

[0042] The gate of the second transistor is electrically connected to the input terminal, the first electrode of the second transistor is electrically connected to the first voltage line, and the second electrode of the second transistor is electrically connected to the first node.

[0043] Optionally, the fourth voltage line is a first low voltage line, and the second voltage line is a second low voltage line;

[0044] The voltage value of the first low voltage signal provided by the first low voltage line is less than the voltage value of the second low voltage signal provided by the second low voltage line.

[0045] The display substrate of at least one embodiment of this disclosure includes a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer arranged sequentially along a direction away from the substrate; the gate of the second transistor includes a first gate of the second transistor and a second gate of the second transistor; the first gate of the second transistor is formed on the first gate metal layer, and the second gate of the second transistor is formed on the light-shielding layer; the active pattern of the second transistor is formed on the first semiconductor layer; the second gate of the first transistor is formed on the second gate metal layer, the first gate of the first transistor is formed on the third gate metal layer, and the active pattern of the first transistor is formed on the second semiconductor layer.

[0046] Optionally, the drive output circuit includes a third transistor and a fourth transistor;

[0047] The active pattern of the third transistor includes at least two active pattern portions;

[0048] The orthographic projection of at least one active pattern portion of the third transistor onto the substrate and the orthographic projection of the active pattern of the fourth transistor onto the substrate are arranged along a first direction.

[0049] Optionally, the drive output circuit includes a third transistor and a fourth transistor; the third transistor is an oxide transistor, and the fourth transistor is a low-temperature polysilicon transistor.

[0050] The third transistor includes a first gate and a second gate;

[0051] The first gate and the second gate of the third transistor are both electrically connected to the cascaded output terminal, the first electrode of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the drive output terminal.

[0052] The gate of the fourth transistor is electrically connected to the cascaded output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage line, and the second electrode of the fourth transistor is electrically connected to the drive output terminal.

[0053] The display substrate of at least one embodiment of this disclosure includes a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer arranged sequentially along a direction away from the substrate; the gate of the fourth transistor includes a first gate and a second gate of the fourth transistor; the first gate of the fourth transistor is formed on the first gate metal layer, and the second gate of the fourth transistor is formed on the light-shielding layer; the active pattern of the fourth transistor is formed on the first semiconductor layer; the second gate of the third transistor is formed on the second gate metal layer, the first gate of the third transistor is formed on the third gate metal layer, and the active pattern of the third transistor is formed on the second semiconductor layer.

[0054] Optionally, the drive output circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0055] The third transistor, the fifth transistor, and the sixth transistor are all oxide transistors, and the fourth transistor is a low-temperature polycrystalline silicon transistor;

[0056] The gate of the third transistor is electrically connected to the cascaded output terminal, the first electrode of the third transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the third transistor is electrically connected to the drive output terminal.

[0057] The gate of the fifth transistor is electrically connected to the cascaded output terminal, and the first electrode of the fifth transistor is electrically connected to the second voltage line;

[0058] The gate of the sixth transistor is electrically connected to the drive output terminal, the first electrode of the sixth transistor is electrically connected to the third voltage line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the third transistor.

[0059] The gate of the fourth transistor is electrically connected to the cascaded output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage line, and the second electrode of the fourth transistor is electrically connected to the drive output terminal.

[0060] The orthographic projection of the third transistor on the substrate and the orthographic projection of the fifth transistor on the substrate are positioned between the orthographic projection of the first voltage line on the substrate and the orthographic projection of the third voltage line on the substrate.

[0061] The orthographic projection of the fourth transistor on the substrate at least partially overlaps with the orthographic projection of the third voltage line on the substrate; the orthographic projection of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the third voltage line on the substrate;

[0062] The fifth transistor and the third transistor are arranged along a first direction.

[0063] Optionally, the third transistor and the fifth transistor are dual-gate transistors, and the first gate and the second gate of the third transistor are both electrically connected to the cascaded output terminal, and the first gate and the second gate of the fifth transistor are both electrically connected to the cascaded output terminal.

[0064] The first gate of the third transistor is a top gate, the second gate of the third transistor is a bottom gate, the first gate of the fifth transistor is a top gate, and the second gate of the fifth transistor is a bottom gate.

[0065] Optionally, the sixth transistor is a dual-gate transistor, and the gate of the sixth transistor is the first gate of the sixth transistor;

[0066] The first gate of the sixth transistor is electrically connected to the drive output terminal;

[0067] The second gate of the sixth transistor is electrically connected to the drive output terminal or the second electrode of the sixth transistor;

[0068] The first gate of the sixth transistor is a top gate, and the second gate of the sixth transistor is a bottom gate.

[0069] The display substrate described in at least one embodiment of this disclosure further includes a fourth voltage line, a start voltage line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

[0070] In the odd-level drive circuit, the first clock signal terminal is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the third clock signal line.

[0071] In the even-level driving circuit, the first clock signal terminal is electrically connected to the second clock signal line, and the second clock signal terminal is electrically connected to the fourth clock signal line.

[0072] The input terminals of the first-stage driving circuit and the second-stage driving circuit are electrically connected to the starting voltage line.

[0073] The cascaded output of the nth stage driver circuit is electrically connected to the input of the (n+2)th stage driver circuit, where n is a positive integer.

[0074] Optionally, the first voltage line, the second voltage line, the third voltage line, the fourth voltage line, the starting voltage line, the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line all extend along a first direction;

[0075] The orthographic projections of the third voltage line on the substrate, the first voltage line on the substrate, the second voltage line on the substrate, the starting voltage line on the substrate, and the fourth voltage line on the substrate are arranged sequentially along a direction away from the display area.

[0076] The orthographic projections of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line on the substrate are disposed between the orthographic projection of the fourth voltage line on the substrate and the orthographic projection of the starting voltage line on the substrate.

[0077] Optionally, the first node control circuit includes a first transistor and a second transistor;

[0078] The first gate of the first transistor is electrically connected to the input terminal, the second gate of the first transistor is electrically connected to the fourth voltage line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node.

[0079] The gate of the second transistor is electrically connected to the input terminal, the first electrode of the second transistor is electrically connected to the first voltage line, and the second electrode of the second transistor is electrically connected to the first node.

[0080] The drive output circuit includes a third transistor and a fourth transistor;

[0081] The first gate and the second gate of the third transistor are both electrically connected to the cascaded output terminal, the first electrode of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the drive output terminal.

[0082] The gate of the fourth transistor is electrically connected to the cascaded output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage line, and the second electrode of the fourth transistor is electrically connected to the drive output terminal.

[0083] The output node control circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, and a second output node control circuit; the drive circuit further includes a first energy storage circuit and a second energy storage circuit.

[0084] The second node control circuit includes a seventh transistor, the first output node control circuit includes an eighth transistor, the second output node control circuit includes a ninth transistor, and the cascaded output circuit includes a tenth transistor and an eleventh transistor.

[0085] The gate of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the input terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the ninth transistor.

[0086] The gate of the eighth transistor is electrically connected to the first clock signal terminal, the first electrode of the eighth transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the eighth transistor is electrically connected to the gate of the tenth transistor.

[0087] The gate of the ninth transistor is electrically connected to the fourth voltage line, and the second electrode of the ninth transistor is electrically connected to the gate of the eleventh transistor.

[0088] The first electrode of the tenth transistor is electrically connected to the first voltage line, and the second electrode of the tenth transistor is electrically connected to the cascaded output terminal.

[0089] The first electrode of the eleventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the cascaded output terminal.

[0090] The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0091] The first plate of the first capacitor is electrically connected to the gate of the eleventh transistor, and the second plate of the first capacitor is electrically connected to the cascaded output terminal.

[0092] The first plate of the second capacitor is electrically connected to the gate of the tenth transistor, and the second plate of the second capacitor is electrically connected to the first voltage line.

[0093] The first and third transistors are oxide transistors, while the second, fourth, seventh, eighth, ninth, tenth, and eleventh transistors are all low-temperature polycrystalline silicon transistors.

[0094] Optionally, the output node control circuit includes at least one transistor that is a low-temperature polysilicon transistor, the low-temperature polysilicon transistor including a first gate and a second gate; the first gate of the low-temperature polysilicon transistor is electrically connected to the second gate of the low-temperature polysilicon transistor; the second gate of the low-temperature polysilicon transistor is formed in a light-shielding layer.

[0095] In a second aspect, embodiments of this disclosure provide a display substrate, including a substrate and a driving module and a third voltage line disposed on the substrate; the driving module includes a cascaded output circuit, a driving output circuit, a driving output signal line, and a cascaded output signal line;

[0096] The cascaded output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal terminal, and the cascaded output terminal, respectively. It is used to control the output of the cascaded output signal through the cascaded output terminal under the control of the potential of the first output node and the potential of the second output node, according to the first voltage signal provided by the first voltage line and the second clock signal provided by the second clock signal terminal.

[0097] The drive output circuit is electrically connected to the cascaded output terminal, the second voltage line, the third voltage line and the drive output terminal respectively, and is used to control the drive signal to be provided through the drive output terminal under the control of the cascaded output signal, according to the second voltage signal provided by the second voltage line and the third voltage signal provided by the third voltage line;

[0098] The cascaded output terminal is electrically connected to the cascaded output signal line, and the drive output terminal is electrically connected to the drive output signal line;

[0099] The orthographic projection of the cascaded output signal line on the substrate and the orthographic projection of the drive output signal line on the substrate do not overlap simultaneously with the orthographic projection of the third voltage line on the substrate.

[0100] In a third aspect, embodiments of this disclosure provide a manufacturing method for manufacturing the aforementioned display substrate, characterized in that the manufacturing method includes:

[0101] A driving module, a first voltage line, a second voltage line, and a third voltage line are fabricated on a substrate. The driving module includes a multi-stage driving circuit. The first voltage line, the second voltage line, the third voltage line, and the driving module are disposed in a peripheral area. The driving circuit includes an output node control circuit, a cascaded output circuit, and a driving output circuit.

[0102] The orthographic projection of at least a portion of the transistors included in the drive output circuit onto the substrate is positioned between the orthographic projection of the first voltage line onto the substrate and the orthographic projection of the third voltage line onto the substrate.

[0103] In a fourth aspect, embodiments of this disclosure provide a manufacturing method for manufacturing the above-described display substrate, the manufacturing method comprising:

[0104] A drive module and a third voltage line are fabricated on a substrate; the drive module includes a multi-stage drive circuit; the drive circuit includes a cascaded output circuit and a drive output circuit;

[0105] The orthographic projections of the cascaded output signal line and the drive output signal line on the substrate are configured to not overlap with the orthographic projection of the third voltage line on the substrate.

[0106] In a fifth aspect, embodiments of the present disclosure provide a display device including the display substrate described above. Attached Figure Description

[0107] Figure 1 is a structural diagram of at least one embodiment of the driving circuit;

[0108] Figure 2 is a structural diagram of at least one embodiment of the driving circuit;

[0109] Figure 3A is a circuit diagram of at least one embodiment of the driving circuit;

[0110] Figure 3B is a timing diagram of at least one embodiment of the driving circuit shown in Figure 3A;

[0111] Figure 4 is a circuit diagram of at least one embodiment of the driving circuit;

[0112] Figure 5 is a circuit diagram of at least one embodiment of the driving circuit;

[0113] Figure 6 is a circuit diagram of at least one embodiment of the driving circuit;

[0114] Figure 7A is a structural diagram of at least one embodiment of the drive module;

[0115] Figure 7B is a timing diagram of at least one embodiment of the drive module shown in Figure 7A;

[0116] Figures 8A, 8B, and 8C are layout diagrams of the four-stage drive circuit included in the drive module;

[0117] Figure 9 is a layout diagram of the light-shielding layer in Figure 8A;

[0118] Figure 10 is a layout diagram of the first semiconductor layer in Figure 8A;

[0119] Figure 11 shows the first gate metal layer in Figure 8A;

[0120] Figure 12 is a layout diagram of the second gate metal layer in Figure 8A;

[0121] Figure 13 is a layout diagram of the second semiconductor layer in Figure 8A;

[0122] Figure 14 is a layout diagram of the third gate metal layer in Figure 8A;

[0123] Figure 15 is a layout diagram of the first source / drain metal layer in Figure 8A;

[0124] Figures 16A and 16B are layout diagrams of the second source / drain metal layer in Figure 8A;

[0125] Figure 17A is a stacking diagram of the light-shielding layer and the first semiconductor layer in Figure 8A;

[0126] Figure 17B is a stack-up diagram of the first semiconductor layer and the first gate metal layer in Figure 8A;

[0127] Figure 17C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 8A;

[0128] Figure 17D is a stack-up diagram of the second gate metal layer and the second semiconductor layer in Figure 8A;

[0129] Figure 17E is a stack-up diagram of the second semiconductor layer and the third gate metal layer in Figure 8A;

[0130] Figure 17F is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 8A;

[0131] Figure 17G is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 8A;

[0132] Figure 17H ​​is a schematic diagram of the first semiconductor layer, the first gate metal layer, the second gate metal layer, and the first source / drain metal layer in Figure 8A being electrically connected through vias penetrating the first interlayer dielectric layer.

[0133] Figure 17I is a schematic diagram of the electrical connection between the second semiconductor layer, the third gate metal layer and the first source / drain metal layer in Figure 8A through a via penetrating the second interlayer dielectric layer.

[0134] Figure 17J is a schematic diagram of the electrical connection between the light-shielding layer and the first source / drain metal layer in Figure 8A through a deep hole penetrating the first interlayer dielectric layer and the second interlayer dielectric layer.

[0135] Figure 17K is a schematic diagram showing the electrical connection between the first source / drain metal layer and the second source / drain metal layer through a via penetrating the passivation layer and the planarization layer.

[0136] Figure 18 is a layout diagram of the four-stage drive circuit included in the drive module;

[0137] Figure 19 is a layout diagram of the light-shielding layer in Figure 18;

[0138] Figure 20 is a layout diagram of the first semiconductor layer in Figure 18;

[0139] Figure 21 is a layout diagram of the first gate metal layer in Figure 18;

[0140] Figure 22 is a layout diagram of the second gate metal layer in Figure 18;

[0141] Figure 23 is a layout diagram of the second semiconductor layer in Figure 18;

[0142] Figure 24 is a layout diagram of the third gate metal layer in Figure 18;

[0143] Figure 25 is a layout diagram of the first source / drain metal layer in Figure 18;

[0144] Figure 26 is a layout diagram of the second source / drain metal layer in Figure 18;

[0145] Figure 27A is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 18;

[0146] Figure 27B is a stack-up diagram of the second gate metal layer and the second semiconductor layer in Figure 18;

[0147] Figure 27C is a stack-up diagram of the second semiconductor layer and the third gate metal layer in Figure 18;

[0148] Figure 27D is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 18;

[0149] Figure 27E is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 18;

[0150] Figure 28 is a layout diagram of the four-stage drive circuit included in the drive module;

[0151] Figure 29 is a layout diagram of the second gate metal layer in Figure 28;

[0152] Figure 30 is a layout diagram of the second semiconductor layer in Figure 28;

[0153] Figure 31 is a layout diagram of the third gate metal layer in Figure 28;

[0154] Figure 32 is a layout diagram of the first source / drain metal layer in Figure 28;

[0155] Figure 33A is a stack-up diagram of the second gate metal layer and the second semiconductor layer in Figure 28;

[0156] Figure 33B is a stack-up diagram of the second semiconductor layer and the third gate metal layer;

[0157] Figure 33C is a stack-up diagram of the third gate metal layer and the first source / drain metal layer;

[0158] Figure 34 is a layout diagram of the four-stage drive circuit included in the drive module;

[0159] Figure 35 is a layout diagram of the second gate metal layer in Figure 34;

[0160] Figure 36 is a layout diagram of the third gate metal layer in Figure 34;

[0161] Figure 37 is a layout diagram of the first source / drain metal layer in Figure 34;

[0162] Figure 38A is a layout diagram of the second gate metal layer and the second semiconductor layer in Figure 34;

[0163] Figure 38B is a layout diagram of the second semiconductor layer and the third gate metal layer in Figure 34;

[0164] Figure 38C is a layout diagram of the third gate metal layer and the first source / drain metal layer in Figure 34. Detailed Implementation

[0165] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0166] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0167] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0168] The display substrate described in this embodiment includes a substrate and a driving module, a first voltage line, a second voltage line and a third voltage line disposed on the substrate. The driving module includes a multi-stage driving circuit.

[0169] As shown in Figure 1, the driving circuit includes an output node control circuit 11, a cascaded output circuit 12, and a driving output circuit 13.

[0170] The output node control circuit 11 is electrically connected to the input terminal I1, the first output node QB, the second output node Q, and the first clock signal terminal CK, respectively, and is used to control the potential of the first output node QB and the potential of the second output node Q under the control of the input signal provided by the input terminal I1 and the first clock signal provided by the first clock signal terminal CK.

[0171] The cascaded output circuit 12 is electrically connected to the first output node QB, the second output node Q, the first voltage line V1, the second clock signal terminal CB, and the cascaded output terminal CR, respectively. It is used to control the output of the cascaded output signal through the cascaded output terminal CR under the control of the potential of the first output node QB and the potential of the second output node Q, according to the first voltage signal provided by the first voltage line V1 and the second clock signal provided by the second clock signal terminal CB.

[0172] The drive output circuit 13 is electrically connected to the cascaded output terminal CR, the second voltage line V2, the third voltage line V3 and the drive output terminal GT respectively, and is used to control the drive signal provided through the drive output terminal GT under the control of the cascaded output signal, according to the second voltage signal provided by the second voltage line V2 and the third voltage signal provided by the third voltage line V3.

[0173] The orthographic projection of at least a portion of the transistors included in the drive output circuit 13 onto the substrate is disposed between the orthographic projection of the first voltage line V1 onto the substrate and the orthographic projection of the third voltage line V3 onto the substrate.

[0174] In a specific implementation, at least a portion of the transistors included in the drive output circuit 13 are orthogonally projected onto the substrate and disposed between the orthogonal projection of the first voltage line V1 onto the substrate and the orthogonal projection of the third voltage line V3 onto the substrate. At least a portion of the transistors included in the drive output circuit 13 are disposed using the space between the first voltage line V1 and the third voltage line V3.

[0175] In at least one embodiment of this disclosure, the cascading and output are set separately, which makes it easy to connect the transistors included in the cascaded output circuit to the first voltage line V1, and also makes it easy to connect the transistors included in the drive output circuit to the third voltage line, which facilitates wiring; in addition, at least one embodiment of this disclosure also utilizes the space of the first voltage line for capacitor layout, which helps to save lateral space.

[0176] The orthographic projection of at least a portion of the transistors included in the drive output circuit 13 onto the substrate does not overlap with the orthographic projection of the first voltage line V1 onto the substrate, thereby reducing the coupling capacitance between the first voltage line V1 and the transistors included in the drive output circuit 13, reducing the coupling capacitance between the third voltage line V3 and the transistors included in the drive output circuit 13, and enhancing the stability of the drive output.

[0177] Optionally, the first voltage line can be a first high voltage line, the second voltage line can be a second low voltage line, and the third voltage line can be a second high voltage line.

[0178] In at least one embodiment of this disclosure, the orthographic projection of the transistors included in the drive output circuit onto the substrate and the orthographic projection of the third voltage line onto the substrate at least partially overlap.

[0179] In a specific implementation, the orthographic projection of the transistors in the drive output circuit onto the substrate and the orthographic projection of the third voltage line onto the substrate overlap at least partially, in order to save the lateral space occupied by the drive module and to achieve a narrow bezel.

[0180] In at least one embodiment of this disclosure, the display substrate includes a display area and a peripheral area; the first voltage line, the second voltage line, the third voltage line, and the driving module are disposed in the peripheral area;

[0181] The orthographic projections of the third voltage line on the substrate, the first voltage line on the substrate, and the second voltage line on the substrate are arranged sequentially along a direction away from the display area.

[0182] In practice, the third voltage line, the first voltage line, and the second voltage line can be arranged sequentially along the direction away from the display area.

[0183] In at least one embodiment of this disclosure, at least a portion of the transistors included in the cascaded output circuit are orthogonally projected onto the substrate between the orthogonal projection of the second voltage line onto the substrate and the orthogonal projection of the first voltage line onto the substrate.

[0184] In a specific implementation, at least a portion of the transistors included in the cascaded output circuit may be disposed between the second voltage line and the first voltage line, so that at least a portion of the transistors included in the cascaded output circuit can be disposed using the space between the second voltage line and the first voltage line.

[0185] In at least one embodiment of this disclosure, the cascaded output circuit includes at least two transistors arranged along a first direction.

[0186] Optionally, the first direction can be the vertical direction.

[0187] In practical implementation, at least two transistors of the cascaded output can be arranged vertically, which helps to save horizontal space and achieve a narrow bezel.

[0188] In at least one embodiment of this disclosure, the driving circuit further includes a first energy storage circuit and a second energy storage circuit;

[0189] The first terminal of the first energy storage circuit is electrically connected to the second output node, and the second terminal of the first energy storage circuit is electrically connected to the cascaded output terminal.

[0190] The first terminal of the second energy storage circuit is electrically connected to the first output node, and the second terminal of the second energy storage circuit is electrically connected to the first voltage line.

[0191] The orthographic projection of the capacitor included in the first energy storage circuit onto the substrate at least partially overlaps with the first voltage line;

[0192] The orthogonal projection of the capacitor included in the second energy storage circuit onto the substrate at least partially overlaps with the first voltage line.

[0193] In a specific implementation, the orthographic projection of the capacitor included in the first energy storage circuit on the substrate at least partially overlaps with the first voltage line, and the orthographic projection of the capacitor included in the second energy storage circuit on the substrate at least partially overlaps with the first voltage line, so as to narrow the lateral space occupied by the drive module and facilitate the realization of a narrow bezel.

[0194] In at least one embodiment of this disclosure, the orthographic projection of the capacitor included in the second energy storage circuit onto the substrate and the orthographic projection of the capacitor included in the first energy storage circuit onto the substrate are arranged along a first direction.

[0195] In a specific implementation, the first energy storage circuit may include a first capacitor, and the second energy storage circuit may include a second capacitor. The orthographic projection of the second capacitor on the substrate and the orthographic projection of the first capacitor on the substrate are arranged in the vertical direction, which helps to narrow the horizontal space occupied by the drive module and facilitates the realization of a narrow bezel.

[0196] The display substrate described in at least one embodiment of this disclosure further includes a fourth voltage line disposed on the substrate;

[0197] As shown in Figure 2, based on at least one embodiment of the driving circuit shown in Figure 1, the output node control circuit includes a first node control circuit 21, a second node control circuit 22, a first output node control circuit 23, and a second output node control circuit 24.

[0198] The first node control circuit 21 is electrically connected to the input terminal I1, the first voltage line V1, the second voltage line V2 and the first node QB1 respectively. It is used to control the connection or disconnection between the first node QB1 and the first voltage line V1, and to control the connection or disconnection between the first node QB1 and the second voltage line V2 under the control of the input signal provided by the input terminal I1.

[0199] The second node control circuit 22 is electrically connected to the first clock signal terminal CK, the input terminal I1, and the second node Q2, respectively, and is used to write the input signal into the second node Q2 under the control of the first clock signal provided by the first clock signal terminal CK.

[0200] The first output node control circuit 23 is electrically connected to the first clock signal terminal CK, the first node QB1 and the first output node QB respectively, and is used to control the connection or disconnection between the first node QB1 and the first output node QB under the control of the first clock signal.

[0201] The second output node control circuit 24 is electrically connected to the fourth voltage line V4, the second node Q2, and the second output node Q, respectively, and is used to control the connection or disconnection between the second node Q2 and the second output node Q under the control of the fourth voltage signal provided by the fourth voltage line V4.

[0202] Optionally, the fourth voltage line can be the first low voltage line.

[0203] In at least one embodiment of this disclosure, the orthographic projection of the transistors included in the second output node control circuit onto the substrate at least partially overlaps with the orthographic projection of the second voltage line onto the substrate.

[0204] In a specific implementation, the orthographic projection of the transistors in the second output node control circuit onto the substrate at least partially overlaps with the orthographic projection of the second voltage line onto the substrate, which helps to narrow the lateral space occupied by the drive module and facilitates the realization of a narrow bezel.

[0205] In at least one embodiment of this disclosure, the orthographic projection of the second voltage line on the substrate and the orthographic projection of the fourth voltage line on the substrate are arranged along a direction away from the display area;

[0206] The orthographic projection of the transistors included in the second node control circuit onto the substrate, and the orthographic projection of the transistors included in the first output node control circuit onto the substrate, are disposed between the orthographic projection of the second voltage line onto the substrate and the orthographic projection of the fourth voltage line onto the substrate.

[0207] In a specific implementation, the transistors included in the second node control circuit and the transistors included in the first output node control circuit are disposed between the second voltage line and the fourth voltage line, so that the space between the second voltage line and the fourth voltage line can be used to set the transistors included in the second node control circuit and the transistors included in the first output node control circuit.

[0208] The display substrate described in at least one embodiment of this disclosure further includes a starting voltage line disposed on the substrate;

[0209] The orthographic projection of the transistors in the first output node control circuit onto the substrate at least partially overlaps with the orthographic projection of the starting voltage line onto the substrate.

[0210] In a specific implementation, the orthographic projection of the transistors in the first output node control circuit onto the substrate and the orthographic projection of the starting voltage line onto the substrate can at least partially overlap, which helps to narrow the lateral space occupied by the drive module and achieve a narrow bezel.

[0211] The display substrate described in at least one embodiment of this disclosure further includes a plurality of clock signal lines disposed on the substrate;

[0212] The orthographic projection of at least some of the transistors in the second node control circuit onto the substrate at least partially overlaps with the orthographic projection of at least one of the clock signal lines onto the substrate.

[0213] In a specific implementation, the orthographic projection of at least some transistors in the second node control circuit onto the substrate at least partially overlaps with the orthographic projection of at least one clock signal line onto the substrate; the orthographic projection of at least some transistors in the first output node control circuit onto the substrate at least partially overlaps with the orthographic projection of at least one clock signal line onto the substrate, which helps to narrow the lateral space occupied by the drive module and facilitates the realization of a narrow bezel.

[0214] The display substrate described in at least one embodiment of this disclosure further includes a plurality of clock signal lines disposed on the substrate;

[0215] The orthographic projection of the clock signal line on the substrate is positioned between the orthographic projection of the second voltage line on the substrate and the orthographic projection of the fourth voltage line on the substrate;

[0216] The first node control circuit includes at least a portion of the transistors whose orthogonal projections on the substrate are disposed between the orthogonal projections of the fourth voltage line on the substrate and the orthogonal projections of the clock signal line on the substrate.

[0217] In a specific implementation, multiple clock signal lines can be provided between the second voltage line and the fourth voltage line. At least a portion of the transistors included in the first node control circuit can be provided between the fourth voltage line and the clock signal lines, so that at least a portion of the transistors included in the first node control circuit can be provided using the space between the fourth voltage line and the clock signal lines.

[0218] In at least one embodiment of this disclosure, at least a portion of the orthographic projection of the first node control circuit including at least one transistor onto the substrate overlaps with the orthographic projection of the fourth voltage line onto the substrate, in order to save lateral space.

[0219] In at least one embodiment of this disclosure, the first node control circuit includes at least two transistors, which are arranged sequentially along a first direction.

[0220] In practical implementation, the first node control circuit includes at least two transistors arranged in sequence along the vertical direction, which helps to narrow the horizontal space occupied by the drive module and achieve a narrow bezel.

[0221] Optionally, the first node control circuit includes a first transistor and a second transistor;

[0222] The first transistor is an oxide transistor, and the second transistor is a low-temperature polysilicon transistor;

[0223] The first transistor includes a first gate and a second gate;

[0224] The first gate of the first transistor is electrically connected to the input terminal, the second gate of the first transistor is electrically connected to the fourth voltage line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node.

[0225] The gate of the second transistor is electrically connected to the input terminal, the first electrode of the second transistor is electrically connected to the first voltage line, and the second electrode of the second transistor is electrically connected to the first node.

[0226] In a specific implementation, the first node control circuit may include a first transistor and a second transistor. The first transistor is an oxide transistor, and the second transistor is an LTPS (low-temperature polysilicon) transistor. The first transistor is a dual-gate transistor with a dual-gate structure. The first gate of the first transistor is electrically connected to the input terminal, and the second gate of the first transistor is electrically connected to the fourth voltage line. The first gate is the top gate, and the second gate is the bottom gate.

[0227] In at least one embodiment of this disclosure, the fourth voltage line is a first low voltage line, and the second voltage line is a second low voltage line;

[0228] The voltage value of the first low voltage signal provided by the first low voltage line is less than the voltage value of the second low voltage signal provided by the second low voltage line.

[0229] In a specific implementation, the bottom gate of the first transistor is electrically connected to the first low-voltage line, and the voltage value of the first low-voltage signal is less than the voltage value of the second low-voltage signal, ensuring that the threshold voltage of the first transistor is not negatively biased.

[0230] On the one hand, assuming the first transistor has no bottom gate, when the threshold voltage of the first transistor is negatively biased, the threshold voltage of the first transistor is less than 0. The gate-source voltage of the first transistor in the off state is Vgl1-Vgl2. By setting Vgl1 to be less than Vgl2 and increasing the absolute value of the difference between Vgl1 and Vgl2, the first transistor can be made to have no leakage current. On the other hand, the bottom gate of the first transistor is connected to a lower voltage value, Vgl1, which can make the gate-source voltage of the first transistor less than 0, so that the threshold voltage of the first transistor itself is not negative, ensuring that the threshold voltage of the first transistor is not negatively biased.

[0231] Wherein, Vgl1 is the voltage value of the first low voltage signal, and Vgl2 is the voltage value of the second low voltage signal. The display substrate of at least one embodiment of this disclosure includes a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer arranged sequentially along a direction away from the substrate; the gate of the second transistor includes a first gate of the second transistor and a second gate of the second transistor; the first gate of the second transistor is formed on the first gate metal layer, and the second gate of the second transistor is formed on the light-shielding layer; the active pattern of the second transistor is formed on the first semiconductor layer; the second gate of the first transistor is formed on the second gate metal layer, the first gate of the first transistor is formed on the third gate metal layer, and the active pattern of the first transistor is formed on the second semiconductor layer.

[0232] In practical implementation, the second gate of the LTPS transistor can be formed in the light-shielding layer to improve the reliability of the LTPS transistor.

[0233] In a specific implementation, the first transistor can be an oxide transistor, and the second transistor can be an LTPS transistor; the first semiconductor layer can be a poly (polycrystalline silicon layer), and the second semiconductor layer can be made of IGZO (Indium Gallium Zinc Oxide);

[0234] The first gate of the second transistor is formed on the first gate metal layer, the second gate of the second transistor is formed on the light-shielding layer, the active pattern of the second transistor is formed on the first semiconductor layer, the second gate of the first transistor is formed on the second gate metal layer, the first gate of the first transistor is formed on the third gate metal layer, and the active pattern of the first transistor is formed on the second semiconductor layer.

[0235] In at least one embodiment of this disclosure, the transistor included in the second node control circuit includes a first gate and a second gate, and the transistor included in the first output node control circuit includes a first gate and a second gate; the first gate of the transistor included in the second node control circuit is integrally formed with the first gate included in the first output node control circuit, and the second gate of the transistor included in the second node control circuit is integrally formed with the second gate included in the first output node control circuit; and / or,

[0236] The active transistors in the second node control circuit have a U-shaped active pattern.

[0237] In a specific implementation, the second node control circuit may include a seventh transistor, and the first output node control circuit may include an eighth transistor. The first gate of the seventh transistor and the first gate of the eighth transistor are integrally formed, and the second gate of the seventh transistor and the second gate of the eighth transistor are integrally formed. This facilitates the connection performance of the gates of the seventh transistor and the eighth transistor by using an integral forming process, and can be formed in one process, simplifying the process.

[0238] The active pattern of the seventh transistor can be U-shaped to ensure good unidirectional uniformity of the channel of the seventh transistor.

[0239] In at least one embodiment of this disclosure, the first gate of the seventh transistor and the first gate of the eighth transistor are respectively located on two horizontal lines, and the second gate of the seventh transistor and the second gate of the eighth transistor are respectively located on two horizontal lines, so as to narrow the lateral space occupied by the driving circuit.

[0240] In at least one embodiment of this disclosure, the drive output circuit includes a third transistor and a fourth transistor;

[0241] The active pattern of the third transistor includes at least two active pattern portions to facilitate heat dissipation;

[0242] The orthographic projection of at least one active pattern portion of the third transistor onto the substrate and the orthographic projection of the active pattern of the fourth transistor onto the substrate are arranged along a first direction.

[0243] Optionally, the first direction is the vertical direction.

[0244] In a specific implementation, at least one active pattern portion of the third transistor and the active pattern of the fourth transistor can be arranged vertically, so that the active pattern of the fourth transistor can be set in the space below at least one active pattern portion of the third transistor, which is beneficial to narrowing the horizontal space and achieving a narrow bezel.

[0245] Optionally, the drive output circuit includes a third transistor and a fourth transistor; the third transistor is an oxide transistor, and the fourth transistor is a low-temperature polysilicon transistor.

[0246] The third transistor includes a first gate and a second gate;

[0247] The first gate and the second gate of the third transistor are both electrically connected to the cascaded output terminal, the first electrode of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the drive output terminal.

[0248] The gate of the fourth transistor is electrically connected to the cascaded output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage line, and the second electrode of the fourth transistor is electrically connected to the drive output terminal.

[0249] In specific implementation, the third transistor can be an oxide transistor, the fourth transistor can be an LTPS transistor, the third transistor can be a dual-gate transistor, the third transistor adopts a top-bottom dual-gate structure, the first gate of the third transistor is electrically connected to the second gate of the third transistor to increase the on-state level of the third transistor, so that the size of the third transistor can be appropriately reduced to save the layout space occupied by the oxide transistor.

[0250] Under the same layout space, the oxide transistor with the top and bottom gates electrically connected has the strongest output capability. That is, when the same output waveform is required (the same rise time tr and the same fall time tf), the transistor with the top and bottom gates electrically connected occupies the smallest layout space, which is more conducive to achieving a narrow bezel.

[0251] The display substrate of at least one embodiment of this disclosure includes a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer arranged sequentially along a direction away from the substrate; the gate of the fourth transistor includes a first gate and a second gate of the fourth transistor; the first gate of the fourth transistor is formed on the first gate metal layer, and the second gate of the fourth transistor is formed on the light-shielding layer to improve the reliability of the fourth transistor; the active pattern of the fourth transistor is formed on the first semiconductor layer; the second gate of the third transistor is formed on the second gate metal layer, the first gate of the third transistor is formed on the third gate metal layer, and the active pattern of the third transistor is formed on the second semiconductor layer.

[0252] In a specific implementation, the third transistor can be an oxide transistor, the fourth transistor can be an LTPS transistor, and both the third and fourth transistors can be dual-gate transistors. The third and fourth transistors adopt a top-bottom dual-gate structure. The first gate of the fourth transistor is formed on the first gate metal layer, and the second gate of the fourth transistor is formed on the light-shielding layer. The active pattern of the fourth transistor is formed on the first semiconductor layer. The second gate of the third transistor is formed on the second gate metal layer, the first gate of the third transistor is formed on the third gate metal layer, and the active pattern of the third transistor is formed on the second semiconductor layer.

[0253] Optionally, the drive output circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0254] The third transistor, the fifth transistor, and the sixth transistor are all oxide transistors, and the fourth transistor is a low-temperature polycrystalline silicon transistor;

[0255] The gate of the third transistor is electrically connected to the cascaded output terminal, the first electrode of the third transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the third transistor is electrically connected to the drive output terminal.

[0256] The gate of the fifth transistor is electrically connected to the cascaded output terminal, and the first electrode of the fifth transistor is electrically connected to the second voltage line;

[0257] The gate of the sixth transistor is electrically connected to the drive output terminal, the first electrode of the sixth transistor is electrically connected to the third voltage line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the third transistor.

[0258] The gate of the fourth transistor is electrically connected to the cascaded output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage line, and the second electrode of the fourth transistor is electrically connected to the drive output terminal.

[0259] The orthographic projection of the third transistor on the substrate and the orthographic projection of the fifth transistor on the substrate are positioned between the orthographic projection of the first voltage line on the substrate and the orthographic projection of the third voltage line on the substrate.

[0260] The orthographic projection of the fourth transistor on the substrate at least partially overlaps with the orthographic projection of the third voltage line on the substrate; the orthographic projection of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the third voltage line on the substrate;

[0261] The fifth transistor and the third transistor are arranged along a first direction.

[0262] In a specific implementation, the drive output circuit may include a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the third transistor, the fifth transistor, and the sixth transistor are all oxide transistors, and the fourth transistor is a low-temperature polysilicon transistor; the third transistor and the fifth transistor are connected in series, and the sixth transistor, under the control of the drive signal provided at the drive output terminal, writes the third voltage signal provided by the third voltage line into the intermediate node between the third transistor and the fifth transistor, so that when GT outputs the corresponding drive signal, it can control the connection between the intermediate node between the third transistor and the fifth transistor and VGH2, thereby reducing the leakage current of T3 and the leakage current of T5, which is beneficial to the output stability of GT.

[0263] In at least one embodiment of this disclosure, the third transistor and the fifth transistor are dual-gate transistors, and the first gate and the second gate of the third transistor are both electrically connected to the cascaded output terminal, and the first gate and the second gate of the fifth transistor are both electrically connected to the cascaded output terminal.

[0264] The first gate of the third transistor is a top gate, the second gate of the third transistor is a bottom gate, the first gate of the fifth transistor is a top gate, and the second gate of the fifth transistor is a bottom gate.

[0265] In a specific implementation, both the third transistor and the fifth transistor are oxide transistors. The third transistor and the fifth transistor adopt a top-bottom dual-gate structure. The first gate, the second gate, the first gate, and the second gate of the third transistor are all electrically connected to the cascaded output terminal, so as to increase the on-state level of the third transistor and the on-state level of the fifth transistor, so that the size of the third transistor and the fifth transistor can be appropriately reduced to save the layout space occupied by the oxide transistor.

[0266] In at least one embodiment of this disclosure, the sixth transistor is a dual-gate transistor, and the gate of the sixth transistor is the first gate of the sixth transistor;

[0267] The first gate of the sixth transistor is electrically connected to the drive output terminal;

[0268] The second gate of the sixth transistor is electrically connected to the drive output terminal or the second electrode of the sixth transistor;

[0269] The first gate of the sixth transistor is a top gate, and the second gate of the sixth transistor is a bottom gate.

[0270] In specific implementation, the sixth transistor is an oxide transistor, which can be a dual-gate transistor. The sixth transistor adopts a top-bottom dual-gate structure, and the first gate of the sixth transistor is electrically connected to the second gate of the sixth transistor, or the first gate of the sixth transistor is electrically connected to the second electrode of the sixth transistor. Setting the sixth transistor as a top-bottom dual-gate structure can increase the on-state level of the sixth transistor, so that the size of the sixth transistor can be appropriately reduced to save the layout space occupied by the oxide transistor.

[0271] In at least one embodiment of this disclosure, the first gate of the sixth transistor is electrically connected to the second gate of the sixth transistor, so as to increase the on-state current of the sixth transistor, thereby making the BTS (Bias Temperature Stress) offset of the sixth transistor smaller and making the sixth transistor more stable.

[0272] The first gate of the sixth transistor is electrically connected to the second electrode of the sixth transistor to enable the SS (subthreshold swing).

[0273] The display substrate described in at least one embodiment of this disclosure further includes a fourth voltage line, a start voltage line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

[0274] In the odd-level drive circuit, the first clock signal terminal is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the third clock signal line.

[0275] In the even-level driving circuit, the first clock signal terminal is electrically connected to the second clock signal line, and the second clock signal terminal is electrically connected to the fourth clock signal line.

[0276] The input terminals of the first-stage driving circuit and the second-stage driving circuit are electrically connected to the starting voltage line.

[0277] The cascaded output of the nth stage driver circuit is electrically connected to the input of the (n+2)th stage driver circuit, where n is a positive integer.

[0278] In a specific implementation, the display substrate may include four clock signal lines. The first clock signal terminal and the second clock signal terminal in the odd-numbered driving circuit are electrically connected to the first clock signal line and the second clock signal line, respectively. The first clock signal terminal and the second clock signal terminal in the even-numbered driving circuit are electrically connected to the third clock signal line and the fourth clock signal line, respectively. The input terminals of the first two driving circuits are electrically connected to the starting voltage line. The nth driving circuit and the (n+2)th driving circuit are cascaded together.

[0279] In at least one embodiment of this disclosure, the first voltage line, the second voltage line, the third voltage line, the fourth voltage line, the starting voltage line, the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line all extend along a first direction;

[0280] The orthographic projections of the third voltage line on the substrate, the first voltage line on the substrate, the second voltage line on the substrate, the starting voltage line on the substrate, and the fourth voltage line on the substrate are arranged sequentially along a direction away from the display area.

[0281] The orthographic projections of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line on the substrate are disposed between the orthographic projection of the fourth voltage line on the substrate and the orthographic projection of the starting voltage line on the substrate.

[0282] In a specific implementation, the first voltage line, the second voltage line, the third voltage line, the fourth voltage line, the starting voltage line, the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line can all extend vertically; the third voltage line, the first voltage line, the second voltage line, the starting voltage line, and the fourth voltage line can be arranged sequentially in a direction away from the display area, and each clock signal line is located between the fourth voltage line and the starting voltage line.

[0283] As shown in Figure 3A, based on at least one embodiment of the driving circuit shown in Figure 2, the first node control circuit includes a first transistor T1 and a second transistor T2.

[0284] The first gate of the first transistor T1 is electrically connected to the input terminal I1, the second gate of the first transistor T1 is electrically connected to the first low voltage line VGL1, the first electrode of the first transistor T1 is electrically connected to the second low voltage line VGL2, and the second electrode of the first transistor T1 is electrically connected to the first node QB1.

[0285] The gate of the second transistor T2 is electrically connected to the input terminal I1, the first electrode of the second transistor T2 is electrically connected to the first high voltage line VGH1, and the second electrode of the second transistor T2 is electrically connected to the first node QB1.

[0286] The drive output circuit includes a third transistor T3 and a fourth transistor T4;

[0287] The first gate and the second gate of the third transistor T3 are both electrically connected to the cascaded output terminal CR. The first electrode of the third transistor T3 is electrically connected to the second low voltage line VGL2. The second electrode of the third transistor T3 is electrically connected to the drive output terminal GT.

[0288] The gate of the fourth transistor T4 is electrically connected to the cascaded output terminal CR, the first electrode of the fourth transistor T4 is electrically connected to the second high voltage line VGH2, and the second electrode of the fourth transistor T4 is electrically connected to the drive output terminal GT.

[0289] The output node control circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, and a second output node control circuit; the drive circuit further includes a first energy storage circuit and a second energy storage circuit.

[0290] The second node control circuit includes a seventh transistor T7, the first output node control circuit includes an eighth transistor T8, the second output node control circuit includes a ninth transistor T9, and the cascaded output circuit includes a tenth transistor T10 and an eleventh transistor T11.

[0291] The gate of the seventh transistor T7 is electrically connected to the first clock signal terminal CK, the first electrode of the seventh transistor T7 is electrically connected to the input terminal I1, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the ninth transistor T9.

[0292] The gate of the eighth transistor T8 is electrically connected to the first clock signal terminal CK, the first electrode of the eighth transistor T8 is electrically connected to the second electrode of the second transistor T2, and the second electrode of the eighth transistor T8 is electrically connected to the gate of the tenth transistor T10.

[0293] The gate of the ninth transistor T9 is electrically connected to the first low voltage line VGL1, and the second electrode of the ninth transistor T9 is electrically connected to the gate of the eleventh transistor T11.

[0294] The first electrode of the tenth transistor T10 is electrically connected to the first high voltage line VGH1, and the second electrode of the tenth transistor T10 is electrically connected to the cascaded output terminal CR.

[0295] The first electrode of the eleventh transistor T11 is electrically connected to the second clock signal terminal CB, and the second electrode of the eleventh transistor T11 is electrically connected to the cascaded output terminal CR.

[0296] The first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0297] The first plate of the first capacitor C1 is electrically connected to the gate of the eleventh transistor T11, and the second plate of the first capacitor C1 is electrically connected to the cascaded output terminal CR.

[0298] The first plate of the second capacitor C2 is electrically connected to the gate of the tenth transistor T10, and the second plate of the second capacitor C2 is electrically connected to the first high voltage line VGH1.

[0299] The gate of the tenth transistor T10 is electrically connected to the first output node QB, and the gate of the eleventh transistor T11 is electrically connected to the second output node Q.

[0300] The first transistor T1 and the third transistor T3 are oxide transistors, while the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are all low-temperature polycrystalline silicon (LTSi) transistors. The gate of each LSi transistor may include a first gate and a second gate. The first gate of each LSi transistor is electrically connected to the second gate of each LSi transistor. The second gate of each LSi transistor is formed in a light-shielding layer to improve the reliability of the LSi transistor.

[0301] T1 and T3 are dual-gate transistors. T3 adopts a top-bottom dual-gate structure to improve its reliability.

[0302] In at least one embodiment of this disclosure, the output node control circuit includes at least one transistor that is a low-temperature polysilicon transistor (LTPS). The LPS includes a first gate and a second gate. The first gate of the LPS is electrically connected to the second gate of the LPS. The second gate of the LPS is formed in a light-shielding layer to improve the reliability of the LPS.

[0303] Figure 3B is a timing diagram of at least one embodiment of the driving circuit described in Figure 3A.

[0304] In Figure 3B, the terminals labeled CR-NT are the adjacent next-stage cascaded output terminals, and the terminals labeled GT-NT are the adjacent next-stage drive output terminals.

[0305] As shown in Figure 3B, the shift register operates as follows when the above structure is used:

[0306] During the first time period P1, when the potential of the input signal input to input terminal I1 changes from high to low, and the potential of the first clock signal provided by CK is high, the potentials of Q2 and Q1 remain high, the potential of QB1 changes from low to high, the potential of QB remains low, the potential of the cascaded signal output by CR remains high, and the drive signal output by GT is a low voltage signal.

[0307] During the second time period P2, when the input signal at input terminal I1 is low voltage and the voltage of the first clock signal at input CK changes from high to low, the potential of QB1 remains high voltage, the potential of QB changes from low to high, and the potentials of Q2 and Q are pulled low by the input signal at input I1. Since the potential of the second clock signal at input CB is high voltage at this time, the cascaded signal output by CR is a high voltage signal, and the drive signal output by GT is a low voltage signal.

[0308] In the third time period P3, when the input signal of I1 is low voltage and the potential of the first clock signal of CK changes from low to high, the potential of QB1 remains high voltage. Due to the voltage regulation effect of C1 and C2, the potentials of Q2 and Q1 remain low voltage, and the potential of QB remains high voltage. Since the second clock signal of CB is high voltage at this time, the potential of the cascaded signal output by CR remains high voltage, and the drive signal output by GT is a low voltage signal.

[0309] In the fourth time period P4, when the input signal at input terminal I1 is low voltage, the first clock signal at input CK is high voltage, and the second clock signal at input CB changes from high voltage to low voltage, the potential of QB1 remains high voltage. Due to the coupling effect of C1, the potential of Q is pulled down due to the voltage change of the cascaded signal output by CR. Due to the voltage limiting effect of T9, the potential of Q2 is pulled down by a much smaller amount than the potential of Q. At this time, the potential of the cascaded signal output by CR changes from high to low, and the potential of the drive signal output by GT changes from low to high.

[0310] In the fifth time period P5, when the input signal at input terminal I1 is low voltage and the first clock signal at input CK is high voltage, the potential of QB1 remains high voltage, the potentials of Q2 and Q remain low voltage, the cascaded signal output by CR remains consistent with the second clock signal input by CB, and the drive signal output by GT is opposite to the second clock signal input by CB.

[0311] In the sixth time period P6, when the input signal at input terminal I1 is high voltage, and the potential of the first clock signal at input CK changes from high to low, the second clock signal at input CB is high voltage, the potential of QB1 changes from high to low, the potentials of Q2 and Q change from low to high, T11 is off, T10 is on, the cascaded signal output by CR maintains high voltage, and the drive signal output by GT is low voltage.

[0312] The difference between at least one embodiment of the driving circuit shown in Figure 4 and at least one embodiment of the driving circuit shown in Figure 3A is as follows: the driving output circuit further includes a fifth transistor T5 and a sixth transistor T6;

[0313] The first gate and the second gate of the third transistor T3 are both electrically connected to the cascaded output terminal CR. The first electrode of the third transistor T3 is electrically connected to the second electrode of the fifth transistor T5. The second electrode of the third transistor T3 is electrically connected to the drive output terminal GT.

[0314] The first gate and the second gate of the fifth transistor T5 are both electrically connected to the cascaded output terminal CR, and the first electrode of the fifth transistor T5 is electrically connected to the second low voltage line VGL2.

[0315] The gate of the sixth transistor T6 is electrically connected to the drive output terminal GT, the first electrode of the sixth transistor T6 is electrically connected to the second high voltage line VGH2, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the third transistor T3.

[0316] In at least one embodiment shown in Figure 4, T1, T3, T5 and T6 are all oxide transistors, T1, T3, T5 and T6 are all n-type transistors, and T1, T3 and T5 are all dual-gate transistors.

[0317] In at least one embodiment of the driving circuit shown in Figure 4, when CR provides a low voltage signal, T4 is turned on, and GT is connected to the second high voltage line VGH2. At this time, T6 is turned on, and the first electrode of the third transistor T3 is electrically connected to the second high voltage line VGH2, so that the node between T3 and T5 is connected to the second high voltage, thereby reducing the potential difference between the node between T3 and T5 and GT, reducing leakage current, and helping to maintain the potential of the driving signal provided by GT.

[0318] In specific implementations, the third and fifth transistors can be oxide transistors, and the third and fifth transistors can be dual-gate transistors. The third and fifth transistors adopt a top-bottom dual-gate structure. The first gate of the third transistor is electrically connected to the second gate of the third transistor, and the first gate of the fifth transistor is electrically connected to the second gate of the fifth transistor. This can increase the on-state level of the third transistor and the fifth transistor, so that the size of the third transistor and the fifth transistor can be appropriately reduced to save the layout space occupied by the oxide transistor.

[0319] The difference between at least one embodiment of the driving circuit shown in Figure 5 and at least one embodiment of the driving circuit shown in Figure 4 is as follows: T6 is a dual-gate transistor;

[0320] The first gate of T6 is electrically connected to the drive output terminal GT; the second gate of T6 is electrically connected to the second electrode of T6; the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the third transistor T3, and the first electrode of the third transistor T3 is electrically connected to the second electrode of the fifth transistor T5.

[0321] The difference between at least one embodiment of the driving circuit shown in Figure 6 and at least one embodiment of the driving circuit shown in Figure 5 is as follows: both the first gate and the second gate of T6 are electrically connected to the driving output terminal GT.

[0322] In at least one embodiment shown in Figure 6, T6 is configured to adopt a top-bottom dual-gate structure to increase the on-state level of the sixth transistor, so that the size of the sixth transistor can be appropriately reduced to save the layout space occupied by the oxide transistor.

[0323] As shown in FIG7A, the display substrate described in at least one embodiment of the present disclosure further includes a first low voltage line VGL1, a start voltage line STV, a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4.

[0324] At least one embodiment of the driving module includes a first-stage driving circuit GA1, a second-stage driving circuit GA2, a third-stage driving circuit GA3, a fourth-stage driving circuit GA4, a fifth-stage driving circuit GA5, and a sixth-stage driving circuit GA6.

[0325] In the first-stage driver circuit GA1, the third-stage driver circuit GA3, and the fifth-stage driver circuit GA5, the first clock signal terminal is electrically connected to the first clock signal line CK1, and the second clock signal terminal is electrically connected to the third clock signal line CK3.

[0326] In the second-stage driver circuit GA2, the fourth-stage driver circuit GA4, and the sixth-stage driver circuit GA6, the first clock signal terminal is electrically connected to the second clock signal line CK2, and the second clock signal terminal is electrically connected to the fourth clock signal line CK4.

[0327] The input terminals of the first-stage drive circuit GA1 and the second-stage drive circuit GA2 are electrically connected to the starting voltage line STV.

[0328] The cascaded output terminal of the first-stage driver circuit GA1 is electrically connected to the input terminal of the third-stage driver circuit GA3. The cascaded output terminal of the second-stage driver circuit GA2 is electrically connected to the input terminal of the fourth-stage driver circuit GA4. The cascaded output terminal of the third-stage driver circuit GA3 is electrically connected to the input terminal of the fifth-stage driver circuit GA5. The cascaded output terminal of the fourth-stage driver circuit GA4 is electrically connected to the input terminal of the sixth-stage driver circuit GA6.

[0329] The drive output terminal of GA1 is the first drive output terminal GT1, and the cascade output terminal of GA1 is the first cascade output terminal CR1; the drive output terminal of GA2 is the second drive output terminal GT2, and the cascade output terminal of GA2 is the second cascade output terminal CR2; the drive output terminal of GA3 is the third drive output terminal GT3, and the cascade output terminal of GA3 is the third cascade output terminal CR3; the drive output terminal of GA4 is the fourth drive output terminal GT4, and the cascade output terminal of GA4 is the fourth cascade output terminal CR4; the drive output terminal of GA5 is the fifth drive output terminal GT5, and the cascade output terminal of GA5 is the fifth cascade output terminal CR5; the drive output terminal of GA6 is the sixth drive output terminal GT6, and the cascade output terminal of GA6 is the sixth cascade output terminal CR6.

[0330] Figure 7B is a timing diagram of at least one embodiment of the drive module shown in Figure 7A.

[0331] Figures 8A and 8B are layout diagrams of the four-stage drive circuit included in the drive module. The structure of the drive circuit in Figure 8A is shown in Figure 3A.

[0332] In Figure 8B, the circuit labeled GAN is the Nth stage driving circuit, the circuit labeled GAN+1 is the N+1th stage driving circuit, the circuit labeled GAN+2 is the N+2nd stage driving circuit, and the circuit labeled GAN+3 is the N+3rd stage driving circuit.

[0333] In Figure 8A, the line labeled VGH2 is the second high voltage line, the line labeled VGH1 is the first high voltage line, the line labeled VGL2 is the second low voltage line, the line labeled VGL1 is the first low voltage line, the line labeled STV is the starting voltage line, the line labeled CK1 is the first clock signal line, the line labeled CK2 is the second clock signal line, the line labeled CK3 is the third clock signal line, and the line labeled CK4 is the fourth clock signal line.

[0334] The transistor labeled T1 is the first transistor, the transistor labeled T2 is the second transistor, the transistor labeled T3 is the third transistor, the transistor labeled T4 is the fourth transistor, the transistor labeled T7 is the seventh transistor, the transistor labeled T8 is the eighth transistor, the transistor labeled T9 is the ninth transistor, the transistor labeled T10 is the tenth transistor, the transistor labeled T11 is the eleventh transistor, the capacitor labeled C1 is the first capacitor, and the capacitor labeled C2 is the second capacitor.

[0335] As shown in Figure 8C, VGH2, VGH1, VGL2, STV, CK4, CK2, CK3, CK1 and VGL1 all extend vertically, and VGH2, VGH1, VGL2, STV, CK4, CK2, CK3, CK1 and VGL1 are arranged sequentially along the direction away from the display area A0;

[0336] The Nth-level drive circuit GAN, the N+1th-level drive circuit GAN+1, the N+2th-level drive circuit GAN+2, and the N+3rd-level drive circuit GAN+3 are all located in the surrounding area AZ.

[0337] At least a portion of the orthographic projection of T3 onto the substrate is disposed between the orthographic projection of VGH1 onto the substrate and the orthographic projection of VGH2 onto the substrate, and T3 is disposed using the space between VGH1 and VGH2.

[0338] At least a portion of the orthographic projection of T3 onto the substrate overlaps with a portion of the orthographic projection of VGH2 onto the substrate, and the orthographic projection of T4 onto the substrate overlaps with a portion of the orthographic projection of VGH2 onto the substrate, which helps to narrow the horizontal space occupied by the drive module and facilitates the achievement of a narrow bezel.

[0339] The orthographic projections of T10 and T11 on the substrate are positioned between the orthographic projections of VGH1 and VGL2 on the substrate. T10 and T11 are positioned using the space between VGH1 and VGL2.

[0340] The orthographic projections of T10 and T11 on the substrate are arranged sequentially in the vertical direction, which helps to reduce the horizontal space occupied by the drive module and achieve a narrow bezel.

[0341] The orthographic projection of C1 on the substrate partially overlaps with the orthographic projection of VGH1 on the substrate, and the orthographic projection of C2 on the substrate partially overlaps with the orthographic projection of VGH1 on the substrate. C2 and C1 are arranged sequentially in the vertical direction, which helps to narrow the horizontal space occupied by the drive module and facilitates the realization of a narrow bezel.

[0342] The orthographic projection of T9 on the substrate partially overlaps with the orthographic projection of VGL2 on the substrate, which helps to narrow the horizontal space occupied by the drive module and achieve a narrow bezel.

[0343] The orthographic projections of T7 and T8 on the substrate are set between the orthographic projections of VGL2 and VGL1 on the substrate, and T7 and T8 are set using the space between VGL1 and VGL2.

[0344] The orthographic projection of T7 on the substrate partially overlaps with the orthographic projection of CK3 on the substrate, the orthographic projection of T7 on the substrate partially overlaps with the orthographic projection of CK2 on the substrate, the orthographic projection of T7 on the substrate partially overlaps with the orthographic projection of CK4 on the substrate, and the orthographic projection of T8 on the substrate partially overlaps with the orthographic projection of STV on the substrate. This helps to narrow the horizontal space occupied by the drive module and facilitates the achievement of a narrow bezel.

[0345] At least a portion of the orthographic projection of T1 onto the substrate and at least a portion of the orthographic projection of T2 onto the substrate are disposed between the orthographic projection of VGL1 onto the substrate and the orthographic projection of CK1 onto the substrate, and at least a portion of T1 and at least a portion of T2 are disposed using the space between VGL1 and CK1.

[0346] The orthographic projections of T1 and T2 on the substrate are arranged vertically, which helps to reduce the horizontal space occupied by the drive module and achieve a narrow bezel.

[0347] As shown in Figures 8A-16A, the first gate G71 of T7 and the first gate G81 of T8 are integrally formed, and the second gate G72 of T7 and the second gate G82 of T8 are integrally formed, so that G71, G81, G72 and G82 are all electrically connected to CK1.

[0348] As shown in Figures 8A-16A, the first gate G71 of T7 and the first gate G81 of T8 are not on the same horizontal line, and the second gate G72 of T7 and the second gate G82 of T8 are not on the same horizontal line to save lateral space.

[0349] The active graphic A7 of T7 is U-shaped;

[0350] The active graphics of T3 include a first active graphics unit A31, a second active graphics unit A31, and a third active graphics unit A32;

[0351] The orthographic projection of the active graphic A4 of T4 onto the substrate is positioned below the orthographic projection of the third active graphic unit A32 onto the substrate.

[0352] The active pattern A10 of T10 and the active pattern A11 of T11 are integrally formed.

[0353] Figure 9 is a layout diagram of the light-shielding layer in Figure 8A, Figure 10 is a layout diagram of the first semiconductor layer in Figure 8A, Figure 11 is a layout diagram of the first gate metal layer in Figure 8A, Figure 12 is a layout diagram of the second gate metal layer in Figure 8A, Figure 13 is a layout diagram of the second semiconductor layer in Figure 8A, Figure 14 is a layout diagram of the third gate metal layer in Figure 8A, Figure 15 is a layout diagram of the first source / drain metal layer in Figure 8A, and Figure 16A is a layout diagram of the second source / drain metal layer in Figure 8A.

[0354] In Figure 9, the gate labeled G22 is the second gate of T2, the gate labeled G42 is the second gate of T4, the gate labeled G72 is the second gate of T7, the gate labeled G82 is the second gate of T8, the gate labeled G92 is the second gate of T9, the gate labeled G102 is the second gate of T10, and the gate labeled G112 is the second gate of T11.

[0355] In Figure 10, the active pattern labeled A2 is T2, the active pattern labeled A4 is T4, the active pattern labeled A7 is T7, the active pattern labeled A8 is T8, the active pattern labeled A9 is T9; the active pattern labeled A10 is T10, and the active pattern labeled A11 is T11.

[0356] In Figure 11, the first gate of T2 is labeled G21, the first gate of T4 is labeled G41, the first gate of T7 is labeled G71, the first gate of T8 is labeled G81, the first gate of T9 is labeled G91, the first gate of T10 is labeled G101, and the first gate of T11 is labeled G111; the first plate of C1 is labeled C1a, and the first plate of C2 is labeled C2a.

[0357] In Figure 12, G12 is the second gate of T1, G32 is the second gate of T3; C1b is the second electrode of C1, and C2b is the second electrode of C2.

[0358] In Figure 13, the active graphic unit labeled A1 is T1; the first active graphic unit labeled A31 is the first active graphic unit; the second active graphic unit labeled A32 is the second active graphic unit; and the third active graphic unit labeled A33 is the third active graphic unit.

[0359] In Figure 14, the gate labeled G11 is the first gate of T1, and the gate labeled G31 is the first gate of T3.

[0360] In Figure 15, the line labeled GTLN is the drive output signal line of the Nth stage drive circuit.

[0361] Figure 17A is a stacking diagram of the light-shielding layer and the first semiconductor layer in Figure 8A;

[0362] Figure 17B is a stack-up diagram of the first semiconductor layer and the first gate metal layer in Figure 8A;

[0363] Figure 17C is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 8A;

[0364] Figure 17D is a stack-up diagram of the second gate metal layer and the second semiconductor layer in Figure 8A;

[0365] Figure 17E is a stack-up diagram of the second semiconductor layer and the third gate metal layer in Figure 8A;

[0366] Figure 17F is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 8A;

[0367] Figure 17G is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 8A.

[0368] The bottom gate of the LTPS transistor is provided in the light-shielding layer shown in Figure 9; as shown in Figure 9, the second gate G22 of T2, the second gate G42 of T4, the second gate G72 of T7, the second gate G82 of T8, the second gate G92 of T9, the second gate G102 of T10 and the second gate G112 of T11 are formed in the light-shielding layer.

[0369] As shown in Figure 9, the second gate G72 of T7 and the second gate G82 of T8 are on different horizontal lines, so as to narrow the horizontal space occupied by the driving circuit.

[0370] In the first semiconductor layer shown in Figure 10, an active pattern of an LTPS transistor is provided; as shown in Figure 10, the active patterns A1 of T2, A4 of T4, A7 of T7, A8 of T8, A9 of T9, A10 of T10, A11 of T11 and A4 of T4 are formed in the first semiconductor layer.

[0371] In the first gate metal layer shown in Figure 11, the top gate of the LTPS transistor and the first plate of the capacitor are formed; as shown in Figure 11, the first gate G21 of T2, the first gate G41 of T4, the first gate G71 of T7, the first gate G81 of T8, the first gate G91 of T9, the first gate G101 of T10, the first gate T11 of T11 and the first gate G41 of T4 are all formed in the first gate metal layer; the first plate C1a of C1 and the first plate C2a of C2 are both formed in the first gate metal layer.

[0372] As shown in Figure 11, the first gate G71 of T7 and the first gate G81 of T8 are on different horizontal lines, so as to narrow the horizontal space occupied by the driving circuit.

[0373] In the second gate metal layer shown in Figure 12, the bottom gate of the oxide transistor and the second plate of the capacitor are formed; as shown in Figure 12, the second gate G12 of T1 and the second gate G32 of T3 are formed in the second gate metal layer, and the second plate C1b of C1 and the second plate C2b of C2 are formed in the second gate metal layer.

[0374] In the second semiconductor layer shown in FIG13, an active pattern of an oxide transistor is formed; as shown in FIG13, the active pattern A1 of T1, the first active pattern portion A31 of T3, the second active pattern portion A32 of T3 and the third active pattern portion A33 of T3 are all formed in the second semiconductor layer.

[0375] In the third gate metal layer shown in Figure 14, the top gate of the oxide transistor is formed; as shown in Figure 14, the first gate G11 of T1 and the first gate G31 of T3 are formed in the third gate metal layer.

[0376] In the first source-drain metal layer shown in Figure 15, drive output lines of each stage of drive circuits are formed; in Figure 15, the line labeled GTLN is the drive output signal line of the Nth stage drive circuit.

[0377] In the second source-drain metal layer shown in Figure 16A, multiple signal lines and cascaded output signal lines of each stage of driving circuits are formed. In Figure 16A, the line labeled CRLN is the cascaded output signal line of the Nth stage driving circuit, and it is formed in the second source-drain metal layer along with the first low voltage line VGL1, the first clock signal line CK1, the third clock signal line CK3, the second clock signal line CK2, the fourth clock signal line CK4, the starting voltage line STV, the second low voltage line VGL2, the first high voltage line VGH1, and the second high voltage line VGH2. The first low voltage line VGL1, the first clock signal line CK1, the third clock signal line CK3, the second clock signal line CK2, the fourth clock signal line CK4, the starting voltage line STV, the second low voltage line VGL2, the first high voltage line VGH1, and the second high voltage line VGH2 are arranged sequentially along the direction close to the display area.

[0378] As shown in Figures 8A-17G, the orthographic projections of G21 and G22 on the substrate at least partially overlap; the orthographic projections of G71 and G72 on the substrate at least partially overlap; the orthographic projections of G81 and G82 on the substrate at least partially overlap; the orthographic projections of G91 and G92 on the substrate at least partially overlap; the orthographic projections of G101 and G102 on the substrate at least partially overlap; the orthographic projections of G111 and G112 on the substrate at least partially overlap; and G41 on the substrate... The orthographic projection of G21 on the substrate at least partially overlaps with the orthographic projection of G42 on the substrate, so that G21 and G22 are electrically connected, G71 and G72 are electrically connected, G81 and G82 are electrically connected, G91 and G92 are electrically connected, G101 and G102 are electrically connected, G111 and G112 are electrically connected, and G41 and G42 are electrically connected, so that T2, T7, T8, T9, T10, T11, T12 and T4 are top-bottom dual-gate transistors, so as to increase the on-state level of the top-bottom dual-gate transistors, so that the size of the top-bottom dual-gate transistors can be appropriately reduced to save the layout space occupied by the transistors.

[0379] As shown in Figure 10, A10 and A11 are integrally formed and are arranged vertically to save horizontal space;

[0380] A2, A7, A8, A9, A10, and A4 are arranged along the direction closest to the display area.

[0381] As shown in Figure 11, G101 and C2a are integrally formed, and G111 and C1a are integrally formed, so as to facilitate the electrical connection between G101 and C2a and between G111 and C1a, thereby improving the connection performance and simplifying the process.

[0382] As shown in Figures 8A-17G, the orthographic projection of C1a on the substrate and the orthographic projection of C1b on the substrate at least partially overlap to increase the facing area of ​​C1a and C1b, which is beneficial for the formation of C1.

[0383] The orthographic projection of C2a onto the substrate and the orthographic projection of C2b onto the substrate at least partially overlap to increase the facing area of ​​C2a and C2b, which is beneficial for the formation of C2.

[0384] As shown in Figures 8A-17G, the orthographic projection of G11 on the substrate and the orthographic projection of G12 on the substrate at least partially overlap, so that G11 and G12 can be electrically connected, so that T1 is a top-bottom dual-gate transistor, so as to increase the on-state level of T1, so that the size of T1 can be appropriately reduced, thereby saving the layout space occupied by oxide transistors.

[0385] The orthographic projection of G31 on the substrate at least partially overlaps with the orthographic projection of G32 on the substrate, so that G31 and G32 can be electrically connected, so that T3 is a top-bottom dual-gate transistor, so as to increase the on-state level of T3, and so that the size of T3 can be appropriately reduced to save the layout space occupied by oxide transistors.

[0386] In Figure 16A, the line labeled CRLN-2 is the cascaded output signal line of the (N-2)th stage driver circuit, the line labeled CRLN is the cascaded output signal line of the Nth stage driver circuit, the line labeled CRLN+1 is the cascaded output signal line of the N+1th stage driver circuit, the line labeled CRLN+2 is the cascaded output signal line of the N+2th stage driver circuit, and the line labeled CRLN+3 is the cascaded output signal line of the N+3rd stage driver circuit.

[0387] As shown in Figure 16B, the part labeled B02 is the second cascaded output line part included in CRLN-2, the part labeled B11 is the first cascaded output line part included in CRLN, the part labeled B12 is the second cascaded output line part included in CRLN, the part labeled B21 is the first cascaded output line part included in CRLN+1, the part labeled B22 is the second cascaded output line part included in CRLN+1, the part labeled B31 is the first cascaded output line part included in CRLN+2, the part labeled B32 is the second cascaded output line part included in CRLN+2, and the part labeled B41 is the first cascaded output line part included in CRLN+3.

[0388] As shown in Figure 16B, B11, B21, B31 and B41 are arranged in sequence along the vertical direction, and B02, B12, B22 and B32 are arranged in the vertical direction.

[0389] B11 is located on the side of B02 furthest from display VGH1, B12 is located on the side of B21 closest to VGH1, B31 is located on the side of B22 furthest from VGH1, and B32 is located on the side of B41 closest to VGH1.

[0390] As shown in Figure 16A, VGL1, CK1, CK3, CK2, CK4, STV, VGL2, VGH1 and VGH2 all extend vertically, and are arranged sequentially along the side closest to the display area.

[0391] As shown in Figure 8A, the orthographic projection of the cascaded output signal line CRLN of the Nth stage driving circuit on the substrate at least partially overlaps with the orthographic projection of the first via H1 on the substrate, and the orthographic projection of the cascaded output signal line CRLN of the Nth stage driving circuit on the substrate at least partially overlaps with the orthographic projection of the second via H2 on the substrate. The cascaded output signal line is set by utilizing the position of the via, which helps to save space.

[0392] The first via H1 is the connection via between the gate of T10 and the second electrode of T8 in the N+1th stage drive circuit;

[0393] The second via H2 is the connection via between the gate of T11 and the second electrode of T9 in the N+1 stage drive circuit.

[0394] Figure 17H ​​is a schematic diagram of the first semiconductor layer, the first gate metal layer, the second gate metal layer, and the first source / drain metal layer in Figure 8A being electrically connected through vias penetrating the first interlayer dielectric layer.

[0395] Figure 17I is a schematic diagram of the electrical connection between the second semiconductor layer, the third gate metal layer and the first source / drain metal layer in Figure 8A through a via penetrating the second interlayer dielectric layer.

[0396] Figure 17J is a schematic diagram of the electrical connection between the light-shielding layer and the first source / drain metal layer in Figure 8A through a deep hole penetrating the first interlayer dielectric layer and the second interlayer dielectric layer.

[0397] Figure 17K is a schematic diagram showing the electrical connection between the first source / drain metal layer and the second source / drain metal layer through vias penetrating the passivation layer and the planarization layer.

[0398] As shown in Figure 17H, the active pattern formed on the first semiconductor layer, the conductive pattern formed on the first gate metal layer, the conductive pattern formed on the second gate metal layer, and the conductive pattern formed on the first source / drain metal layer can be electrically connected to each other through vias penetrating the first interlayer dielectric layer.

[0399] As shown in Figure 17I, the active pattern formed on the second semiconductor layer, the conductive pattern formed on the third gate metal layer, and the conductive pattern formed on the first source / drain metal layer can be electrically connected to each other through vias penetrating the second interlayer dielectric layer.

[0400] As shown in Figure 17J, the conductive patterns formed on the light-shielding layer and the conductive patterns formed on the first source / drain metal layer can be electrically connected to each other through the stacked vias penetrating the first interlayer dielectric layer and the second interlayer dielectric layer.

[0401] As shown in Figure 17K, the conductive patterns formed in the first source / drain metal layer and the conductive patterns formed in the second source / drain metal layer can be electrically connected to each other through the stacked vias penetrating the passivation layer and the planarization layer.

[0402] Figure 18 is a layout diagram of the four-stage drive circuit included in the drive module. The structure of the drive circuit in Figure 18 is shown in Figure 4.

[0403] In Figure 18, the transistor labeled T3 is the third transistor, the transistor labeled T4 is the fourth transistor, the transistor labeled T5 is the fifth transistor, and the transistor labeled T6 is the sixth transistor.

[0404] As shown in Figure 18, T5 and T3 are arranged in the vertical direction;

[0405] The orthographic projection of T6 onto the substrate at least partially overlaps with the orthographic projection of VGH2 onto the substrate;

[0406] The orthographic projection of T4 onto the substrate at least partially overlaps with the orthographic projection of VGH2 onto the substrate;

[0407] T6 and T4 are arranged vertically.

[0408] The difference between the at least one embodiment shown in Figure 18 and the at least one embodiment shown in Figure 8A is that T5 and T6 are added;

[0409] Setting T5 above T3 and utilizing the space above T3 helps to narrow the horizontal space and achieve a narrow bezel; setting T6 on the side of T5 closer to the display area, and the orthographic projection of T6 on the substrate at least partially overlaps with the orthographic projection of VGH2 on the substrate.

[0410] As shown in Figure 22, the second gate G52 of T5 and the second gate G32 of T3 are formed on the second gate metal layer;

[0411] As shown in Figure 23, the first part A51 of the active pattern of T5, the first part A31 of the active pattern of T3, the second part A52 of the active pattern of T5, the second part A32 of the active pattern of T3, and the active pattern A6 of T6 are all formed on the second semiconductor layer.

[0412] As shown in Figure 24, the first gate G51 of T5, the first gate G31 of T3, and the gate G6 of T6 are all formed on the third gate metal layer.

[0413] Figure 19 is a layout diagram of the light-shielding layer in Figure 18, Figure 20 is a layout diagram of the first semiconductor layer in Figure 18, Figure 21 is a layout diagram of the first gate metal layer in Figure 18, Figure 22 is a layout diagram of the second gate metal layer in Figure 18, Figure 23 is a layout diagram of the second semiconductor layer in Figure 18, Figure 24 is a layout diagram of the third gate metal layer in Figure 18, Figure 25 is a layout diagram of the first source / drain metal layer in Figure 18, and Figure 26 is a layout diagram of the second source / drain metal layer in Figure 18.

[0414] As shown in Figure 22, G52 is the second gate of T5, and G32 is the second gate of T3. G52 and G32 are integrally formed to improve the connection performance between the second gate G52 of T5 and the second gate G32 of T3, and to simplify the process.

[0415] As shown in Figure 23, A51 is the first part of the active pattern of T5, and A52 is the second part of the active pattern of T5.

[0416] The active graphic of T3 is labeled A31, which is the first part, and the active graphic of T3 is labeled A32, which is the second part.

[0417] A51 and A31 are integrally molded, and A52 and A32 are integrally molded to improve the connection performance between A51 and A31, improve the connection performance between A52 and A32, and simplify the process;

[0418] The active graphic labeled A6 is T6.

[0419] In Figure 24, the gate labeled G51 is the first gate of T5, the gate labeled G31 is the first gate of T3, and the gate labeled G6 is the gate of T6.

[0420] G51 and G31 are integrally molded to improve the connection performance between the first gate G51 of T5 and the first gate G31 of T3, and to simplify the process.

[0421] In at least one embodiment shown in Figures 18-26, T6 is a single-gate transistor.

[0422] In Figure 25, the line labeled GTLN is the drive output signal line of the Nth stage drive circuit.

[0423] In Figure 26, the line labeled CRLN is the cascaded output signal line of the Nth stage drive circuit.

[0424] Figure 27A is a stack-up diagram of the first gate metal layer and the second gate metal layer in Figure 18;

[0425] Figure 27B is a stack-up diagram of the second gate metal layer and the second semiconductor layer in Figure 18;

[0426] Figure 27C is a stack-up diagram of the second semiconductor layer and the third gate metal layer in Figure 18;

[0427] Figure 27D is a stack-up diagram of the third gate metal layer and the first source / drain metal layer in Figure 18;

[0428] Figure 27E is a stack-up diagram of the first source / drain metal layer and the second source / drain metal layer in Figure 18.

[0429] Figure 28 is a layout diagram of the four-stage drive circuit included in the drive module. The structure of the drive circuit in Figure 28 is shown in Figure 5.

[0430] In Figure 28, the transistor labeled T3 is the third transistor, the transistor labeled T4 is the fourth transistor, the transistor labeled T5 is the fifth transistor, and the transistor labeled T6 is the sixth transistor.

[0431] As shown in Figure 28, T5 and T3 are arranged in the vertical direction;

[0432] The orthographic projection of T6 onto the substrate at least partially overlaps with the orthographic projection of VGH2 onto the substrate;

[0433] The orthographic projection of T4 onto the substrate at least partially overlaps with the orthographic projection of VGH2 onto the substrate;

[0434] T6 and T4 are arranged vertically, and T6 is placed in the space above T4, which helps to save space.

[0435] In at least one embodiment shown in FIG28, the first gate G61 of T6 is electrically connected to the Nth stage drive output terminal; the Nth stage drive output terminal is electrically connected to the drive output signal line GTLN of the Nth stage drive circuit.

[0436] The second gate G62 of T6 is electrically connected to the second electrode D6 of T6, and the second electrode D6 of T6 is electrically connected to the first electrode S3 of T3.

[0437] The difference between the at least one embodiment shown in Figure 28 and the at least one embodiment shown in Figure 18 is as follows: T6 is a dual-gate transistor;

[0438] As shown in Figure 29, the second gate G62 of T6 is formed on the second gate metal layer;

[0439] In Figure 31, the first gate G61 of T6 is formed on the third gate metal layer.

[0440] Figure 29 is a layout diagram of the second gate metal layer in Figure 28, Figure 30 is a layout diagram of the second semiconductor layer in Figure 28, Figure 31 is a layout diagram of the third gate metal layer in Figure 28, and Figure 32 is a layout diagram of the first source / drain metal layer in Figure 28.

[0441] The layout of the light-shielding layer in Figure 28 can be shown in Figure 19, the layout of the first semiconductor layer in Figure 28 can be shown in Figure 20, the layout of the first gate metal layer in Figure 28 can be shown in Figure 21, and the layout of the second source / drain metal layer in Figure 28 can be shown in Figure 26.

[0442] As shown in Figure 29, the gate labeled G52 is the second gate of T5, the gate labeled G32 is the second gate of T3, and the gate labeled G62 is the second gate of T6.

[0443] In Figure 30, the electrode labeled D6 is the second electrode of T6;

[0444] In Figure 31, the gate labeled G51 is the first gate of T5, the gate labeled G31 is the first gate of T3, and the gate labeled G61 is the first gate of T6.

[0445] In Figure 32, the electrode labeled S3 is the first electrode of T3, and the electrode labeled GTLN is the drive output signal line of the Nth stage drive circuit.

[0446] As shown in Figure 29, the second gate G62 of T6 is L-shaped, and the first electrode S3 of T3 is L-shaped, so that G62, S3 and D6 can be electrically connected to each other.

[0447] In at least one embodiment shown in Figures 28-32, T6 is a dual-gate transistor.

[0448] Figure 33A is a stacked diagram of the second gate metal layer and the second semiconductor layer in Figure 28, Figure 33B is a stacked diagram of the second semiconductor layer and the third gate metal layer, and Figure 33C is a stacked diagram of the third gate metal layer and the first source / drain metal layer.

[0449] Figure 34 is a layout diagram of the four-stage drive circuit included in the drive module. The structure of the drive circuit in Figure 34 is shown in Figure 6.

[0450] Figure 35 is a layout diagram of the second gate metal layer in Figure 34. In Figure 35, the second gate of T6 is labeled G62.

[0451] Figure 36 is a layout diagram of the third gate metal layer in Figure 34. In Figure 36, the first gate of T6 is labeled G61.

[0452] Figure 37 is a layout diagram of the first source-drain metal layer in Figure 34; in Figure 37, the line labeled GTLN is the drive output signal line of the Nth stage drive circuit.

[0453] The layout of the shielding layer in Figure 34 can be shown in Figure 19. The layout of the first semiconductor layer in Figure 34 is shown in Figure 20. The layout of the first gate metal layer in Figure 34 is shown in Figure 21. The layout of the second semiconductor layer in Figure 34 is shown in Figure 23. The layout of the second source / drain metal layer in Figure 34 is shown in Figure 26.

[0454] As shown in Figures 34-37, G61 and G62 are both electrically connected to GTLN, and T6 is a top-bottom dual-gate transistor.

[0455] In at least one embodiment shown in Figures 34-37, G62 and G61 are strips.

[0456] Figure 38A is a layout diagram of the second gate metal layer and the second semiconductor layer in Figure 34, Figure 38B is a layout diagram of the second semiconductor layer and the third gate metal layer in Figure 34, and Figure 38C is a layout diagram of the third gate metal layer and the first source / drain metal layer in Figure 34.

[0457] The display substrate described in this embodiment includes a substrate and a driving module and a third voltage line disposed on the substrate; the driving module includes a cascaded output circuit, a driving output circuit, a driving output signal line, and a cascaded output signal line;

[0458] The cascaded output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal terminal, and the cascaded output terminal, respectively. It is used to control the output of the cascaded output signal through the cascaded output terminal under the control of the potential of the first output node and the potential of the second output node, according to the first voltage signal provided by the first voltage line and the second clock signal provided by the second clock signal terminal.

[0459] The drive output circuit is electrically connected to the cascaded output terminal, the second voltage line, the third voltage line and the drive output terminal respectively, and is used to control the drive signal to be provided through the drive output terminal under the control of the cascaded output signal, according to the second voltage signal provided by the second voltage line and the third voltage signal provided by the third voltage line;

[0460] The cascaded output terminal is electrically connected to the cascaded output signal line, and the drive output terminal is electrically connected to the drive output signal line;

[0461] The orthographic projection of the cascaded output signal line on the substrate and the orthographic projection of the drive output signal line on the substrate do not overlap simultaneously with the orthographic projection of the third voltage line on the substrate.

[0462] In at least one embodiment of this disclosure, the orthographic projection of the cascaded output signal line on the substrate and the orthographic projection of the drive output signal line on the substrate do not overlap with the orthographic projection of the third voltage line on the substrate at the same time, so as to prevent the coupling interference of signals between the cascaded output signal line and the drive output signal line.

[0463] Furthermore, when the orthographic projection of the cascaded output signal line on the substrate or the orthographic projection of the drive output signal line on the substrate overlaps with the orthographic projection of the third voltage line on the substrate, lateral space can be saved, which is beneficial for achieving a narrow bezel.

[0464] Optionally, the third voltage line can be the second high voltage line.

[0465] In Figure 15, the line labeled GTLN is the drive output signal line of the Nth stage drive circuit.

[0466] In Figure 16A, the line labeled CRLN is the cascaded output signal line of the Nth stage drive circuit.

[0467] As shown in Figure 8A, the line labeled VGH1 is the first high-voltage line;

[0468] As shown in Figures 8A-17G, the orthographic projection of GTLN on the substrate and the orthographic projection of CRLN on the substrate are set on opposite sides of the orthographic projection of VGH1 on the substrate.

[0469] The orthographic projections of GTLN and VGH1 on the substrate do not overlap, and the orthographic projections of CRLN and VGH1 on the substrate do not overlap. This reduces the coupling capacitance between the drive output signal line of the Nth stage drive circuit and the first high-voltage line VGH1, and also reduces the coupling capacitance between the cascaded output signal line CRLN of the Nth stage drive circuit and the first high-voltage line VGH1, thereby stabilizing the output of the drive signal and the cascaded signal.

[0470] The manufacturing method described in this disclosure is used to manufacture the above-mentioned display substrate, and the manufacturing method includes:

[0471] A driving module, a first voltage line, a second voltage line, and a third voltage line are fabricated on a substrate. The driving module includes a multi-stage driving circuit. The first voltage line, the second voltage line, the third voltage line, and the driving module are disposed in a peripheral area. The driving circuit includes an output node control circuit, a cascaded output circuit, and a driving output circuit.

[0472] The orthographic projection of at least a portion of the transistors included in the drive output circuit onto the substrate is positioned between the orthographic projection of the first voltage line onto the substrate and the orthographic projection of the third voltage line onto the substrate.

[0473] The manufacturing method described in this disclosure is used to manufacture the above-mentioned display substrate, and the manufacturing method includes:

[0474] A drive module and a third voltage line are fabricated on a substrate; the drive module includes a multi-stage drive circuit; the drive circuit includes a cascaded output circuit and a drive output circuit;

[0475] The orthographic projections of the cascaded output signal line and the drive output signal line on the substrate are configured to not overlap with the orthographic projection of the third voltage line on the substrate.

[0476] In at least one embodiment of this disclosure, the orthographic projection of the cascaded output signal line on the substrate and the orthographic projection of the drive output signal line on the substrate do not overlap with the orthographic projection of the third voltage line on the substrate at the same time, so as to prevent the coupling interference of signals between the cascaded output signal line and the drive output signal line.

[0477] Furthermore, when the orthographic projection of the cascaded output signal line on the substrate or the orthographic projection of the drive output signal line on the substrate overlaps with the orthographic projection of the third voltage line on the substrate, lateral space can be saved, which is beneficial for achieving a narrow bezel.

[0478] The display device described in this disclosure includes the display substrate described above.

[0479] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising a substrate and a driving module, a first voltage line, a second voltage line and a third voltage line disposed on the substrate, wherein the driving module includes a multi-stage driving circuit; The driving circuit includes an output node control circuit, a cascaded output circuit, and a driving output circuit. The output node control circuit is electrically connected to the input terminal, the first output node, the second output node and the first clock signal terminal respectively, and is used to control the potential of the first output node and the potential of the second output node under the control of the input signal provided by the input terminal and the first clock signal provided by the first clock signal terminal. The cascaded output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal terminal, and the cascaded output terminal, respectively. It is used to control the output of the cascaded output signal through the cascaded output terminal under the control of the potential of the first output node and the potential of the second output node, according to the first voltage signal provided by the first voltage line and the second clock signal provided by the second clock signal terminal. The drive output circuit is electrically connected to the cascaded output terminal, the second voltage line, the third voltage line and the drive output terminal respectively, and is used to control the drive signal to be provided through the drive output terminal under the control of the cascaded output signal, according to the second voltage signal provided by the second voltage line and the third voltage signal provided by the third voltage line; The orthographic projection of at least a portion of the transistors included in the drive output circuit onto the substrate is disposed between the orthographic projection of the first voltage line onto the substrate and the orthographic projection of the third voltage line onto the substrate.

2. The display substrate as claimed in claim 1, wherein, The orthographic projection of the transistors in the drive output circuit onto the substrate and the orthographic projection of the third voltage line onto the substrate at least partially overlap.

3. The display substrate as described in claim 1, wherein, The display substrate includes a display area and a peripheral area; the first voltage line, the second voltage line, the third voltage line, and the driving module are disposed in the peripheral area; The orthographic projections of the third voltage line on the substrate, the first voltage line on the substrate, and the second voltage line on the substrate are arranged sequentially along a direction away from the display area.

4. The display substrate as described in claim 3, wherein, The cascaded output circuit includes at least a portion of the transistors whose orthogonal projections on the substrate are disposed between the orthogonal projections of the second voltage line on the substrate and the orthogonal projections of the first voltage line on the substrate.

5. The display substrate as claimed in claim 4, wherein, The cascaded output circuit includes at least two transistors, which are arranged along a first direction.

6. The display substrate as claimed in claim 3, wherein, The driving circuit also includes a first energy storage circuit and a second energy storage circuit; The first terminal of the first energy storage circuit is electrically connected to the second output node, and the second terminal of the first energy storage circuit is electrically connected to the cascaded output terminal. The first terminal of the second energy storage circuit is electrically connected to the first output node, and the second terminal of the second energy storage circuit is electrically connected to the first voltage line. The orthographic projection of the capacitor included in the first energy storage circuit onto the substrate at least partially overlaps with the first voltage line; The orthogonal projection of the capacitor included in the second energy storage circuit onto the substrate at least partially overlaps with the first voltage line.

7. The display substrate as claimed in claim 6, wherein, The orthographic projection of the capacitor included in the second energy storage circuit onto the substrate and the orthographic projection of the capacitor included in the first energy storage circuit onto the substrate are arranged along the first direction.

8. The display substrate according to any one of claims 1 to 7, wherein, It also includes a fourth voltage line disposed on the substrate; the output node control circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, and a second output node control circuit; The first node control circuit is electrically connected to the input terminal, the first voltage line, the second voltage line and the first node respectively, and is used to control the connection or disconnection between the first node and the first voltage line, and the connection or disconnection between the first node and the second voltage line under the control of the input signal provided by the input terminal; The second node control circuit is electrically connected to the first clock signal terminal, the input terminal, and the second node, respectively, and is used to write the input signal into the second node under the control of the first clock signal provided by the first clock signal terminal; The first output node control circuit is electrically connected to the first clock signal terminal, the first node and the first output node respectively, and is used to control the connection or disconnection between the first node and the first output node under the control of the first clock signal. The second output node control circuit is electrically connected to the fourth voltage line, the second node, and the second output node, respectively, and is used to control the connection or disconnection between the second node and the second output node under the control of the fourth voltage signal provided by the fourth voltage line.

9. The display substrate as claimed in claim 8, wherein, The orthographic projection of the transistors in the second output node control circuit onto the substrate at least partially overlaps with the orthographic projection of the second voltage line onto the substrate.

10. The display substrate as claimed in claim 8, wherein, The orthographic projections of the second voltage line onto the substrate and the orthographic projections of the fourth voltage line onto the substrate are aligned along a direction away from the display area; The orthographic projection of the transistors included in the second node control circuit onto the substrate, and the orthographic projection of the transistors included in the first output node control circuit onto the substrate, are disposed between the orthographic projection of the second voltage line onto the substrate and the orthographic projection of the fourth voltage line onto the substrate.

11. The display substrate as claimed in claim 8, wherein, It also includes a starting voltage line disposed on the substrate; The orthographic projection of the transistors in the first output node control circuit onto the substrate at least partially overlaps with the orthographic projection of the starting voltage line onto the substrate.

12. The display substrate as claimed in claim 8, wherein, It also includes multiple clock signal lines disposed on the substrate; The orthographic projection of at least some of the transistors in the second node control circuit onto the substrate at least partially overlaps with the orthographic projection of at least one of the clock signal lines onto the substrate.

13. The display substrate as claimed in claim 8, wherein, It also includes multiple clock signal lines disposed on the substrate; The orthographic projection of the clock signal line on the substrate is positioned between the orthographic projection of the second voltage line on the substrate and the orthographic projection of the fourth voltage line on the substrate; The first node control circuit includes at least a portion of the transistors whose orthogonal projections on the substrate are disposed between the orthogonal projections of the fourth voltage line on the substrate and the orthogonal projections of the clock signal line on the substrate.

14. The display substrate as claimed in claim 13, wherein, The first node control circuit includes at least two transistors, which are arranged sequentially along a first direction.

15. The display substrate as claimed in claim 13, wherein, The first node control circuit includes a first transistor and a second transistor; The first transistor is an oxide transistor, and the second transistor is a low-temperature polysilicon transistor; The first transistor includes a first gate and a second gate; The first gate of the first transistor is electrically connected to the input terminal, the second gate of the first transistor is electrically connected to the fourth voltage line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node. The gate of the second transistor is electrically connected to the input terminal, the first electrode of the second transistor is electrically connected to the first voltage line, and the second electrode of the second transistor is electrically connected to the first node.

16. The display substrate as claimed in claim 15, wherein, The fourth voltage line is the first low voltage line, and the second voltage line is the second low voltage line; The voltage value of the first low voltage signal provided by the first low voltage line is less than the voltage value of the second low voltage signal provided by the second low voltage line.

17. The display substrate as claimed in claim 15, wherein, The device includes a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer arranged sequentially along a direction away from the substrate; the gate of the second transistor includes a first gate of the second transistor and a second gate of the second transistor; the first gate of the second transistor is formed on the first gate metal layer, and the second gate of the second transistor is formed on the light-shielding layer; the active pattern of the second transistor is formed on the first semiconductor layer; the second gate of the first transistor is formed on the second gate metal layer, the first gate of the first transistor is formed on the third gate metal layer, and the active pattern of the first transistor is formed on the second semiconductor layer.

18. The display substrate as claimed in claim 8, wherein, The drive output circuit includes a third transistor and a fourth transistor; The active pattern of the third transistor includes at least two active pattern portions; The orthographic projection of at least one active pattern portion of the third transistor onto the substrate and the orthographic projection of the active pattern of the fourth transistor onto the substrate are aligned along a first direction.

19. The display substrate as claimed in claim 1, wherein, The drive output circuit includes a third transistor and a fourth transistor; the third transistor is an oxide transistor, and the fourth transistor is a low-temperature polysilicon transistor. The third transistor includes a first gate and a second gate; The first gate and the second gate of the third transistor are both electrically connected to the cascaded output terminal, the first electrode of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the drive output terminal. The gate of the fourth transistor is electrically connected to the cascaded output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage line, and the second electrode of the fourth transistor is electrically connected to the drive output terminal.

20. The display substrate as claimed in claim 19, wherein, The device includes a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer arranged sequentially along a direction away from the substrate; the gate of the fourth transistor includes a first gate and a second gate of the fourth transistor; the first gate of the fourth transistor is formed on the first gate metal layer, and the second gate of the fourth transistor is formed on the light-shielding layer; the active pattern of the fourth transistor is formed on the first semiconductor layer; the second gate of the third transistor is formed on the second gate metal layer, the first gate of the third transistor is formed on the third gate metal layer, and the active pattern of the third transistor is formed on the second semiconductor layer.

21. The display substrate as claimed in claim 1, wherein, The drive output circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The third transistor, the fifth transistor, and the sixth transistor are all oxide transistors, and the fourth transistor is a low-temperature polycrystalline silicon transistor; The gate of the third transistor is electrically connected to the cascaded output terminal, the first electrode of the third transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the third transistor is electrically connected to the drive output terminal. The gate of the fifth transistor is electrically connected to the cascaded output terminal, and the first electrode of the fifth transistor is electrically connected to the second voltage line; The gate of the sixth transistor is electrically connected to the drive output terminal, the first electrode of the sixth transistor is electrically connected to the third voltage line, and the second electrode of the sixth transistor is electrically connected to the first electrode of the third transistor. The gate of the fourth transistor is electrically connected to the cascaded output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage line, and the second electrode of the fourth transistor is electrically connected to the drive output terminal. The orthographic projection of the third transistor on the substrate and the orthographic projection of the fifth transistor on the substrate are positioned between the orthographic projection of the first voltage line on the substrate and the orthographic projection of the third voltage line on the substrate. The orthographic projection of the fourth transistor on the substrate at least partially overlaps with the orthographic projection of the third voltage line on the substrate; The orthographic projection of the sixth transistor on the substrate at least partially overlaps with the orthographic projection of the third voltage line on the substrate; The fifth transistor and the third transistor are arranged along a first direction.

22. The display substrate as claimed in claim 21, wherein, The third transistor and the fifth transistor are dual-gate transistors. The first gate and the second gate of the third transistor are both electrically connected to the cascaded output terminal, and the first gate and the second gate of the fifth transistor are both electrically connected to the cascaded output terminal. The first gate of the third transistor is a top gate, the second gate of the third transistor is a bottom gate, the first gate of the fifth transistor is a top gate, and the second gate of the fifth transistor is a bottom gate.

23. The display substrate as claimed in claim 22, wherein, The sixth transistor is a dual-gate transistor, and the gate of the sixth transistor is the first gate of the sixth transistor; The first gate of the sixth transistor is electrically connected to the drive output terminal; The second gate of the sixth transistor is electrically connected to the drive output terminal or the second electrode of the sixth transistor; The first gate of the sixth transistor is a top gate, and the second gate of the sixth transistor is a bottom gate.

24. The display substrate as claimed in claim 8, wherein, It also includes a fourth voltage line, a starting voltage line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; In the odd-level drive circuit, the first clock signal terminal is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the third clock signal line. In the even-level driving circuit, the first clock signal terminal is electrically connected to the second clock signal line, and the second clock signal terminal is electrically connected to the fourth clock signal line. The input terminals of the first-stage driving circuit and the second-stage driving circuit are electrically connected to the starting voltage line. The cascaded output of the nth stage driver circuit is electrically connected to the input of the (n+2)th stage driver circuit, where n is a positive integer.

25. The display substrate as claimed in claim 24, wherein, The first voltage line, the second voltage line, the third voltage line, the fourth voltage line, the starting voltage line, the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line all extend along a first direction; The orthographic projections of the third voltage line on the substrate, the first voltage line on the substrate, the second voltage line on the substrate, the starting voltage line on the substrate, and the fourth voltage line on the substrate are arranged sequentially along a direction away from the display area. The orthographic projections of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line on the substrate are disposed between the orthographic projection of the fourth voltage line on the substrate and the orthographic projection of the starting voltage line on the substrate.

26. The display substrate as claimed in claim 24, wherein, The first node control circuit includes a first transistor and a second transistor; The first gate of the first transistor is electrically connected to the input terminal, the second gate of the first transistor is electrically connected to the fourth voltage line, the first electrode of the first transistor is electrically connected to the second voltage line, and the second electrode of the first transistor is electrically connected to the first node. The gate of the second transistor is electrically connected to the input terminal, the first electrode of the second transistor is electrically connected to the first voltage line, and the second electrode of the second transistor is electrically connected to the first node. The drive output circuit includes a third transistor and a fourth transistor; The first gate and the second gate of the third transistor are both electrically connected to the cascaded output terminal, the first electrode of the third transistor is electrically connected to the second voltage line, and the second electrode of the third transistor is electrically connected to the drive output terminal. The gate of the fourth transistor is electrically connected to the cascaded output terminal, the first electrode of the fourth transistor is electrically connected to the third voltage line, and the second electrode of the fourth transistor is electrically connected to the drive output terminal. The output node control circuit includes a first node control circuit, a second node control circuit, a first output node control circuit, and a second output node control circuit; the drive circuit further includes a first energy storage circuit and a second energy storage circuit. The second node control circuit includes a seventh transistor, the first output node control circuit includes an eighth transistor, the second output node control circuit includes a ninth transistor, and the cascaded output circuit includes a tenth transistor and an eleventh transistor. The gate of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the input terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the ninth transistor. The gate of the eighth transistor is electrically connected to the first clock signal terminal, the first electrode of the eighth transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the eighth transistor is electrically connected to the gate of the tenth transistor. The gate of the ninth transistor is electrically connected to the fourth voltage line, and the second electrode of the ninth transistor is electrically connected to the gate of the eleventh transistor. The first electrode of the tenth transistor is electrically connected to the first voltage line, and the second electrode of the tenth transistor is electrically connected to the cascaded output terminal. The first electrode of the eleventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the cascaded output terminal. The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The first plate of the first capacitor is electrically connected to the gate of the eleventh transistor, and the second plate of the first capacitor is electrically connected to the cascaded output terminal. The first plate of the second capacitor is electrically connected to the gate of the tenth transistor, and the second plate of the second capacitor is electrically connected to the first voltage line. The first and third transistors are oxide transistors, while the second, fourth, seventh, eighth, ninth, tenth, and eleventh transistors are all low-temperature polycrystalline silicon transistors.

27. The display substrate as claimed in claim 1, wherein, The output node control circuit includes at least one transistor that is a low-temperature polysilicon transistor, the low-temperature polysilicon transistor including a first gate and a second gate; the first gate of the low-temperature polysilicon transistor is electrically connected to the second gate of the low-temperature polysilicon transistor; the second gate of the low-temperature polysilicon transistor is formed in a light-shielding layer.

28. A display substrate, comprising a substrate and a driving module and a third voltage line disposed on the substrate; the driving module includes a cascaded output circuit, a driving output circuit, a driving output signal line, and a cascaded output signal line; The cascaded output circuit is electrically connected to the first output node, the second output node, the first voltage line, the second clock signal terminal, and the cascaded output terminal, respectively. It is used to control the output of the cascaded output signal through the cascaded output terminal under the control of the potential of the first output node and the potential of the second output node, according to the first voltage signal provided by the first voltage line and the second clock signal provided by the second clock signal terminal. The drive output circuit is electrically connected to the cascaded output terminal, the second voltage line, the third voltage line and the drive output terminal respectively, and is used to control the drive signal to be provided through the drive output terminal under the control of the cascaded output signal, according to the second voltage signal provided by the second voltage line and the third voltage signal provided by the third voltage line; The cascaded output terminal is electrically connected to the cascaded output signal line, and the drive output terminal is electrically connected to the drive output signal line; The orthographic projection of the cascaded output signal line on the substrate and the orthographic projection of the drive output signal line on the substrate do not overlap simultaneously with the orthographic projection of the third voltage line on the substrate.

29. A method of manufacturing a display substrate as described in any one of claims 1 to 27, the method comprising: A driving module, a first voltage line, a second voltage line, and a third voltage line are fabricated on a substrate, wherein the driving module includes a multi-stage driving circuit. The first voltage line, the second voltage line, and the third voltage line are disposed in the surrounding area; the driving circuit includes an output node control circuit, a cascaded output circuit, and a driving output circuit. The orthographic projection of at least a portion of the transistors included in the drive output circuit onto the substrate is positioned between the orthographic projection of the first voltage line onto the substrate and the orthographic projection of the third voltage line onto the substrate.

30. A method for manufacturing a display substrate as described in claim 28, the method comprising: Fabricate the drive module and the third voltage line on the substrate; The drive module includes a multi-stage drive circuit; The driving circuit includes a cascaded output circuit and a driving output circuit; The orthographic projections of the cascaded output signal line and the drive output signal line on the substrate are configured to not overlap with the orthographic projection of the third voltage line on the substrate.

31. A display device comprising a display substrate as claimed in any one of claims 1 to 28.

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