Stacked-chip package and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of packaging, and provides a stacked-chip package and a manufacturing method therefor, and an electronic device. In a package structure, an upper wiring structure and a lower wiring structure (for example, two redistribution layers) are connected by using a prefabricated interconnection module. The stacked-chip package comprises a first chip and a second chip that are stacked, a first wiring structure, a second wiring structure, and a prefabricated interconnection module; the first wiring structure is arranged on the side of the first chip away from the second chip and is electrically connected to the first chip; the second wiring structure is arranged between the first chip and the second chip and is electrically connected to the second chip; the prefabricated interconnection module is connected between the second wiring structure and the first wiring structure; the prefabricated interconnection module comprises a metal pillar and solder points, and by means of the solder points, one end of the metal pillar is electrically connected to the second wiring structure or the first wiring structure, and the other end of the metal pillar is electrically connected to the first wiring structure or the second wiring structure. Use of the prefabricated interconnection module can satisfy the evolution requirements of the package structure.

Description

Chip stacking packaging and its fabrication methods, electronic devices Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a chip stacking package and its manufacturing method, and electronic devices. Background Technology

[0002] POP (package-on-package) packaging is a technology that packages multiple integrated circuits (ICs, chips) together to achieve smaller, lighter, and thinner electronic devices. In POP packaging, one package is stacked on top of another. This technology can improve board space utilization, reduce the overall size and weight of the device, and improve performance.

[0003] Referring to Figure 1, the existing POP package includes a stacked upper package and a lower package. The lower package includes a first rewiring layer RDL1 and a first chip D1 disposed on the first rewiring layer RDL1. The upper package includes a second rewiring layer RDL2 and a second chip D2 disposed on the second rewiring layer RDL2. The first rewiring layer RDL1 and the second rewiring layer RDL2 are connected by a through mold via (TMV).

[0004] As stacked packaging technology continues to evolve, the thickness of the first chip (D1) is increasing, requiring larger heights for the molded via TMV and correspondingly smaller aspect ratios (AR). Furthermore, to meet high-density interconnect requirements, the density of molded via TMVs also needs to be increased. However, current molded via TMV fabrication primarily focuses on thick-film and dry-film processes. This involves first creating a thick layer of photoresist (PR) and opening it, then using electroplating to fabricate the molded via TMV. This method cannot meet the evolving demands of molded via TMVs in terms of AR and density. Summary of the Invention

[0005] This application provides a chip stacking package and its manufacturing method, as well as an electronic device. By using pre-fabricated interconnect modules to achieve the connection between two upper and lower routing structures (such as redistribution layers), it can meet the evolution requirements of chip stacking packages.

[0006] This application provides a chip stacked package, comprising: a first chip and a second chip stacked together, a first wiring structure, a second wiring structure, and a pre-fabricated interconnect module. The first wiring structure is disposed on the side of the first chip away from the second chip and is electrically connected to the first chip. The second wiring structure is disposed between the first chip and the second chip and is electrically connected to the second chip. The pre-fabricated interconnect module connects the second wiring structure and the first wiring structure. The pre-fabricated interconnect module includes metal pillars and solder joints. One end of the metal pillar is electrically connected to the second wiring structure via a solder joint, and the other end is electrically connected to the first wiring structure. Alternatively, one end of the metal pillar is electrically connected to the first wiring structure via a solder joint, and the other end is electrically connected to the second wiring structure.

[0007] In the aforementioned packaging structure, a pre-fabricated interconnect module is used to connect the first and second trace structures. This pre-fabricated interconnect module can be customized according to the requirements of the packaging structure. It is assembled and soldered between the first and second trace structures to meet the vertical interconnection requirements of the first and second trace structures. The vertical interconnect structure (metal pillar) used in this pre-fabricated interconnect module does not need to be fabricated based on thick adhesive or dry film processes, but can be fabricated using other processes (such as electroplating). This allows the aspect ratio (AR) and density of the metal pillars to be unrestricted, thereby meeting the evolving needs of chip stacking packaging.

[0008] In some possible implementations, the first routing structure can be the first routing layer.

[0009] In some possible implementations, the second routing structure can be a second routing layer.

[0010] In some possible implementations, the metal pillars include a first metal pillar and a second metal pillar interconnected along the axial direction. In this case, the metal pillars can be fabricated in segments, thereby better meeting the evolving needs of chip stacking packaging.

[0011] In some possible implementations, the prefabricated interconnect module includes a molding layer and a through-mold via (TMV) disposed in the molding layer, the TMV being used to form a metal pillar. In this case, one end of the TMV is connected to a first or second trace structure via a solder joint, and the other end is connected to either the second or first trace structure.

[0012] In some possible implementations, the molded through-hole (TMV) includes a first copper pillar and a second copper pillar interconnected in a vertical direction, and the first and second copper pillars are connected by a seed layer. The first and second copper pillars can be fabricated using an electroplating process, and a seed layer is formed as an adhesive layer before fabricating the copper pillars; thus, a seed layer is provided between the first and second copper pillars.

[0013] In some possible implementations, the pre-fabricated interconnect module includes a silicon wafer and through-silicon vias (TSVs) disposed in the silicon wafer, which are used to form metal pillars. In this case, one end of the TSV is connected to a first or second trace structure via a solder joint, and the other end is connected to the second or first trace structure.

[0014] In some possible implementations, the prefabricated interconnect module includes a glass sheet and a through-glass via (TGV) disposed within the glass sheet, the TGV serving to form a metal pillar. In this case, one end of the TGV is connected to a first or second trace structure via a solder joint, and the other end is connected to either the second or first trace structure.

[0015] In some possible implementations, the chip stack package also includes a heat sink. A window is provided in the first wiring corresponding to the first chip, and the heat sink is located on the side of the first chip away from the first wiring structure and extends into the window.

[0016] In some possible implementations, the first chip includes a system-on-a-chip (SOC).

[0017] In some possible implementations, the second chip includes a double data rate (DDR) synchronous dynamic random access memory chip.

[0018] In some possible implementations, the thickness of the first chip is greater than 200 μm.

[0019] This application also provides a method for fabricating a chip stacked package, the method comprising: fabricating a first wiring structure; providing a pre-fabricated interconnect module, soldering the pre-fabricated interconnect module to the surface of the first wiring structure, and soldering a first chip to the surface of the first wiring structure; wherein the pre-fabricated interconnect module includes metal pillars and solder joints, and the bottom end of the metal pillar is electrically connected to the first wiring structure through the solder joint; encapsulating the first chip and the pre-fabricated interconnect module with plastic, and exposing the top end of the metal pillar through a grinding process; fabricating a second wiring structure, and placing a second chip on the second wiring structure; wherein the second chip is electrically connected to the metal pillar through the second wiring structure.

[0020] In this fabrication method, a prefabricated interconnect module is used to connect the first wiring structure and the second wiring structure. The vertical interconnect structure (metal pillar) used in the prefabricated interconnect module does not need to be fabricated based on thick adhesive or dry film processes, but can be fabricated using other processes (such as electroplating processes). This allows the aspect ratio (AR) and density of the metal pillars to be unrestricted, thereby meeting the evolution requirements of chip stacking packaging.

[0021] In some possible implementations, the aforementioned prefabricated interconnect module includes: forming a plurality of first metal pillars on a carrier plate, encapsulating the plurality of first metal pillars, and exposing the tops of the plurality of first metal pillars by grinding. A plurality of second metal pillars are formed on the tops of the plurality of first metal pillars, and encapsulated; wherein the bottoms of the plurality of second metal pillars are respectively connected to the tops of the plurality of first metal pillars via conductive adhesive layers. The carrier plate is removed, and a plurality of solder joints are formed at the bottoms of the plurality of first metal pillars, and the tops of the plurality of second metal pillars are exposed by grinding. In other words, the metal pillars in this prefabricated interconnect module are manufactured in segments, thereby effectively meeting the aspect ratio (AR) requirements of the metal pillars.

[0022] This application also provides a method for fabricating a chip stacked package, comprising: fabricating a second wiring structure; providing a pre-fabricated interconnect module; soldering the pre-fabricated interconnect module to the surface of the second wiring structure; and mounting a first chip onto the surface of the second wiring structure; wherein the pre-fabricated interconnect module includes metal pillars and solder joints, and the bottom end of the metal pillars is electrically connected to the second wiring structure through the solder joints; encapsulating the first chip and the pre-fabricated interconnect module with plastic, and exposing the top end of the metal pillars and the connection pads on the surface of the first chip through a grinding process; fabricating a first wiring structure, which is electrically connected to the top end of the metal pillars and the connection pads on the surface of the first chip; and placing a second chip on the surface of the second wiring structure away from the first chip.

[0023] In this fabrication method, a prefabricated interconnect module is used to connect the first wiring structure and the second wiring structure. The vertical interconnect structure (metal pillar) used in the prefabricated interconnect module does not need to be fabricated based on thick adhesive or dry film processes, but can be fabricated using other processes (such as electroplating processes). This allows the aspect ratio (AR) and density of the metal pillars to be unrestricted, thereby meeting the evolution requirements of chip stacking packaging.

[0024] In some possible implementations, the aforementioned prefabricated interconnect module includes: forming a plurality of first metal pillars on a carrier plate, encapsulating the plurality of first metal pillars, and exposing the tops of the plurality of first metal pillars by grinding. A plurality of second metal pillars are formed on the tops of the plurality of first metal pillars, and encapsulated; wherein the bottoms of the plurality of second metal pillars are respectively connected to the tops of the plurality of first metal pillars via conductive adhesive layers. The carrier plate is removed, and a plurality of solder joints are formed at the bottoms of the plurality of first metal pillars, and the tops of the plurality of second metal pillars are exposed by grinding. In other words, the metal pillars in this prefabricated interconnect module are manufactured in segments, thereby effectively meeting the aspect ratio (AR) requirements of the metal pillars.

[0025] This application also provides an electronic device including a circuit board and a chip stack package as provided in any of the aforementioned possible methods, wherein the circuit board is electrically connected to the chip stack package. Attached Figure Description

[0026] Figure 1 is a schematic diagram of a stacked package structure provided in the prior art;

[0027] Figure 2 is a schematic diagram of a stacked package structure provided in an embodiment of this application;

[0028] Figure 3 is a schematic diagram of a stacked package structure provided in an embodiment of this application;

[0029] Figure 4 is a schematic diagram of a stacked package structure provided in an embodiment of this application;

[0030] Figure 5 is a structural schematic diagram of a prefabricated interconnect module provided in an embodiment of this application;

[0031] Figure 6 is a structural schematic diagram of a prefabricated interconnect module provided in an embodiment of this application;

[0032] Figure 7 is a flowchart illustrating the manufacturing process of a prefabricated interconnect module according to an embodiment of this application.

[0033] Figure 8 is a schematic diagram of the manufacturing process of a prefabricated interconnect module provided in an embodiment of this application;

[0034] Figure 9 is a flowchart illustrating the fabrication process of a stacked package according to an embodiment of this application;

[0035] Figure 10 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0036] Figure 11 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0037] Figure 12 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0038] Figure 13 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0039] Figure 14 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0040] Figure 15 is a flowchart illustrating the fabrication process of a stacked package according to an embodiment of this application;

[0041] Figure 16 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0042] Figure 17 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0043] Figure 18 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0044] Figure 19 is a schematic diagram of a stacked package in the manufacturing process according to an embodiment of this application;

[0045] Figure 20 is a schematic diagram of the manufacturing process of a stacked package provided in an embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. "A plurality" refers to two or more. "Connected," "interconnected," etc., should be interpreted broadly, for example, as electrical, mechanical, or integral connections; direct or indirect connections via an intermediate medium. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. "Upper," "lower," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0048] This application provides an electronic device that employs a novel chip stacking packaging structure. During the fabrication process, the chip stacking packaging structure uses pre-fabricated interconnect modules to achieve the connection between the upper and lower redistribution layers. These pre-fabricated interconnect modules can be customized according to the needs of the packaging structure, without the need for fabrication based on thick adhesive or dry film processes, thereby meeting the evolving needs of chip stacking packaging.

[0049] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product, such as consumer electronics, home electronics, vehicle electronics, financial terminal products, communication electronics, etc.

[0050] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can include servers, storage devices, radar, base stations, and other communication equipment.

[0051] Depending on actual needs, the above-mentioned electronic devices may also include other devices that are electrically connected to the chip stack package, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0052] The specific structure of the novel chip stacking package provided in the embodiments of this application will be described below.

[0053] Schematic, referring to Figure 2, this application embodiment provides a chip stacked package, also known as a fan-out package on package. This package structure includes a first rewiring layer RDL1, a second rewiring layer RDL2, a first chip D1, and a second chip D2. The first chip D1 and the second chip D2 are stacked. The first chip D1 is located between the first rewiring layer RDL1 and the second rewiring layer RDL2, with its active surface facing the first rewiring layer RDL1 and electrically connected to it. The second chip D2 is located on the side of the second rewiring layer RDL2 away from the first chip D1 and is electrically connected to the second rewiring layer RDL2.

[0054] Solder joints can be provided on the back side of the first wiring layer RDL (i.e., the side opposite to the first chip). This package structure achieves interconnection and communication with external devices through solder joints. Of course, other devices, such as capacitors, can also be provided on the back side of the first wiring layer RDL to meet the functional requirements of the package structure.

[0055] The solder joints involved in this application can be pads, solder balls, bumps, controlled collapse chip connections (C4), etc. This application does not limit them, and in practice, they can be selected and set according to packaging requirements.

[0056] It should be noted that the first wiring layer RDL1 described above can also be a substrate with wiring patterns or other routing structures. This application does not impose any restrictions on this, and it can be configured as needed in practice. Similarly, the second wiring layer RDL2 can also be a substrate with wiring patterns or other routing structures. This application does not impose any restrictions on this, and it can be configured as needed in practice. In the embodiments of this application, the first wiring layer RDL1 and the second wiring layer RDL2 are used as examples for illustration.

[0057] It should be understood that the redistribution layer is formed by alternating layers of conductive and dielectric layers. The substrate with the wiring pattern includes a substrate and conductive and dielectric layers formed alternately on the substrate.

[0058] This application does not restrict the types of the first chip D1 and the second chip D2; in practice, they can be set as needed.

[0059] Illustratively, in some possible implementations, the first chip D1 can be a system-on-chip (SOC).

[0060] As illustrated, in some possible implementations, the second chip D2 can be a double data rate synchronous dynamic random access memory (DDR).

[0061] In addition, this application does not restrict the connection method between the first chip D1 and the first redistribution layer RDL1; in practice, it can be set as needed.

[0062] For example, in some possible implementations, referring to Figure 2, the first chip D1 can be manufactured using a chip-last process, soldered onto the surface of the first multi-layer routing layer RDL1 in a flip-chip (FC) manner. In this case, the solder joints (such as C4, bump) of the first chip D1 are connected to the first multi-layer routing layer RDL1 via solder joints, and the specific process can be found in the corresponding fabrication method below.

[0063] For example, in some possible implementations, referring to Figure 3, the first chip D1 can be mounted on the lower surface of the second redistribution layer RDL2 using a chip-first process via an adhesive layer 10. In this case, the solder joints (such as C4 and bump) of the first chip D1 are directly connected to the first redistribution layer RDL1. For details, please refer to the corresponding fabrication method below.

[0064] It should be understood that for a chip, the side with solder joints is the front side, which can be called the active side, while the back side of the chip does not have solder joints and can be called the non-active side.

[0065] Similarly, this application does not restrict the connection method between the second chip D2 and the second redistribution layer RDL2; in practice, it can be set as needed.

[0066] For example, in some possible implementations, referring to Figures 2 and 3, the back side (i.e., the non-active side) of the second chip D2 is mounted on the substrate 11, with the active side of the second chip D2 facing upward and bonded to the substrate 11 by wire bonding. The back side of the substrate 11 can be connected to the upper surface of the second redistribution layer RDL2 by solder joints, thereby realizing the electrical connection between the second chip D2 and the second redistribution layer RDL2.

[0067] For example, in some possible implementations, the active side of the second chip D2 is facing down and is soldered to the upper surface of the second redistribution layer RDL2 in a flip-chip (FC) manner, thereby achieving an electrical connection between the second chip D2 and the second redistribution layer RDL2.

[0068] In addition, in order to improve the heat dissipation performance of the package structure, as shown in Figure 4, in some possible implementations, the package structure also includes a heat sink 12. The second redistribution layer RDL2 has a window d at the position corresponding to the first chip D1. The heat sink 12 is disposed on the surface of the first chip D1 through the window area, and the top of the heat sink 12 can protrude from the upper surface of the second redistribution layer RDL2.

[0069] This application does not limit the material of the heat sink 12, as long as it can meet the heat dissipation requirements of the package structure. Indicatively, in some possible implementations, the heat sink 12 can be made of silicon.

[0070] Based on this, referring to Figure 2, the packaging structure also includes a pre-fabricated interconnect module 100, which is located on the side of the first chip D1 and connected between the first redistribution layer RDL1 and the second redistribution layer RDL2.

[0071] Referring to Figures 2 and 5, the prefabricated interconnect module 100 includes metal pillars 101 and solder joints 102. The solder joints 102 are located below the metal pillars 101 (i.e., near the end of the first rewiring layer RDL1), and the lower end of the metal pillars 101 is connected to the first rewiring layer RDL1 via the solder joints 102. The upper end of the metal pillars 101 is connected to the second rewiring layer RDL2. In this case, when fabricating the package structure, the prefabricated interconnect module 100 can be soldered to the surface of the first rewiring layer RDL1 in a manner similar to flip-chip (FC).

[0072] Of course, in other possible implementations, as shown in Figures 3 and 5, the solder joint 102 can be positioned above the metal pillar 101 (i.e., near one end of the second rewiring layer RDL2), with the upper end of the metal pillar 101 connected to the second rewiring layer RDL2 via the solder joint 102, and the lower end of the metal pillar 102 connected to the first rewiring layer RDL1. In this case, when fabricating the package structure, the pre-fabricated interconnect module 100 can be soldered onto the surface of the second rewiring layer RDL2 using a method similar to flip-chip (FC).

[0073] In the prior art, the molded via TMV connecting the first multi-layer routing layer RDL1 and the second multi-layer routing layer RDL2 is made based on thick adhesive or dry film processes, which cannot meet the evolving requirements for aspect ratio (AR) and density.

[0074] In contrast, this application employs a pre-fabricated interconnect module 100 for connection between the first routing layer RDL1 and the second routing layer RDL2. This pre-fabricated interconnect module 100 can be customized according to the requirements of the packaging structure. It is assembled and soldered between the first routing layer RDL1 and the second routing layer RDL2 to satisfy the vertical interconnection between the first routing layer RDL1 and the second routing layer RDL2. The vertical interconnect structure (metal pillar 101) used in this pre-fabricated interconnect module 100 does not need to be fabricated based on thick adhesive or dry film processes, but can be fabricated using other processes (such as electroplating). This allows the aspect ratio (AR) and density of the metal pillar 101 to be unrestricted, thereby meeting the evolutionary requirements of chip stacking packaging.

[0075] As illustrated, when the thickness of the first chip D1 is greater than 200 μm, the existing technology of fabricating molded vias (TMVs) based on thick adhesive or dry film processes cannot meet the requirements for aspect ratio (AR). However, by adopting the design scheme of this application, the use of prefabricated interconnect modules 100 can meet the requirement that the metal pillars 101 are greater than 200 μm.

[0076] In some possible implementations, to meet the aspect ratio (AR) requirement of the metal column 101, the metal column 101 can adopt a segmented structure, that is, the metal column 101 includes multiple segments distributed along the axial direction and interconnected, such as 2 segments, 3 segments, 4 segments, etc. In this case, the metal column 101 can be manufactured in segments.

[0077] Schematic, referring to Figure 6, in some possible implementations, the metal pillar 101 may include a first metal pillar a1 and a second metal pillar a2 distributed along the axial direction, and the first metal pillar a1 and the second metal pillar a2 are connected by a conductive adhesive layer b.

[0078] In addition, this application does not restrict the setting form of the metal column 101, and it can be set as needed in practice.

[0079] For example, in some possible implementations, the prefabricated interconnect module 100 may include a molding layer having a through mold via (TMV) which serves as a metal pillar 101.

[0080] For example, in some possible implementations, the prefabricated interconnect module 100 may include a silicon wafer in which through silicon vias (TSVs) are provided, which serve as metal pillars 101.

[0081] For example, in some possible implementations, the prefabricated interconnect module 100 may include a glass sheet with a through glass via (TGV) that serves as a metal pillar 101.

[0082] To illustrate, taking the metal pillar 101 using a molded hole TMV as an example, when the metal pillar 101 includes a first metal pillar a1 and a second metal pillar a2, the first metal pillar a1 and the second metal pillar a2 can be copper pillars, that is, a first copper pillar (a1) and a second copper pillar (a2). The first copper pillar (a1) and the second copper pillar (a2) can be manufactured using an electroplating process. In this case, the conductive bonding layer b between the first copper pillar (a1) and the second copper pillar (a2) is a seed layer. This seed layer can include multiple Ti layers and multiple Cu layers, and the Ti layers and Cu layers are alternately arranged to form a composite layer.

[0083] The following section, in conjunction with the manufacturing method of the prefabricated interconnect module 100, further explains the segmented fabrication of the metal pillar 101.

[0084] As illustrated in Figure 7, this application embodiment provides a method for manufacturing a prefabricated interconnect module 100, which may include:

[0085] Step 11: Referring to Figure 8(a) and (b), an electroplating process is used to form multiple first metal pillars a1 on the carrier plate 1. The multiple first metal pillars a1 are then encapsulated and their tops are exposed by grinding.

[0086] Schematic, in some possible implementations, step 11 above may include: referring to Figure 8(a), providing a carrier plate 1 and coating PI (polyimide) onto the carrier plate 1. Then, referring to Figure 8(b), forming a first copper pillar (a1) using a first electroplating process, and molding a plurality of first copper pillars (a1) into a first molding layer M1 by molding, and exposing the tops of the plurality of first copper pillars (a1) by grinding.

[0087] The carrier plate involved in this application can be a glass carrier, a molded carrier, etc. This application does not limit it, and it can be selected and set as needed in practice.

[0088] Step 12: Referring to Figure 8(c) and (d), a plurality of second metal pillars a2 are formed at the top of the plurality of first metal pillars a1, and the plurality of second metal pillars a2 are encapsulated; wherein, the bottom of the plurality of second metal pillars a2 is connected to the top of the plurality of first metal pillars a1 respectively through conductive adhesive layer b (see Figure 6).

[0089] Schematic, in some possible implementations, step 12 may include: referring to Figure 8(c), using a second electroplating process to form second copper pillars (a2) on top of the plurality of first copper pillars (a1). It should be understood that when using the electroplating process to fabricate the copper pillars, a seed layer (b) needs to be fabricated first, and the copper pillars are fabricated on the seed layer (b), as shown in Figure 6. In this case, the second copper pillars (a2) are interconnected with the first copper pillars (a1) through the seed layer (b) to form metal pillars 101, serving as the vertical interconnect structure in the prefabricated interconnect module 100. Then, referring to Figure 8(d), the plurality of second copper pillars (a2) are encapsulated using a molding process, encapsulating the plurality of second copper pillars (a2) in a second molding layer M2.

[0090] Of course, the first molding layer M1 and the second molding layer M2 can be made of the same material or different materials. This application does not impose any restrictions on this, and it can be set as needed in practice. In this embodiment, the example is taken where the first molding layer M1 and the second molding layer M2 are made of the same material, and the two can form an integral molded seal.

[0091] Step 13: Referring to Figure 8(e) and (f), remove the carrier plate 1, form multiple solder points 102 at the bottom of multiple first metal pillars a1, and expose the top of multiple second metal pillars a2 by grinding.

[0092] Indicatively, in some possible implementations, step 13 may include: referring to Figure 8(e), the edges of the molding layers (M1, M2) may be cut first, and the back carrier plate 1 may be unbonded. Then, referring to Figure 8(f), multiple solder points 102 are made at the bottom ends of the multiple first copper pillars (a1) (i.e., the side where the carrier plate 1 is removed), and multiple solder points 103 are respectively connected to the bottom ends of the multiple first copper pillars (a1). Afterwards, the molding layers (M1, M2) may be ground to expose the tops of the second copper pillars (a2), and multiple prefabricated interconnect modules 100 may be formed into a single structure by cutting.

[0093] Of course, this application is not limited to using the above steps 11 to 13 to manufacture the prefabricated interconnect module 100. Other related manufacturing methods can also be used to manufacture the prefabricated interconnect module 100, as long as the structural requirements of the prefabricated interconnect module 100 can be met.

[0094] The following description, in conjunction with the fabrication method of chip stacking packaging, further illustrates the chip stacking packaging provided in the embodiments of this application.

[0095] As illustrated in Figure 2, taking the chip-first process stacked packaging as an example, as shown in Figure 9, this application embodiment provides a method for manufacturing a chip stacked package, which may include:

[0096] Step 101: Referring to Figure 10, create the first rewiring layer RDL1.

[0097] Indicatively, in some possible implementations, step 101 above may include: referring to FIG10, providing a carrier board 2, first coating a PI layer on the carrier board 2, and then fabricating a first redistribution layer RDL1 on the PI layer.

[0098] Step 102: Referring to Figure 11, a pre-fabricated interconnect module 100 is provided, and the pre-fabricated interconnect module 100 is soldered to the surface of the first redistribution layer RDL1, and the first chip D1 is soldered to the surface of the first redistribution layer RDL1; wherein, the pre-fabricated interconnect module 100 includes metal pillars 101 and solder joints 102, and the bottom end of the metal pillars 101 is electrically connected to the first redistribution layer RDL through the solder joints 102.

[0099] Indicatively, in some possible implementations, step 102 may include: as shown in FIG11, providing a pre-fabricated interconnect module 100, and soldering the pre-fabricated interconnect module 100 to the surface of the first redistribution layer RDL1 via solder joints 102. Furthermore, providing a first chip D1 (such as a SOC), and soldering the first chip D1 to the surface of the first redistribution layer RDL1 in a flip-chip (FC) manner.

[0100] For details on the structure and manufacturing method of the prefabricated interconnect module 100, please refer to the relevant content above, which will not be repeated here.

[0101] Step 103: Referring to Figure 12, the first chip D1 and the prefabricated interconnect module 100 are encapsulated, and the top of the metal pillar 101 is exposed through a grinding process.

[0102] Indicatively, in some possible implementations, step 103 may include: molding the first chip D1 and the pre-fabricated interconnect module 100 using a molding process, as shown in FIG12(a); and then, as shown in FIG12(b), exposing the top of the metal pillars 101 in the pre-fabricated interconnect module 100 by grinding.

[0103] Step 104: Referring to Figures 13 and 14, fabricate a second redistribution layer RDL2 and place a second chip D2 on the second redistribution layer RDL2; wherein, the second chip D2 is electrically connected to the metal pillar 101 through the second redistribution layer RDL2.

[0104] Indicatively, in some possible implementations, step 104 may include: as shown in FIG13, fabricating a second rewiring layer RDL2 on the molding layer, the second rewiring layer RDL2 being connected to the top of the metal pillar 101 in the prefabricated interconnect module 100. Then, as shown in FIG14, a second chip D2 (such as DDR) is disposed on the second rewiring layer RDL2, and the entire assembly is encapsulated. Referring to FIG13, the second chip D2 may be pre-mounted on the surface of the substrate 11 and wire-bonded, and after encapsulation, soldered to the surface of the second rewiring layer RDL2 via solder joints on the back of the substrate 11. Alternatively, the second chip D2 may be soldered to the surface of the second rewiring layer RDL2 using a flip-chip (FC) method.

[0105] Next, referring to Figure 14, the back substrate 2 of the first multi-layer wiring layer RDL1 is debonded, and ball bearings and other devices (such as capacitors) are installed on the back of the first multi-layer wiring layer RDL1, and packaged units are formed by cutting.

[0106] Additionally, in some possible implementations, referring to Figure 4, the process of fabricating the second redistribution layer RDL2 in step 104 may include: fabricating a second redistribution layer RDL2 with a window d, exposing the top of the first chip D1 in the window d region. Afterward, the method for fabricating this package structure further includes: providing a heat sink 12 (such as a silicon block), and mounting the heat sink 12 on the exposed top of the first chip D1. The heat sink 12 may protrude from the surface of the second redistribution layer RDL2. In this way, the heat sink 12 can improve the heat dissipation performance of the package structure.

[0107] As illustrated in Figure 3, taking the chip-first process stacked packaging as an example, as shown in Figure 15, this application embodiment provides a method for manufacturing a chip stacked package, which may include:

[0108] Step 201: Referring to Figure 16, create the second routing layer RDL2.

[0109] Indicatively, in some possible implementations, step 201 above may include: referring to FIG16, providing a carrier board 31, first coating a PI layer on the carrier board 31, and then fabricating a second redistribution layer RDL2 on the PI layer.

[0110] Step 202, referring to Figure 17, a pre-fabricated interconnect module 100 is provided, the pre-fabricated interconnect module 100 is soldered to the surface of the second redistribution layer RDL2, and the first chip D1 is attached to the surface of the second redistribution layer RDL2 using an adhesive material; wherein, the pre-fabricated interconnect module 100 includes metal pillars 101 and solder joints 102, and the bottom end of the metal pillars 101 is electrically connected to the second redistribution layer RDL2 through the solder joints 102.

[0111] Indicatively, in some possible implementations, step 202 may include: referring to FIG17, providing a pre-fabricated interconnect module 100, and soldering the pre-fabricated interconnect module 100 to the surface of the second redistribution layer RDL2 via solder joints 102. Furthermore, providing a first chip D1 (such as a SOC), and attaching the back side (i.e., the passive side) of the first chip D1 to the surface of the second redistribution layer RDL2 via an adhesive layer 10.

[0112] For details on the structure and manufacturing method of the prefabricated interconnect module 100, please refer to the relevant content above, which will not be repeated here.

[0113] Step 203: Referring to Figure 18, the first chip D1 and the prefabricated interconnect module 100 are encapsulated, and the top of the metal pillar 101 is exposed through a grinding process.

[0114] Indicatively, in some possible implementations, step 203 may include: molding the first chip D1 and the prefabricated interconnect module 100 using a molding process, as shown in FIG18(a); and then, as shown in FIG18(b), exposing the top of the metal pillars 101 in the prefabricated interconnect module 100 and the connection pads on the surface of the first chip D1 by grinding.

[0115] Step 204: Referring to Figure 19, fabricate the first redistribution layer RDL1; wherein, the first redistribution layer RDL1 is electrically connected to the top of the metal pillar 101 and the connection pad on the surface of the first chip D1.

[0116] Indicatively, in some possible implementations, step 204 may include: as shown in FIG19, fabricating a first rewiring layer RDL1 on the molding layer, wherein the first rewiring layer RDL1 forms an electrical connection with the top of the metal pillar 101 in the prefabricated interconnect module 100 and the connection pad on the surface of the first chip D1.

[0117] Step 205: Referring to Figure 20, a second chip D2 is disposed on the surface of the second redistribution layer RDL2 away from the first chip D1.

[0118] Indicatively, in some possible implementations, step 204 may include: as shown in FIG20(a), bonding the carrier 32 to the first redistribution layer RDL1; then, as shown in FIG20(b), debonding the carrier 31 located on the back side of the second redistribution layer RDL2, and placing a second chip D2 on the back side of the second redistribution layer RDL2. The second chip D2 may be pre-mounted on the surface of the substrate 11 and wire-bonded, and after packaging, soldered to the surface of the second redistribution layer RDL2 via solder joints on the back side of the substrate 11. Alternatively, the second chip D2 may be soldered to the surface of the second redistribution layer RDL2 using a flip-chip (FC) method.

[0119] Next, referring to Figure 20(c), the carrier board 32 located on the back of the first multi-layer RDL1 is debonded, ball-mounting and other devices (such as capacitors) are installed on the back of the first multi-layer RDL1, and a package unit is formed by cutting.

[0120] It should be understood that in the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0121] For other related content in the above manufacturing method, please refer to the corresponding parts in the aforementioned packaging structure embodiment, which will not be repeated here; for other settings in the aforementioned packaging structure embodiment, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.

[0122] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip stacking package, characterized in that, include: The first and second chips are stacked together. The first trace structure is located on the side of the first chip away from the second chip and is electrically connected to the first chip; The second wiring structure is disposed between the first chip and the second chip, and is electrically connected to the second chip; A prefabricated interconnect module is connected between the second wiring structure and the first wiring structure; The prefabricated interconnect module includes metal pillars and solder joints; one end of the metal pillar is electrically connected to the second wiring structure through the solder joint, and the other end is electrically connected to the first wiring structure; or, one end of the metal pillar is electrically connected to the first wiring structure through the solder joint, and the other end is electrically connected to the second wiring structure.

2. The chip stacking package according to claim 1, characterized in that, The metal pillars include a first metal pillar and a second metal pillar that are interconnected along the axial direction.

3. The chip stacking package according to claim 1 or 2, characterized in that, The prefabricated interconnect module includes a molding layer and a molded through-hole (TMV) disposed in the molding layer, the molded through-hole (TMV) being used to form the metal pillar.

4. The chip stacking package according to claim 3, characterized in that, The molded through-hole TMV includes a first copper pillar and a second copper pillar interconnected in the vertical direction; wherein the first copper pillar and the second copper pillar are connected by a seed layer.

5. The chip stacking package according to claim 1 or 2, characterized in that, The prefabricated interconnect module includes a silicon wafer and through-silicon vias (TSVs) disposed in the silicon wafer, the TSVs being used to form the metal pillars.

6. The chip stacking package according to claim 1 or 2, characterized in that, The prefabricated interconnect module includes a glass sheet and glass vias (TGVs) disposed in the glass sheet, the glass vias (TGVs) being used to form the metal pillars.

7. The chip stacking package according to any one of claims 1-6, characterized in that, The chip stack package also includes a heat sink; The first rewiring has a window corresponding to the first chip, and the heat sink is located on the side of the first chip away from the first wiring structure and extends into the window.

8. The chip stacking package according to any one of claims 1-7, characterized in that, The first chip includes a system-on-a-chip (SOC).

9. The chip stacking package according to any one of claims 1-8, characterized in that, The second chip includes a Double Data Rate (DMR) synchronous dynamic random access memory chip (DDR).

10. The chip stacking package according to any one of claims 1-9, characterized in that, The thickness of the first chip is over 200 μm.

11. A method for fabricating a chip stacked package, characterized in that, include: Create the first wiring structure; A prefabricated interconnect module is provided, the prefabricated interconnect module is soldered to the surface of a first trace structure, and a first chip is soldered to the surface of the first trace structure; wherein, the prefabricated interconnect module includes metal pillars and solder joints, and the bottom end of the metal pillars is electrically connected to the first trace structure through the solder joints; The first chip and the pre-fabricated interconnect module are encapsulated in plastic, and the top of the metal pillar is exposed through a grinding process; A second trace structure is fabricated, and a second chip is disposed on the second trace structure; wherein the second chip is electrically connected to the metal pillar through the second trace structure.

12. The method for fabricating a chip stacked package according to claim 11, characterized in that, The provision of the prefabricated interconnect module includes: Multiple first metal pillars are formed on a carrier plate, and the multiple first metal pillars are encapsulated in plastic, and the tops of the multiple first metal pillars are exposed by grinding; Multiple second metal pillars are formed at the top of the plurality of first metal pillars, and the plurality of second metal pillars are encapsulated; wherein, the bottom of the plurality of second metal pillars is connected to the top of the plurality of first metal pillars respectively through a conductive adhesive layer; Remove the carrier plate, form multiple solder joints at the bottom of the plurality of first metal pillars, and expose the tops of the plurality of second metal pillars by grinding.

13. A method for fabricating a chip stacked package, characterized in that, include: Create a second wiring structure; A prefabricated interconnect module is provided, the prefabricated interconnect module is soldered to the surface of a second trace structure, and a first chip is mounted on the surface of the second trace structure; wherein, the prefabricated interconnect module includes metal pillars and solder joints, and the bottom end of the metal pillars is electrically connected to the second trace structure through the solder joints; The first chip and the pre-fabricated interconnect module are encapsulated in plastic, and the top of the metal pillar and the connection pad on the surface of the first chip are exposed by a grinding process. Fabricate a first wiring structure; wherein the first wiring structure is electrically connected to the top of the metal pillar and the connection pad on the surface of the first chip; A second chip is disposed on the surface of the second wiring structure away from the first chip.

14. The method for fabricating a chip stacked package according to claim 13, characterized in that, The provision of the prefabricated interconnect module includes: Multiple first metal pillars are formed on a carrier plate, and the multiple first metal pillars are encapsulated in plastic, and the tops of the multiple first metal pillars are exposed by grinding; Multiple second metal pillars are formed at the top of the plurality of first metal pillars, and the plurality of second metal pillars are encapsulated; wherein, the bottom of the plurality of second metal pillars is connected to the top of the plurality of first metal pillars respectively through a conductive adhesive layer; Remove the carrier plate, form multiple solder joints at the bottom of the plurality of first metal pillars, and expose the tops of the plurality of second metal pillars by grinding.

15. An electronic device, characterized in that, It includes a circuit board and a chip stack package as described in any one of claims 1-10, wherein the circuit board is electrically connected to the chip stack package.

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