Three-dimensional chip and electronic device

Abstract

Embodiments of the present application relate to the technical field of chips, and provide a three-dimensional chip and an electronic device, for use in alleviating the problem that existing three-dimensional chips need to be provided with more redundant interfaces. The three-dimensional chip comprises a first die and a second die. The first die comprises a first memory device and a redundant memory device, and the second die comprises a first input / output port and a multiplexer array. The multiplexer array is configured to selectively connect the first input / output port to the first memory device by means of a first interconnection interface, or connect the first input / output port to the redundant memory device by means of a redundant interconnection interface. The memory devices on the first die are connected to the multiplexer array on the second die by means of the interconnection interfaces, and therefore, when the multiplexer array is used to repair the memory devices, the interconnection interfaces between the memory devices and the multiplexer array can also be repaired without additionally providing a large number of redundant interconnection interfaces, thereby saving winding resources.

Description

3D chips and electronic devices

[0001] This application claims priority to Chinese patent application No. 202411540461.8, filed with the State Intellectual Property Office of China on October 30, 2024, entitled “Three-dimensional chip and electronic device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a three-dimensional chip and electronic device. Background Technology

[0003] 3D stacked chips typically employ interconnect interfaces to achieve signal interconnection between dies. Examples of interconnect interfaces include hybrid bonding and micro-bump bonding. These interconnect interfaces are characterized by high density and small spacing to meet the demands for increased interconnect count and bandwidth. Interconnect interfaces are the critical medium for connecting dies to dies, and their yield directly affects chip quality. Currently, redundancy can be used to repair interconnect interface faults, thereby improving the yield of 3D stacked chips.

[0004] Three-dimensional stacked chips consist of multiple dies, which can be divided into control dies and memory dies according to their functions. Among them, the memory devices in the memory dies may also have yield problems. The usual way to repair memory device failures is to add redundant devices and repair logic to the memory die. After the location of the defective memory device is obtained through testing, the repair logic is used to replace the defective memory device with a redundant device.

[0005] The yield problems of memory dies and interconnect interfaces can affect 3D stacked chips simultaneously. Therefore, it is desirable to propose a technology that can repair defects in memory dies and interconnect interfaces. Summary of the Invention

[0006] This application provides a three-dimensional chip and electronic device to improve the problem of needing to set up a lot of redundant interfaces in existing three-dimensional storage chips.

[0007] The technical solution adopted in this application is as follows:

[0008] In a first aspect, a three-dimensional chip is provided, comprising a first die, a second die, and a plurality of interconnect interfaces. The first die and the second die are stacked along the thickness direction and coupled through the plurality of interconnect interfaces. The first die includes a first memory device and a redundant memory device, and the plurality of interconnect interfaces include a first interconnect interface and a redundant interconnect interface. The second die includes a first input / output port and a multiplexer array. The multiplexer array is electrically connected to the first input / output port and is used to selectively connect the first input / output port to the first memory device through the first interconnect interface, or to connect the first input / output port to the redundant memory device through the redundant interconnect interface.

[0009] In the three-dimensional chip provided in this application embodiment, the repair of faulty memory devices can be achieved by using a multiplexer array combined with redundant memory devices. The multiplexer array is set on the second die, and the memory devices on the first die are connected to the multiplexer array on the second die through interconnect interfaces. Therefore, when repairing memory devices using the multiplexer array, the interconnect interface fault between the memory devices and the multiplexer array can be repaired. The repair logic of the memory devices is used to realize the interconnect interface fault repair, without the need to set up a large number of redundant interconnect interfaces, thus saving wiring resources.

[0010] In one possible implementation, the multiplexer array is used to select and connect the first input / output port to the first storage device via the first interconnect interface when both the first interconnect interface and the first storage device are functioning correctly. The multiplexer array is also used to select and connect the first input / output port to a redundant storage device via a redundant interconnect interface when either the first interconnect interface or the first storage device fails. This allows for repair by switching redundancy in the event of a failure in the interconnect interface or the storage device connected to the interconnect interface.

[0011] In one possible implementation, the multiplexer array includes a first multiplexer, which includes a fixed terminal, a first selection terminal, and a second selection terminal. The fixed terminal of the first multiplexer is connected to a first input / output port. The first selection terminal of the first multiplexer is connected to a first storage device via a first interconnect interface. The second selection terminal of the first multiplexer is connected to a redundant storage device via a redundant interconnect interface. When the first interconnect interface and the first storage device are functioning correctly, the first multiplexer selects to connect the first selection terminal and the fixed terminal of the first multiplexer. When either the first interconnect interface or the first storage device fails, the first multiplexer selects to connect the second selection terminal and the fixed terminal of the first multiplexer.

[0012] In one possible implementation, the first die further includes a second storage device, and the second die further includes a second input / output port. A multiplexer array is electrically connected to the second input / output port, and the multiple interconnect interfaces further include a second interconnect interface. The multiplexer array is used to selectively connect the first input / output port to the first storage device through the first interconnect interface and connect the second input / output port to the second storage device through the second interconnect interface, or connect the first input / output port to a redundant storage device through a redundant interconnect interface and connect the second input / output port to the first storage device through the first interconnect interface.

[0013] In one possible implementation, when the second interconnect interface and the second storage device are functioning correctly, the multiplexer array is used to connect the first input / output port to the first storage device via the first interconnect interface and to the second input / output port via the second interconnect interface; when the second interconnect interface or the second storage device is faulty, the multiplexer array is used to connect the first input / output port to the redundant storage device via the redundant interconnect interface and to the second input / output port via the first interconnect interface.

[0014] In one possible implementation, the multiplexer array includes a first multiplexer and a second multiplexer. Both the first and second multiplexers include a fixed terminal, a first selection terminal, and a second selection terminal. The fixed terminal of the first multiplexer is connected to a first input / output port, and the first selection terminal of the first multiplexer is connected to a first storage device via a first interconnect interface. The second selection terminal of the first multiplexer is connected to a redundant storage device via a redundant interconnect interface. The fixed terminal of the second multiplexer is connected to a second input / output port, and the first selection terminal of the second multiplexer is connected to a second storage device via a second interconnect interface. The second selection terminal of the second multiplexer is connected to the first storage device via a first interconnect interface. When the second interconnect interface and the second storage device are functioning correctly, the first multiplexer connects its first selector and its fixed terminal, and the second multiplexer connects its first selector and its fixed terminal. When either the second interconnect interface or the second storage device malfunctions, the first multiplexer connects its second selector and its fixed terminal, and the second multiplexer connects its second selector and its fixed terminal.

[0015] In one possible implementation, the first die includes any one of a static random access memory die, a dynamic random access memory die, and a flash memory die.

[0016] In one possible implementation, the interconnect interface includes a first terminal disposed on a first die and a second terminal disposed on a second die, the first terminal being coupled to the second terminal, and the coupling method between the first terminal and the second terminal including at least one of hybrid bonding and micro / nano bonding.

[0017] In a second aspect, a die is provided, the second die including a first input / output port and a multiplexer array, the multiplexer array being electrically connected to the first input / output port, the multiplexer array being used to selectively connect the first input / output port to a first memory device in the first die through a first interconnect interface, or to connect the first input / output port to a redundant memory device in the first die through a redundant interconnect interface.

[0018] In one possible implementation, the multiplexer array is used to select to connect the first input / output port to the first storage device through the first interconnect interface when the first interconnect interface and the first storage device are fault-free; the multiplexer array is also used to select to connect the first input / output port to the redundant storage device through the redundant interconnect interface when the first interconnect interface or the first storage device fails.

[0019] In one possible implementation, the die further includes a second input / output port, and a multiplexer array is electrically connected to the second input / output port. The multiplexer array is used to selectively connect the first input / output port to a first memory device in the first die via a first interconnect interface, and connect the second input / output port to a second memory device in the first die via a second interconnect interface, or connect the first input / output port to a redundant memory device in the first die via a redundant interconnect interface, and connect the second input / output port to the first memory device in the first die via a first interconnect interface.

[0020] In one possible implementation, when the second interconnect interface and the second storage device are functioning correctly, the multiplexer array is used to connect the first input / output port to the first storage device via the first interconnect interface and to the second input / output port via the second interconnect interface; when the second interconnect interface or the second storage device is faulty, the multiplexer array is used to connect the first input / output port to the redundant storage device via the redundant interconnect interface and to the second input / output port via the first interconnect interface.

[0021] Thirdly, a die is provided, the die including a first memory device and a redundant memory device, the first memory device being coupled to a multiplexer array in a second die via a first interconnect interface; the redundant memory device being coupled to a multiplexer array in the second die via a redundant interconnect interface; the multiplexer array is used to selectively connect a first input / output port to the first memory device via the first interconnect interface, or to connect the first input / output port to the redundant memory device via the redundant interconnect interface.

[0022] Fourthly, an electronic device is provided, comprising a circuit board and a three-dimensional chip as described in the first aspect and any implementation thereof, the three-dimensional chip being electrically connected to the circuit board. Attached Figure Description

[0023] Figure 1 is a schematic diagram of a three-dimensional stacked chip provided in an embodiment of this application;

[0024] Figure 2 is a schematic diagram of another three-dimensional stacked chip provided in an embodiment of this application;

[0025] Figure 3 is a schematic diagram of the repair of an interconnection interface provided in an embodiment of this application;

[0026] Figure 4 is a schematic diagram of a storage die provided in an embodiment of this application;

[0027] Figure 5 is a schematic diagram of the repair of the storage die provided in an embodiment of this application;

[0028] Figure 6 is a schematic diagram of another three-dimensional stacked chip provided in an embodiment of this application;

[0029] Figure 7 is a schematic diagram of another three-dimensional stacked chip provided in an embodiment of this application;

[0030] Figure 8 is a schematic diagram of another three-dimensional stacked chip provided in an embodiment of this application;

[0031] Figure 9 is a schematic diagram of another three-dimensional stacked chip provided in an embodiment of this application;

[0032] Figure 10 is a schematic diagram of the repair of a three-dimensional stacked chip provided in an embodiment of this application;

[0033] Figure 11 is a schematic diagram of another three-dimensional stacked chip provided in an embodiment of this application;

[0034] Figure 12 is a schematic diagram of another three-dimensional stacked chip repair provided in an embodiment of this application;

[0035] Figure 13 is a schematic diagram of another three-dimensional stacked chip repair provided in the embodiment of this application. Detailed Implementation

[0036] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this description and technology, and do not limit the scope of this application. Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to those skilled in the art.

[0037] Circuits or other components may be described or referred to as "used for" or "configured for" performing one or more tasks. In this context, "used for" or "configured for" is used to imply a structure (e.g., a circuit system) by indicating that the circuit / component includes a structure that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can be referred to as "used for performing that task." Circuits / components used with the term "used for" include hardware, such as circuits that perform operations.

[0038] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" refers to one or more, and "more than one" can refer to two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, a, b, and c; where a, b, and c can be single or multiple.

[0039] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0040] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0041] The integrated circuit industry has been developing rapidly in accordance with "Moore's Law," which states that the number of transistors that can be placed on an integrated circuit roughly doubles every 18 to 24 months. However, as "Moore's Law" has progressed, the number of devices and transistors has increased, and their size has become smaller and smaller. From this perspective, the size of transistors can no longer be shrunk after reaching a certain size, and the number of transistors that can be placed on a single die is limited. Therefore, in recent years, three-dimensional (3D) stacked chips have become a research hotspot in the industry.

[0042] Referring to Figure 1, which shows a schematic diagram of a three-dimensional stacked chip, a three-dimensional stacked chip refers to the integration of multiple dies with the same or different functions onto the same chip or into the same package through technologies such as integrated stacking packaging. For example, as shown in Figure 1, the first die and the second die are stacked vertically, and the first die and the second die are interconnected through an interconnection interface.

[0043] 3D stacked chips vertically stack multiple dies, expanding chip functionality without increasing chip area. For example, multiple dies with storage capabilities can be vertically stacked and packaged into a single 3D stacked chip, multiplying storage capacity; alternatively, dies with storage and dies with computing capabilities can be vertically stacked and packaged into a single 3D stacked chip, enabling in-memory computing functionality. Here, "vertical" refers to being perpendicular to the chip or the die. The stacked dies are interconnected using hybrid bonding, micro-bump bonding, or other interconnect interfaces (also known as interconnect media). Taking hybrid bonding as an example, Figure 2 shows a schematic diagram of another three-dimensional stacked chip, including a first die and a second die. The first die and the second die are interconnected through hybrid bonding. Hybrid bonding refers to the coupling method of a first terminal distributed on the first die and a second terminal located on the second die. The first terminal can be a conductive bump or spring on the first die, and the second terminal can be a conductive bump or spring on the second die. When the first die and the second die are stacked, the conductive bumps or springs on the first die and the conductive bumps or springs on the second die engage and connect to achieve the interconnection of the first die and the second die. Multiple dies in a three-dimensional stacked chip can also adopt other interconnection methods, which are not limited in this embodiment.

[0044] In the related technologies of 3D stacked chips, the yield of interconnect interfaces directly affects the yield of chips. Interconnect interface failures will prevent signal interaction between dies, affecting the realization of chip functions. Therefore, improving the yield of interconnect interfaces can improve the quality of 3D stacked chips.

[0045] Related technologies can repair faulty interconnect interfaces. A common solution for repairing interconnect interface faults is to set redundancy, such as double redundancy, as shown in Figure 3. Figure 3 shows a schematic diagram of interconnect interface repair, in which port D1 of the first die is coupled to port Q1 of the second die through interconnect interface HB1, thereby enabling signal transmission between port D1 and port Q1; port D2 of the first die is coupled to port Q2 of the second die through interconnect interface HB2, thereby enabling signal transmission between port D2 and port Q2; port D3 of the first die is coupled to port Q3 of the second die through interconnect interface HB3, thereby enabling signal transmission between port D3 and port Q3; and an additional redundant interconnect interface is set for each signal, for example, an interconnect interface HB1' is set between port D1 and port Q1, an interconnect interface HB2' is set between port D2 and port Q2, and an interconnect interface HB3' is set between port D3 and port Q3. Each interconnect interface between the first and second dies is configured with one redundancy, hence this scheme is called double redundancy. Without redundancy, each signal corresponds to one interconnect interface, and if that interconnect interface fails, the signal cannot be transmitted. With double redundancy, each signal corresponds to two interconnect interfaces, both of which can be used to transmit signals. If one of them fails, the other can still transmit signals normally. For example, if either interconnect interface HB1 or interconnect interface HB1' between port D1 and port Q1 fails, the signal can still be transmitted through the other normal interconnect interface. If the yield of a single interconnect interface is 90%, with double redundancy, the theoretical yield of the two interconnect interfaces can reach 99%. Therefore, double redundancy can effectively improve the yield of 3D stacked chips.

[0046] Depending on their function, chips or dies can be categorized into various types, such as memory chips, communication chips, and processor chips. Here, "chip" can refer to a chip packaged from a single die, or a stacked chip formed by three-dimensional stacking of multiple dies. Taking memory chips as an example, they can be static random access memory (SRAM), dynamic random access memory (DRAM), NAND flash memory, read-only memory (ROM), etc. Memory chips typically consist of multiple memory devices. As chip size increases, yield issues arise; for example, some memory devices may fail. To prevent faulty memory devices from affecting the operation of the entire memory chip, they usually need to be repaired.

[0047] A common repair method is to use redundant memory devices to replace the faulty memory device when it fails, thus completing the repair. Here, memory devices can refer to memory cells, memory columns, memory cell arrays, or other memory elements of granularity. For example, referring to Figure 4, Figure 4 shows a schematic diagram of a memory die. The memory die includes a first input / output port IO1, a second input / output port IO2, a third input / output port IO3, a first memory device, a second memory device, a third memory device, and redundant memory devices. The memory also includes a multiplexer array, such as the first multiplexer Mux1, the second multiplexer Mux2, and the third multiplexer Mux3 shown in the figure. The multiplexer array can switch the connection relationships between each memory device and multiple input / output ports.

[0048] The first input / output port IO1 is used to access the first storage device, such as reading and writing data from it; the second input / output port IO2 is used to access the second storage device; and the third input / output port IO3 is used to access the third storage device. If any of these storage devices malfunctions, the faulty location must first be determined through testing. Then, repair logic is used to remap the faulty location to other storage devices. In some cases, this remapping can map the faulty storage device to a redundant storage device. In other cases, multiple storage devices can be remapped by mapping the faulty storage device to an intermediate storage device, or by remapping another intermediate storage device to a redundant storage device.

[0049] For example, taking Figure 5 as an example, when the storage device is not faulty, the first multiplexer connects the first input / output port IO1 to the first storage device, the second multiplexer connects the second input / output port IO2 to the second storage device, and the third multiplexer connects the third input / output port IO3 to the third storage device. If the third storage device fails, then the first multiplexer connects the first input / output port IO1 to the redundant storage device, the second multiplexer connects the second input / output port IO2 to the first storage device, and the third multiplexer connects the third input / output port IO3 to the second storage device. This is equivalent to replacing the faulty storage device with an intermediate storage device and replacing the intermediate storage device with a redundant storage device.

[0050] The above only shows a schematic diagram of the repair of a memory die, in which the repair logic is implemented using a multiplexer array. In other repair schemes, it can also be a switch array or other time-limited arrays with gating functions. In addition, in other memory repair schemes, redundant memory devices can be used to replace the faulty memory devices, or the memory can have other repair schemes. This application embodiment does not limit these.

[0051] In 3D stacked chips, the yield problems of memory devices and interconnect interfaces will affect the chip simultaneously. Therefore, it is necessary to set up repair methods to repair memory device failures and interconnect interface failures to avoid affecting chip quality.

[0052] One possible repair method is to combine a single interconnect interface scheme with memory repair logic, as shown in Figure 6. The 3D stacked chip includes a first die and a second die. Redundant devices and repair logic are added to the second die. After the defect location is determined through testing, the repair logic can replace the defect location with a redundant device. The interconnect interface does not use redundancy. If one of them is damaged, the connection signal between the first and second dies will be broken or short-circuited, potentially causing malfunctions in the chip and directly resulting in a loss of chip yield. If the number of connection signals between the two dies is N, the number of interconnect interfaces required is also N. The lack of redundancy in the interconnect interface means that its damage will directly translate into a loss of chip yield.

[0053] Another possible repair scheme is to combine memory repair logic with redundant interconnect repair schemes, as shown in Figure 7. Redundant devices and repair logic are added to the memory die. After the defect location is determined through testing, the repair logic can replace the defect location with a redundant device. For interconnects, double redundancy can be used, with each signal corresponding to two interconnects. If one is damaged, the other is used as a replacement. This repair scheme can repair both memory devices and interconnects, improving the yield of 3D stacked chips. If the number of connection signals between dies is N, the required number of interconnects is 2N. All interconnects are connected to the die's winding layer via interconnect vias. These interconnect vias occupy the winding resources of the winding layer. The occupied winding resources are proportional to the pitch and number of interconnect vias. If the pitch of the interconnect vias cannot be reduced, double redundancy in interconnects will result in double the waste of winding resources.

[0054] To address the aforementioned issues, this application provides a three-dimensional stacked chip, or simply a three-dimensional chip, which utilizes memory repair logic to repair memory devices and interconnect interfaces. This eliminates the need for double interconnect interface redundancy to repair potentially faulty interconnect interfaces, reducing unnecessary interconnect interface redundancy, minimizing wasted wiring resources, and improving the yield of the three-dimensional stacked chip.

[0055] Referring to Figure 8, Figure 8 shows a schematic diagram of a three-dimensional chip provided in an embodiment of this application. The three-dimensional chip includes a first die 10, a second die 20, and multiple interconnect interfaces. The first die 10 and the second die 20 are coupled through the multiple interconnect interfaces.

[0056] The structure of the interconnect interface can be seen in Figure 2 above. For example, the interconnect interface includes a first terminal disposed on the first die 10 and a second terminal disposed on the second die 20. The first terminal and the second terminal are coupled by hybrid bonding, micro-nano bonding and other methods to realize the interconnection of the first die 10 and the second die 20.

[0057] The first die 10 can be a storage die, and the first die 10 includes multiple storage devices, such as a first storage device, a second storage device, and a redundant storage device. The aforementioned multiple interconnect interfaces include a first interconnect interface HB1, a second interconnect interface, and a redundant interconnect interface HB'. The first storage device is coupled to the second die 20 through the first interconnect interface HB1, the second storage device is coupled to the second die 20 through the second interconnect interface HB2, and the redundant storage device is coupled to the second die 20 through the redundant interconnect interface HB'.

[0058] The second die 20 can be a control die, etc. The second die 20 includes multiple input / output ports and a multiplexer array 210. For example, the second die includes a first input / output port IO1 and a second input / output port IO2. The first input / output port IO1 is used to connect to the first memory device through a first interconnect interface HB1, and the second input / output port IO2 is used to connect to the second memory device through a second interconnect interface HB2. The multiplexer array 210 is used to repair faults by utilizing redundant memory devices and redundant interconnect interfaces in the event of a fault in the memory device or its corresponding interconnect interface.

[0059] In the embodiments of this application, the use of redundant storage devices and redundant interconnect interfaces to repair faults includes at least two forms: one is direct replacement, that is, replacing the faulty storage device or interconnect interface with redundant storage devices and redundant interconnect interfaces. For example, if the first interconnect interface HB1 or the first storage device fails, it is replaced by the redundant interconnect interface HB` and the redundant storage device. At this time, the multiplexer array connects the first input / output port IO1 with the redundant interconnect interface HB`, that is, the first input / output port IO1 is connected to the redundant storage device through the redundant interconnect interface HB`.

[0060] Secondly, faulty storage devices or interconnects are repaired through a shift repair method. This involves replacing the faulty storage device or interconnect with an intermediate storage device and its corresponding interconnect, and replacing the intermediate storage device and interconnect with a redundant storage device and interconnect. An intermediate storage device refers to a storage device other than the faulty or redundant storage device. For example, if the second storage device or the second interconnect HB2 fails, the multiplexer array controls the second input / output port IO2 to conduct with the first interconnect HB1, and controls the first input / output port IO1 to conduct with the redundant interconnect HB`. In other words, the second input / output port IO2 is connected to the first storage device through the first interconnect HB1, and the first input / output port is connected to the redundant storage device through the redundant interconnect HB`. In this case, the first storage device is an intermediate storage device. The shift repair method uses the intermediate storage device to replace the faulty storage device and the redundant storage device to replace the intermediate storage device.

[0061] For example, in the solution provided in the embodiments of this application, the multiplexer array 210 is used to selectively connect the first input / output port IO1 to the first storage device through the first interconnect interface HB1, or connect the first input / output port IO1 to the redundant storage device through the redundant interconnect interface HB`. Here, the first storage device and the first interconnect interface HB1 are faulty storage devices or interconnect interfaces, or the first storage device and the first interconnect interface HB1 are intermediate storage devices and interconnect interfaces used to replace faulty storage devices and interconnect interfaces. Through the selection of the multiplexer array 210, the faulty interconnect interface or faulty storage device can be repaired.

[0062] The three-dimensional chip provided in this application embodiment utilizes a multiplexer array 210, redundant storage devices, and redundant interconnect interfaces HB' to achieve fault repair. The multiplexer array 210 is set in the second die 20, and the storage devices are coupled to the multiplexer array 210 in the second die 20 through interconnect interfaces. In this way, when repairing the storage devices using the multiplexer array 210, the interconnect interfaces can also be switched, that is, the faults of the interconnect interfaces can be repaired. The faulty interconnect interfaces can be repaired by using the multiplexer array 210 to achieve the repair of the faulty interconnect interfaces without setting double redundancy, which can reduce the number of redundant interconnect interfaces HB' and reduce the waste of winding resources caused by setting a large number of redundant interconnect interfaces HB'.

[0063] The following detailed description of the repair scheme provided in the embodiments of this application, with specific examples, shows that in the embodiments of this application, redundant storage devices and redundant interconnect interfaces can be used to replace faulty storage devices or interconnect interfaces to achieve fault repair.

[0064] For example, referring to Figure 9, the three-dimensional chip includes a first die 10 and a second die 20 stacked along the chip thickness direction, and the first die 10 and the second die 20 are coupled through multiple interconnect interfaces. The first die 10 includes multiple memory devices, such as a first memory device, a second memory device, a third memory device, and a redundant memory device. The first memory device is coupled to the second die 20 through a first interconnect interface HB1, the second memory device is coupled to the second die 20 through a second interconnect interface HB2, the third memory device is coupled to the second die 20 through a third interconnect interface HB3, and the redundant memory device is coupled to the second die 20 through a redundant interconnect interface HB'.

[0065] The second die 20 includes a first input / output port IO1, a second input / output port IO2, a third input / output port IO3, and a multiplexer array 210. The multiplexer array 210 includes a first multiplexer Mux1, which includes a fixed terminal p0, a first selection terminal p1, a second selection terminal p2, and a third selection terminal p3. The fixed terminal p0 is coupled to a redundant storage device through the redundant interconnect interface HB`. The first selection terminal p1 is coupled to the first input / output port IO1, the second selection terminal p2 is coupled to the second input / output port IO2, and the third selection terminal p3 is coupled to the third input / output port IO3. The first input / output port IO1 is also connected to the first interconnect interface HB1, the second input / output port IO2 is also connected to the second interconnect interface HB2, and the third input / output port IO3 is also connected to the third interconnect interface HB3.

[0066] In a fault-free state, the first storage device is connected to the first input / output port IO1 via the first interconnect interface HB1, the second storage device is connected to the second input / output port IO2 via the second interconnect interface HB2, and the third storage device is connected to the third input / output port IO3 via the third interconnect interface HB3. If any of the storage devices or interconnect interfaces fails, the first multiplexer Mux1 selects a redundant storage device and a redundant interconnect interface HB' to replace the faulty storage device or interconnect interface. For example, referring to Figure 10, which is a schematic diagram of the repair of a three-dimensional stacked chip provided in an embodiment of this application, if the first storage device or the first interconnect interface HB1 fails, the first multiplexer Mux1 connects the fixed terminal p0 to the first selected terminal p1, and the first input / output port IO1 is connected to the redundant storage device via the first multiplexer Mux1 and the redundant interconnect interface HB', thereby achieving fault repair.

[0067] In the three-dimensional chip provided in this application embodiment, the repair of faulty memory devices can be achieved by using a multiplexer array 210 in combination with redundant memory devices. The multiplexer array 210 is disposed on the second die 20. The memory devices on the first die 10 are connected to the multiplexer array 210 on the second die 20 through interconnect interfaces. Therefore, when repairing memory devices using the multiplexer array 210, the interconnect interfaces between the memory devices and the multiplexer array 210 can be repaired together, without the need to set up a large number of redundant interconnect interfaces HB', thus saving wiring resources.

[0068] The above embodiments describe the replacement and repair scheme provided by the embodiments of this application. The embodiments of this application can also adopt a shift repair scheme, that is, replace the faulty storage device and interconnection interface with intermediate storage device and corresponding interconnection interface, and replace intermediate storage device and interconnection with redundant storage device and interconnection interface.

[0069] For example, referring to FIG11, FIG11 is a schematic diagram of another three-dimensional stacked chip provided in an embodiment of the present application. The three-dimensional chip includes a first die 10 and a second die 20 stacked along the chip thickness direction. The first die 10 and the second die 20 are coupled through multiple interconnect interfaces.

[0070] The first die 10 includes multiple memory devices, such as a first memory device, a second memory device, a third memory device, and a redundant memory device. The first memory device is coupled to the second die 20 via a first interconnect interface HB1, the second memory device is coupled to the second die 20 via a second interconnect interface HB2, the third memory device is coupled to the second die 20 via a third interconnect interface HB3, and the redundant memory device is coupled to the second die 20 via a redundant interconnect interface HB'.

[0071] The second die 20 includes a first input / output port IO1, a second input / output port IO2, a third input / output port IO3, and a multiplexer array 210. The multiplexer array 210 includes a first multiplexer Mux1, a second multiplexer Mux2, and a third multiplexer Mux3. Each of the first multiplexer Mux1, the second multiplexer Mux2, and the third multiplexer Mux3 includes a fixed terminal, a first selection terminal, and a second selection terminal.

[0072] The fixed terminal p0 of the first multiplexer Mux1 is connected to the first input / output port IO1. The first selection terminal p1 of the first multiplexer Mux1 is connected to the first storage device through the first interconnect interface HB1. The second selection terminal p2 of the first multiplexer Mux1 is connected to the redundant storage device through the redundant interconnect interface HB`. The fixed terminal p0 of the second multiplexer Mux2 is connected to the second input / output port IO2. The first selection terminal p1 of the second multiplexer Mux2 is connected to the second storage device through the second interconnect interface HB2. The second selection terminal p2 of the second multiplexer Mux2 is connected to the first storage device through the first interconnect interface HB1. The fixed terminal p0 of the third multiplexer Mux3 is connected to the third input / output port IO3. The first selection terminal p1 of the third multiplexer Mux3 is connected to the third storage device through the third interconnect interface HB3. The second selection terminal p2 of the third multiplexer Mux3 is connected to the second storage device through the second interconnect interface HB2.

[0073] In the absence of faults, the first multiplexer Mux1 selects to connect its first selection terminal p1 and its fixed terminal p0; the second multiplexer Mux2 selects to connect its first selection terminal p1 and its fixed terminal p0; and the third multiplexer Mux3 selects to connect its first selection terminal p1 and its fixed terminal p0.

[0074] In the event of a failure of an interconnect or storage device, the multiplexer array 210 replaces the failed storage device and interconnect with intermediate storage devices and interconnects; and replaces intermediate storage devices and interconnects with redundant storage devices and interconnects.

[0075] For example, referring to Figure 12, in the event of a fault in the third interconnect interface HB3 or the third storage device, the first multiplexer Mux1 connects its second selection terminal p2 and its fixed terminal p0; the second multiplexer Mux2 connects its second selection terminal p2 and its fixed terminal p0; and the third multiplexer Mux3 connects its second selection terminal p2 and its fixed terminal p0. Thus, in... In the event of a failure in the third interconnect interface HB3 or the third storage device, the multiplexer array 210 uses the second storage device and the second interconnect interface HB2 to replace the third storage device and the third interconnect interface HB3 to connect with the third input / output port IO3; it uses the first storage device and the first interconnect interface HB1 to replace the second storage device and the second interconnect interface HB2 to connect with the second input / output port IO2; and it uses a redundant storage device and a redundant interconnect interface HB` to replace the first storage device and the first interconnect interface HB1 to connect with the second input / output port IO2, thereby achieving fault repair.

[0076] For example, referring to Figure 13, in the event of a failure in the second interconnect interface HB2 or the second storage device, the first multiplexer Mux1 connects its second selection terminal p2 and its fixed terminal p0; the second multiplexer Mux2 connects its second selection terminal p2 and its fixed terminal p0; the third multiplexer Mux3 connects its first selection terminal p1 and its fixed terminal p0; in the event of a failure in the second interconnect interface HB2 or the second storage device, the multiplexer array 210 uses the first storage device and the first interconnect interface HB1 to replace the second storage device and the second interconnect interface HB2 to connect with the second input / output port IO2; and uses redundant storage devices and redundant interconnect interfaces HB' to replace the first storage device and the first interconnect interface HB1 to connect with the second input / output port IO2, thereby repairing the failure.

[0077] Alternatively, if the first interconnect interface HB1 or the first storage device fails, the first multiplexer Mux1 connects its second selection terminal p2 to its fixed terminal p0; the second multiplexer Mux2 connects its first selection terminal p1 to its fixed terminal p0; and the third multiplexer Mux3 connects its first selection terminal p1 to its fixed terminal p0. In the event of a failure in the first interconnect interface HB1 or the first storage device, the multiplexer array 210 uses redundant storage devices and redundant interconnect interfaces HB' to replace the first storage device and the first interconnect interface HB1 in connection with the first input / output port IO1, thereby repairing the failure.

[0078] In the three-dimensional chip provided in this application embodiment, the repair of faulty memory devices can be achieved by using a multiplexer array 210 in combination with redundant memory devices. The multiplexer array 210 is disposed on the second die 20. The memory devices on the first die 10 are connected to the multiplexer array 210 on the second die 20 through interconnect interfaces. Therefore, when repairing memory devices using the multiplexer array 210, the interconnect interfaces between the memory devices and the multiplexer array 210 can be repaired together without the need to set up a large number of redundant interconnect interfaces HB'. For N-channel signals, only N+1 interconnect interfaces need to be set up, instead of setting up 2N interconnect interfaces as in traditional redundant repair schemes. This reduces the number of interconnect interfaces and saves wiring resources.

[0079] The above examples are merely illustrative of the repair solutions provided in this application. The multiplexer array provided in the embodiments of this application may also have other implementations, so that it may have different connection relationships with storage devices and interconnection interfaces, or other devices with similar functions may be used to replace the multiplexer array, such as a switch array may be used to replace the multiplexer array. The embodiments of this application do not limit this.

[0080] This application also provides a die, such as the first die 10 in the aforementioned embodiments. The first die 10 is coupled to the second die 20 through multiple interconnect interfaces. The first die 10 includes multiple memory devices, such as a first memory device, a redundant memory device, etc. The first memory device is connected to the multiplexer array of the second die 20 through a first interconnect interface, and the redundant memory device is connected to the multiplexer array of the second die 20 through a redundant interconnect interface. The first die 10 can be a storage die, such as a static random access memory (SRAM), dynamic random access memory (DRAM), flash memory (NAND flash), read-only memory (ROM), etc.

[0081] This application embodiment also provides another die, such as the second die 20 in the aforementioned embodiment. The second die 20 is coupled to the first die 10 through multiple interconnect interfaces. The second die 20 includes a first input / output port IO1 and a multiplexer array 210. The multiplexer array 210 is electrically connected to the first input / output port IO1. The multiplexer array 210 is used to selectively connect the first input / output port IO1 to a first memory device in the first die 10 through the first interconnect interface HB1, or to connect the first input / output port IO1 to a redundant memory device in the first die 10 through a redundant interconnect interface HB'. In this way, by using the multiplexer array to select and repair the memory device, and the interconnect interface between the repair memory device and the multiplexer array, there is no need to set up a large number of redundant interconnect interfaces, saving wiring resources.

[0082] The structure and principle of the first and second wafers have been described in detail in the foregoing embodiments and will not be repeated here. For details, please refer to the relevant content in the foregoing embodiments.

[0083] This application also provides an electronic device, which includes a circuit board and the three-dimensional chip provided in the foregoing embodiments. The three-dimensional chip is electrically connected to the circuit board. The three-dimensional chip includes a first die 10 and a second die 20. For example, the first die 10 can be a storage die, and the second die 20 can be a control die. By stacking the storage die and the control die, a three-dimensional chip integrating in-memory computing can be realized. This chip can be applied to processors such as central processing units, graphics processing units, and neural network processors in electronic devices, thereby improving the processor's computing efficiency and the performance of the electronic device.

[0084] Alternatively, both the first die 10 and the second die 20 can be memory dies. By stacking multiple memory dies, the storage capacity can be multiplied to realize a three-dimensional memory chip, which can be applied to the memory of electronic devices, such as dynamic random access memory.

[0085] Alternatively, the first wafer 10 and the second wafer 20 can be other types of wafers, which are not limited in this application embodiment.

[0086] The beneficial effects that the first die, the second die, and the electronic device provided in this embodiment can achieve are similar to the beneficial effects in the chip system provided above, and will not be repeated here.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A three-dimensional chip, characterized in that, The three-dimensional chip includes a first die, a second die, and multiple interconnect interfaces. The first die and the second die are stacked along the thickness direction and coupled through the multiple interconnect interfaces. The first die includes a first memory device and a redundant memory device, and the plurality of interconnect interfaces include a first interconnect interface and a redundant interconnect interface; The second die includes a first input / output port and a multiplexer array. The multiplexer array is electrically connected to the first input / output port. The multiplexer array is used to selectively connect the first input / output port to the first storage device through the first interconnect interface, or to connect the first input / output port to the redundant storage device through the redundant interconnect interface.

2. The three-dimensional chip according to claim 1, characterized in that, The multiplexer array is used to select to connect the first input / output port to the first storage device through the first interconnect interface, provided that the first interconnect interface and the first storage device are fault-free. The multiplexer array is also configured to select whether to connect the first input / output port to the redundant storage device via the redundant interconnect interface in the event of a failure of the first interconnect interface or the first storage device.

3. The three-dimensional chip according to claim 2, characterized in that, The multiplexer array includes a first multiplexer, which includes a fixed terminal, a first selection terminal, and a second selection terminal. The fixed terminal of the first multiplexer is connected to the first input / output port, the first selection terminal of the first multiplexer is connected to the first storage device through the first interconnect interface, and the second selection terminal of the first multiplexer is connected to the redundant storage device through the redundant interconnect interface. When the first interconnection interface and the first storage device are fault-free, the first multiplexer selects to connect the first selection terminal and the fixed terminal of the first multiplexer. In the event of a failure in the first interconnect interface or the first storage device, the first multiplexer selects to connect the second selection terminal of the first multiplexer and the fixed terminal of the first multiplexer.

4. The three-dimensional chip according to claim 1, characterized in that, The first die also includes a second memory device, the second die also includes a second input / output port, the multiplexer array is also electrically connected to the second input / output port, and the plurality of interconnect interfaces also include a second interconnect interface; The multiplexer array is used to selectively connect the first input / output port to the first storage device through the first interconnect interface, and connect the second input / output port to the second storage device through the second interconnect interface, or connect the first input / output port to the redundant storage device through the redundant interconnect interface and connect the second input / output port to the first storage device through the first interconnect interface.

5. The three-dimensional chip according to claim 4, characterized in that, When the second interconnect interface and the second storage device are fault-free, the multiplexer array is used to connect the first input / output port to the first storage device through the first interconnect interface and to connect the second input / output port to the second storage device through the second interconnect interface. In the event of a failure of the second interconnect interface or the second storage device, the multiplexer array is used to connect the first input / output port to the redundant storage device through the redundant interconnect interface, and to connect the second input / output port to the first storage device through the first interconnect interface.

6. The three-dimensional chip according to claim 4, characterized in that, The multiplexer array includes a first multiplexer and a second multiplexer, each of which includes a fixed terminal, a first selection terminal, and a second selection terminal. The fixed terminal of the first multiplexer is connected to the first input / output port, the first selection terminal of the first multiplexer is connected to the first storage device through the first interconnect interface, and the second selection terminal of the first multiplexer is connected to the redundant storage device through the redundant interconnect interface. The fixed terminal of the second multiplexer is connected to the second input / output port, the first selection terminal of the second multiplexer is connected to the second storage device through the second interconnect interface, and the second selection terminal of the second multiplexer is connected to the first storage device through the first interconnect interface. When the second interconnect interface and the second storage device are fault-free, the first multiplexer selects to connect the first selection terminal of the first multiplexer to the fixed terminal of the first multiplexer, and the second multiplexer selects to connect the first selection terminal of the second multiplexer to the fixed terminal of the second multiplexer. In the event of a failure in the second interconnect interface or the second storage device, the first multiplexer connects the second selector terminal of the first multiplexer to the fixed terminal of the first multiplexer, and the second multiplexer connects the second selector terminal of the second multiplexer to the fixed terminal of the second multiplexer.

7. The three-dimensional chip according to any one of claims 1 to 6, characterized in that, The first die includes any one of static random access memory (SRAM) die, dynamic random access memory (DRAM) die, and flash memory die.

8. The three-dimensional chip according to any one of claims 1 to 7, characterized in that, The interconnect interface includes a first terminal disposed on the first die and a second terminal disposed on the second die. The first terminal is coupled to the second terminal, and the coupling method between the first terminal and the second terminal includes at least one of hybrid bonding and micro-nano bonding.

9. A bare wafer, characterized in that, The die includes a first input / output port and a multiplexer array. The multiplexer array is electrically connected to the first input / output port. The multiplexer array is used to selectively connect the first input / output port to a first memory device in the first die through a first interconnect interface, or to connect the first input / output port to a redundant memory device in the first die through a redundant interconnect interface.

10. The bare die according to claim 9, characterized in that, The multiplexer array is used to select to connect the first input / output port to the first storage device through the first interconnect interface, provided that the first interconnect interface and the first storage device are fault-free. The multiplexer array is also configured to select whether to connect the first input / output port to the redundant storage device via the redundant interconnect interface in the event of a failure of the first interconnect interface or the first storage device.

11. The bare die according to claim 9, characterized in that, The die also includes a second input / output port, and the multiplexer array is also electrically connected to the second input / output port; The multiplexer array is used to selectively connect the first input / output port to the first memory device in the first die through the first interconnect interface, and connect the second input / output port to the second memory device in the first die through the second interconnect interface, or connect the first input / output port to the redundant memory device in the first die through the redundant interconnect interface, and connect the second input / output port to the first memory device in the first die through the first interconnect interface.

12. The bare die according to claim 11, characterized in that, When the second interconnect interface and the second storage device are fault-free, the multiplexer array is used to connect the first input / output port to the first storage device through the first interconnect interface and to connect the second input / output port to the second storage device through the second interconnect interface. In the event of a failure of the second interconnect interface or the second storage device, the multiplexer array is used to connect the first input / output port to the redundant storage device through the redundant interconnect interface, and to connect the second input / output port to the first storage device through the first interconnect interface.

13. A bare wafer, characterized in that, The die includes a first memory device and a redundant memory device. The first memory device is coupled to a multiplexer array in the second die through a first interconnect interface. The redundant memory device is coupled to a selector array in the second die through a redundant interconnect interface. The multiplexer array is used to selectively connect the first input / output port of the second die to the first storage device through the first interconnect interface, or to connect the first input / output port to the redundant storage device through a redundant interconnect interface.

14. An electronic device, characterized in that, The electronic device includes a circuit board and a three-dimensional chip as described in any one of claims 1 to 8, wherein the three-dimensional chip is electrically connected to the circuit board.

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