Data error detection method and apparatus, storage medium, and program product

Abstract

Disclosed are a data error detection method and apparatus, a storage medium, and a program product, relating to the technical field of information. The efficiency and accuracy of data error detection is improved, and the storage of metadata is supported. The method comprises: in response to a first instruction from a target device, acquiring target data in a memory, the target data comprising user data and an error correction code corresponding to the user data; and determining a target polynomial on the basis of a first check matrix and the target data, the first check matrix being used for detecting whether a target type of error occurs in the target data, wherein in the first check matrix, the sum of each group of target elements in a first finite field GF(2n) is zero, each group of target elements is related to target data stored in the same memory cell in a memory, and n is a positive integer; and wherein if the target polynomial is equal to a first value, it is indicated that the target type of error does not occur in the target data, and if the target polynomial is equal to a second value, it is indicated that the target type of error occurs in the target data.

Description

Data error detection method and device, storage medium and program product

[0001] The present application claims priority to the Chinese patent application No. 202411550530.3, filed on October 31, 2024, and entitled "Data error detection method and device, storage medium and program product", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of information technology, and in particular to a data error detection method and device, a storage medium and a program product. BACKGROUND

[0003] In the working process of the memory (such as the memory and the hard disk) in the computing device, due to electromagnetic interference and other factors, it is impossible to avoid errors in the stored user data. For example, a certain bit in the stored user data originally is 1, but becomes 0 due to interference. Such data errors can seriously affect the normal operation of the business and cause huge losses. Therefore, an efficient detection method is needed.

[0004] At present, the industry usually sets a storage space (or called check bit) for storing error correction code in the memory. When writing user data into the memory, the user data and the corresponding generated error correction code are written into the memory together. When reading data later, whether the data has errors is detected according to the error correction code. However, the traditional data error detection method needs to detect whether the data is wrong and determine the error position through iteration. This method is inefficient. SUMMARY

[0005] The present application provides a data error detection method and device, a storage medium and a program product. By designing a check matrix for the characteristics of the target type of error, the detection efficiency and accuracy of the target type of error can be significantly improved using the check matrix. The process of determining the error position and error value is simplified, thereby improving the efficiency of the error correction process. Moreover, the storage demand of the metadata can also be met.

[0006] In a first aspect, the present application provides a data error detection method, which comprises: in response to a first instruction of a target device, obtaining target data in a memory, the target data comprising user data and error correction code corresponding to the user data; determining a target polynomial according to a first check matrix and the target data; the first check matrix is used to detect whether the target data has a target type of error, wherein each group of target elements in the first check matrix is in a first finite field GF(2 neach group of target elements is related to target data stored in the same storage grain in the memory, and n is a positive integer; wherein, if the target polynomial is a first value, it indicates that the target data has no error of the target type, and if the target polynomial is a second value, it indicates that the target data has an error of the target type.

[0007] It can be understood that the first check matrix is designed for the target type of error, and therefore contains feature information about the target type of error, which is specifically manifested as: each group of target elements in the first check matrix is summed to zero in the first finite field GF(2 n ) and the second finite field GF(2 n ), and the target type of error is related to the target data stored in the same storage grain in the memory. By using this property, the detection efficiency and accuracy of whether the target data has an error of the target type can be significantly improved, and the error correction performance is improved.

[0008] In a possible implementation, if the target polynomial is the second value, the method further includes: determining an error position in the target data based on the error feature corresponding to the target type of error and the target polynomial; and decoding the target data according to the error position to obtain a first decoding result, wherein the first decoding result is a decoding result obtained by performing error correction on the target data by using the target polynomial and the error feature corresponding to the target type of error.

[0009] It can be understood that, since the error feature corresponding to the target type of error limits the position and quantity of data errors, in other words, more abundant information is provided for the decoding process, the process of determining the error position in the target data can be simplified, the efficiency of determining the error position is improved, the decoding efficiency is improved, and better error correction effect is achieved.

[0010] In a possible implementation, the user data is stored in a user data grain in the memory, the error correction code is stored in a redundant data grain in the memory, and if the target data further includes metadata, the metadata is stored in the redundant data grain.

[0011] It can be understood that, by using the special property in the first check matrix designed for the target type of error, that is, each group of target elements in the first check matrix is summed to zero in the first finite field GF(2 n ), more abundant information is provided for the decoding process, so that the redundant data grain can give up part of the storage space to store the metadata, and the error correction performance is not reduced.

[0012] In a possible implementation, before obtaining the target data in the memory in response to the first instruction of the target device, the method further includes: obtaining to-be-stored data in response to a second instruction of the target device; obtaining an error correction code corresponding to the to-be-stored data according to the to-be-stored data; and writing the to-be-stored data and the error correction code into the memory.

[0013] It can be understood that, by obtaining the error correction code corresponding to the to-be-stored data and writing the to-be-stored data and the error correction code into the memory together, a data basis is provided for subsequent data error detection and correction.

[0014] In a possible implementation, if the size of the to-be-stored data is A bits and the size of the target symbol is B bits, A and B are both positive integers, and the error correction code corresponding to the to-be-stored data is obtained according to the to-be-stored data, including: if A cannot be divided by B, filling the to-be-stored data with C bits of target characters to obtain filled to-be-stored data, the sum of A and C is an integer multiple of B; and obtaining the error correction code corresponding to the filled to-be-stored data.

[0015] It can be understood that, in the encoding and decoding process of the error correction code, a plurality of bits can usually be regarded as a symbol, and the plurality of symbols can be used for error correction encoding and decoding, which can significantly improve the error correction performance.

[0016] In a possible implementation, if the sum of the data amount of the to-be-stored data and the error correction code exceeds the storage space of the corresponding storage grain in the memory, writing the to-be-stored data and the error correction code into the memory includes: if the to-be-stored data includes metadata, removing data with a size of bits exceeding the storage space from the metadata and / or the error correction code to obtain to-be-written data; and writing the to-be-written data into the corresponding storage grain in the memory.

[0017] It can be understood that, by removing the data with a size of bits exceeding the storage space from the metadata and / or the error correction code, the to-be-written data obtained after removal can be completely written into the corresponding storage grain in the memory, and data loss caused by direct storage can be avoided.

[0018] In a possible implementation, the method further includes: determining a second decoding result, the second decoding result being a decoding result obtained by performing error correction on the target data by using a first decoding algorithm; if the target data includes metadata, determining the backhaul data according to the first decoding result; the first decoding result being a decoding result obtained by performing error correction on the target data by using a target polynomial and an error feature corresponding to an error of a target type; otherwise, determining the backhaul data according to the first decoding result and the second decoding result; and sending the backhaul data to the target device.

[0019] It can be understood that, by using at least two decoding methods for decoding and comprehensively determining the backhaul data according to two decoding results, the accuracy of error correction can be further improved.

[0020] In a possible implementation, the backhaul data is determined according to the first decoding result and the second decoding result, including: if the first decoding result and the second decoding result both indicate that decoding is successful, and include one same error-corrected target data, determining that the error-corrected target data is the backhaul data; or, if the first decoding result indicates that decoding is successful, the second decoding result indicates that decoding fails, and the first decoding result only includes one error-corrected target data, determining that the error-corrected target data is the backhaul data; or, if the first decoding result indicates that decoding fails, the second decoding result indicates that decoding is successful, and the second decoding result only includes one error-corrected target data, determining that the error-corrected target data is the backhaul data; otherwise, determining that the exception alarm information is the backhaul data.

[0021] It can be understood that, according to the first decoding result and the second decoding result, whether the decoding is successful and the error-corrected target data are determined to determine the backhaul data, the accuracy of error correction can be further improved, and in some cases where error correction fails, the exception alarm information is returned, which can avoid the business loss caused by directly returning error data.

[0022] In a second aspect, the present application provides a data error detection device, which comprises a module for executing the method of the first aspect or any of the implementation manners of the first aspect.

[0023] In a possible implementation, the data error detection device can be divided into functional modules according to the method provided in the first aspect. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. For example, the data error detection device can be divided into an acquisition module, a first determination module, and the like according to functions. The possible technical solutions and beneficial effects of each functional module described above can be referred to the technical solutions provided in the first aspect or the corresponding possible implementation manners thereof, which will not be described herein again.

[0024] In a third aspect, the present application provides a computing device, which comprises a processor and a memory controller, wherein the memory controller is configured to execute the data error detection method according to the instructions of the processor.

[0025] In a fourth aspect, the present application provides a memory controller, which comprises a logic circuit, the logic circuit is configured to be coupled with an input / output interface, and transmit data through the input / output interface to execute the data error detection method according to the above aspect.

[0026] Fifthly, embodiments of this application provide a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the data error detection method as described above.

[0027] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing at least one computer program instruction, which is loaded and executed by a processor to implement the data error detection method as described above.

[0028] For a detailed description of aspects two through six and their various implementations in this application, please refer to the detailed description in aspect one and its various implementations; and for a detailed description of the beneficial effects of aspects two through six and their various implementations, please refer to the beneficial effect analysis in aspect one and its various implementations, which will not be repeated here.

[0029] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0030] Figure 1 is a schematic diagram of data reading and writing provided in an embodiment of this application;

[0031] Figure 2 is a schematic diagram of memory read / write data provided in an embodiment of this application;

[0032] Figure 3 is a schematic diagram of a memory degradation scenario provided in an embodiment of this application;

[0033] Figure 4 is a schematic diagram of another memory read / write data provided in an embodiment of this application;

[0034] Figure 5 is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0035] Figure 6 is a schematic diagram of a memory controller according to the embodiment shown in Figure 5;

[0036] Figure 7 is a flowchart illustrating a data error detection method provided in an embodiment of this application;

[0037] Figure 8 is a schematic diagram of a memory configuration according to the embodiment shown in Figure 7;

[0038] Figure 9 is a schematic diagram of an encoding process involved in the embodiment shown in Figure 7;

[0039] Figure 10 is a schematic diagram of an encoding result involved in the embodiment shown in Figure 7;

[0040] Figure 11 is a schematic diagram of determining the returned data according to the embodiment shown in Figure 7;

[0041] Figure 12 is a schematic diagram of another memory configuration provided in an embodiment of this application;

[0042] Figure 13 is a schematic diagram of an encoding result involved in the embodiment shown in Figure 12;

[0043] Figure 14 is a schematic diagram of another encoding result involved in the embodiment shown in Figure 12;

[0044] Figure 15 is a schematic diagram of the structure of a data error detection device provided in an embodiment of this application. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0046] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0047] Furthermore, in the description of the embodiments of this application, unless otherwise stated, "multiple" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0048] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0049] First, the application scenarios of the embodiments of this application will be introduced by way of example.

[0050] Modern computing devices typically include memory, with varying read / write speeds and capacities. For example, the central processing unit (CPU) contains a cache (typically only a few megabytes or tens of megabytes). Computing devices also include main memory (RAM), which is usually random access memory (RAM). Therefore, RAM is sometimes referred to as RAM. RAM capacity typically ranges from several gigabytes (GB) to tens of gigabytes, and multiple RAM modules can be further combined into memory arrays. Computing devices also include hard drives (mechanical hard drives and solid-state drives), which typically have very large capacities, reaching several or even tens of terabytes (TB).

[0051] The central processing unit in a computing device needs to frequently use the aforementioned various types of memory to read and write data, as shown in Figure 1. Figure 1 is a schematic diagram of data reading and writing provided in an embodiment of this application. Figure 1 mainly shows the process of the central processing unit reading and writing data to memory, specifically including the central processing unit issuing a read or write instruction to the memory controller, and then the memory controller responding to the instruction of the central processing unit to read data from the memory array through the memory interface or write data to the memory array.

[0052] When the memory controller writes data to the memory array, the data in the memory array may change due to factors such as electromagnetic interference from the external environment. If the changed data is directly sent back to the central processing unit, it may cause related programs to malfunction or even cause the computing device to crash.

[0053] To address this issue, the industry has proposed corresponding error checking and correcting mechanisms. Specifically, the memory controller shown in Figure 1 also includes an error correction module. Before writing data to the memory array, the error correction module can first generate some redundant data (or check data) based on the data. Typically, one or more error correcting codes are generated, such as cyclic redundancy check (CRC), parity check, and reed-solomon code. Then, the data to be written and the corresponding error correction code are written together to the memory array.

[0054] Then, when the central processing unit instructs the memory controller to read the aforementioned data, the memory controller reads the stored data and the corresponding error correction code from the memory array. The error correction module uses the corresponding decoding algorithm to perform error detection on the data. If it is determined that the data has no error, the data is sent back to the central processing unit. If it is determined that the data has an error, it is corrected. If the error correction is successful, the corrected data is sent back to the central processing unit. If the error correction fails, the corresponding alarm information can be sent back to the central processing unit, thereby improving the reliability of the data and the stability of the system.

[0055] Depending on the nature of the stored information, the common memory configuration is to form a group of data blocks consisting of several user data granules and a few redundant data granules. The user data granules are usually used to store user data, while the redundant data granules can be used to store check data (therefore, the storage space corresponding to the redundant data granules is also called check bits), such as the error correction code mentioned above.

[0056] However, as the demand for user data storage continues to grow, the parity bits in each data block are often used to store user data in order to meet storage needs. For example, in double data rate 4 (DDR4) memory, some parity bits may need to be allocated to metadata storage, such as the poison bit, which is used to mark whether user data is erroneous. Similarly, in double data rate 5 (DDR5) specifications, two parity bits may be required, one for the poison bit and the other for the compression bit. However, this occupancy of parity bits reduces the accuracy of error detection and correction, and consequently decreases reliability.

[0057] For example, referring to Figure 2, Figure 2 is a schematic diagram of memory read and write data provided in an embodiment of this application. The memory configuration shown in Figure 2 is 16 user data particles combined with 2 redundant data particles (referred to as 16+2 particle configuration). Since it is necessary to support poison-bit, the memory read and write data process shown in Figure 2 uses 15-bit cyclic redundancy check (CRC-15) combined with parity check as error correction code.

[0058] Specifically, the memory array 101 shown in Figure 2 is a 16-row × 18-column memory array. Each column in the memory array 101 corresponds to a memory chip in the memory chip module 102 shown in Figure 2. The memory chip module 102 specifically includes 18 memory chips, namely memory chip-0 to memory chip-16. The memory chip module 102 also includes a memory chip parity bit (PAR).

[0059] In this column, the data marked PAR (hereinafter referred to as the PAR column data) corresponds to memory particle -PAR, the data marked 0 (hereinafter referred to as the 0th column data) corresponds to memory particle -0, the data marked 1 (hereinafter referred to as the 1st column data) corresponds to memory particle -1, and so on.

[0060] In Figure 2, the central processing unit (CPU) sends user data and metadata (such as the aforementioned poison-bit) to the memory controller. After receiving the user data and metadata, the error correction module in the memory controller (Figure 2) performs error correction encoding to obtain the error correction code shown in Figure 2 (specifically, CRC-15 and parity bits). Then, the error correction module sends the user data, metadata, and the corresponding error correction code to the memory chip module 102 via the memory interface, specifically to each chip in the memory chip module 102, so that each piece of data is stored in its corresponding column. Each memory chip in the memory chip module 102 shown in Figure 2 can be used to store a corresponding column of data. Specifically, d1 to d256 in Figure 2 represent the user data, m represents the metadata, c0 to c14 represent the CRC-15 error correction code, p1 to p15 represent the parity bits in the error correction code, memory chip-1 stores the first column of data d1 to d16, memory chip-0 stores the 0th column of data (poison and CRC), and memory chip-PAR stores the PAR column of data (parity).

[0061] As can be seen, in this method, the data in column 0 corresponding to memory chip -0 gives up 1 bit of the parity bit to store metadata. This will result in an error pattern that is completely uncorrectable when any chip in the memory chip module 102 fails (chip-kill). The error correction performance of CRC-15 with parity bit is limited, and it is inefficient in detecting whether the data is erroneous. Moreover, if it is necessary to further support the storage of more metadata, its error correction performance will be even worse.

[0062] Static memory (DDR DRAM) that supports double data rate-dynamic random access is commonly referred to as DDR memory. The DRAM protocol specifies column data widths, including 4-bit, 8-bit, and 16-bit. Therefore, common DDR memory types include three categories: x4, x8, and x16. Furthermore, note that the data (DQ) width of the DRAM chip is the same as the column data width. Therefore, it can also be said that DDR memory can be divided into three categories based on the DQ bus width: x4 DQ, x8 DQ, and x16 DQ.

[0063] In DDR4 storage systems, memory bank / device replacement involves discarding expired memory chips and using valid redundant data chips as general user data chips. This method can also be called memory degradation, as shown in Figure 3. Figure 3 is a schematic diagram of a memory degradation scenario provided by an embodiment of this application.

[0064] As shown in Figure 3, the memory module has a 16+2 chip configuration. Specifically, memory chip module 301 in Figure 3 includes 18 memory chips. These 18 memory chips (memory chip 0 to memory chip 17) correspond one-to-one with 18 columns of data. Memory chip 0 corresponds to column 0, DRAM chip 1 corresponds to column 1, and so on. Similarly, memory chip module 302 also includes 18 memory chips, and the other correspondences are similar to those of memory chip module 301, which will not be repeated here.

[0065] When not downgraded, both memory chip modules 301 and 302 have two redundant data chips for storing redundant data (such as error correction codes). However, if memory chips 7 and 11 in memory chip module 301 fail, memory chip modules 301 and 302 will be downgraded, and memory chips 7 and 11 in memory chip module 301 will be discarded.

[0066] In the downgraded memory module 301, 16 memory chips remain valid and are used to store user data. Memory chips 2 through 17 in memory module 302 are also used to store user data, while memory chips 0 and 1 in memory module 302 are used to store redundant data. It is evident that memory chips 0 and 1 in memory module 301, originally used to store redundant data, are now used to store user data after downgrading. Clearly, the storage space provided for redundant data in memory modules 301 and 302 is reduced to half of its original size after downgrading, impacting error correction performance.

[0067] In response to the need to store poison bits in DDR4, the industry has also proposed corresponding technical solutions. See Figure 4, which is a schematic diagram of another memory read and write data provided in an embodiment of this application.

[0068] In Figure 4, the central processing unit sends user data and metadata (such as the aforementioned poison-bit) to the memory controller. After receiving the aforementioned user data and metadata, the error correction module in the memory controller shown in Figure 2 can first analyze the content of the metadata. As shown in Figure 4, if the poison-bit is 1, it indicates that the user data is erroneous. The error correction module directly encodes the user data into a preset invalid codeword and sends the preset invalid codeword to the memory chip module 103 through the memory interface to be stored in the user chip, so that each piece of data is saved in the corresponding column. The memory chip module 103 is similar to the memory chip module 102 shown in Figure 2, and will not be described in detail here. In this way, when the central processing unit (CPU) instructs the memory controller to read the data, the error correction module obtains a preset invalid codeword, indicating that the data's poison-bit was 1 at the time of storage. Therefore, it can send the preset invalid codeword and the data with a poison-bit of 1 back to the CPU. Since the received poison-bit is 1, the CPU knows that the data is erroneous. Conversely, if the data stored has a poison-bit of 0, this method can skip storing the poison-bit and directly perform error correction encoding and writing. In this case, the data obtained by the error correction module is not the preset invalid codeword, indicating that the data's poison-bit was 0 at the time of storage. The error correction module can then decode the data normally and send the data with a poison-bit of 0 back to the CPU. It can be seen that this method replaces the poison-bit by using a preset invalid codeword, avoiding the poison-bit's occupation of the check bit. However, this method can only support specific metadata poison bits and cannot support storing more metadata.

[0069] In view of this, this application provides a data error detection method. By using a check matrix designed for the characteristics of the target type of error, the detection efficiency and accuracy of the target type of error can be significantly improved, and the process of determining the error location and error value can be simplified, thereby improving the efficiency of the error correction process. Moreover, it can also meet the storage requirements of metadata.

[0070] In some feasible embodiments, the method includes: in response to a first instruction from a target device, acquiring target data in a memory, the target data including user data and error correction codes corresponding to the user data; determining a target polynomial based on a first parity check matrix and the target data; the first parity check matrix is ​​used to detect whether the target data has a target type error, wherein each set of target elements in the first parity check matrix is ​​in the first finite field GF(2 n The summation in the first check matrix is ​​zero, and each set of target elements is related to target data stored in the same memory particle. If the target polynomial has a first value, it indicates that the target data has not experienced a target type error; if the target polynomial has a second value, it indicates that the target data has experienced a target type error. Since the first check matrix is ​​designed for target type errors, it contains characteristic information about the target type error, specifically: each set of target elements in the first check matrix is ​​in the first finite field GF(2... n The summation of the values ​​in the data is zero. By utilizing this property, the detection efficiency and accuracy of whether target data has encountered errors of the target type can be significantly improved, thereby enhancing error correction performance.

[0071] Secondly, the system architecture of the embodiments of this application will be described by way of example.

[0072] Figure 5 is a schematic diagram of a computing device provided in an embodiment of this application. The computing device 200 shown in Figure 5 includes a processor 210, a memory controller 220, and a memory 230. The processor 210 can read data stored in the memory 230 through the memory controller 220, and can also save data to the memory 230 through the memory controller 220.

[0073] In some feasible embodiments, the memory 230, the memory controller 220, and the processor 210 may be different components (chips or circuits), and the memory 230, the memory controller 220, and the CPU 310 may be connected via a bus.

[0074] In other feasible embodiments, the memory controller 220 and the processor 210 can be integrated into a single component. For example, the memory controller 220 and the processor 210 can be integrated into a single chip or system-on-chip (SoC). In this case, the memory controller 220 and the processor 210 within the chip (or SoC) can be connected via an on-chip bus (also referred to as an internal bus). The chip (or SoC) and the memory 230 can be connected via a system bus (also referred to as an internal bus).

[0075] In other feasible embodiments, the memory 230, memory controller 220, and processor 210 can be integrated into the same component. For example, the memory 230, memory controller 220, and CPU 310 can be integrated into a single chip or SoC. In this case, the memory 230, memory controller 220, and processor 210 within the chip (or SoC) can be connected via an on-chip bus (also referred to as an internal bus).

[0076] In addition to the processor 210, memory controller 220, and memory 230, the computing device 200 shown in Figure 5 may also include other components, such as the communication circuit 240 shown in Figure 5. The processor 210 can communicate with other components in the computing device 200 through the communication circuit 240.

[0077] Furthermore, Figure 6 is a schematic diagram of the structure of a memory controller according to the embodiment shown in Figure 5. The memory controller 220 shown in Figure 6 is the same as the memory controller 220 in Figure 5. As shown in Figure 5, the memory controller 220 includes an error correction module 221 and a communication interface 222.

[0078] The error correction module 221 can be used to generate error correction codes corresponding to the data to be written to the memory and to determine the data to be sent back to the processor. The communication interface 222 is used to receive data from the memory or send data to the memory, or to receive data from the processor or send data to the processor.

[0079] Optionally, the processor 210 may specifically be a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), etc.

[0080] Optionally, the memory 230 can be memory, hard disk, etc. For example, the memory 230 can be static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM), etc.; the memory 230 can also be a solid-state drive (SSD).

[0081] Correspondingly, the memory controller 220 can be a controller corresponding to the memory 230, such as a memory control chip, an SSD control chip, etc.

[0082] The error correction module 221 and the communication interface 222 can be logic circuits on the memory controller 220 or software units in its system.

[0083] It should be noted that the application scenarios and system architectures described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0084] For ease of understanding, the data error detection method provided in this application is described below with reference to the accompanying drawings. This data error detection method is applicable to the computing device shown in Figure 5.

[0085] Figure 7 shows a flowchart of a data error detection method provided in an embodiment of this application. The data error detection method includes the following steps:

[0086] S110, in response to the second instruction from the target device, the memory controller writes the data to be stored into the memory.

[0087] The target device may refer to the processor 210 in the computing device 200 shown in Figure 5, the memory controller may refer to the memory controller 220 in the computing device 200 shown in Figure 5, and the memory may refer to the memory 230 in the computing device 200 shown in Figure 5.

[0088] For example, the specific configuration of the memory can be seen in Figure 8. Figure 8 is a schematic diagram of the memory configuration according to the embodiment shown in Figure 7. The memory shown in Figure 8 is used in X user data particles (specifically, C0 particles - C shown in Figure 8). X-1 The configuration of P0 particles with Y redundant data particles (specifically, as shown in Figure 8, P0 particle - P...) Y-1 (Particles), in which user data can be stored in user data particles, and metadata and redundant data (error correction codes) can be stored in redundant data particles.

[0089] In some feasible embodiments, step S110 can be further divided into the following three steps:

[0090] S111: In response to a second instruction from the target device, the memory controller acquires the data to be stored.

[0091] In this step, the target device can send a data storage instruction (second instruction) to the memory controller. The instruction includes the data to be stored or the address of the data to be stored, so that the memory controller can obtain the data to be stored corresponding to the instruction after receiving the instruction. The data to be stored includes at least user data.

[0092] Optionally, the data to be stored may also include metadata, which is usually about user data, such as the aforementioned error data indication information (poison-bit) and compression bit.

[0093] S112: The memory controller obtains the error correction code corresponding to the data to be stored based on the data to be stored.

[0094] In this step, the process of obtaining the error correction code corresponding to the data to be stored can also be called the encoding process. In the embodiments of this application, the error correction code can be the Reed-Solomon code (RS code). It should be noted that the RS code selected in the embodiments of this application can be the traditional RS code, or other variations based on the traditional RS code, such as the extended RS code. This application does not limit this.

[0095] In the encoding and decoding processes of RS code, multiple bits can be treated as a single symbol. Specifically, the encoding and decoding processes typically occur within a finite field GF(2). n In the space of GF(2πf), n bits are considered as a symbol, where n is a positive integer greater than or equal to 1. Thus, the error-correcting performance of RS code can satisfy the requirement of correcting errors for one or more symbols. For example, in the finite field GF(2πf), ... 8In the space of ), 8 bits are regarded as a symbol, and the RS code with a code length of (N+K) represents a total of N+K symbols (N and K are positive integers greater than or equal to 1), including N user data symbols and K error correction code symbols. Each symbol consists of n bits, so there are a total of n×(N+K) bits. The error correction performance can reach the error correction of K / 2 symbols. It should be noted that the aforementioned error correction performance is an explanation of the existing RS code, while the method provided in the embodiments of this application can achieve better error correction performance, which will be explained in the following content.

[0096] In some cases, the size of the data to be stored is not an integer multiple of the size of a symbol. For example, if the size of a symbol is 8 bits, and the data to be stored includes 256 bits of user data and 2 bits of metadata, totaling 258 bits, and 258 is not an integer multiple of 8, the memory controller cannot directly obtain the RS code corresponding to this data to be stored.

[0097] To address this situation, this application provides a possible implementation method, specifically including: if the size of the data to be stored is A bits and the size of the target symbol is B bits, where A and B are both positive integers, and if A is not divisible by B, the memory controller fills the data to be stored with C bits of target characters to obtain the filled data to be stored, where the sum of A and C is an integer multiple of B; and obtains the error correction code corresponding to the filled data to be stored.

[0098] For example, if the target symbol is 8 bits in size and the data to be stored is 258 bits in size, the memory controller can fill the data to be stored with 6 bits of the target character. The target character can be "0". The result is the data to be stored after filling. The size of the data to be stored after filling is 264 bits. 264 is a multiple of 8. The memory controller then obtains the RS code corresponding to the data to be stored after filling.

[0099] S113: The memory controller writes the data to be stored and the error correction code into the memory.

[0100] In this step, referring to Figure 8, the memory controller can write the user data in the data to be stored into the user data granules in the memory, and write the metadata in the data to be stored, as well as the error correction code corresponding to the data to be stored, into the redundant data granules in the memory.

[0101] In some feasible embodiments, the sum of the data to be stored and the error correction code exceeds the storage space of the corresponding storage granularity in the memory. For example, the memory controller has filled the data to be stored and obtained the error correction code corresponding to the filled data. In this case, if the data to be stored includes metadata, the memory controller can remove bits of data exceeding the storage space from the metadata and / or error correction code to obtain the data to be written, and then write the data to be written to the corresponding storage granularity in the memory.

[0102] For example, referring to Figure 9, which is a schematic diagram of an encoding process involved in the embodiment shown in Figure 7, in step S210, the memory controller obtains the data to be stored, which includes 256 bits of user data and 2 bits of metadata; in step S220, the memory controller obtains the error correction code corresponding to the data to be stored, first fills the data to be stored into 264 bits, and then performs RS encoding with a code length of (33+8). The code encoding process yields an error correction code of 64 bits. In step S230, the memory controller removes bits as needed. Since the sum of the data to be stored and the error correction code is 328 bits, and the memory contains 8 user data particles and 2 redundant data particles, each with a storage space of 32 bits, the total storage space for these particles is 320 bits. The sum of the data to be stored and the error correction code exceeds 8 bits. Therefore, the memory controller can remove the last 8 bits of the error correction code or reduce its size using primitive polynomial modular division, specifically by reducing it by 8 bits. This results in 320 bits of data to be written, which can then be completely written into the corresponding storage particle in the memory.

[0103] Through the above steps S111-S113, the memory controller obtains the error correction code corresponding to the data to be stored and writes the data to be stored and the error correction code together into the memory, providing a data foundation for subsequent data error detection and correction. A possible encoding result is shown in Figure 10. Figure 10 is a schematic diagram of an encoding result involved in the embodiment shown in Figure 7. In Figure 10, X user data particles (C0 particles - C...) X-1 User data (symbol C) is stored in the particle. 0,0 - Symbol C X-1,m-1 ), and Y redundant data particles (P0 particles - P Y-1 The error correction code (symbol P) is stored in the particle. 0,0 - Symbol P Y-1,m-n ), removing some bits (P in Figure 10). Y-1,m-1 It also stores metadata (symbol M). Y-1,0 symbol M Y-1,n-1 ), where the symbol P in Figure 10Y-1,m-n With symbol M Y-1,0 In reality, they share a symbol. In other words, part of the bit data in this symbol is metadata, while the other part is error correction code. This way, while meeting the storage requirements of metadata, more error correction code can be stored, which helps to improve error correction performance.

[0104] S120, in response to the first instruction from the target device, the memory controller acquires the target data from the memory.

[0105] In this step, the target device can send a data read instruction (first instruction) to the memory controller. The instruction includes the storage address of the target data in the memory, so that after the memory controller receives the instruction, it can obtain the target data corresponding to the instruction from the corresponding location in the memory. The target data includes user data and the error correction code corresponding to the user data.

[0106] In one possible implementation, user data is stored in user data granules in memory, and error correction codes are stored in redundant data granules in memory. If the target data also includes metadata, the metadata is stored in the redundant data granules. For an example, please refer to Figure 10 above, which will not be elaborated here.

[0107] S130, the memory controller determines the target polynomial based on the first parity check matrix and the target data.

[0108] The first check matrix is ​​designed for target type errors and can therefore be used to detect whether the target data has a target type error. In this embodiment, the target type error can refer to a 1C1S error. A 1C1S error refers to a chip-kill error where one chip in a group of data blocks fails, and a symbol in another chip in the same data block fails randomly. According to industry statistics, this is a relatively frequent error among the possible errors in memory.

[0109] The aforementioned chip-kill refers to an error that occurs throughout the entire data block and the corresponding column in the parity bit due to the failure of a single chip, while random error refers to a random error occurring within a data block.

[0110] For example, a 1C1S error could be a chip-kill occurring in the C0 chip shown in Figure 10, and the symbol C in the C1 chip... 1,m-1 A random error occurred.

[0111] The first check matrix is ​​designed based on the error characteristics of the 1C1S error, and each target element in the first check matrix is ​​in the first finite field GF(2). n The summation in the array is zero. Each set of target elements is associated with target data stored in the same memory chip. n is a positive integer. In some feasible embodiments, n can be determined based on the number of bits included in a symbol during the encoding and decoding process. For example, n = 8 means that a symbol is 8 bits.

[0112] For example, for the encoding result shown in Figure 10, the corresponding first check matrix can be:

[0113] Among them, all W k All are finite fields GF(2) n The elements in ) can be represented in polynomial form, for example: W k =k n-1 α n-1 +k n-2 α n-2 +…+k1α+k0, where k i =0 or 1, depending on the subscript, W k This corresponds to the different symbols in Figure 10. Furthermore, the elements in each column of this matrix are arranged in ascending order from the power of 0 to the power of t, where t is related to the amount of redundant data. In this matrix, the first check matrix element W corresponds to all data stored in the same user data particle or redundant data particle. k In the first finite field GF(2) n The summation in GF(2) is zero, meaning that the summation in GF(2) is zero. n When performing a summation operation in a domain, we have: as well as The properties of.

[0114] In step S130, specifically, the error correction module in the memory controller (error correction module 221 as shown in Figure 6) determines the target polynomial by multiplying the target data and the first parity check matrix, and determines whether the target data has an error of the target type based on the target polynomial. Specifically, if the target polynomial is a first value, it indicates that the target data has not had an error of the target type; if the target polynomial is a second value, it indicates that the target data has had an error of the target type. In one possible implementation, the first value is 0, and all other non-zero values ​​are the second value.

[0115] S140, the memory controller determines the data to be returned and sends it to the target device.

[0116] In this step, specifically, the error correction module in the memory controller (error correction module 221 as shown in Figure 6) first determines whether the target data has an error of the target type based on the target polynomial obtained in step S130. That is, if the target polynomial is the first value, the memory controller can determine that the user data and metadata in the target data are return data and send them to the target device.

[0117] Furthermore, when it is determined that an error has occurred in the target data, the memory controller corrects the erroneous target data by: determining the error location in the target data based on the error characteristics corresponding to the error type of the target data and the target polynomial; and decoding the target data according to the error location to obtain a first decoding result. The first decoding result is the decoding result obtained by correcting the target data through the target polynomial and the error characteristics corresponding to the error type of the target data.

[0118] For example, the error characteristics corresponding to the target type error are a chip kill in one chip and an error in a symbol in another chip. Therefore, it can be assumed that the error occurs in the i-th chip and the j-th symbol (and this symbol will not occur in the i-th chip), which simplifies the derivation of the error location formula. There is no need to use the traditional iterative method for calculation. The error location in the target data can be determined by traversal and error correction can be performed. The bits at the error location are reversed to obtain the first decoding result. If the first decoding result indicates successful decoding and contains only one error-corrected target data (or has a unique solution), the memory controller can determine the error-corrected target data as the return data and send it to the target device.

[0119] To further improve error correction performance and maintain the characteristics of traditional RS codes, this application provides a possible implementation, including: a memory controller determining a second decoding result, wherein the second decoding result is a decoding result obtained by correcting the target data using a first decoding algorithm; if the target data includes metadata, the memory controller determines the return data based on the first decoding result; the first decoding result is a decoding result obtained by correcting the target data using the error features corresponding to the target polynomial and the target type error; otherwise, the memory controller determines the return data based on the first and second decoding results; and sends the return data to the target device.

[0120] Specifically, the memory controller can execute in parallel the algorithm for 1C1S error (or 1C1S algorithm) provided in the embodiments of this application, as well as other RS ​​code decoding algorithms (first decoding algorithms), such as the Berlekamp-Massey algorithm (BM algorithm), the Sugiyama algorithm, and the Chien search algorithm, etc.

[0121] It should be noted that RS code algorithms other than the 1C1S algorithm (such as the aforementioned BM algorithm) cannot support storing metadata. That is, if the target data obtained by the memory controller includes metadata, the decoding results of other RS ​​code algorithms are unreliable. In this case, the memory controller determines the data to be returned based on the decoding result of the 1C1S algorithm. However, if the target data obtained by the memory controller does not include metadata, the decoding results of multiple algorithms are reliable. In this case, the memory controller can determine the data to be returned based on multiple decoding results.

[0122] For example, taking the parallel execution of the 1C1S algorithm and the BM algorithm by the memory controller as an example, when the target data obtained by the memory controller does not include metadata, the various possible situations for determining the return data are shown in Figure 11. Figure 11 is a schematic diagram of determining the return data in the embodiment shown in Figure 7. In this diagram, the decoding result obtained by the 1C1S algorithm is called the first decoding result, and the decoding result obtained by the BM algorithm is called the second decoding result. The main cases include the following four situations:

[0123] Case 1: Both the first and second decoding results indicate successful decoding (or a solution is available) and include the same error-corrected target data. The memory controller determines that the error-corrected target data is the return data.

[0124] For example, both the first decoding result and the second decoding result indicate successful decoding, and the first decoding result includes the error-corrected target data A and the error-corrected target data C, while the second decoding result includes the error-corrected target data B. The memory controller determines that the same error-corrected target data, that is, the aforementioned error-corrected target data B, is the return data.

[0125] Case 2: The first decoding result indicates successful decoding, the second decoding result indicates decoding failure (or no solution), and the first decoding result only includes one error-corrected target data. The memory controller determines that the error-corrected target data is the return data.

[0126] Case 3: The first decoding result indicates decoding failure, the second decoding result indicates decoding success, and the second decoding result contains only one error-corrected target data. The memory controller determines that the error-corrected target data is the return data.

[0127] If any of the three conditions mentioned above are not met, it indicates that the decoding has failed and the corrected target data cannot be sent back to the target device. This corresponds to condition 4: the memory controller determines that the abnormal alarm information is data to be sent back. In this way, even if the decoding fails, sending back the abnormal alarm information can prevent greater losses.

[0128] Through the above steps S110-S140 and various possible implementation methods, it is possible to store one or more bits of metadata into redundant data particles in the memory, and to realize error detection and correction of the target data through the 1C1S algorithm (including the first parity check matrix), thereby reducing the amount of computation and the latency. By improving the efficiency of error detection and correction, and by combining multiple decoding results to determine the data to be returned without storing metadata, the error correction performance is improved.

[0129] The data error detection method provided in this application will be explained and illustrated again below with a memory configuration of 8 user data granules and 2 redundant data granules (each granule has a storage space of 32 bits).

[0130] Referring to Figure 12, which is a schematic diagram of another memory configuration provided in an embodiment of this application, the memory shown in Figure 12 uses a configuration of 8 user data particles (specifically, particles C0-C7 shown in Figure 12) and 2 redundant data particles (specifically, particles P0-P1 shown in Figure 12). User data can be stored in the user data particles, and metadata and redundant data (error correction codes) can be stored in the redundant data particles.

[0131] Based on the configuration shown in Figure 12, the memory controller (specifically, the error correction module within the memory controller) treats 8 bits as a symbol and compiles it using RS code with a code length of (33+8). The data to be stored indicated by the target device (such as the CPU) includes user data C. 0,0 ,…,C 0,3 C 1,0 ,…,C 1,3 ,…,C 7,0 ,…,C 7,3 There are 32 symbols in total, with a data size of 256 bits and 1 bit of metadata. The memory controller fills these in to obtain a symbol M. 1,0 The data size is 8 bits.

[0132] Taking the requirement of metadata for the target device as an example, the memory controller will, according to M 1,0 The value is encoded accordingly. If the user does not need to transmit metadata, the memory controller can encode M. 1,0 The symbol is set to 0 (all 8 bits are 0) for encoding.

[0133] After the memory controller encodes the user data and metadata using (33+8) RS codes, the corresponding error correction code is obtained, which specifically includes 8 symbols P. 0,0 ,…,P 0,3 ,P 1,0 ,…,P 1,3 The data size is 64 bits. Therefore, the sum of the user data, padded metadata, and error correction code data is 328 bits (corresponding to 41 symbols). See Figure 13 for the specific encoding result. Figure 13 is a schematic diagram of an encoding result related to the embodiment shown in Figure 12, where the user data corresponds to 32 symbols C. 0,0 ,…,C 0,3 C 1,0 ,…,C 1,3 ,…,C 7,0 ,…,C 7,3 These are stored in granules C0 through C7 respectively, and the metadata after filling corresponds to one symbol M. 1,0 The 8 symbols corresponding to the error correction code clearly overflow the storage space (64 bits) of the redundant data particles P0 and P1. If the target device does not require metadata, the memory controller can directly remove M. 1,0 (i.e., 0 symbol) Complete storage of P 1,3 If the target device requires metadata, the memory controller can... 1,3 Remove 1 bit (using modulo division) to get The vacant bit position can be used to store 1 bit of metadata indicated by the target device.

[0134] In this embodiment, the memory controller selects the following first parity check matrix during decoding:

[0135] In this matrix, all W k All are GF(2) 8 () elements of the field.

[0136] For example, W k =k7α 7 +k6α 6 +…+k1α+k0,k=k72 7 +k62 6 +…+k12+k0, then W3=α+1, W4=α 2 ,…,W43 =α 5 +α 3 +α+1. Furthermore, in GF(2 8 When performing field operations, W can be obtained. 4i+3 +…+W 4i The property of i = 0, i = 1, ..., 10 can reduce the amount of computation and improve the efficiency of error detection and correction.

[0137] Because it supports storing metadata, the memory controller determines the data to be returned and returns it to the target device based on the decoding result of the 1C1S algorithm. Specifically, if the decoding result of the 1C1S algorithm indicates successful decoding and includes only one error-corrected target data (or a unique solution exists), the memory controller determines that the error-corrected target data is the data to be returned and returns it to the target device. Otherwise, the memory controller determines that the abnormal alarm information is the data to be returned and returns it to the target device.

[0138] Based on the configuration shown in Figure 12, but unlike the previous case where the target device indicated that the data to be stored included 1 bit of metadata, this case includes 16 bits of metadata.

[0139] Taking a target device requiring 16 bits of metadata as an example, since 16 bits is an integer multiple of 8 bits, the memory controller does not need to pad the metadata and can directly store the corresponding symbol M. 1,0 M 1,1 The value is encoded accordingly. If the user does not need to transmit metadata, the memory controller can encode M. 1,0 M 1,1 Encode the symbols by setting them to 0 (each symbol has 8 bits that are all 0).

[0140] In some feasible embodiments, if the target device only needs a portion of the 16-bit metadata during reading, then during encoding, the memory controller can flexibly set the bits of the metadata that do not need to be returned to 0.

[0141] For example, if only 3 bits of metadata out of 16 bits need to be returned, the memory controller can send M... 1,0 Treated as a 0 symbol, M 1,1 Encode the specified 3-bit metadata accordingly.

[0142] After encoding with (34+8) RS code, the memory controller generates 8 redundant data symbols P. 0,0 ,…,P 0,3 ,P 1,0 ,…,P 1,3 This yields the corresponding error correction code, specifically including 8 symbols P. 0,0 ,…,P 0,3,P 1,0 ,…,P 1,3 The data size is 64 bits. Therefore, the sum of the user data, padded metadata, and error correction code data is 336 bits (corresponding to 42 symbols). See Figure 14 for the specific encoding result. Figure 14 is a schematic diagram of another encoding result involved in the embodiment shown in Figure 12, where the 32 symbols C corresponding to the user data... 0,0 ,…,C 0,3 C 1,0 ,…,C 1,3 ,…,C 7,0 ,…,C 7,3 These are stored respectively in particles C0-C7, and the 16 bits of metadata correspond to two symbols M. 1,0 M 1,1 The 8 symbols corresponding to the error correction code clearly overflow the storage space (64 bits) of the redundant data particles P0 and P1. If the target device does not require any metadata, the memory controller can directly remove M. 1,0 and, M 1,1 Complete storage P 1,2 and P 1,3 If the target device requires 16 bits of metadata, the memory controller can... 1,2 and P 1,3 Remove and arrange M completely. 1,0 and M 1,1 (As shown in Figure 14)

[0143] In this embodiment, the storage of 16 bits of metadata, or 2 symbols, is supported. Therefore, the actual data stored in the granular material can be adjusted based on the amount of metadata to be returned, determining the number of bits to be removed. For example, if the target device requires 3 bits of metadata, the memory controller can use M during encoding. 1,0 Treated as a 0 symbol, M 1,1 The 3-bit metadata specified for the target device is encoded. Therefore, when storing the chip, the memory controller can discard the M. 1,0 Complete placement of P 1,2 And P can be 1,3 Remove 3 bits (modulo division can be used to obtain) The three empty bit positions can be used to place M. 1,1 .

[0144] In this embodiment, the error correction code still uses RS code, but it is not the traditional RS code, but an extended RS code. Correspondingly, the first parity check matrix selected by the memory controller during decoding is as follows, which has two more columns of data:

[0145] In this matrix, all W k All are GF(2) 8 () elements of the field.

[0146] For example, W k =k7α 7 +k6α 6 +…+k1α+k0,k=k72 7 +k62 6 +…+k12+k0, then W3=α+1, W4=α 2 ,…,W 43 =α 5 +α 3 +α+1. Furthermore, in GF(2 8 When performing field operations, W can be obtained. 4i+3 +…+W 4i The property of i = 0, i = 1, ..., 10 can reduce the amount of computation and improve the efficiency of error detection and correction.

[0147] Because it supports storing metadata, the memory controller determines the data to be returned and returns it to the target device based on the decoding result of the 1C1S algorithm. Specifically, if the decoding result of the 1C1S algorithm indicates successful decoding and includes only one error-corrected target data (or a unique solution exists), the memory controller determines that the error-corrected target data is the data to be returned and returns it to the target device. Otherwise, the memory controller determines that the abnormal alarm information is the data to be returned and returns it to the target device.

[0148] In summary, the error detection method and various possible implementations provided in this application can guarantee the ability to detect and correct target errors while supporting the storage of metadata. This achieves a breakthrough in error correction capabilities compared to traditional RS decoders, reduces computational load and latency, improves the efficiency of error detection and correction, and allows for the parallel use of other traditional RS code decoding algorithms to further enhance error correction performance.

[0149] The foregoing mainly describes the solutions of the embodiments of this application from a methodological perspective. It is understood that, in order to achieve the above functions, the data error detection device includes at least one of the hardware structures and software modules corresponding to each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0150] This application embodiment can divide the data error detection device into functional units according to the above method example. For example, each function can be divided into its own functional unit, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0151] For example, Figure 15 is a schematic diagram of the structure of a data error detection device provided in an embodiment of this application. The data error detection device 800 shown in Figure 15 can be applied to a computing device, or the data error detection device 800 can be a computing device. The data error detection device 800 includes:

[0152] The acquisition module 810 is used to acquire target data in the memory in response to a first instruction from the target device. The target data includes user data and error correction codes corresponding to the user data.

[0153] The first determining module 820 is used to determine the target polynomial based on the first verification matrix and the target data; the first verification matrix is ​​used to detect whether the target data has an error in target type, wherein each group of target elements in the first verification matrix is ​​in the first finite field GF(2 n The summation in the target polynomial is zero. Each set of target elements is associated with target data stored in the same storage particle in the memory, where n is a positive integer. If the target polynomial has a first value, it indicates that the target data has not experienced an error of the target type. If the target polynomial has a second value, it indicates that the target data has experienced an error of the target type.

[0154] For example, referring to Figure 7, the acquisition module 810 can be used to execute S120 as shown in Figure 7, and the first determination module 820 can be used to execute S130 as shown in Figure 7.

[0155] In one possible implementation, if the target polynomial has a second value, the apparatus further includes a decoding module for:

[0156] Based on the error characteristics corresponding to the target type and the target polynomial, the error location in the target data is determined;

[0157] Based on the error location, the target data is decoded to obtain a first decoding result. The first decoding result is the decoding result obtained by correcting the target data through the error features corresponding to the error of the target polynomial and the target type.

[0158] In one possible implementation, the user data is stored in user data granules in the memory, the error correction code is stored in redundant data granules in the memory, and if the target data also includes metadata, the metadata is stored in the redundant data granules.

[0159] In one possible implementation, before acquiring target data from the memory in response to a first instruction from the target device, the device further includes a writing module, configured to: acquire data to be stored in response to a second instruction from the target device; acquire an error correction code corresponding to the data to be stored based on the data to be stored; and write the data to be stored and the error correction code into the memory.

[0160] In one possible implementation, if the size of the data to be stored is A bits and the size of the target symbol is B bits, where A and B are both positive integers, the writing module is further configured to: if A is not divisible by B, fill the data to be stored with C bits of target character to obtain the filled data to be stored, where the sum of A and C is an integer multiple of B; and obtain the error correction code corresponding to the filled data to be stored.

[0161] In one possible implementation, if the sum of the data to be stored and the error correction code exceeds the storage space of the corresponding storage granule in the memory, the writing module is further configured to: if the data to be stored includes metadata, remove data of a size exceeding the storage space from the metadata and / or the error correction code to obtain the data to be written; and write the data to be written into the corresponding storage granule in the memory.

[0162] In one possible implementation, the apparatus further includes a second determining module, configured to: determine a second decoding result, wherein the second decoding result is a decoding result obtained by correcting the target data using a first decoding algorithm; if the target data includes metadata, determine return data based on the first decoding result; wherein the first decoding result is a decoding result obtained by correcting the target data using the target polynomial and the error features corresponding to the error of the target type; otherwise, determine return data based on the first decoding result and the second decoding result; and send the return data to the target device.

[0163] In one possible implementation, the second determining module is further configured to:

[0164] If both the first decoding result and the second decoding result indicate successful decoding and include the same error-corrected target data, then the error-corrected target data is determined to be the returned data; or,

[0165] If the first decoding result indicates successful decoding, the second decoding result indicates decoding failure, and the first decoding result includes only one error-corrected target data, then the error-corrected target data is determined to be the returned data; or...

[0166] If the first decoding result indicates decoding failure, and the second decoding result indicates decoding success, and the second decoding result includes only one error-corrected target data, then the error-corrected target data is determined to be the returned data;

[0167] Otherwise, the abnormal alarm information is determined to be the returned data.

[0168] In one exemplary embodiment, a computer-readable storage medium is also provided for storing at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement all or part of the steps in the data error detection method described above. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0169] In one exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform all or part of the steps of the method shown in any of the embodiments of FIG7.

[0170] In some embodiments, the methods shown in this application can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0171] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0172] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0173] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0174] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0175] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0176] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

A data error detection method, characterized in that, The method includes: In response to a first instruction from the target device, target data in the memory is acquired, the target data including user data and error correction codes corresponding to the user data; Based on the first check matrix and the target data, the target polynomial is determined; the first check matrix is ​​used to detect whether the target data has an error of the target type, wherein each group of target elements in the first check matrix is ​​in the first finite field GF(2 n The summation in the memory is zero. Each set of target elements is related to target data stored in the same storage particle in the memory, where n is a positive integer. Wherein, if the objective polynomial has a first value, it indicates that the objective data has not experienced an error of the target type; if the objective polynomial has a second value, it indicates that the objective data has experienced an error of the target type. The method according to claim 1, characterized in that, If the target polynomial has a second value, the method further includes: Based on the error characteristics corresponding to the target type and the target polynomial, the error location in the target data is determined; Based on the error location, the target data is decoded to obtain a first decoding result. The first decoding result is the decoding result obtained by correcting the target data through the error features corresponding to the error of the target polynomial and the target type. The method according to claim 1 or 2, characterized in that, The user data is stored in user data particles in the memory, the error correction code is stored in redundant data particles in the memory, and if the target data also includes metadata, the metadata is stored in the redundant data particles. The method according to any one of claims 1-3, characterized in that, Before retrieving the target data from the memory in response to the first instruction from the target device, the method further includes: In response to a second instruction from the target device, acquire the data to be stored; Based on the data to be stored, obtain the error correction code corresponding to the data to be stored; The data to be stored and the error correction code are written into the memory. The method according to claim 4, characterized in that, If the size of the data to be stored is A bits and the size of the target symbol is B bits, where A and B are both positive integers, the step of obtaining the error correction code corresponding to the data to be stored includes: If A is not divisible by B, fill the data to be stored with C bits of target characters to obtain the filled data to be stored, where the sum of A and C is an integer multiple of B. Obtain the error correction code corresponding to the filled data to be stored. The method according to claim 4 or 5, characterized in that, If the sum of the data to be stored and the error correction code exceeds the storage space of the corresponding storage granule in the memory, writing the data to be stored and the error correction code into the memory includes: If the data to be stored includes metadata, remove data in bits exceeding the storage space from the metadata and / or the error correction code to obtain the data to be written; The data to be written is written into the corresponding storage chip in the memory. The method according to any one of claims 1 to 6, characterized in that, The method further includes: Determine a second decoding result, which is a decoding result obtained by correcting the target data using a first decoding algorithm; If the target data includes metadata, the data to be returned is determined based on the first decoding result; the first decoding result is the decoding result obtained by correcting the target data using the error features corresponding to the error of the target polynomial and the target type; otherwise... Based on the first decoding result and the second decoding result, determine the data to be transmitted back; The returned data is sent to the target device. The method according to claim 7, characterized in that, The step of determining the return data based on the first decoding result and the second decoding result includes: If both the first decoding result and the second decoding result indicate successful decoding and include the same error-corrected target data, then the error-corrected target data is determined to be the returned data; or, If the first decoding result indicates successful decoding, the second decoding result indicates decoding failure, and the first decoding result includes only one error-corrected target data, then the error-corrected target data is determined to be the returned data; or... If the first decoding result indicates decoding failure, and the second decoding result indicates decoding success, and the second decoding result includes only one error-corrected target data, then the error-corrected target data is determined to be the returned data; Otherwise, the abnormal alarm information is determined to be the returned data. A data error detection device, characterized in that, The device includes: The acquisition module is used to acquire target data in the memory in response to a first instruction from the target device. The target data includes user data and error correction codes corresponding to the user data. The first determining module is used to determine the target polynomial based on the first verification matrix and the target data; the first verification matrix is ​​used to detect whether the target data has an error in target type, wherein each group of target elements in the first verification matrix is ​​in the first finite field GF(2). n The summation in the target polynomial is zero. Each set of target elements is associated with target data stored in the same storage particle in the memory, where n is a positive integer. If the target polynomial has a first value, it indicates that the target data has not experienced an error of the target type. If the target polynomial has a second value, it indicates that the target data has experienced an error of the target type. The apparatus according to claim 9 is characterized in that, If the target polynomial has a second value, the apparatus further includes a decoding module for: Based on the error characteristics corresponding to the target type and the target polynomial, the error location in the target data is determined; Based on the error location, the target data is decoded to obtain a first decoding result. The first decoding result is the decoding result obtained by correcting the target data through the error features corresponding to the error of the target polynomial and the target type. The apparatus according to claim 9 or 10 is characterized in that, The user data is stored in user data particles in the memory, the error correction code is stored in redundant data particles in the memory, and if the target data also includes metadata, the metadata is stored in the redundant data particles. The apparatus according to any one of claims 9-11 is characterized in that, Before retrieving target data from memory in response to a first instruction from the target device, the apparatus further includes a writing module for: In response to a second instruction from the target device, acquire the data to be stored; Based on the data to be stored, obtain the error correction code corresponding to the data to be stored; The data to be stored and the error correction code are written into the memory. The apparatus according to claim 12 is characterized in that, If the size of the data to be stored is A bits and the size of the target symbol is B bits, where A and B are both positive integers, the writing module is further configured to: If A is not divisible by B, fill the data to be stored with C bits of target characters to obtain the filled data to be stored, where the sum of A and C is an integer multiple of B. Obtain the error correction code corresponding to the filled data to be stored. The apparatus according to claim 12 or 13 is characterized in that, If the sum of the data to be stored and the error correction code exceeds the storage space of the corresponding storage granule in the memory, the writing module is further configured to: If the data to be stored includes metadata, remove data in bits exceeding the storage space from the metadata and / or the error correction code to obtain the data to be written; The data to be written is written into the corresponding storage chip in the memory. The apparatus according to any one of claims 9 to 14 is characterized in that, The device further includes a second determining module, used for: Determine a second decoding result, which is a decoding result obtained by correcting the target data using a first decoding algorithm; If the target data includes metadata, the data to be returned is determined based on the first decoding result; the first decoding result is the decoding result obtained by correcting the target data through the error features corresponding to the error of the target polynomial and the target type. otherwise, Based on the first decoding result and the second decoding result, determine the data to be transmitted back; The returned data is sent to the target device. The apparatus according to claim 15 is characterized in that, The second determining module is further configured to: If both the first decoding result and the second decoding result indicate successful decoding and include the same error-corrected target data, then the error-corrected target data is determined to be the returned data; or, If the first decoding result indicates successful decoding, the second decoding result indicates decoding failure, and the first decoding result includes only one error-corrected target data, then the error-corrected target data is determined to be the returned data; or... If the first decoding result indicates decoding failure, and the second decoding result indicates decoding success, and the second decoding result includes only one error-corrected target data, then the error-corrected target data is determined to be the returned data; Otherwise, the abnormal alarm information is determined to be the returned data. A computing device, characterized in that, include: A processor and a memory controller, the memory controller being configured to execute the data error detection method as described in any one of claims 1-8 in response to instructions from the processor. A memory controller, characterized in that, include: A logic circuit, the logic circuit being coupled to an input / output interface, through which data is transmitted to perform the data error detection method as described in any one of claims 1-8. A computer program product, characterized in that, The computer program product includes instructions that, when executed by a computing device, cause the computing device to perform the data error detection method as described in any one of claims 1-8. A computer-readable medium, characterized in that, It includes computer program instructions, which, when executed by a computing device, enable the computing device to perform the data error detection method as described in any one of claims 1-8.

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