Method and apparatus for adjusting power-off holdup time, and microcontroller unit and storage medium

Abstract

Provided in the embodiments of the present application are a method and apparatus for adjusting a power-off holdup time, and a microcontroller unit, a storage medium, an electronic device and a computer program product. The method comprises: when it is determined that a power-off holdup time of a server power supply needs to be adjusted, acquiring an input power consumption of the server power supply which is measured by a first measurement circuit and the voltage difference between output voltages of a power supply power factor correction stage circuit, which output voltages are measured by a second measurement circuit; on the basis of the input power consumption and the voltage difference, determining a correspondence between the power-off holdup time of the server power supply and output capacitance of the power supply power factor correction stage circuit; and according to the correspondence, adjusting the output capacitance, so as to adjust the power-off holdup time of the server power supply to a first power-off holdup time.

Description

Methods, devices, microprocessors, and storage media for adjusting power outage duration

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411530391.8, filed on October 30, 2024, entitled “Method, Apparatus, Microprocessor and Storage Medium for Adjusting Power-Off Duration”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computers, and more specifically, to a method, apparatus, microprocessor, storage medium, electronic device, and computer program product for adjusting the power outage duration. Background Technology

[0004] In the field of server power supplies, ensuring power continuity to cope with voltage interruptions or sudden drops is a core design challenge. Solutions in related technologies often rely on hardware enhancements, such as introducing additional boost circuits to maintain stable output voltage. However, this approach generally leads to increased power supply size and cost, and may reduce overall power density.

[0005] Currently, there is a lack of effective control methods in related technologies to optimize the server power outage sustainment time without adding additional hardware such as boost circuits. Summary of the Invention

[0006] This application provides a method, apparatus, microprocessor, storage medium, electronic device, and computer program product for adjusting power outage duration, in order to at least solve the problems in the related art that require additional hardware such as boost circuits to optimize server power outage duration, resulting in increased power supply size, higher costs, and lower reliability of server power supplies.

[0007] According to one embodiment of this application, a method for adjusting the power-off duration is provided, applied in a microprocessor. The microprocessor is configured with multiple pairs of pins, wherein different pin pairs are connected to detection circuits configured to perform different detection functions. The method includes: when it is determined that the power-off duration of a server power supply needs to be adjusted, acquiring the voltage difference between the input power consumption of the server power supply detected by a first detection circuit and the output voltage of the power factor correction circuit detected by a second detection circuit; determining the correspondence between the power-off duration of the server power supply and the output capacitance of the power factor correction circuit based on the input power consumption and the voltage difference; and adjusting the output capacitance according to the correspondence to adjust the power-off duration of the server power supply to a first power-off duration.

[0008] In one exemplary embodiment, obtaining the input power consumption of the server power supply detected by the first detection circuit includes: obtaining the output power consumption, output percentage, and power conversion efficiency of the server power supply detected by the first detection circuit; and determining the input power consumption based on the output power consumption, output percentage, and conversion efficiency.

[0009] In an exemplary embodiment, the input power consumption is determined based on the output power consumption, the output percentage, and the conversion efficiency, including: determining the input power consumption Pin by the following formula (1): Pin = Pout × Load / η Formula (1); where Pout is the output power consumption, Load is the output percentage, and η is the conversion efficiency.

[0010] In one exemplary embodiment, obtaining the voltage difference of the output voltage of the power factor correction electrode circuit detected by the second detection circuit includes: obtaining the highest value of the output voltage of the power factor correction electrode circuit detected by the second detection circuit, and the lowest value of the voltage used to maintain the server power output; and determining the difference between the highest voltage value and the lowest voltage value as the voltage difference.

[0011] In an exemplary embodiment, determining the correspondence between the power outage duration of the server power supply and the output capacitance of the power factor correction circuit based on the input power consumption and voltage difference includes: determining the correspondence between the power outage duration T_holdup of the server power supply and the output capacitance C_bulk using the following formula (2): T_holdup=C_bulk×ΔV^2 / (2×Pin) Formula (2), where ΔV is the voltage difference and Pin is the input power consumption.

[0012] In an exemplary embodiment, when it is determined that the power outage duration of the server power supply needs to be adjusted, the method further includes: determining the correspondence between the power outage duration of the server power supply and the output voltage of the power factor correction circuit; adjusting the output voltage of the power factor correction circuit according to the correspondence to adjust the power outage duration of the server power supply to a second power outage duration.

[0013] In an exemplary embodiment, determining the correspondence between the power outage holding time of the server power supply and the output voltage of the power factor correction circuit includes: determining the following formula (3) based on formula (2), wherein formula (3) is used to indicate the correspondence between the power outage holding time T_holdup of the server power supply and the output voltage Pout of the power factor correction circuit: T_holdup=C_bulk×(1-C_error)×(Vbulk_high^2-Vbulk_low^2)×η / (2×Pout×Load) formula (3); wherein C_error is the error value of the output capacitor, Vbulk_high is the highest output voltage of the power factor correction circuit, and Vbulk_low is the lowest voltage used to maintain the output of the server power supply.

[0014] In one exemplary embodiment, adjusting the output voltage of the power factor correction circuit according to a correspondence to adjust the power outage duration of the server power supply to a second power outage duration includes: determining a target output voltage, wherein when the output voltage of the power factor correction circuit is the target output voltage, the power outage duration of the server power supply remains at the second power outage duration; and adjusting the duty cycle based on the current input voltage of the power factor correction circuit and the correspondence between the input voltage and output voltage of the power factor correction circuit to adjust the output voltage of the power factor correction circuit to the target output voltage.

[0015] In an exemplary embodiment, before adjusting the duty cycle, the method further includes: determining the correspondence between the input voltage Vin and the output voltage Vout of the power factor correction circuit by the following formula (4): Vout=Vin / (1-D) formula (4); where D is the duty cycle.

[0016] In one exemplary embodiment, before adjusting the duty cycle, the method further includes: acquiring the current input voltage of the power factor correction circuit detected by the third detection circuit.

[0017] In an exemplary embodiment, the third detection circuit includes a first resistor and a second resistor, wherein a first end of the first resistor is connected to the input voltage detection terminal of the power factor correction circuit, a second end of the first resistor is connected to the target pin of the microprocessor and the first end of the second resistor, and the second end of the second resistor is grounded.

[0018] In one exemplary embodiment, the first resistor includes a first sub-resistor and a second sub-resistor, wherein the resistance values ​​of both the first sub-resistor and the second sub-resistor are 499KΩ, and the resistance value of the second resistor is 5.57KΩ.

[0019] According to another embodiment of this application, an apparatus for adjusting the power-off duration is provided, applied in a microprocessor. The microprocessor is configured with multiple pairs of pins, wherein different pin pairs are connected to detection circuits configured to perform different detection functions. The apparatus includes: a first acquisition module, configured to acquire, when it is determined that the power-off duration of a server power supply needs to be adjusted, the voltage difference between the input power consumption of the server power supply detected by the first detection circuit and the output voltage of the power factor correction circuit detected by the second detection circuit; a first determination module, configured to determine the correspondence between the power-off duration of the server power supply and the output capacitance of the power factor correction circuit based on the input power consumption and the voltage difference; and a first adjustment module, configured to adjust the output capacitance according to the correspondence to adjust the power-off duration of the server power supply to a first power-off duration.

[0020] According to yet another embodiment of this application, a microprocessor is provided, including: the above-described means for adjusting the power outage duration.

[0021] According to yet another embodiment of this application, a non-volatile computer-readable storage medium is also provided, wherein a computer program is stored in the non-volatile computer-readable storage medium, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0022] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein a computer program is stored in the memory and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0023] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0024] This application provides an effective control method for optimizing the power outage sustaining time of server power supplies during input voltage interruptions or drops. It eliminates the need for an additional boost circuit, adjusting the output capacitor according to a specific relationship between the power outage sustaining time and the output capacitor, thereby achieving adjustment of the power outage sustaining time. Compared to traditional methods that rely on additional hardware such as boost circuits, this application significantly reduces costs, saves space, increases the power density of server power supplies, and simplifies maintenance procedures. It effectively solves the problems in related technologies where additional hardware such as boost circuits is required to optimize server power supply power outage sustaining time, leading to increased power supply size, higher costs, and lower reliability. Attached Figure Description

[0025] Figure 1 is a schematic diagram of the input voltage interruption waveform in related technologies;

[0026] Figure 2 is a schematic diagram of the input voltage drop waveform in the relevant technology;

[0027] Figure 3 is a hardware structure block diagram of a server device for a method of adjusting power outage duration according to an embodiment of this application.

[0028] Figure 4 is a flowchart of a method for adjusting the power outage duration according to an embodiment of this application;

[0029] Figure 5 is a schematic diagram of the server power supply according to an embodiment of this application;

[0030] Figure 6 is a block diagram of the active power factor correction electrode circuit boost circuit structure according to an embodiment of this application;

[0031] Figure 7 is a schematic diagram of the waveform of the inductor in a boost circuit according to an embodiment of this application;

[0032] Figure 8 is a power supply PFC circuit and control architecture diagram according to an embodiment of this application;

[0033] Figure 9 is a schematic diagram of the PFC output voltage amplification process when the input voltage is interrupted and suddenly drops according to an embodiment of this application;

[0034] Figure 10 is a schematic diagram of an input voltage detection circuit according to an embodiment of this application;

[0035] Figure 11 is a structural block diagram of a device for adjusting the power outage duration according to an embodiment of this application. Detailed Implementation

[0036] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0038] Based on the IEEE definition of power quality disturbances and waveform analysis, power quality problems can be classified into the following seven types:

[0039] (1) Transient phenomenon; (2) Interruption; (3) Voltage sag / undervoltage; (4) Voltage swell / overvoltage; (5) Waveform distortion; (6) Voltage fluctuation; (7) Frequency jitter.

[0040] An input interruption is defined as the complete disappearance of the supply voltage or load current. Depending on its duration, interruptions can be classified as transient interruptions, temporary interruptions, short-term interruptions, or continuous interruptions. Figure 1 shows a schematic diagram of an input voltage interruption waveform; the duration ranges for various interruption types are as follows:

[0041] Transient interruption lasts from 0.5 to 30 cycles;

[0042] Temporarily interrupt for 30 cycles to 2 seconds;

[0043] Short interruptions of 2 seconds to 2 minutes;

[0044] The interruption lasted for more than 2 minutes.

[0045] A voltage sag refers to a drop in AC voltage at a given frequency (50-60Hz), lasting for a short period from half a cycle to one minute before returning to normal. According to European standard EN50160, a voltage drop below 90% of the standard value followed by a recovery to above 90% lasts for 10ms to 60s. Therefore, a voltage drop lasting more than one minute is considered a power outage. Using the standard value as a reference, a 3% drop from 92% of the standard value constitutes an 11% voltage sag. Figure 2 shows the input voltage sag waveform. The process by which power infrastructure attempts to eliminate remote faults can cause problems for end users. If the problem is significant, it will be considered an outage. However, problems that are eliminated quickly or recovered rapidly may also manifest as voltage sags.

[0046] Input interruptions or voltage drops are typically caused by power supply system failures, including starting heavy loads (such as starting a large air conditioning unit for the first time) and troubleshooting remote power equipment failures. Similarly, starting a large motor in an industrial plant can also cause a significant voltage drop. Other factors include short circuits in power supply equipment, trees growing on overhead cables, cable damage, and equipment failures such as those occurring during excavation work. Weather factors, such as overhead cables tripping due to lightning strikes, can also contribute. Whether transient, temporary, short-term, or persistent, interruptions can cause disruption, damage, and downtime for users ranging from small households to large industrial enterprises. Home or small business computer users may lose important data due to data corruption caused by power outages.

[0047] Data centers typically employ uninterruptible power supplies (UPS) to prevent input interruptions or voltage drops. A UPS is a device that continuously provides backup AC power to electrical loads in the event of power grid anomalies (such as power outages, undervoltage, interference, or surges), maintaining the normal operation of the appliances. Typically, UPS systems are used to maintain the uninterrupted operation of critical commercial equipment or precision instruments such as computers (especially servers) or switches, preventing data loss, telephone communication network interruptions, or loss of instrument control. If the mains power fails, the UPS will switch to battery power to ensure the system does not shut down. Switching time refers to the time required for the UPS to complete the switch to ensure uninterrupted power supply. It also refers to the time required for the UPS to switch back to mains power after the problem is resolved, which typically takes one to half an AC cycle. For example, with an AC power supply frequency of 50Hz, it would take 1 / 50Hz to 1 / (2 x 50Hz) = 20ms to 10ms; with an AC power supply frequency of 60Hz, it would take 1 / 60Hz to 1 / (2 x 60Hz) = 16ms to 8ms. Therefore, it is recommended that the UPS switch to battery power within 20ms under full system load. This means that the server power supply must maintain a 100% load output for at least 20ms during a power outage (it should be noted that this duration is used as an example in this application; in subsequent applications, this duration can be flexibly set based on actual conditions, such as 30ms, 50ms, etc.). This application provides a server power supply that can maintain an optimal 20ms hold-up time during power outages when the input is interrupted or the voltage drops, even when the power supply is operating at 75% to 100% load. The following describes this application with reference to embodiments:

[0048] The methods and embodiments provided in this application can be executed in a server device or a similar computing device. Taking a server device as an example, FIG3 is a hardware structure block diagram of a server device for a method of adjusting power outage duration according to an embodiment of this application. As shown in FIG3, the server device may include one or more (only one is shown in FIG3) processors 302 (processors 302 may include, but are not limited to, microprocessors MCUs or programmable logic devices FPGAs, etc.) and a memory 304 configured to store data. The server device may also include a transmission device 306 for communication functions and an input / output device 308. It will be understood by those skilled in the art that the structure shown in FIG3 is only illustrative and does not limit the structure of the server device. For example, the server device may also include more or fewer components than shown in FIG3, or have a different configuration than shown in FIG3.

[0049] The memory 304 may be configured to store computer programs, such as application software programs and modules, like the computer program corresponding to the method for adjusting the power outage duration in this embodiment. The processor 302 executes various functional applications and data processing by running the computer program stored in the memory 304, thereby implementing the aforementioned method. The memory 304 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 304 may further include memory remotely located relative to the processor 302, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0050] Transmission device 306 is configured to receive or transmit data via a network. Examples of such networks may include a wireless network provided by a communication provider for the server device. In one example, transmission device 306 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, transmission device 306 may be a Radio Frequency (RF) module configured to communicate wirelessly with the Internet.

[0051] This embodiment provides a method for adjusting the power-off duration. This method can be applied to a microprocessor (Microcontroller Unit, or MCU) with multiple pairs of pins, where different pin pairs are connected to detection circuits configured to perform different detection functions. Figure 4 is a flowchart of the method for adjusting the power-off duration according to an embodiment of this application. As shown in Figure 4, the process includes the following steps:

[0052] Step S402: If it is determined that the power outage duration of the server power supply needs to be adjusted, the input power consumption of the server power supply detected by the first detection circuit and the voltage difference between the output voltage of the power factor correction circuit detected by the second detection circuit are obtained.

[0053] Step S404: Determine the relationship between the power outage duration of the server power supply and the output capacitance of the power factor correction circuit based on the input power consumption and voltage difference.

[0054] Step S406: Adjust the output capacitor according to the corresponding relationship to adjust the power outage duration of the server power supply to the first power outage duration.

[0055] In the above embodiments, the server power supply can also be called a Server PSU (Server Power Supply Unit). The structure of the power supply can be seen in Figure 5 (the circuit diagram in Figure 5 can also be called an AC / DC digital power supply unit block diagram). In this figure, multiple pairs of pins are configured in the MCU, and each pair of pins is connected to a specific detection circuit, which is set to monitor different key parameters of the server power supply in real time. For example, the first detection circuit is responsible for detecting the input power consumption of the server power supply, while the second detection circuit detects the voltage of the power factor correction stage (PFC stage) circuit. For instance, the second detection circuit can detect the voltage difference between the output voltage of the PFC stage circuit (or simply the PFC circuit). This second detection circuit can detect the highest output voltage of the PFC circuit and the lowest voltage that can maintain the server's output voltage, and then determine the voltage difference based on these two values. Furthermore, the MCU can be connected to other circuits to detect different parameters. For example, it can be connected to a circuit to detect the input current of the PFC circuit (by detecting this input circuit, specific current protection operations can be performed, or specific operations can be performed based on the current detection results), or a circuit to detect the input voltage of the PFC circuit, etc. The types of circuits connected can be flexibly configured based on actual conditions. Through the cooperation of these pins and the detection circuits, the MCU can quickly identify parameter changes in specific scenarios, such as any changes in input voltage, including interruptions or voltage drops, and accurately measure the impact of these changes on the server power supply.

[0056] In the above embodiments, there are several ways to adjust the output capacitor. For example, multiple capacitor connection branches can be pre-configured, and the required capacitor branch can be selected based on the actual situation to achieve the purpose of adjusting the output capacitor. Another example is that the charging and discharging state of the capacitor, i.e., the voltage across the capacitor, can indirectly affect the energy that the capacitor can provide during power outages, thereby extending the power outage duration. The energy storage capacity of a capacitor is proportional to the product of its voltage and capacitance. Therefore, without replacing the capacitor, software control can be used to charge the capacitor to a higher voltage before power outages, increasing the energy it can provide and thus extending the duration. For instance, when a sudden drop or interruption in the input voltage is detected, the output voltage of the PFC circuit can be adjusted to allow the capacitor to store more energy at the moment of power outage, i.e., increasing the voltage across the capacitor to simulate the effect of increasing its capacity. The key to this technology lies in accurately determining the occurrence of voltage interruption or drop and adjusting the control signal of the PFC circuit in a timely manner to quickly increase the capacitor voltage.

[0057] In the above embodiments, an effective control method is provided to optimize the power outage sustaining time of server power supplies when the input voltage is interrupted or suddenly drops. This method eliminates the need for an additional boost circuit, adjusting the output capacitor according to a specific correspondence between the power outage sustaining time and the output capacitor, thereby achieving adjustment of the power outage sustaining time. Compared to traditional methods that rely on adding additional hardware such as boost circuits, this application significantly reduces costs, saves space, increases the power density of server power supplies, and simplifies maintenance procedures. It effectively solves the problems in related technologies where additional hardware such as boost circuits is required to optimize the power outage sustaining time, leading to increased power supply size, higher costs, and lower reliability.

[0058] In one exemplary embodiment, acquiring the input power consumption of the server power supply detected by the first detection circuit includes: acquiring the output power consumption, output percentage, and power conversion efficiency of the server power supply detected by the first detection circuit; and determining the input power consumption based on the output power consumption, output percentage, and conversion efficiency. In the above embodiment, the input power consumption of the server power supply can be determined based on its output power consumption, output percentage, and power conversion efficiency. The output power consumption of the server power supply can be measured by the sum of the products of all its DC output voltages and currents. For example, if the server power supply provides multiple output voltages such as +12V, +5V, and +3.3V, then the power consumption (power) of each output is the product of that output voltage and its corresponding current. The total output power consumption (Pout) is the sum of all output power; the output percentage reflects the ratio between the server power supply's total output power and its full-load power, i.e., the ratio of the current actual load to the maximum possible load. This parameter is typically determined by monitoring key performance indicators such as the server's current CPU utilization, RAM usage, and hard drive activity; the server power supply's conversion efficiency evaluates its ability to convert AC input power consumption into usable DC output power consumption.

[0059] In one exemplary embodiment, the input power consumption is determined based on the output power consumption, output percentage, and conversion efficiency, including: determining the input power consumption Pin using the following formula (1): Pin = Pout × Load / η (Formula (1)); where Pout is the output power consumption, Load is the output percentage, and η is the conversion efficiency. Through the above embodiments, the output power consumption of the server power supply can be accurately calculated and determined, thereby achieving the goals of optimizing power management, improving energy efficiency, and predicting and preventing potential power problems.

[0060] In one exemplary embodiment, obtaining the voltage difference of the output voltage of the power factor correction electrode circuit detected by the second detection circuit includes: obtaining the highest value of the output voltage of the power factor correction electrode circuit detected by the second detection circuit, and the lowest value of the voltage used to maintain the server power output; and determining the difference between the highest voltage value and the lowest voltage value as the voltage difference.

[0061] In the above embodiment, the second detection circuit is responsible for monitoring the output voltage of the PFC circuit in the server power supply. Under normal operating conditions, it continuously monitors and records the peak voltage across the bulk capacitor (PFC circuit output capacitor), i.e., the highest output voltage. This value reflects the maximum voltage support that the PFC circuit can provide under full load and light load conditions. Additionally, to ensure the server power supply maintains a stable output during power outages, a minimum voltage sustaining value (or minimum voltage) needs to be set. This value is the minimum voltage required to maintain the server's critical load operation after a power outage. This minimum voltage is typically set based on the server power supply's minimum output voltage requirements and power outage sustaining time standards, ensuring that the power supply output does not fall below the voltage threshold required to maintain stable server operation under any possible grid disturbances. The voltage difference mentioned above is the difference between the highest and lowest voltage values, which reflects the range of energy that the PFC circuit output capacitor can release during a power outage.

[0062] In an exemplary embodiment, determining the correspondence between the power outage duration of the server power supply and the output capacitor of the power factor correction circuit based on the input power consumption and voltage difference includes: determining the correspondence between the power outage duration T_holdup and the output capacitor C_bulk using the following formula (2): T_holdup=C_bulk×ΔV^2 / (2×Pin) Formula (2), where ΔV is the voltage difference and Pin is the input power consumption. The above formula allows for accurate calculation of the correspondence between the power outage duration and the output capacitor, enabling precise calculation and optimization of the server power outage duration. This not only improves the intelligence and reliability of power management but also optimizes power supply design, increases energy efficiency, and simplifies maintenance processes. It is of great significance for improving the stability and business continuity of high-performance servers in complex power environments.

[0063] In an exemplary embodiment, when it is determined that the power outage duration of the server power supply needs to be adjusted, the method further includes: determining the correspondence between the power outage duration of the server power supply and the output voltage of the power factor correction circuit; adjusting the output voltage of the power factor correction circuit according to the correspondence to adjust the power outage duration of the server power supply to a second power outage duration. In this embodiment, the purpose of the output capacitance of the PFC circuit can be achieved by adjusting the output voltage of the PFC circuit. In addition, based on the aforementioned embodiment of adjusting the power outage duration by adjusting the output capacitance, the power outage duration can be further adjusted by adjusting the output voltage of the PFC circuit. For example, a partial adjustment of the power outage duration can be achieved based on the aforementioned correspondence between the output capacitance and the power outage duration, and then the remaining duration can be adjusted based on the correspondence between the power outage duration and the output voltage. The power outage duration can be adjusted to the required value through the above two adjustment operations, such as 20ms, 25ms, 30ms, etc. The multi-stage adjustment method described above allows for more precise control of power outage duration, ensuring that the server power supply can achieve optimal power outage duration under different load and voltage conditions, thus meeting the needs of different scenarios.

[0064] In an exemplary embodiment, determining the correspondence between the power outage holding time of the server power supply and the output voltage of the power factor correction circuit includes: determining the following formula (3) based on formula (2), wherein formula (3) is used to indicate the correspondence between the power outage holding time T_holdup of the server power supply and the output voltage Pout of the power factor correction circuit: T_holdup=C_bulk×(1-C_error)×(Vbulk_high^2-Vbulk_low^2)×η / (2×Pout×Load) formula (3); wherein C_error is the error value of the output capacitor, Vbulk_high is the highest output voltage value of the power factor correction circuit, and Vbulk_low is the lowest voltage value used to maintain the output of the server power supply. In the above embodiment, the aforementioned formula (2) was further optimized to obtain formula (3). In formula (3), the error value of the output capacitor of the PFC circuit is comprehensively considered, and the calculation deviation caused by measurement error or other uncertainties is corrected, so as to more accurately calculate the energy that the capacitor can store and release during the power outage. This better matches the actual capacitor performance, providing a more reliable energy estimate. Furthermore, the calculation method for the square of the voltage difference (ΔV^2) has been optimized. The optimized formula highlights the relationship between the highest and lowest voltage values ​​of the PFC circuit and the power-off duration, making the calculation simpler and more accurate.

[0065] In one exemplary embodiment, adjusting the output voltage of the power factor correction (PFC) circuit according to a correspondence to adjust the power outage duration of the server power supply to a second power outage duration includes: determining a target output voltage, wherein when the output voltage of the PFC circuit is the target output voltage, the power outage duration of the server power supply remains at the second power outage duration; and adjusting the duty cycle based on the current input voltage of the PFC circuit and the correspondence between the input and output voltages of the PFC circuit to adjust the output voltage of the PFC circuit to the target output voltage. In this embodiment, the input and output voltages of the PFC circuit also satisfy a certain correlation. Based on the current input voltage, the output voltage can be adjusted to an ideal value by adjusting the duty cycle. The input voltage detection can be implemented by the MCU through a specific detection circuit, and the output voltage detection can also be implemented by the MCU through a specific detection circuit. The circuit that detects the output voltage can further verify whether the output voltage has been adjusted to the ideal value.

[0066] In an exemplary embodiment, before adjusting the duty cycle, the method further includes: determining the correspondence between the input voltage Vin and the output voltage Vout of the power factor correction circuit by the following formula (4): Vout=Vin / (1-D) formula (4); where D is the duty cycle.

[0067] In an exemplary embodiment, before adjusting the duty cycle, the method further includes: acquiring the current input voltage of the power factor correction circuit detected by the third detection circuit. In this embodiment, the structure of the third detection circuit can be flexibly configured based on the actual application scenario and the requirements for detection accuracy. The structure of the third detection circuit is described below as an example:

[0068] In one exemplary embodiment, the third detection circuit includes a first resistor and a second resistor. A first terminal of the first resistor is connected to the input voltage detection terminal of the power factor correction circuit, and a second terminal of the first resistor is connected to the target pin of the microprocessor and the first terminal of the second resistor. The second terminal of the second resistor is grounded. In this embodiment, the first resistor includes a first sub-resistor and a second sub-resistor, both with a resistance value of 499KΩ, and the second resistor has a resistance value of 5.57KΩ. It should also be noted that the number of the first and second resistors can be other values. For example, there can be one of each, or one first resistor and two second resistors, etc. When the number of resistors varies, the resistance values ​​of each resistor can also be different, and the resistance values ​​can be adjusted based on the actual structure of the detection circuit.

[0069] The present application will now be described in its entirety with reference to specific embodiments:

[0070] The implementation of this application's embodiments is divided into three main parts:

[0071] I. Determining the input voltage of the power factor correction (PFC) circuit (also referred to as PFC) of the Server PSU (Server Power Supply Unit, corresponding to the aforementioned server power supply);

[0072] II. Amplification of the power factor correction (PFC) control signal of the Server PSU;

[0073] III. Design of the output voltage of the power factor correction (PFC) electrode of the Server PSU.

[0074] The following sections will explain each part in detail:

[0075] I. Determining the power factor correction electrode voltage of a Server PSU:

[0076] The overvoltage detection implementation for Server PSU power factor correction has two parts:

[0077] (1) Determine when the input voltage interruption and sudden drop occur;

[0078] (2) PFC voltage boosting conditions when input voltage interruption and sudden drop occur.

[0079] in:

[0080] (1) Determine if the input voltage is interrupted or suddenly drops:

[0081] In related technologies, server power supplies (PSUs) are controlled by MCUs, which perform functions such as converter switching control, fan control, LED (Light Emitting Diode) control, monitoring, protection, and communication. In terms of division of labor, MCUs are divided into primary side MCUs and secondary side MCUs.

[0082] The primary side MCU has the following main functions: 1) Power factor correction circuit (PFC) switch control; 2) AC input voltage and current monitoring and protection; 3) Inrush current protection switch control; 4) Communication functions such as UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), etc.; 5) FRU (Field Replacement Unit) data storage.

[0083] The main functions of the secondary side MCU are: 1) switching control of high-efficiency converter (DCDC, Direct Current to Direct Current Converter); 2) monitoring and protection of DC output voltage and current; 3) PSU fan control and over-temperature protection; 4) communication functions such as UART, SPI, I2C, etc.

[0084] The power factor correction (PFC) stage circuit is responsible for the hold-up time during power input and circuit control when power is lost. Many electrical products have very low power factors due to their internal impedance characteristics. To improve the power factor of these products, a power factor correction circuit must be installed at the power input. However, adding this circuit inevitably increases manufacturing costs, which are ultimately passed on to consumers. Therefore, manufacturers, prioritizing cost savings, often focus on low prices and are unwilling to pass on these environmental costs to customers. Most consumers, unaware of the importance of power factor correction circuits, believe that building power plants is the only solution to power shortages, a major problem in the power supply of most developing countries.

[0085] The main function of a power factor correction (PFC) stage circuit is to ensure that the voltage and current are in phase and that the load is approximately resistive. Therefore, there are many methods for circuit design. Based on the components used, they can be classified into passive and active power factor correctors. Passive power factor correctors, even under optimal conditions, can only achieve a power factor (PF) of 70%, making them unsuitable for stringent power factor requirements. To achieve a PF of over 85% across the entire voltage range (90V~265Vac) under both light and heavy load conditions, an active power factor corrector is necessary. Active power factor correction circuits are mostly based on a boost topology.

[0086] Figure 6 shows a block diagram of the active power factor correction boost circuit in this embodiment of the application, and Figure 7 shows a waveform diagram of the inductor effect in the boost circuit in this embodiment of the application. The input voltage requirement is 180V~265Vac, which is 255V~375V DC voltage at point Vd. The boost circuit boosts the output voltage Vo to 415V DC. Its working process is as follows:

[0087] 1. When Q is turned on, the voltage across the inductor is VL = Vd. At this time, Vd, L and Q form a circuit. Vd charges the inductor L. The circuit is shown by the dashed line in Figure 6. At this time, the inductor current ζL rises along the same slope until Q is turned off, and the working cycle (DT) ends.

[0088] 2. When Q is off, the inductor voltage is reversed and Vd is added to the output terminal through diode D. At this time, capacitor C is in a charging state, and RL maintains Vo output. The magnitude of Vo is the input voltage Vd plus the value of the inductor voltage (-VL) (since the inductor voltage is reversed, -VL is positive). The circuit is shown by the gray line in Figure 6 until Q is turned on again (that is, the (1-D)T time period ends).

[0089] If the boost circuit of the active power factor correction stage shown in Figure 7 is to have power factor correction functionality, the control signal for Q must come from an integrated circuit (PFC IC) with power factor correction capabilities. Feedback control must be implemented using voltage and current loops, sending these signals back to the PFC IC to control the conduction and cutoff of Q, thereby achieving current waveform shaping. There are two types of PFC ICs: discontinuous current mode power factor correctors (DCM PFC), suitable for power factor correction at lower power requirements. European energy regulations mandate that power supplies above 70W must have PFC circuitry; DCM PFC is generally used below 200W. The other type is continuous current mode power factor correctors (CCM PFC), generally used from 200W to several kilowatts. The primary side MCU controls the input and output voltages of the power factor correction stage (PFC stage), provides feedback control, and controls the switching signals. Figure 8 shows the power supply PFC circuit and control architecture diagram in this embodiment of the application. The input voltage sag and interruption judgment process can be referred to Figure 9, which illustrates the PFC output voltage amplification process when the input voltage is interrupted or sags. Judgment logic needs to be added to the primary side MCU firmware to determine when an input voltage interruption or sag occurs. This can include the following steps:

[0090] S902: PFC input voltage detection;

[0091] S904, determine whether the interrupt and sudden drop conditions are met (this condition can be set according to the conditions shown in Figure 9, or it can be set to other similar conditions);

[0092] S906 performs PFC load adjustment if the interrupt and sudden drop conditions are met;

[0093] S908 performs PFC output voltage adjustment operation.

[0094] The interruption conditions include the following: transient interruption of 0.5 to 30 AC cycles; voltage sag refers to a drop in AC voltage at a given frequency (50-60Hz), followed by a brief period of half a cycle to one minute before returning to normal. According to European standard EN50160, the voltage drops to below 90% of the standard value and then recovers to above 90%, with a duration of 10ms to 60s.

[0095] The hold-up time design for the PFC circuit during power failure is as follows:

[0096] The power-off sustaining time of the PFC circuit mainly relies on the PFC output capacitor Bulk Cap. Therefore, the power-off sustaining time can be obtained using the energy conservation theorem in capacitor mode: Pin×ΔT_holdup=1 / 2×C_bulk×ΔV^2;

[0097] Therefore, the holdup time during power outage can be obtained by phase shifting: ΔT_holdup=C_bulk×ΔV^2 / (2×Pin);

[0098] Where ΔV^2 is ΔV raised to the power of 2, and the meanings of the parameters are as follows:

[0099] 1) Pin: Server PSU input power consumption, which is also equal to Pin = Pout (Server PSU output power consumption) × Load (output ratio %) / η (Server PSU conversion efficiency);

[0100] 2) ΔT_holdup: Hold-up time during power outage (i.e., the power outage duration mentioned above);

[0101] 3) C_bulk: The capacitance value of the PFC output capacitor Bulk Cap, and C_error: The error value of the Bulk Cap capacitance value, with a maximum of 20%;

[0102] 4) ΔV: The voltage difference between the PFC circuit output voltage Vbulk and its peak value, which is sufficient to maintain the output, can be expressed as:

[0103] Vbulk_high-Vbulk_low;

[0104] Therefore, by substituting into the aforementioned formula and making appropriate modifications, we can obtain the formula for the hold-up time when the PFC circuit is de-energized: ΔT_holdup=C_bulk×(1-C_error)×(Vbulk_high^2-Vbulk_low^2)×η / (2×Pout ×Load).

[0105] For example, for a server with a maximum output of 1600W, based on the PFC output capacitor Bulk Cap value and the operating load range, the sustaining time of the PFC circuit during power failure is shown in Table 1:

[0106] Table 1

[0107] If a full-load output of 100% is required to reach more than 20ms, the output capacitor must be 1000uF or more to achieve this. The limited number of manufacturers that can support this design value makes design and material selection difficult.

[0108] By adjusting the PFC circuit output voltage from 450V to 290V (these two values ​​are illustrative examples; in practical applications, the ideal PFC voltage and the voltage after the voltage drop can be set based on actual conditions, such as setting the ideal voltage to 480V or 500V, etc.), the power-off sustaining time can be effectively extended. In this case, an 810uF output capacitor with a voltage rating of 600V should be selected to achieve a full-load output of over 20ms at 100% capacity. No special capacitor values ​​are required; many manufacturers offer suitable options, as shown in Table 2.

[0109] Table 2

[0110] (2) Determining the PFC voltage boost when the input voltage is interrupted or drops sharply:

[0111] The feedback voltage determination formula is as follows when the input voltage drops sharply:

[0112] 1) The input voltage is 0, and Vin = 0 is maintained for 0.5 to 30 AC cycles.

[0113] 2) The input voltage drops by 90% for 0 to 0.5 AC cycles.

[0114] 3) The input voltage drops by 30% for 1 to 3000 AC cycles.

[0115] It should be noted that the above judgment methods are just a few examples. In practical applications, other judgment methods can also be used, such as a voltage drop of 50% for 1 to 500 cycles, a voltage drop of 70% for 1 to 2000 AC cycles, etc. The judgment conditions can be set based on the actual situation.

[0116] II. Amplification of the Server PSU Power Factor Correction (PFC) Control Signal:

[0117] The power factor correction stage (PFC stage) and control signal architecture in the power supply circuit are shown in Figure 8. The PWM (Pulse Width Modulation) signal provided by the primary side MCU is sent to the main switch Q via the Gate Driver as a drive signal to complete the power factor correction and output PFC voltage.

[0118] Therefore, limiting the duty cycle (D, Duty) of the PFC control signal can achieve the purpose of controlling the PFC voltage range. The relationship between PFC voltage, input voltage (Vin), and duty cycle D is PFC Vout = Vin / (1-D), where D < 1 (the duty cycle will be less than 1). That is, for a PFC circuit, when Vin is significantly less than PFC Vout, the circuit needs to provide a larger D to meet the boost requirement. Therefore, the wider the input voltage range, the greater the chip's duty cycle adjustment capability. In this case, if a voltage drop or interruption occurs and PFC Vout needs to rise to 450V, the duty cycle D limit setting is as follows:

[0119] (a) Input voltage is 0, Vin = 0 for 0.5 to 30 AC cycles:

[0120] At this point, Vin is 0, and the PFC output needs to be increased to 450V. At this point, the input voltage is 220Vac, which means the PFC output voltage drops from 220 × 1.414 = 311 to 290V.

[0121] The duty cycle D increases by 450 = 311 / (1-D) ~ 450 = 290 / (1-D) => At this time, the duty cycle D is 0.3 ~ 0.35.

[0122] (ii) The input voltage drops by 90% for 0 to 0.5 AC cycles:

[0123] At this point, Vin is 220Vac, which drops by 90% to 22V. The PFC Voltage needs to be increased to 450V.

[0124] The duty cycle D increases by 450 = 22 × 1.414 / (1 - D) => At this point, the duty cycle needs to be increased to 0.93.

[0125] (iii) The input voltage drops by 30% for 1 to 3000 AC cycles:

[0126] At this point, Vin is 220Vac, which drops by 30% to 154V. The PFC Voltage needs to be increased to 450V.

[0127] The duty cycle D limit is 440 = 154 × 1.414 / (1-D) => At this time, the duty cycle needs to be increased to 0.52.

[0128] III. Design of the output voltage of the power factor correction (PFC) electrode in the Server PSU:

[0129] The core is that the output voltage (V_Bulk) of the power factor correction stage (PFC stage) is controlled by the primary side MCU and needs to be adjusted to 450V. The input voltage detection circuit is shown in Figure 10. When the server PSU power factor correction stage PFC output voltage is reached, the feedback voltage judgment formula is as follows: Vo=Vref×(R1+R2+R3) / R3;

[0130] M1 is the primary side MCU;

[0131] The constant feedback reference voltage Vref = 2.5V;

[0132] The feedback resistor has an accuracy of 1% and is a high-voltage withstand resistor;

[0133] The design values ​​for R1, R2, and R3 are as follows:

[0134] According to the formula, the output voltage needs to be stable at 450V, Vref is set to 2.5V, R1 and R2 are both 499K ohms, and R3 is 5.57Kohms. The parameters can be found in Table 3.

[0135] Table 3

[0136] Therefore, when the input voltage drops suddenly or is interrupted, this firmware function can be placed into the primary side MCU, which can effectively extend the power outage sustaining time of the server. There are many manufacturers that can support this without special capacitor values, and it maintains the optimal 20ms under power supply load of 75% to 100%.

[0137] It should be noted that the application scenarios of the above embodiments are quite extensive. For example, in the field where data centers and servers are located, there may be instances where the input voltage drops suddenly due to starting heavy loads (such as starting large air conditioning equipment), troubleshooting remote power equipment, or starting large motors in industrial plants. In such scenarios, the solutions in the embodiments of this application can be adopted.

[0138] The following effects can be achieved through the embodiments of this application:

[0139] By pre-setting this firmware function to the primary-side MCU when the input voltage drops or is interrupted, the power outage sustainment time of the server can be effectively extended without adding any hardware functions or special capacitor values, and the optimal 20ms is maintained even when the power supply is operating at 75% to 100% load.

[0140] This eliminates the need for maintenance personnel to go to the computer room to troubleshoot problems caused by "sudden drop or interruption of input voltage".

[0141] No additional hardware setup or special capacitor values ​​are required; this function can be added to the existing architecture and firmware.

[0142] It does not require special technologies or new materials, making it relatively easy to achieve.

[0143] The firmware design steps are proposed to effectively extend the power server's power outage sustainment time without adding hardware.

[0144] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0145] This embodiment also provides a device for adjusting the power outage duration, which is used to implement the above embodiments and optional implementations; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0146] Figure 11 is a structural block diagram of a device for adjusting the power-off duration according to an embodiment of this application. As shown in Figure 11, the device is applied in a microprocessor, which is configured with multiple pairs of pins, wherein different pin pairs are connected to detection circuits configured to perform different detection functions; including: a first acquisition module 112, configured to acquire, when it is determined that the power-off duration of the server power supply needs to be adjusted, the input power consumption of the server power supply detected by the first detection circuit and the voltage difference between the output voltage of the power factor correction circuit detected by the second detection circuit; a first determination module 114, configured to determine the correspondence between the power-off duration of the server power supply and the output capacitance of the power factor correction circuit based on the input power consumption and the voltage difference; and a first adjustment module 116, configured to adjust the output capacitance according to the correspondence to adjust the power-off duration of the server power supply to a first power-off duration.

[0147] In an exemplary embodiment, the first acquisition module 112 includes: a first acquisition unit configured to acquire the output power consumption, output percentage, and power conversion efficiency of the server power supply detected by the first detection circuit; and a first determination unit configured to determine the input power consumption based on the output power consumption, output percentage, and conversion efficiency.

[0148] In an exemplary embodiment, the first determining unit includes: a determining subunit configured to determine the input power consumption Pin by the following formula (1): Pin = Pout × Load / η formula (1); where Pout is the output power consumption, Load is the output percentage, and η is the conversion efficiency.

[0149] In one exemplary embodiment, the first acquisition module 112 includes: a second acquisition unit configured to acquire the highest value of the output voltage of the power factor correction electrode circuit detected by the second detection circuit, and configured to maintain the lowest value of the voltage output of the server power supply; and a second determination unit configured to determine the difference between the highest voltage value and the lowest voltage value as a voltage difference.

[0150] In an exemplary embodiment, the first determining module 114 includes a third determining unit, configured to determine the correspondence between the power outage duration T_holdup of the server power supply and the output capacitor C_bulk by the following formula (2): T_holdup=C_bulk×ΔV^2 / (2×Pin) formula (2); where ΔV is the voltage difference and Pin is the input power consumption.

[0151] In one exemplary embodiment, the apparatus further includes: a second determining module, configured to determine a correspondence between the power outage duration of the server power supply and the output voltage of the power factor correction circuit when it is determined that the power outage duration of the server power supply needs to be adjusted; and a second adjusting module, configured to adjust the output voltage of the power factor correction circuit according to the correspondence, so as to adjust the power outage duration of the server power supply to a second power outage duration.

[0152] In an exemplary embodiment, the second determining module includes: a fourth determining unit, configured to determine the following formula (3) based on formula (2), wherein formula (3) is used to indicate the correspondence between the power outage holding time T_holdup of the server power supply and the output voltage Pout of the power factor correction electrode circuit: T_holdup=C_bulk×(1-C_error)×(Vbulk_high^2-Vbulk_low^2)×η / (2×Pout×Load) formula (3); wherein C_error is the error value of the output capacitor, Vbulk_high is the highest output voltage value of the power factor correction electrode circuit, and Vbulk_low is the lowest voltage value used to maintain the output of the server power supply.

[0153] In one exemplary embodiment, the second adjustment module includes: a fifth determining unit configured to determine a target output voltage, wherein, when the output voltage of the power factor correction circuit is the target output voltage, the power outage duration of the server power supply is maintained at a second power outage duration; and an adjustment unit configured to adjust the duty cycle based on the current input voltage of the power factor correction circuit and the correspondence between the input voltage and the output voltage of the power factor correction circuit, so as to adjust the output voltage of the power factor correction circuit to the target output voltage.

[0154] In an exemplary embodiment, the apparatus further includes a third determining module, configured to determine the correspondence between the input voltage Vin and the output voltage Vout of the power factor correction circuit by the following formula (4) before adjusting the duty cycle: Vout=Vin / (1-D) formula (4); where D is the duty cycle.

[0155] In one exemplary embodiment, the apparatus further includes a second acquisition module configured to acquire the current input voltage of the power factor correction circuit detected by the third detection circuit before adjusting the duty cycle.

[0156] In an exemplary embodiment, the third detection circuit includes a first resistor and a second resistor, wherein a first end of the first resistor is connected to the input voltage detection terminal of the power factor correction circuit, a second end of the first resistor is connected to the target pin of the microprocessor and the first end of the second resistor, and the second end of the second resistor is grounded.

[0157] In one exemplary embodiment, the first resistor includes a first sub-resistor and a second sub-resistor, wherein the resistance values ​​of both the first sub-resistor and the second sub-resistor are 499KΩ, and the resistance value of the second resistor is 5.57KΩ.

[0158] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0159] Embodiments of this application also provide a microprocessor (MCU) including any of the foregoing means for adjusting the power-off duration.

[0160] Embodiments of this application also provide a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when it is run.

[0161] In one exemplary embodiment, the aforementioned non-volatile computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0162] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0163] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0164] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0165] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0166] The embodiments described herein also provide a computer program that includes computer instructions stored in a non-volatile computer-readable storage medium; a processor of a computer device reads the computer instructions from the non-volatile computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps in any of the above method embodiments.

[0167] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0168] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0169] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for adjusting the power outage duration, characterized in that, It is applied in a microprocessor, wherein the microprocessor is configured with multiple pairs of pins, wherein different pin pairs are connected to detection circuits configured to perform different detection functions; include: If it is determined that the power outage duration of the server power supply needs to be adjusted, the input power consumption of the server power supply detected by the first detection circuit and the voltage difference between the output voltage of the power factor correction circuit detected by the second detection circuit are obtained. The relationship between the power outage duration of the server power supply and the output capacitance of the power factor correction circuit is determined based on the input power consumption and the voltage difference. Adjust the output capacitor according to the aforementioned correspondence to adjust the power outage duration of the server power supply to the first power outage duration.

2. The method according to claim 1, characterized in that, The step of acquiring the input power consumption of the server power supply detected by the first detection circuit includes: The output power consumption, output percentage, and power conversion efficiency of the server power supply are obtained by the first detection circuit. The input power consumption is determined based on the output power consumption, the output percentage, and the conversion efficiency.

3. The method according to claim 2, characterized in that, Determining the input power consumption based on the output power consumption, the output percentage, and the conversion efficiency includes: The input power consumption Pin is determined by the following formula (1): Pin = Pout × Load / η Formula (1); Wherein, Pout is the output power consumption, Load is the output percentage, and η is the conversion efficiency.

4. The method according to claim 1, characterized in that, The step of obtaining the voltage difference of the output voltage of the power factor correction circuit detected by the second detection circuit includes: The highest output voltage value of the power factor correction circuit detected by the second detection circuit is obtained, as well as the lowest voltage value used to maintain the power output of the server. The difference between the highest voltage value and the lowest voltage value is defined as the voltage difference.

5. The method according to claim 1 or 4, characterized in that, Determining the relationship between the power outage duration of the server power supply and the output capacitance of the power factor correction circuit based on the input power consumption and the voltage difference includes: The relationship between the power outage duration T_holdup of the server power supply and the output capacitor C_bulk is determined by the following formula (2): T_holdup=C_bulk×ΔV^2 / (2×Pin) Formula (2); Where ΔV is the voltage difference and Pin is the input power consumption.

6. The method according to claim 5, characterized in that, If it is determined that the power outage duration of the server power supply needs to be adjusted, the method further includes: Determine the correspondence between the power outage duration of the server power supply and the output voltage of the power factor correction circuit of the power supply; Adjust the output voltage of the power factor correction circuit according to the aforementioned correspondence to adjust the power outage duration of the server power supply to the second power outage duration.

7. The method according to claim 6, characterized in that, Determining the correspondence between the power outage duration of the server power supply and the output voltage of the power factor correction circuit includes: Based on the above formula (2), the following formula (3) is determined, wherein the formula (3) is used to indicate the correspondence between the power outage holding time T_holdup of the server power supply and the output voltage Pout of the power factor correction circuit of the power supply: T_holdup=C_bulk×(1-C_error)×(Vbulk_high^2-Vbulk_low^2)×η / (2×Pout× Load) formula (3); Wherein, C_error is the error value of the output capacitor, Vbulk_high is the highest output voltage value of the power factor correction circuit, and Vbulk_low is the lowest voltage value used to maintain the server power output.

8. The method according to claim 6, characterized in that, The step of adjusting the output voltage of the power factor correction circuit according to the corresponding relationship to adjust the power outage duration of the server power supply to the second power outage duration includes: The target output voltage is determined, wherein, when the output voltage of the power factor correction circuit is the target output voltage, the power outage duration of the server power supply is maintained at the second power outage duration. Based on the current input voltage of the power factor correction circuit and the correspondence between the input voltage and output voltage of the power factor correction circuit, the duty cycle is adjusted to adjust the output voltage of the power factor correction circuit to the target output voltage.

9. The method according to claim 8, characterized in that, Before adjusting the duty cycle, the method further includes: The relationship between the input voltage Vin and the output voltage Vout of the power factor correction circuit is determined by the following formula (4): Vout = Vin / (1-D) Formula (4); Where D is the duty cycle.

10. The method according to claim 8, characterized in that, Before adjusting the duty cycle, the method further includes: Obtain the current input voltage of the power factor correction circuit detected by the third detection circuit.

11. The method according to claim 10, characterized in that, The third detection circuit includes a first resistor and a second resistor. The first end of the first resistor is connected to the input voltage detection terminal of the power factor correction circuit. The second end of the first resistor is connected to the target pin of the microprocessor and the first end of the second resistor. The second end of the second resistor is grounded.

12. The method according to claim 11, characterized in that, The first resistor includes a first sub-resistor and a second sub-resistor, wherein the resistance values ​​of the first sub-resistor and the second sub-resistor are both 499KΩ, and the resistance value of the second resistor is 5.57KΩ.

13. The method according to claim 1, characterized in that, Adjusting the output capacitor according to the aforementioned correspondence includes: According to the aforementioned correspondence, select the capacitor branch to be connected from a plurality of pre-configured capacitor connection branches to adjust the output capacitor.

14. The method according to claim 1, characterized in that, Adjusting the output capacitor according to the aforementioned correspondence includes: Adjust the voltage across the capacitor in the power factor correction circuit according to the aforementioned correspondence to adjust the input capacitor.

15. The method according to claim 2, characterized in that, The output power consumption is determined in the following way: It is determined based on the sum of the products of all DC output voltages and currents provided by the server power supply.

16. A device for adjusting the power outage duration, characterized in that, It is applied in a microprocessor, wherein the microprocessor is configured with multiple pairs of pins, wherein different pin pairs are connected to detection circuits configured to perform different detection functions; include: The first acquisition module is configured to acquire, when it is determined that the power outage duration of the server power supply needs to be adjusted, the input power consumption of the server power supply detected by the first detection circuit and the voltage difference between the output voltage of the power factor correction electrode circuit detected by the second detection circuit. The first determining module is configured to determine the correspondence between the power outage duration of the server power supply and the output capacitance of the power factor correction circuit based on the input power consumption and the voltage difference. The first adjustment module is configured to adjust the output capacitor according to the corresponding relationship, so as to adjust the power outage duration of the server power supply to the first power outage duration.

17. A microprocessor, characterized in that, include: The apparatus for adjusting the power outage duration as described in claim 16.

18. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 15.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 15.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 15.

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