Display panel and display apparatus

Abstract

The present disclosure belongs to the technical field of display. Provided are a display panel and a display apparatus. The display panel of the present disclosure comprises source driver integrated circuits, switching circuits, and at least two signal transmission lines, wherein each source driver integrated circuit comprises at least four level shifting sub-circuits and a driver sub-circuit; each level shifting sub-circuit comprises a first control end, a first input end and a first output end; each switching circuit comprises at least two second control ends, a second input end, and at least two second output ends; the at least four level shifting sub-circuits include at least two effective level shifting sub-circuits; for any signal transmission line, the signal transmission line is electrically connected to the first output end of at least one effective level shifting sub-circuit in the source driver integrated circuits; different signal transmission lines are electrically connected to different effective level shifting sub-circuits; and one signal transmission line is electrically connected to one of the second control ends of the switching circuits, and different signal transmission lines are electrically connected to different second control ends.

Description

Display panel and display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel and a display device. Background Technology

[0002] With the rapid development of the display industry, the resolution of display panels is constantly improving. For example, the current Full High Definition (FHD) resolution is 1920×1080, and the Ultra High Definition (UHD) resolution is 3840x2160, or even higher resolution displays.

[0003] Taking a resolution of 3840×2160 as an example, the number of data lines in the display panel is 3840×3=11520, where "3840" represents the number of pixels in a row, and "3" represents the number of sub-pixels (red sub-pixel R, green sub-pixel G, and blue sub-pixel B) included in one pixel. Assuming a source driver IC (SDIC) has 1920 output channels, six SDICs are needed to drive all the sub-pixels in the entire display panel. However, in actual operation, driving six SDICs simultaneously leads to numerous disadvantages, such as higher product costs, more complex manufacturing processes, and difficulty in achieving UHD resolution in small-sized display panels. Summary of the Invention

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a display panel and a display device.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of this disclosure is a display panel, including a substrate, a plurality of source driving circuits disposed on the substrate, a switching circuit corresponding to each of the source driving circuits, and at least two signal transmission lines; the source driving circuit includes at least four level conversion sub-circuits and driving sub-circuits; the level conversion sub-circuit includes a first control terminal, a first input terminal, and a first output terminal; the switching circuit includes at least two second control terminals, a second input terminal, and at least two second output terminals.

[0006] At least two of the four level-shifting sub-circuits are active level-shifting sub-circuits;

[0007] For any one of the signal transmission lines, it is electrically connected to the first output terminal of at least one of the effective level conversion sub-circuits in each of the source drive circuits; the effective level conversion sub-circuits electrically connected to different signal transmission lines are different.

[0008] One of the signal transmission lines is electrically connected to one of the second control terminals of each of the switching circuits, and the second control terminals electrically connected to different signal transmission lines are different.

[0009] The effective level conversion sub-circuit is configured to adjust the first signal received at the first input terminal to a second signal in response to the enable signal input at the first control terminal, and output the signal through the first output terminal.

[0010] The driving sub-circuit is configured to output a data signal;

[0011] The switching circuit is configured to respond to a second signal input to the second control terminal and output the data signal received at the second input terminal through the second output terminal.

[0012] In some embodiments, the switching circuit includes M switching transistors; M is an integer greater than or equal to 2; the number of switching transistors is the same as the number of signal transmission lines;

[0013] For the switching circuit, one of the switching transistors is electrically connected to one of the signal transmission lines, and different switching transistors are electrically connected to different signal transmission lines.

[0014] In some embodiments, the switching circuit includes a first switching transistor and a second switching transistor; the signal transmission line includes a first transmission line and a second transmission line; the display panel also includes multiple data lines.

[0015] The first electrode of the first switching transistor is electrically connected to the second input terminal, the second electrode is electrically connected to a data line, and the control electrode is electrically connected to the first transmission line.

[0016] The first electrode of the second switching transistor is electrically connected to the second input terminal, the second electrode is electrically connected to another data line, and the control electrode is electrically connected to the second transmission line.

[0017] In some embodiments, the orthographic projection of the switching circuit on the substrate is located between the orthographic projection of the source driving circuit on the substrate and the orthographic projection of the signal transmission line on the substrate.

[0018] Multiple source drive circuits are arranged side by side along a first direction; the signal transmission line extends in the first direction; the source drive circuit includes four level conversion sub-circuits, which are divided into two groups of sub-circuits, and each group of sub-circuits includes two level conversion sub-circuits.

[0019] The orthographic projections of the two sets of sub-circuit groups on the substrate are respectively located on two opposite sides of the orthographic projection of the driving sub-circuit on the substrate in the first direction.

[0020] In some embodiments, for any of the source drive circuits, the level conversion sub-circuits in at least one group of the sub-circuits are all effective level conversion sub-circuits;

[0021] The effective level conversion sub-circuit in the same sub-circuit group is electrically connected to different signal transmission lines.

[0022] In some embodiments, for any of the source drive circuits, the two sets of sub-circuit groups include a first sub-circuit group and a second sub-circuit group;

[0023] All level conversion sub-circuits in the first sub-circuit group are effective level conversion sub-circuits;

[0024] All the level conversion sub-circuits in the second sub-circuit group are invalid level conversion sub-circuits.

[0025] In some embodiments, for any of the source drive circuits, the level conversion sub-circuits in both sets of sub-circuits are the effective level conversion sub-circuits.

[0026] In some embodiments, for a portion of the source drive circuit, all level conversion sub-circuits in one group of sub-circuits are active level conversion sub-circuits; for another portion of the source drive circuit, all level conversion sub-circuits in both groups of sub-circuits are active level conversion sub-circuits.

[0027] The effective level conversion sub-circuit in the same sub-circuit group is electrically connected to different signal transmission lines.

[0028] In some embodiments, the source drive circuit includes N, where N is an integer greater than or equal to 2; the two sets of sub-circuit groups include a first sub-circuit group and a second sub-circuit group;

[0029] For the i-th source drive circuit, all level conversion sub-circuits in the first sub-circuit group are valid level conversion sub-circuits; all level conversion sub-circuits in the second sub-circuit group are invalid level conversion sub-circuits; the orthographic projection of the first sub-circuit group on the substrate is located on the side of the orthographic projection of the second sub-circuit group on the substrate away from the (i+1)-th source drive circuit; where i is an odd number from 1 to (N-1);

[0030] For the (i+1)th source drive circuit, the level conversion sub-circuits in the first sub-circuit group and the second sub-circuit group are all effective level conversion sub-circuits;

[0031] When N is an odd number, for the Nth source drive circuit, all level conversion sub-circuits in the first sub-circuit group are invalid level conversion sub-circuits; all level conversion sub-circuits in the second sub-circuit group are valid level conversion sub-circuits.

[0032] In some embodiments, the display panel further includes signal leads that correspond one-to-one with the first output terminal; the first output terminal is electrically connected to a signal transmission line through the corresponding signal lead;

[0033] The orthographic projection of the signal lead on the substrate is located on one of the two opposite sides of the orthographic projection of the switching circuit on the substrate in a first direction, and does not overlap with the orthographic projection of the switching circuit on the substrate.

[0034] In some embodiments, the level conversion sub-circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first amplifier, and a second amplifier;

[0035] The first electrode of the first transistor is electrically connected to the first input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first control terminal.

[0036] The first electrode of the second transistor is electrically connected to the second node, the second electrode is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the first node;

[0037] The first electrode of the third transistor is electrically connected to the second power supply terminal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth node.

[0038] The first electrode of the fourth transistor is electrically connected to the second power supply terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the third node.

[0039] The first electrode of the fifth transistor is electrically connected to the fourth node, the second electrode is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the output terminal of the first amplifier.

[0040] The input terminal of the first amplifier is electrically connected to the first node;

[0041] The input terminal of the second amplifier is electrically connected to the second node, and the output terminal is electrically connected to the first output terminal.

[0042] In some embodiments, the display panel further includes a timing control circuit; the timing control circuit includes a third output terminal, and the first input terminal of each of the effective level conversion sub-circuits is electrically connected to the third output terminal;

[0043] The timing control circuit is configured to output the first signal through the third output terminal.

[0044] In some embodiments, the timing control circuit further includes at least one fourth output terminal; the fourth output terminal is electrically connected to the first control terminal of the effective level conversion sub-circuit.

[0045] The timing control circuit is further configured to output the enable signal through the fourth output terminal to control whether the effective level conversion sub-circuit outputs the second signal.

[0046] In some embodiments, the source drive circuit includes W, where W is an integer greater than or equal to 3; the two sets of sub-circuit groups include a first sub-circuit group and a second sub-circuit group; the level conversion sub-circuit in the first sub-circuit group and the second sub-circuit group are all effective level conversion sub-circuits;

[0047] The fourth output terminal includes four; the signal transmission line includes a first transmission line and a second transmission line.

[0048] For the effective level conversion sub-circuit electrically connected to the first transmission line, a first control terminal in the first sub-circuit group of the first source drive circuit and a first control terminal in the second sub-circuit group of the Nth source drive circuit are both electrically connected to the first fourth output terminal.

[0049] For the effective level conversion sub-circuit electrically connected to the first transmission line, one of the first control terminals in the second sub-circuit group of the first source drive circuit, one of the first control terminals in the first sub-circuit group of the Nth source drive circuit, and two of the first control terminals in the kth source drive circuit are all electrically connected to the second fourth output terminal, where k is an integer from 2 to (N-1).

[0050] For the effective level conversion sub-circuit electrically connected to the second transmission line, the other first control terminal in the first sub-circuit group of the first source drive circuit and the other first control terminal in the second sub-circuit group of the Nth source drive circuit are both electrically connected to the third fourth output terminal.

[0051] For the effective level conversion sub-circuit electrically connected to the second transmission line, the other first control terminal in the second sub-circuit group of the first source drive circuit, the other first control terminal in the first sub-circuit group of the Nth source drive circuit, and the other two first control terminals of the kth source drive circuit are all electrically connected to the fourth output terminal.

[0052] In some embodiments, the fourth output terminal is connected to the first control terminal in a one-to-one correspondence.

[0053] In some embodiments, the source drive circuit includes four effective level conversion sub-circuits; the fourth output terminal includes four; and the signal transmission line includes a first transmission line and a second transmission line.

[0054] For each effective level conversion sub-circuit electrically connected to the first transmission line, one of the first control terminals in each of the source drive circuits is electrically connected to the first fourth output terminal; the other first control terminal in each of the source drive circuits is electrically connected to the second fourth output terminal.

[0055] For each of the effective level conversion sub-circuits electrically connected to the second transmission line, one of the first control terminals of each of the source drive circuits is electrically connected to the third fourth output terminal; and the other of the first control terminals of each of the source drive circuits is electrically connected to the fourth fourth output terminal.

[0056] In some embodiments, the display panel further includes a main control circuit; the main control circuit includes a fifth output terminal, and the first control terminal of each of the effective level conversion sub-circuits is electrically connected to the fifth output terminal;

[0057] The main control circuit is configured to output the enable signal through the fifth output terminal to control whether the effective level conversion sub-circuit outputs the second signal.

[0058] Secondly, embodiments of this disclosure also provide a display device, including a display panel as described in any one of the first aspects. Attached Figure Description

[0059] Figure 1 is a schematic diagram of the circuit structure of a one-to-two switching circuit;

[0060] Figure 2 is a schematic diagram of a display panel;

[0061] Figure 3 shows the waveform of the second signal at the position of the dashed line in the structure test of Figure 2;

[0062] Figure 4 is a schematic diagram of a display panel provided in an embodiment of this disclosure;

[0063] Figure 5 is a schematic diagram of the signal flow in the circuit provided in the embodiment of this disclosure;

[0064] Figure 6 is a schematic diagram of the specific structure of the switching circuit provided in the embodiment of this disclosure;

[0065] Figure 7 is a schematic diagram of a display driving circuit provided in an embodiment of this disclosure;

[0066] Figure 8 is a schematic diagram showing the position distribution of the level conversion sub-circuit in the source drive circuit according to an embodiment of this disclosure;

[0067] Figure 9 is a schematic diagram showing the positional distribution of an effective level conversion sub-circuit when there are three source drive circuits provided in the embodiments of this disclosure.

[0068] Figure 10 is a schematic diagram showing the positional distribution of another effective level conversion sub-circuit when three source drive circuits are provided in the embodiments of this disclosure.

[0069] Figure 11 shows the waveform of the second signal at the position of the dashed line in the structural test of Figure 10;

[0070] Figure 12 is a schematic diagram showing the positional distribution of another effective level conversion sub-circuit when there are three source drive circuits provided in the embodiments of this disclosure.

[0071] Figure 13 is a detailed circuit structure diagram of the level conversion sub-circuit provided in the embodiment of this disclosure;

[0072] Figure 14 is a schematic diagram of the electrical connection between the timing control circuit and the first input terminal of the effective level conversion sub-circuit provided in the embodiment of this disclosure;

[0073] Figures 15a to 15d are schematic diagrams of the electrical connection between a timing control circuit and a first control terminal of an effective level conversion sub-circuit provided in an embodiment of the present disclosure.

[0074] Figure 16 is a schematic diagram of the electrical connection between the first control terminal of another timing control circuit and the effective level conversion sub-circuit provided in an embodiment of this disclosure;

[0075] Figure 17 is a schematic diagram of the electrical connection between the first control terminal of a timing control circuit and an effective level conversion sub-circuit provided in another embodiment of the present disclosure.

[0076] Figure 18 is a schematic diagram of the electrical connection between the first control terminal of a timing control circuit and an effective level conversion sub-circuit provided in another embodiment of the present disclosure.

[0077] Figure 19 is a schematic diagram of the electrical connection between the sub-pixels of the display panel and the source driving circuit provided in the embodiment of this disclosure. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0079] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0080] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0081] Taking an ultra-high definition (UHD) resolution of 3840×2160 as an example, a display panel needs to integrate six SDICs simultaneously to drive all sub-pixels within the entire display panel. However, in the actual operation of the display panel, the six SDICs significantly increase the cost of the product, such as the cost of various materials, components, and raw materials required for the product or project. At the same time, the more SDICs there are, the more bonding processes are involved, resulting in a significant loss in factory yield. Furthermore, for small-sized display panels, such as 14-inch and 13.3-inch panels and smaller, the bottom bezel space cannot accommodate six SDICs, making it difficult to achieve UHD resolution for these sizes.

[0082] As shown in Figure 1, a one-to-two design scheme of the switching circuit (MUX) 2 can be adopted to split one output channel of the source drive circuit (SDIC) 1 into two branches, which are electrically connected to different data lines in the display panel (such as data line Data1 and data line Data2). This can reduce the number of source drive circuits 1 by half. Taking the ultra-high definition (UHD) resolution of 3840×2160 as an example, only 3 source drive circuits 1 are needed to meet the driving conditions, thereby reducing product costs and making the circuit structure of the display panel simpler, which is conducive to achieving ultra-high definition (UHD) resolution in small-sized display panels.

[0083] Figure 2 shows a schematic diagram of a display panel. The display panel includes Q source drive circuits 1, a switching circuit 2 corresponding to each source drive circuit 1, and two signal transmission lines 3. The two signal transmission lines 3 are respectively referred to as the first transmission line 31 and the second transmission line 32. The source drive circuit 1 includes four level conversion sub-circuits 11 and a drive sub-circuit 12. The level conversion sub-circuit 11 includes a first control terminal 11a, a first input terminal 11b, and at least one first output terminal 11c. The switching circuit 2 includes at least one second control terminal 2a, a second input terminal 2b, and at least one second output terminal 2c.

[0084] The four level-shifting sub-circuits 11 in the first and Qth source driver circuits 1 are divided into two groups of sub-circuits, respectively located on the left and right sides of the driver sub-circuit 12. Each group of sub-circuits includes two level-shifting sub-circuits 11. In one group, the level-shifting sub-circuits 11 are active level-shifting sub-circuits 110, and in the other group, they are inactive level-shifting sub-circuits 111. For example, the level-shifting sub-circuit 11 closer to the left is active level-shifting sub-circuit 110, and the level-shifting sub-circuit 11 closer to the right is inactive level-shifting sub-circuit 111. Q is an integer greater than or equal to 2. The level-shifting sub-circuits 11 in the second to (Q-1)th source driver circuits 1 are all inactive level-shifting sub-circuits 111. In this context, "effective level conversion sub-circuit 110" refers to a level conversion sub-circuit 11 electrically connected to the switching circuit 2, used to transmit signals to the switching circuit 2; "ineffective level conversion sub-circuit 111" refers to a level conversion sub-circuit 11 not electrically connected to the switching circuit 2, where all ports of the ineffective level conversion sub-circuit 111, such as the first control terminal 11a, the first input terminal 11b, and the first output terminal 11c, are either in a floating state or a grounded state. Simply put, only the level conversion sub-circuit 11 in the leftmost group of sub-circuits of the leftmost source drive circuit 1 and the level conversion sub-circuit 11 in the rightmost group of sub-circuits of the rightmost source drive circuit 1 are effective on the aforementioned display panel.

[0085] It should be noted that in the actual production process of SDIC, it is mass-produced, so the circuit structure of each source drive circuit 1 is the same, without distinction between effective and invalid. Only in the subsequent manufacturing or assembly process of the display panel will the specific effective level conversion sub-circuit 11 and the invalid level conversion sub-circuit 11 be defined.

[0086] The first output terminal 11c of an effective level conversion sub-circuit 110 in the first source driver circuit 1 and the first output terminal 11c of an effective level conversion sub-circuit 110 in the Qth source driver circuit 1 are both electrically connected to the first transmission line 31; the first output terminal 11c of another effective level conversion sub-circuit 110 in the first source driver circuit 1 and the first output terminal 11c of another effective level conversion sub-circuit 110 in the Qth source driver circuit 1 are both electrically connected to the second transmission line 32. One second control terminal 2a in each switch circuit 2 is electrically connected to the first transmission line 31; the other second control terminal 2a in each switch circuit 2 is electrically connected to the second transmission line 32. The effective level conversion sub-circuit 110 is configured to adjust the first signal V1 received at the first input terminal 11b to a second signal V2 in response to the enable signal EN input at the first control terminal 11a, and output it through the first output terminal 11c. The driver sub-circuit 12 is configured to output a data signal D0. The switching circuit 2 is configured to output the data signal D0 received at the second input terminal 2b through the second output terminal 2c in response to the second signal V2 input at the second control terminal 2a.

[0087] Since the middle source drive circuit 1 (the 2nd to (Q-1)th source drive circuit 1) is not electrically connected to the signal transmission line 3, the middle switch circuit 2 (the 2nd to (Q-1)th switch circuit 2) is switched on and off by receiving the second signal V2 provided by the effective level conversion sub-circuit 110 from the 1st source drive circuit 1 and the Qth source drive circuit 1, as shown in Figure 2, and its current flow gradually passes from both sides to the middle.

[0088] Under low load (or high power consumption), the aforementioned display panel has no adverse effect on the final displayed image. However, under high load (or high power consumption), using the same display panel will result in a darkened center display, affecting the quality of the displayed image. This is because under high load, the rising or falling edge of the waveform of the second signal V2 in the middle of signal transmission line 3 is severely distorted, meaning the transition delay time is long, as shown in Figure 3. Measuring the waveform of the second signal V2 at the position indicated by the dotted line in Figure 2, the transition delay time reaches 830 nanoseconds (ns). This leads to insufficient charging of the pixel driving circuit data signal D0 (data signal) in the middle area of ​​the display panel, resulting in the darkened center display of the display panel under high load.

[0089] In view of this, the present disclosure provides a display panel that adopts a design scheme of one-to-many switching circuits, which simplifies the display panel and reduces costs; at the same time, it solves the problem of the display panel's central display effect being dim under high load.

[0090] As shown in Figure 4, the display panel includes a substrate, a plurality of source drive circuits 1 disposed on the substrate, a switching circuit 2 corresponding to each source drive circuit 1, and at least two signal transmission lines 3. The display panel has a display area AA and a peripheral area BB surrounding the display area AA. Optionally, the plurality of source drive circuits 1, the switching circuit 2 corresponding to each source drive circuit 1, and the at least two signal transmission lines 3 are all located on one side of the peripheral area BB, and the orthographic projection of the switching circuit 2 on the substrate is located between the orthographic projection of the source drive circuit 1 on the substrate and the orthographic projection of the signal transmission line 3 on the substrate.

[0091] The source drive circuit 1 includes at least four level conversion sub-circuits 11 and a drive sub-circuit 12; the level conversion sub-circuit 11 includes a first control terminal 11a, a first input terminal 11b, and a first output terminal 11c; the switch circuit 2 includes at least two second control terminals 2a, a second input terminal 2b, and at least two second output terminals 2c. At least two of the at least four level conversion sub-circuits 11 include at least two active level conversion sub-circuits 110; for any signal transmission line 3, it is electrically connected to the first output terminal 11c of at least one active level conversion sub-circuit 110 in each source drive circuit 1; different signal transmission lines 3 are electrically connected to different active level conversion sub-circuits 110; a signal transmission line 3 is electrically connected to one of the second control terminals 2a of each switch circuit 2, and different signal transmission lines 3 are electrically connected to different second control terminals 2a.

[0092] For the source drive circuit 1 and the corresponding switch circuit 2, the first output terminal 11c of the effective level conversion sub-circuit 110 is electrically connected to a second control terminal 2a in the switch circuit 2 via a signal transmission line 3, and provides a second signal V2 to the second control terminal 2a to control the switch circuit 2 to open and transmit the data signal D0 externally. A second output terminal 2c is electrically connected to a data line (not shown in the figure) to provide the data signal D0 to the data line.

[0093] Each source drive circuit 1 includes at least four level conversion sub-circuits 11. For example, three source drive circuits 1 include at least twelve level conversion sub-circuits 11.

[0094] Optionally, as shown in Figure 4, the source drive circuit 1 includes four level conversion sub-circuits 11; if three source drive circuits 1 are provided, a total of twelve level conversion sub-circuits 11 are included. Each of the four level conversion sub-circuits 11 in the source drive circuit 1 includes at least two active level conversion sub-circuits 110, for example, two or four. Figure 4 illustrates this with two as an example.

[0095] Optionally, the number of second control terminals 2a in the switching circuit 2 is the same as the number of signal transmission lines 3.

[0096] Optionally, as shown in Figure 4, the display panel includes two signal transmission lines 3, denoted as the first transmission line 31 and the second transmission line 32, respectively. The first transmission line 31 is electrically connected to the first output terminal 11c of one effective level conversion sub-circuit 110 in each source drive circuit 1; the second transmission line 32 is electrically connected to the first output terminal 11c of the other effective level conversion sub-circuit 110 in each source drive circuit 1. The switching circuit 2 includes two second control terminals 2a; the first transmission line 31 is electrically connected to one of the second control terminals 2a in each switching circuit 2; the second transmission line 31 is electrically connected to the other second control terminal 2a in each switching circuit 2.

[0097] As shown in Figure 5, the effective level conversion sub-circuit 110 is configured to adjust the first signal V1 received at the first input terminal 11b to the second signal V2 in response to the enable signal EN input at the first control terminal 11a, and output it through the first output terminal 11c; the drive sub-circuit 12 is configured to output the data signal D0; and the switch circuit 2 is configured to output the data signal D0 received at the second input terminal 2b through the second output terminal 2c in response to the second signal V2 input at the second control terminal 2a.

[0098] As shown in Figure 5, the driving sub-circuit 12 includes a data input terminal 12a and a data output terminal 12b. The data input terminal 12a receives image data, which is then processed by the logic within the driving sub-circuit 12, and a data signal D0 is output through the data output terminal 12b. This data signal D0 represents the image data to be displayed on the display panel. The data output terminal 12b is electrically connected to the second input terminal 2b of the switching circuit 2.

[0099] The first control terminal 11a receives the enable signal EN, and the first input terminal 11b receives the first signal V1. The effective level conversion sub-circuit 110 responds to the enable signal EN and begins to adjust the received first signal V1, for example, by pulling it high or low, to obtain the second signal V2. The first output terminal 11c is electrically connected to the signal transmission line 3, and the second signal V2 is output through the first output terminal 11c and transmitted to the second control terminal 2a of the switching circuit 2 through the signal transmission line 3.

[0100] The second control terminal 2a receives the second signal V2, and the second input terminal 2b receives the data signal D0. In response to the second signal V2, the switching circuit 2 closes its internal switch, outputting the data signal D0 through the second output terminal 2c. The second output terminal 2c is electrically connected to the data lines in the display panel to provide the data signal D0 to the data lines, thereby driving the sub-pixels of the display panel to display the image.

[0101] In this embodiment of the disclosure, each source drive circuit 1 includes at least four level conversion sub-circuits 11. For example, three source drive circuits 1 include at least twelve level conversion sub-circuits 11. The at least four level conversion sub-circuits 11 include at least two active level conversion sub-circuits 110, which means that three source drive circuits 1 include at least six active level conversion sub-circuits 110, or even more. Any signal transmission line 3 is electrically connected to at least one effective level conversion sub-circuit 110 in each source drive circuit 1, and the effective level conversion sub-circuits 110 electrically connected to different signal transmission lines 3 are different. Since multiple source drive circuits 1 are arranged side by side along the first direction X, the effective level conversion sub-circuits 110 on multiple source drive circuits 1 are arranged side by side along the first direction X. The first output terminal 11c on it is electrically connected to the signal transmission line 3 nearby, so that the access points of different second signals V2 connected to the signal transmission line 3 are different. Each access point has a second control terminal 2a that is closest to it, that is, the second control terminal 2a on the switch circuit 2 corresponding to the source drive circuit 1 connected to the access point. The second signal V2 introduced from the access point will enter the second control terminal 2a that is closest to it the fastest. In this embodiment, each second control terminal 2a is provided with a corresponding and closest access point (or effective level conversion sub-circuit 110), thereby quickly providing the second control terminal 2a with the second signal V2, causing the switch in the switching circuit 2 to close and conduct rapidly, so as to quickly output the data signal D0 through the second output terminal 2c to the data line on the display panel. This greatly reduces the waveform delay phenomenon of the second signal V2 at the middle position of the signal transmission line 3, effectively solves the problem of insufficient charging of the pixel driving circuit data signal D0 (data signal), and thus eliminates the bad phenomenon of the display panel dimming under high load.

[0102] Compared to the technical solution shown in Figure 2, where only the level conversion sub-circuit 11 in the leftmost group of sub-circuits of the leftmost source drive circuit 1 and the level conversion sub-circuit 11 in the rightmost group of sub-circuits of the rightmost source drive circuit 1 are effective, in this embodiment, each source drive circuit 1 includes at least one effective level conversion sub-circuit 110, and the signal transmission line 3 is electrically connected to one of the first output terminals 11c of each effective level conversion sub-circuit 110, so that the access points of the signal transmission line 3 are expanded to at least n, where n is the number of source drive circuits 1, thereby improving the transmission speed of the second signal V2 on the signal transmission line 3, and shortening the time for each second control terminal 2a to receive the second signal V2, greatly reducing the waveform delay phenomenon of the second signal V2 in the middle position of the signal transmission line 3, and solving the problem of the dark display effect in the middle of the display panel under high load.

[0103] In some embodiments, as shown in FIG6, the switching circuit 2 includes M switching transistors T0; the signal transmission lines 3 include M lines; where M is an integer greater than or equal to 2; for the switching circuit 2, one switching transistor T0 is electrically connected to one signal transmission line 3, and different switching transistors T0 are electrically connected to different signal transmission lines 3. For example, the switching circuit 2 adopts a one-to-two design scheme, in which case M can be 2, the switching circuit 2 includes 2 switching transistors T0; the signal transmission lines 3 include 2 lines, respectively denoted as the first transmission line 31 and the second transmission line 32.

[0104] The display panel also includes multiple data lines (Data). The data lines (Data) are located in the display area AA and extend to the peripheral area BB, where they are electrically connected to the second terminal of the switching transistor T0. They are used to transmit data signals (D0) to the pixel driving circuit to drive the sub-pixels for image display.

[0105] In this embodiment, a corresponding signal transmission line 3 is set for each data signal D0 transmission path (i.e., each switching transistor T0) in the switching circuit 2, which improves the stability of the second signal V2 on the signal transmission line 3 under high load and ensures that each switching transistor T0 responds to its received second signal V2 and turns on synchronously.

[0106] Optionally, the switching circuit 2 includes a plurality of switching transistors T0, which are arranged side by side along a first direction X.

[0107] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between their source and drain. In the embodiments of this disclosure and the following description, to distinguish the source and drain of the transistor, one of them is called the first electrode, the other is called the second electrode, and the gate is called the control electrode. In addition, according to the characteristics of the transistor, transistors can be divided into N-type and P-type. Among them, N-type thin-film transistors refer to those with N-type ion doping in the active layer of the thin-film transistor; P-type thin-film transistors refer to those with P-type ion doping in the active layer of the thin-film transistor. The operating level signal of N-type thin-film transistors is a high-level signal; the operating level signal of P-type thin-film transistors is a low-level signal. Taking the switching transistor T0 as a P-type thin-film transistor as an example, the effective level conversion sub-circuit 110 pulls the first signal V1 high to the second signal V2, where the first signal V1 is a low-level signal and the second signal V2 is a high-level signal. Then, the switching transistor T0 turns on in response to the high-level signal and outputs the data signal D0 through the second output terminal 2c. Taking an N-type thin-film transistor as an example, the effective level conversion sub-circuit 110 pulls the first signal V1 low to the second signal V2, where the first signal V1 is a high-level signal and the second signal V2 is a low-level signal. Then, the switching transistor T0 turns on in response to the low-level signal and outputs the data signal D0 through the second output terminal 2c. In the following embodiments, a P-type thin-film transistor is used as an example for the switching transistor T0, but this disclosure is not limited to P-type thin-film transistors and can also be an N-type thin-film transistor.

[0108] In some embodiments, as shown in FIG7, the switching circuit 2 includes a first switching transistor T01 and a second switching transistor T02; the signal transmission line 3 includes two lines, referred to as the first transmission line 31 and the second transmission line 32, respectively; wherein, the first electrode of the first switching transistor T01 is electrically connected to the second input terminal 2b, the second electrode is electrically connected to a data line Data1, and the control electrode is electrically connected to a signal transmission line 3 (such as the first transmission line 31); the first electrode of the second switching transistor T02 is electrically connected to the second input terminal 2b, the second electrode is electrically connected to another data line Data2, and the control electrode is electrically connected to another signal transmission line 3 (such as the second transmission line 32). Here, the first electrode of the first switching transistor T01 and the second electrode of the second switching transistor T02 are connected in series.

[0109] The first transmission line 31 is electrically connected to the control electrode of the first switching transistor T01; the second transmission line 32 is electrically connected to the control electrode of the second switching transistor T02; in response to the second signal V2 provided by the first transmission line 31, the first and second electrodes of the first switching transistor T01 are turned on, and the data signal D0 is output through the second output terminal 2c. In response to the second signal V2 provided by the second transmission line 32, the first and second electrodes of the second switching transistor T02 are turned on, and the data signal D0 is output through another second output terminal 2c.

[0110] In addition to the above-mentioned one-to-two design scheme, the number of switching transistors T0 in the switching circuit 2 can also be adjusted according to the actual resolution of the display panel. For example, the switching circuit 2 can also adopt a one-to-three, one-to-four, one-to-five, or one-to-six design scheme, etc., and the principle is the same as the one-to-two design scheme described above. These will not be listed one by one in the embodiments disclosed herein.

[0111] In some embodiments, as shown in FIG8, multiple source drive circuits 1 are arranged side by side along the first direction X; the extension direction of the signal transmission line 3 is the first direction X; the source drive circuit 1 includes four level conversion sub-circuits 11, which are divided into two groups of sub-circuit groups 100, each group of sub-circuit groups 100 including two level conversion sub-circuit groups 11; the orthographic projections of the two groups of sub-circuit groups 100 on the substrate are respectively located on two opposite sides of the orthographic projection of the drive sub-circuit 12 on the substrate in the first direction X, so that the subsequent signal lead 4 can bypass the switching circuit 2 and be electrically connected to the signal transmission line 3, avoiding unnecessary parasitic capacitance and affecting signal transmission.

[0112] Taking three source driver circuits 1 as an example, if only one set of sub-circuit groups 100 in each source driver circuit 1 has a valid level conversion sub-circuit 110, then the three source driver circuits 1 include three valid sub-circuit groups 100. If two sets of sub-circuit groups 100 in each source driver circuit 1 have valid level conversion sub-circuit 110, then the three source driver circuits 1 include six valid sub-circuit groups 100. If two sets of sub-circuit groups 100 in one source driver circuit 1 have valid level conversion sub-circuit 110, one set of sub-circuit groups 100 in one source driver circuit 1 has a valid level conversion sub-circuit 110, and one set of sub-circuit groups 100 in the last source driver circuit 1 has a valid level conversion sub-circuit 110, then the three source driver circuits 1 include four valid sub-circuit groups 100. If the level conversion sub-circuit 11 in both sub-circuit groups 100 of the two source drive circuits 1 are both effective level conversion sub-circuit 110, and the level conversion sub-circuit 11 in one sub-circuit group 100 of one source drive circuit 1 is effective level conversion sub-circuit 110, then the three source drive circuits 1 include five effective sub-circuit groups 100.

[0113] In some embodiments, as shown in FIG9 or FIG10, for any source drive circuit 1, at least one set of sub-circuit groups 100 has level conversion sub-circuits 11 that are all effective level conversion sub-circuits 110; the effective level conversion sub-circuits 110 in the same set of sub-circuit groups 100 are electrically connected to different signal transmission lines 3.

[0114] In some embodiments, as shown in FIG9, for any source drive circuit 1, the two sub-circuit groups 100 include a first sub-circuit group 1001 and a second sub-circuit group 1002; the level conversion sub-circuits 11 in the first sub-circuit group 1001 are all active level conversion sub-circuits 110; the level conversion sub-circuits 11 in the second sub-circuit group 1002 are all inactive level conversion sub-circuits 111. In FIG9, the first sub-circuit group 1001 is on the left and the second sub-circuit group is on the right, but of course, the first sub-circuit group 1001 can also be on the right and the second sub-circuit group is on the left.

[0115] The orthographic projection of the first sub-circuit group 1001 on the substrate is located on one of the two opposite sides of the orthographic projection of the driving sub-circuit 12 on the substrate in the first direction X. This facilitates bypassing the switching circuit 2 and electrically connecting it to the signal transmission line 3, avoiding unnecessary parasitic capacitance and affecting signal transmission.

[0116] Optionally, as shown in Figure 9, the display panel further includes signal leads 4 corresponding one-to-one with the first output terminal 11c; optionally, the extension direction of the signal leads 4 is the second direction Y, and the first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y. The first output terminal 11c is electrically connected to the signal transmission line 3 through the corresponding signal leads 4; the connection node between the signal leads 4 and the signal transmission line 3 is the first input node N1; the connection node between the second control terminal 2a and the signal transmission line 3 is the second input node N2. There is a second input node N2 between two adjacent first input nodes N1 on the signal transmission line 3. There is a first input node N1 between two adjacent second input nodes N2 on the signal transmission line 3.

[0117] Optionally, for the same signal transmission line 3, the distance between adjacent first input nodes N1 is equal; the distance between adjacent second input nodes N2 is equal.

[0118] In this embodiment, the first input nodes N1 on both sides of the second input node N2 introduce the second signal V2, and simultaneously transmit it towards the second input node N2 located in the middle. This allows the second signals V2 introduced by the two first input nodes N1 to quickly converge at the second input node N2, thereby quickly providing the second signal V2 to the second control terminal 2a corresponding to the second input node N2. This causes the switching transistor T0 to close and conduct rapidly, so as to quickly output the data signal D0 through the second output terminal 2c to the data line on the display panel. This greatly reduces the waveform delay phenomenon of the second signal V2 on the signal transmission line 3, effectively solves the problem of insufficient charging of the pixel driving circuit data signal D0 (data signal) in the display panel, and thus eliminates the bad phenomenon of the display panel dimming under high load.

[0119] In some embodiments, as shown in FIG10, for any source drive circuit 1, the level conversion sub-circuits 11 in both sub-circuit groups 100 are effective level conversion sub-circuits 110.

[0120] The orthographic projections of the first sub-circuit group 1001 and the second sub-circuit group 1002 on the substrate are located on opposite sides of the orthographic projection of the driving sub-circuit 12 on the substrate in the first direction X. This facilitates bypassing the switching circuit 2 and electrically connecting to the signal transmission line 3, avoiding unnecessary parasitic capacitance and affecting signal transmission.

[0121] Optionally, as shown in Figure 10, the display panel further includes signal leads 4 corresponding to the first output terminal 11c; the first output terminal 11c is electrically connected to the signal transmission line 3 through the corresponding signal leads 4; the connection node between the signal leads 4 and the signal transmission line 3 is the first input node N1; the connection node between the second control terminal 2a and the signal transmission line 3 is the second input node N2. The signal transmission line 3 includes multiple electrically connected sub-segments 30; each sub-segment 30 corresponds to the source drive circuit 1, and for any sub-segment 30, it includes two first input nodes N1 and a second input node N2 located between the two first input nodes N1. Specifically, for any sub-segment 30, it includes a first input node N1 connected to two effective level conversion sub-circuits 110 on the source drive circuit 1, and a second input node N2 connected to the switch circuit 2, and the second input node N2 is located between the two first input nodes N1.

[0122] In this embodiment, the signal transmission line 3 includes segments 30 that correspond one-to-one with the source drive circuit 1. The second input node N2 in this segment 30 is located between two first input nodes N1, and the distances to the two first input nodes N1 are approximately equal. The second signal V2 introduced from the first input node N1 will quickly enter the adjacent second input node N2. For any sub-segment 30, the second signals V2 introduced by the two first input nodes N1 are simultaneously transmitted towards the second input node N2 located in the middle position. This causes the second signals V2 introduced by the two first input nodes N1 to converge quickly at the second input node N2, thereby quickly providing the second signal V2 to the second control terminal 2a corresponding to the second input node N2. This causes the switching transistor T0 to close and conduct rapidly, so as to quickly output the data signal D0 through the second output terminal 2c to the data line on the display panel. This greatly reduces the waveform delay of the second signal V2 on the sub-segment 30. As shown in Figure 11, the waveform of the second signal V2 at the position of the dashed line in Figure 10 is measured, and its transition delay time is shortened to 340 nanoseconds (ns). Compared with the waveform of the second signal V2 at the position of the dashed line in the structure shown in Figure 2, this disclosure greatly reduces the waveform delay of the second signal V2, effectively solves the problem of insufficient charging of the pixel driving circuit data signal D0 (data signal) in the display panel, and thus eliminates the bad phenomenon of the display panel dimming under high load.

[0123] In some embodiments, as shown in FIG12, for a portion of the source drive circuit 1, all level conversion sub-circuits 11 in one group of sub-circuit groups 100 are effective level conversion sub-circuits 110; for another portion of the source drive circuit 1, all level conversion sub-circuits 11 in both groups of sub-circuit groups 100 are effective level conversion sub-circuits 110. The effective level conversion sub-circuits 110 in the same group of sub-circuit groups 100 are electrically connected to different signal transmission lines 3 (i.e., the first transmission line 31 and the second transmission line 32).

[0124] Optionally, the source drive circuit 1 includes N circuits, where N is an integer greater than or equal to 2. For example, N can be 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0125] As shown in Figure 12, the two sub-circuit groups 100 include a first sub-circuit group 1001 and a second sub-circuit group 1002. For the i-th source drive circuit 1, all level conversion sub-circuits 11 in the first sub-circuit group 1001 are valid level conversion sub-circuits 110; all level conversion sub-circuits 11 in the second sub-circuit group 1002 are invalid level conversion sub-circuits 111. The orthographic projection of the first sub-circuit group 1001 on the substrate is located at the orthographic projection of the second sub-circuit group 1002 on the substrate, away from the (i+1)-th source drive circuit. One side of path 1; where i is an odd number from 1 to (N-1); for the (i+1)th source drive circuit 1, the level conversion sub-circuits 11 in the first sub-circuit group 1001 and the second sub-circuit group 1002 are all valid level conversion sub-circuits 110; when N is an odd number, for the Nth source drive circuit 1, the level conversion sub-circuits 11 in the first sub-circuit group 1001 are all invalid level conversion sub-circuits 111; the level conversion sub-circuits 11 in the second sub-circuit group 1002 are all valid level conversion sub-circuits 110.

[0126] Taking N=3 as an example, in the first source drive circuit 1, all level conversion sub-circuits 11 in the first sub-circuit group 1001 are valid level conversion sub-circuits 110, and all level conversion sub-circuits 11 in the second sub-circuit group 1002 are invalid level conversion sub-circuits 111; in the second source drive circuit 1, all level conversion sub-circuits 11 in the first sub-circuit group 1001 and the second sub-circuit group 1002 are valid level conversion sub-circuits 110; in the third source drive circuit 1, all level conversion sub-circuits 11 in the first sub-circuit group 1001 are invalid level conversion sub-circuits 110, and all level conversion sub-circuits 11 in the second sub-circuit group 1002 are valid level conversion sub-circuits 111.

[0127] In this embodiment, by setting some level conversion sub-circuits 11 as effective level conversion sub-circuits 110 and the remaining level conversion sub-circuits 11 as ineffective effective level conversion sub-circuits 111, the waveform of the second signal under high power consumption can be improved to a certain extent. At the same time, it avoids increasing the power consumption of effective level conversion sub-circuits 110 when a large number of effective level conversion sub-circuits 110 are introduced, that is, saving the power consumption of the remaining level conversion sub-circuits.

[0128] Optionally, as shown in Figure 12, the display panel further includes signal leads 4 corresponding one-to-one with the first output terminal 11c; the first output terminal 11c is electrically connected to the signal transmission line 3 through the corresponding signal leads 4; the connection node between the signal leads 4 and the signal transmission line 3 is the first input node N1; the connection node between the second control terminal 2a and the signal transmission line 3 is the second input node N2. The first input node N1 connected to the effective level conversion sub-circuit 110 of the first source drive circuit 1 on the signal transmission line 3 is located on the side of the second input node N2 connected to the first switch circuit 2 on the signal transmission line 3, away from the side of the first input node N1 connected to the effective level conversion sub-circuit 110 of the second source drive circuit 1 on the signal transmission line 3. The second input node N2 connected to the second switch circuit 2 on the signal transmission line 3 is located between the two first input nodes N1 connected to the two effective level conversion sub-circuits 110 of the second source drive circuit 1 on the signal transmission line 3. The first input node N1, which is connected to the effective level conversion sub-circuit 110 of the third source drive circuit 1 on the signal transmission line 3, is located on the side away from the first input node N1, which is connected to the effective level conversion sub-circuit 110 of the second source drive circuit 1 on the signal transmission line 3 and the second input node N2, which is connected to the third switch circuit 2 on the signal transmission line 3.

[0129] In this embodiment, the first input nodes N1 on both sides of the second input node N2 introduce the second signal V2, and simultaneously transmit it towards the second input node N2 located in the middle. This allows the second signals V2 introduced by the two first input nodes N1 to converge quickly at the second input node N2, thereby quickly providing the second signal V2 to the second control terminal 2a corresponding to the second input node N2. This causes the switching transistor T0 to close and conduct rapidly, so as to quickly output the data signal D0 through the second output terminal 2c to the data line on the display panel. This greatly reduces the waveform delay phenomenon of the second signal V2 on the sub-segment 30, effectively solves the problem of insufficient charging of the pixel driving circuit data signal D0 (data signal) in the display panel, and thus eliminates the bad phenomenon of the display panel dimming under high load.

[0130] In some embodiments, as shown in Figures 9 to 12, the orthographic projection of the signal lead 4 on the substrate is located on one of the two opposite sides of the orthographic projection of the switch circuit 2 on the substrate in the first direction X, and does not overlap with the orthographic projection of the switch circuit 2 on the substrate. This can effectively avoid the switch circuit 2 and prevent the generation of parasitic capacitance between the signal lead 4 and the switch transistor T0 (active layer, control electrode, first electrode and second electrode), which would affect the transmission stability of the second signal V2.

[0131] In some embodiments, as shown in FIG13, the level conversion sub-circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first amplifier U1, and a second amplifier U2. The first transistor M1 has its first electrode electrically connected to the first input terminal 11b, its second electrode electrically connected to the first node P1, and its control electrode electrically connected to the first control terminal 11a; the second transistor M2 has its first electrode electrically connected to the second node P2, its second electrode electrically connected to the first power supply terminal VSS, and its control electrode electrically connected to the first node P1; the third transistor M3 has its first electrode electrically connected to the second power supply terminal VDD, its second electrode electrically connected to the third node P3, and its control electrode electrically connected to the fourth node P4; the fourth transistor M4 has its first electrode electrically connected to the second power supply terminal VDD, its second electrode electrically connected to the fourth node P4, and its control electrode electrically connected to the third node P3; the fifth transistor M5 has its first electrode electrically connected to the fourth node P4, its second electrode electrically connected to the first power supply terminal VSS, and its control electrode electrically connected to the output terminal of the first amplifier U1; the input terminal of the first amplifier U1 is electrically connected to the first node P1; the input terminal of the second amplifier U2 is electrically connected to the second node P2, and its output terminal is electrically connected to the first output terminal 11c.

[0132] The first transistor M1 turns on in response to the enable signal EN, writing the first signal V1 from the first input terminal 11b to the first node P. The first amplifier U1 is connected to a first reference voltage terminal, which provides a first reference signal VGL, i.e., a low-level signal, to the first amplifier U1. Using the first reference signal VGL, the first amplifier U1 is instructed to pull the first signal V1 low, for example, from 0V to -8V. The second amplifier U2 is connected to a second reference voltage terminal, which provides a second reference signal VGH, i.e., a high-level signal, to the second amplifier U2. Using the second reference signal VGH, the second amplifier U2 is instructed to pull the first signal V1 high, for example, from 0V to +8V.

[0133] In some embodiments, as shown in FIG14, the display panel further includes a timing control circuit 5 (TCON); the timing control circuit 5 includes a third output terminal 5a, and the first input terminal 11b of each effective level conversion sub-circuit 110 is electrically connected to the third output terminal 5a; the timing control circuit 5 is configured to output a first signal V1 through the third output terminal 5a.

[0134] In some embodiments, as shown in Figures 15a to 15d or Figure 16, the timing control circuit 5 further includes at least one fourth output terminal 5b; the fourth output terminal 5b is electrically connected to the first control terminal 11a of the effective level conversion sub-circuit 110; the timing control circuit 5 is also configured to output an enable signal EN through the fourth output terminal 5b to control whether the effective level conversion sub-circuit 110 outputs the second signal V2.

[0135] All level-shifting sub-circuits 11 in the source drive circuit 1 are active level-shifting sub-circuits 110. Optionally, in low-power mode, the timing control circuit 5 can control some active level-shifting sub-circuits 110 to pull the first signal V1 high to the second signal V2 and output it via the enable signal EN; at the same time, it controls another part of the active level-shifting sub-circuits 110 not to process the first signal V1 (i.e., no output or output of the first signal V1), or pull the first signal V1 lower. Optionally, in high-power mode, the timing control circuit 5 can control all active level-shifting sub-circuits 110 to pull the first signal V1 high to the second signal V2 via the enable signal EN. Optionally, different power consumption modes can be customized, and it is not limited to only low-power and high-power modes. In different power consumption modes, the timing control circuit 5 can analyze the complexity of the displayed screen and, according to the pre-set correspondence between the complexity and the power consumption mode, control at least part of the effective level conversion sub-circuit 110 to pull the first signal V1 high to the second signal V2 through the enable signal EN. The remaining part of the effective level conversion sub-circuit 110 does not process the first signal V1, or pulls the first signal V1 lower.

[0136] For example, the enable signal EN can be a square wave signal, where a low level is an active level that controls the active level conversion sub-circuit 110 to output a second signal V2, and a high level is an inactive level that controls the active level conversion sub-circuit 110 to have no output, or output a first signal V1, or output a signal with a lower level than the first signal V1.

[0137] In this embodiment, the timing control circuit 5 controls whether the effective level conversion sub-circuit 110 outputs the second signal V2, thereby achieving dynamic adjustment between low power consumption and high power consumption. In low power consumption mode, some effective level conversion sub-circuits 110 can be turned off, thereby saving power consumption of the source drive circuit 1.

[0138] Optionally, as shown in Figures 15a-15d, the timing control circuit 5 includes multiple fourth output terminals 5b, the number of which is less than the number of first control terminals 11a. Some of the fourth output terminals 5b are connected to multiple second control terminals 2a. The timing control circuit 5 can adapt to high-power and low-power modes by selecting some of the fourth output terminals 5b to output an active-level enable signal EN and selecting others to output an inactive-level enable signal EN. Having fewer fourth output terminals 5b than the number of first control terminals 11a saves on the number of output terminals occupied by the timing control circuit 5. Alternatively, a timing control circuit 5 with fewer output terminals can be selected to save on component costs.

[0139] Specifically, the source drive circuit 1 includes W units, where W is an integer greater than or equal to 3; the two sub-circuit groups 100 include a first sub-circuit group 1001 and a second sub-circuit group 1002; the level conversion sub-circuit 11 in the first sub-circuit group 1001 and the second sub-circuit group 1002 are both effective level conversion sub-circuit 110. Due to the limited interface of some timing control circuits 5, the fourth output terminal 5b includes four units; the signal transmission line 3 includes a first transmission line 31 and a second transmission line 32.

[0140] As shown in Figure 15a, for the effective level conversion sub-circuit 110 that is electrically connected to the first transmission line 31, a first control terminal 11a in the first sub-circuit group 1001 of the first source drive circuit 1 and a first control terminal 11a in the second sub-circuit group 1002 of the Nth source drive circuit 1 are both electrically connected to the first fourth output terminal 5b1.

[0141] As shown in Figure 15b, for the effective level conversion sub-circuit 110 electrically connected to the first transmission line 31, one first control terminal 11a in the second sub-circuit group 1002 of the first source drive circuit 1, one first control terminal 11a in the first sub-circuit group 1001 of the Nth source drive circuit 1, and two first control terminals 11a in the kth source drive circuit 1 are all electrically connected to the second fourth output terminal 5b2. k takes an integer from 2 to (N-1).

[0142] As shown in Figure 15c, for the effective level conversion sub-circuit 110 electrically connected to the second transmission line 32, another first control terminal 11a in the first sub-circuit group 1001 of the first source drive circuit 1 and another first control terminal 11a in the second sub-circuit group 1002 of the Nth source drive circuit 1 are both electrically connected to the third fourth output terminal 5b3.

[0143] As shown in Figure 15d, for the effective level conversion sub-circuit 110 electrically connected to the second transmission line 32, another first control terminal 11a in the second sub-circuit group 1002 of the first source drive circuit 1, another first control terminal 11a in the first sub-circuit group 1001 of the Nth source drive circuit 1, and the other two first control terminals 11a of the kth source drive circuit 1 are all electrically connected to the fourth output terminal 5b2.

[0144] For example, W can be 3, 4, 5, 6, 7, 8, 9, or 10.

[0145] Optionally, as shown in Figure 16, the timing control circuit 5 includes multiple fourth output terminals 5b, each corresponding to a first control terminal 11a and electrically connected to it. Under different power consumption modes (low-power mode and high-power mode), the timing control circuit 5 can selectively control at least some of the fourth output terminals 5b to output enable signals EN. For example, in high-power mode, the timing control circuit 5 can selectively control all fourth output terminals 5b to output continuously active enable signals EN; in low-power mode, the timing control circuit 5 can selectively control a small number (e.g., 2, 3, or 4) of the fourth output terminals 5b to output continuously active enable signals EN.

[0146] Optionally, as shown in Figure 17, the timing control circuit 5 includes a fourth output terminal 5b, which is electrically connected to all the first control terminals 11a, and is used to simultaneously provide the second signal V2 to each of the first control terminals 11a. In high-power mode, the timing control circuit 5 can control all the enable signals EN to be continuously active, so as to control the active level conversion sub-circuit 110 to continuously output the second signal V2, thereby continuously turning on the switching transistor T0, and thus continuously outputting the data signal D0.

[0147] In some embodiments, as shown in FIG18, the display panel further includes a main control circuit 6; the main control circuit 6 includes a fifth output terminal 6a, and the first control terminal 11a of each effective level conversion sub-circuit 110 is electrically connected to the fifth output terminal 6a; the main control circuit 6 is configured to output an enable signal EN through the fifth output terminal 6a to control whether the effective level conversion sub-circuit 110 outputs the second signal V2.

[0148] Optionally, the main control circuit 6 can be configured to continuously output an enable signal EN to control the effective level conversion sub-circuit 110 to continuously output a second signal V2, thereby continuously turning on the switching transistor T0 and continuously outputting the data signal D0.

[0149] Optionally, the traces between the main control circuit 6 and the source drive circuit (SDIC) 1 are carried by a flexible printed circuit board (FPC), and the main control circuit 6 is carried by a printed circuit board (PCB). When the display panel is assembled, the printed circuit board (PCB) is bent to the backlight side of the display panel.

[0150] In some embodiments, the traces between the source drive circuit (SDIC) 1 and the switching circuit 2 are carried by a flexible printed circuit board (FPC), and the source drive circuit (SDIC) 1 and the main control circuit 6 are carried by a printed circuit board (PCB). When the display panel is assembled, the printed circuit board (PCB) is bent to the backlight side of the display panel.

[0151] In some embodiments, as shown in FIG19, the display panel further includes sub-pixels 7 located in display area AA, and a pixel driving circuit (not shown in the figure) for driving the sub-pixels 7. The display panel also includes a plurality of gate lines extending along a first direction X, and a plurality of data lines extending along a second direction Y. Optionally, the sub-pixels 7 are arranged in an array, with the first direction X being the row direction and the second direction Y being the column direction. The gate lines are used to provide gate driving signals to the switching sub-circuit in the pixel driving circuit, and the data lines are used to provide data signals D0 to the switching sub-circuit in the pixel driving circuit to drive the sub-pixels 7 of the display panel to display an image.

[0152] In some embodiments, the control electrode of the switching transistor T0 is on the same layer as the control electrode of the switching transistor (not shown in the figure) in the switching sub-circuit of the pixel driving circuit, and the two can be fabricated simultaneously. The first and second electrodes of the switching transistor T0 are on the same layer as the first and second electrodes of the switching transistor in the switching sub-circuit of the pixel driving circuit, and the two can be fabricated simultaneously.

[0153] In some embodiments, the control electrode of the switching transistor T0 and the signal transmission line 3 are both located on the same conductive layer.

[0154] In some embodiments, the signal transmission line 3 and the signal lead 4 are both located in the same conductive layer.

[0155] In some embodiments, the display panel is an organic light-emitting diode (OLED) display panel.

[0156] Of course, the display panel involved in this embodiment can also be a quantum dot light-emitting diode (QLED) display panel or a micro light-emitting diode (Micro LED) display panel, etc.

[0157] The display panel provided in this embodiment fully utilizes the feature that there are level conversion sub-circuits 11 on both sides of the SDIC, and makes full use of the idle level conversion sub-circuits 11 in the SDIC as effective level conversion sub-circuits 110, thereby increasing the access points on the signal data lines, such as the first node N1 between two adjacent SDICs, thereby reducing the waveform delay phenomenon of the second signal V2 on the signal transmission line 3, effectively solving the problem of insufficient charging of the data signal D0 (data signal) in the pixel driving circuit, and thus eliminating the poor phenomenon of dim display effect of the display panel under high load; at the same time, it ensures that the large-size display panel with the one-to-two design of the switching circuit 2 still maintains a high-quality display image under high load, improves the application prospects of large-size OLED display panels, and also greatly reduces the cost of various materials, components and raw materials required for the product.

[0158] In addition, this disclosure also provides a display device, which includes the display panel described in the above embodiments. This display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are readily understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0159] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display panel, comprising a substrate, a plurality of source driving circuits disposed on the substrate, a switching circuit corresponding to each of the source driving circuits, and at least two signal transmission lines; wherein the source driving circuits include at least four level conversion sub-circuits and driving sub-circuits; the level conversion sub-circuit includes a first control terminal, a first input terminal, and a first output terminal; and the switching circuit includes at least two second control terminals, a second input terminal, and at least two second output terminals. At least two of the four level-shifting sub-circuits are active level-shifting sub-circuits; For any one of the signal transmission lines, it is electrically connected to the first output terminal of at least one of the effective level conversion sub-circuits in each of the source drive circuits; different signal transmission lines are electrically connected to different effective level conversion sub-circuits. One of the signal transmission lines is electrically connected to one of the second control terminals of each of the switching circuits, and the second control terminals electrically connected to different signal transmission lines are different. The effective level conversion sub-circuit is configured to adjust the first signal received at the first input terminal to a second signal in response to the enable signal input at the first control terminal, and output the signal through the first output terminal. The driving sub-circuit is configured to output a data signal; The switching circuit is configured to respond to a second signal input to the second control terminal and output the data signal received at the second input terminal through the second output terminal.

2. The display panel according to claim 1, wherein, The switching circuit includes M switching transistors; M is an integer greater than or equal to 2; the number of switching transistors is the same as the number of signal transmission lines; For the switching circuit, one of the switching transistors is electrically connected to one of the signal transmission lines, and different switching transistors are electrically connected to different signal transmission lines.

3. The display panel according to claim 2, wherein, The switching circuit includes a first switching transistor and a second switching transistor; the signal transmission line includes a first transmission line and a second transmission line; the display panel also includes multiple data lines. The first electrode of the first switching transistor is electrically connected to the second input terminal, the second electrode is electrically connected to a data line, and the control electrode is electrically connected to the first transmission line. The first electrode of the second switching transistor is electrically connected to the second input terminal, the second electrode is electrically connected to another data line, and the control electrode is electrically connected to the second transmission line.

4. The display panel according to claim 1, wherein, The orthographic projection of the switching circuit on the substrate is located between the orthographic projection of the source drive circuit on the substrate and the orthographic projection of the signal transmission line on the substrate. Multiple source drive circuits are arranged side by side along a first direction; the signal transmission line extends in the first direction; the source drive circuit includes four level conversion sub-circuits, which are divided into two groups of sub-circuits, and each group of sub-circuits includes two level conversion sub-circuits. The orthographic projections of the two sets of sub-circuit groups on the substrate are respectively located on two opposite sides of the orthographic projection of the driving sub-circuit on the substrate in the first direction.

5. The display panel according to claim 4, wherein, For any of the source drive circuits, at least one group of the sub-circuits in the sub-circuit group are all effective level conversion sub-circuits; The effective level conversion sub-circuit in the same sub-circuit group is electrically connected to different signal transmission lines.

6. The display panel according to claim 5, wherein, For any of the source drive circuits, the two sets of sub-circuit groups include a first sub-circuit group and a second sub-circuit group; All level conversion sub-circuits in the first sub-circuit group are effective level conversion sub-circuits; All the level conversion sub-circuits in the second sub-circuit group are invalid level conversion sub-circuits.

7. The display panel according to claim 5, wherein, For any of the source drive circuits, the level conversion sub-circuits in both sets of sub-circuits are all effective level conversion sub-circuits.

8. The display panel according to claim 4, wherein, For a portion of the source drive circuit, all level conversion sub-circuits in one group of sub-circuits are valid level conversion sub-circuits; for another portion of the source drive circuit, all level conversion sub-circuits in both groups of sub-circuits are valid level conversion sub-circuits. The effective level conversion sub-circuit in the same sub-circuit group is electrically connected to different signal transmission lines.

9. The display panel according to claim 8, wherein, The source drive circuit includes N circuits, where N is an integer greater than or equal to 2; the two sets of sub-circuit groups include a first sub-circuit group and a second sub-circuit group. For the i-th source drive circuit, all level conversion sub-circuits in the first sub-circuit group are valid level conversion sub-circuits; all level conversion sub-circuits in the second sub-circuit group are invalid level conversion sub-circuits; the orthographic projection of the first sub-circuit group on the substrate is located on the side of the orthographic projection of the second sub-circuit group on the substrate away from the (i+1)-th source drive circuit; where i is an odd number from 1 to (N-1); For the (i+1)th source drive circuit, the level conversion sub-circuits in the first sub-circuit group and the second sub-circuit group are all effective level conversion sub-circuits; When N is an odd number, for the Nth source drive circuit, all level conversion sub-circuits in the first sub-circuit group are invalid level conversion sub-circuits; all level conversion sub-circuits in the second sub-circuit group are valid level conversion sub-circuits.

10. The display panel according to any one of claims 4 to 9, wherein, The display panel also includes signal leads that correspond one-to-one with the first output terminal; the first output terminal is electrically connected to a signal transmission line through the corresponding signal lead. The orthographic projection of the signal lead on the substrate is located on one of the two opposite sides of the orthographic projection of the switching circuit on the substrate in a first direction, and does not overlap with the orthographic projection of the switching circuit on the substrate.

11. The display panel according to any one of claims 1 to 9, wherein, The level conversion sub-circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first amplifier, and a second amplifier; The first electrode of the first transistor is electrically connected to the first input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first control terminal. The first electrode of the second transistor is electrically connected to the second node, the second electrode is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the second power supply terminal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth node. The first electrode of the fourth transistor is electrically connected to the second power supply terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the third node. The first electrode of the fifth transistor is electrically connected to the fourth node, the second electrode is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the output terminal of the first amplifier. The input terminal of the first amplifier is electrically connected to the first node; The input terminal of the second amplifier is electrically connected to the second node, and the output terminal is electrically connected to the first output terminal.

12. The display panel according to any one of claims 4 to 9, wherein, The display panel further includes a timing control circuit; the timing control circuit includes a third output terminal, and the first input terminal of each of the effective level conversion sub-circuits is electrically connected to the third output terminal; The timing control circuit is configured to output the first signal through the third output terminal.

13. The display panel according to claim 12, wherein, The timing control circuit further includes at least one fourth output terminal; the fourth output terminal is electrically connected to the first control terminal of the effective level conversion sub-circuit. The timing control circuit is further configured to output the enable signal through the fourth output terminal to control whether the effective level conversion sub-circuit outputs the second signal.

14. The display panel according to claim 13, wherein, The source drive circuit includes W units, where W is an integer greater than or equal to 3; the two sub-circuit groups include a first sub-circuit group and a second sub-circuit group; the level conversion sub-circuit in the first sub-circuit group and the second sub-circuit group are all effective level conversion sub-circuits; The fourth output terminal includes four; the signal transmission line includes a first transmission line and a second transmission line. For the effective level conversion sub-circuit electrically connected to the first transmission line, a first control terminal in the first sub-circuit group of the first source drive circuit and a first control terminal in the second sub-circuit group of the Nth source drive circuit are both electrically connected to the first fourth output terminal. For the effective level conversion sub-circuit electrically connected to the first transmission line, one of the first control terminals in the second sub-circuit group of the first source drive circuit, one of the first control terminals in the first sub-circuit group of the Nth source drive circuit, and two of the first control terminals in the kth source drive circuit are all electrically connected to the second fourth output terminal, where k is an integer from 2 to (N-1). For the effective level conversion sub-circuit electrically connected to the second transmission line, the other first control terminal in the first sub-circuit group of the first source drive circuit and the other first control terminal in the second sub-circuit group of the Nth source drive circuit are both electrically connected to the third fourth output terminal. For the effective level conversion sub-circuit electrically connected to the second transmission line, the other first control terminal in the second sub-circuit group of the first source drive circuit, the other first control terminal in the first sub-circuit group of the Nth source drive circuit, and the other two first control terminals of the kth source drive circuit are all electrically connected to the fourth output terminal.

15. The display panel according to claim 13, wherein, The fourth output terminal is connected to the first control terminal in a one-to-one correspondence.

16. The display panel according to claim 13, wherein, The source drive circuit includes four effective level conversion sub-circuits; the fourth output terminal includes four; the signal transmission line includes a first transmission line and a second transmission line. For each effective level conversion sub-circuit electrically connected to the first transmission line, one of the first control terminals in each of the source drive circuits is electrically connected to the first fourth output terminal; the other first control terminal in each of the source drive circuits is electrically connected to the second fourth output terminal. For each of the effective level conversion sub-circuits electrically connected to the second transmission line, one of the first control terminals of each of the source drive circuits is electrically connected to the third fourth output terminal; and the other of the first control terminals of each of the source drive circuits is electrically connected to the fourth fourth output terminal.

17. The display panel according to claim 1, wherein, The display panel also includes a main control circuit; the main control circuit includes a fifth output terminal, and the first control terminal of each of the effective level conversion sub-circuits is electrically connected to the fifth output terminal; The main control circuit is configured to output the enable signal through the fifth output terminal to control whether the effective level conversion sub-circuit outputs the second signal.

18. A display device, wherein, Includes the display panel as described in any one of claims 1 to 17.

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