Driving circuit, driving module, driving method and display apparatus

Abstract

Provided in the present disclosure are a driving circuit, a driving module, a driving method and a display apparatus. The driving circuit comprises a first node control circuit and a first node reset circuit, wherein the first node control circuit is electrically connected to a first control end and a first node, respectively, and is used for controlling the potential of the first node under the control of a first control signal provided by the first control end; and the first node reset circuit is electrically connected to a second control end and the first node, respectively, and is used for controlling the reset of the potential of the first node under the control of a second control signal provided by the second control end. The present disclosure enables flexible display.

Description

Drive circuit, drive module, drive method and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411535758.5, filed in China on October 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a driving circuit, driving module, driving method and display device. Background Technology

[0004] Currently, all areas of the displays on the market have a single refresh rate, such as the common 30Hz, 60Hz, 90Hz, 120Hz, and 144Hz. To comprehensively consider the battery life and user experience, current system integrators typically use a low refresh rate (e.g., 60Hz) for static display scenarios like reading ebooks, and switch to a high refresh rate (e.g., 120Hz) for watching videos or playing games.

[0005] To further improve overall battery life and user experience, the optimal solution is for the display to support flexible display, with different areas of the screen corresponding to different refresh rates. That is, areas requiring a high refresh rate should be refreshed at a high refresh rate, and areas requiring a low refresh rate should be refreshed at a low refresh rate, adjusting the refresh rate according to the current displayed image. However, current products are limited by the GOA (Gate Driver On Array) model and cannot achieve this effect. Summary of the Invention

[0006] The main objective of this disclosure is to provide a driving circuit, driving module, driving method, and display device to solve the problem of inconvenient and flexible display in related technologies.

[0007] In one aspect, embodiments of this disclosure provide a driving circuit, including a first node control circuit and a first node reset circuit;

[0008] The first node control circuit is electrically connected to the first control terminal and the first node respectively, and is used to control the potential of the first node under the control of the first control signal provided by the first control terminal;

[0009] The first node reset circuit is electrically connected to the second control terminal and the first node, respectively, and is used to control the reset of the potential of the first node under the control of the second control signal provided by the second control terminal.

[0010] Optionally, the first control terminal includes at least one pull-up start control terminal;

[0011] The first node control circuit is used to control the potential of the first node to be an effective voltage under the control of the signal provided by the at least one pull-up start control terminal.

[0012] Optionally, the second control terminal includes at least one pull-down start control terminal;

[0013] The first node reset circuit is used to control the potential of the first node to be an invalid voltage under the control of the signal provided by the at least one pull-down start control terminal.

[0014] The driving circuit described in at least one embodiment of this disclosure further includes a cascaded control circuit;

[0015] The cascaded control circuit is electrically connected to the carry control clock signal terminal, the carry input terminal, the carry reset terminal, and the nth-level carry signal output terminal, respectively. It is used to provide the nth-level carry signal through the nth-level carry signal output terminal based on the carry control clock signal provided by the carry control clock signal terminal, the carry input signal provided by the carry input terminal, and the carry reset signal provided by the carry reset terminal; n is a positive integer.

[0016] The first control terminal is electrically connected to the nth level carry signal output terminal;

[0017] The first node control circuit is also electrically connected to the input control terminal, and is used to control the potential of the first node according to the input control signal provided by the input control terminal under the control of the nth level carry signal.

[0018] Optionally, the first node control circuit includes an input circuit;

[0019] The input circuit is electrically connected to the nth level carry signal output terminal, the input control terminal, and the first node, respectively, and is used to control the connection or disconnection between the input control terminal and the first node under the control of the nth level carry signal output terminal.

[0020] Optionally, the cascaded control circuit includes a first control module, a second control module, a third control module, and a first potential holding module;

[0021] The first control module is electrically connected to the carry control clock signal terminal, the carry input terminal, and the nth level carry control node, respectively, and is used to control the potential of the nth level carry control node according to the carry input signal under the control of the carry control clock signal;

[0022] The second control module is electrically connected to the nth carry control node, the first voltage terminal, and the nth carry signal output terminal, respectively, and is used to control the connection or disconnection between the nth carry signal output terminal and the first voltage terminal under the control of the potential of the nth carry control node;

[0023] The third control module is electrically connected to the carry reset terminal, the nth level carry signal output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth level carry signal output terminal and the second voltage terminal under the control of the carry reset signal;

[0024] The first potential holding module is electrically connected to the output terminal of the nth level carry signal and is used to maintain the potential of the nth level carry signal.

[0025] Optionally, the cascaded control circuit is also electrically connected to the nth-level carry control node and the nth-level control node, respectively, for controlling the potential of the nth-level carry control node according to the carry input signal provided by the carry input terminal and the carry reset signal provided by the carry reset terminal; controlling the potential of the nth-level control node under the control of the potential of the nth-level carry control node; controlling the connection or disconnection between the nth-level carry signal output terminal and the carry control clock signal terminal under the control of the potential of the nth-level carry control node; and resetting the nth-level carry signal provided by the nth-level carry signal output terminal under the control of the potential of the nth-level control node.

[0026] Optionally, the first node control circuit includes a control circuit and an input circuit;

[0027] The control circuit is electrically connected to the nth level carry signal output terminal, the input control terminal, and the input control node, respectively, and is used to control the connection or disconnection between the input control terminal and the input control node under the control of the nth level carry signal output terminal;

[0028] The input circuit is electrically connected to the input control node and the first node respectively, and is used to control the potential of the first node according to the potential of the input control node.

[0029] Optionally, the cascaded control circuit includes a fourth control module and a fifth control module;

[0030] The fourth control module is electrically connected to the carry input terminal, the carry reset terminal, the nth level carry control node, and the second voltage terminal, respectively. It is used to control the potential of the nth level carry control node under the control of the carry input signal, and to control the connection or disconnection between the nth level carry control node and the second voltage terminal under the control of the carry reset signal.

[0031] The fifth control module is electrically connected to the nth level carry control node and the nth level control node, respectively, and is used to control the potential of the nth level control node according to the potential of the nth level carry control node.

[0032] Optionally, the cascaded control circuit further includes a carry-in energy storage module and a sixth control module;

[0033] The first end of the carry-in energy storage module is electrically connected to the nth level carry-in control node, and the second end of the carry-in energy storage module is electrically connected to the nth level control node;

[0034] The sixth control module is electrically connected to the nth level carry signal output terminal, the nth level carry control node, the nth level control node, the carry control clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth level carry signal output terminal and the carry control clock signal terminal under the control of the potential of the nth level carry control node, and to control the connection or disconnection between the nth level carry signal output terminal and the second voltage terminal under the control of the potential of the nth level control node.

[0035] Optionally, the second control terminal is the carry-reset terminal.

[0036] Optionally, the first node control circuit includes a first control transistor; the gate of the first control transistor is electrically connected to a first pull-up start control terminal, the first terminal of the first control transistor is electrically connected to the gate or a third voltage terminal of the first control transistor, and the second terminal of the first control transistor is electrically connected to the first node; or,

[0037] The first node control circuit includes at least two control transistors, namely a first control transistor and a second control transistor. The gate of the first control transistor is electrically connected to a first pull-up start control terminal. The first terminal of the first control transistor is electrically connected to a first pull-up start control terminal, a second pull-up start control terminal, or a third voltage terminal. The gate of the second control transistor is electrically connected to a second pull-up start control terminal. The first terminal of the second control transistor is electrically connected to the second terminal of the first control transistor. The second terminal of the second control transistor is electrically connected to the first node. Alternatively...

[0038] The first node control circuit includes at least three control transistors, namely a first control transistor, a second control transistor, and a third control transistor. The gate of the first control transistor is electrically connected to a first pull-up start control terminal. The first terminal of the first control transistor is electrically connected to a first pull-up start control terminal, a second pull-up start control terminal, a third pull-up start control terminal, or a third voltage terminal. The gate of the second control transistor is electrically connected to a second pull-up start control terminal, and the first terminal of the second control transistor is electrically connected to the second terminal of the first control transistor. The gate of the third control transistor is electrically connected to a third pull-up start control terminal, and the first terminal of the third control transistor is electrically connected to the second terminal of the second control transistor. The second terminal of the third control transistor is electrically connected to the first node.

[0039] Optionally, the first node reset circuit includes at least two control transistors, including a first second control transistor and a second second control transistor; the gate of the first second control transistor is electrically connected to a first pull-down start control terminal, the first terminal of the first second control transistor is electrically connected to the first node, the second terminal of the first second control transistor is electrically connected to the first terminal of the second second control transistor, the gate of the second second control transistor is electrically connected to a second pull-down start control terminal, and the second terminal of the second second control transistor is electrically connected to a first voltage terminal; or,

[0040] The first node reset circuit includes at least three control transistors, namely a first second control transistor, a second second control transistor, and a third second control transistor. The gate of the first second control transistor is electrically connected to a first pull-down start control terminal, the first terminal of the first second control transistor is electrically connected to a first node, the second terminal of the first second control transistor is electrically connected to the first terminal of the second second control transistor, the gate of the second second control transistor is electrically connected to a second pull-down start control terminal, the second terminal of the second second control transistor is electrically connected to the first terminal of the third second control transistor, the gate of the third second control transistor is electrically connected to a third pull-down start control terminal, and the second terminal of the third second control transistor is electrically connected to a first voltage terminal.

[0041] Optionally, the input circuit includes a first transistor;

[0042] The gate of the first transistor is electrically connected to the nth carry signal output terminal, the first electrode of the first transistor is electrically connected to the input control terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0043] Optionally, the first control module includes a second transistor and a third transistor, the second control module includes a fourth transistor, the third control module includes a fifth transistor, and the first potential holding module includes a first capacitor;

[0044] The gate of the second transistor is electrically connected to the carry control clock signal terminal, the first terminal of the second transistor is electrically connected to the carry input terminal, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor.

[0045] The gate of the third transistor is electrically connected to the first terminal of the third transistor, and the second terminal of the third transistor is electrically connected to the nth carry control node;

[0046] The gate of the fourth transistor is electrically connected to the nth carry control node, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the nth carry signal output terminal.

[0047] The gate of the fifth transistor is electrically connected to the carry reset terminal, the first terminal of the fifth transistor is electrically connected to the nth carry signal output terminal, and the second terminal of the fifth transistor is electrically connected to the second voltage terminal.

[0048] The first terminal of the first capacitor is electrically connected to the nth level carry signal output terminal, and the second terminal of the first capacitor is electrically connected to the DC voltage terminal.

[0049] Optionally, the control circuit includes a sixth transistor, and the input circuit includes a first transistor;

[0050] The gate of the sixth transistor is electrically connected to the nth carry signal output terminal, the first terminal of the sixth transistor is electrically connected to the input control terminal, and the second terminal of the sixth transistor is electrically connected to the gate of the first transistor.

[0051] The gate of the first transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the first transistor is electrically connected to the first node.

[0052] Optionally, the fourth control module includes a seventh transistor and an eighth transistor, and the fifth control module includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

[0053] The gate and the first terminal of the seventh transistor are both electrically connected to the carry input terminal, and the second terminal of the seventh transistor is electrically connected to the gate of the nth carry control node.

[0054] The gate of the eighth transistor is electrically connected to the carry-reset terminal, the first terminal of the eighth transistor is electrically connected to the nth carry control node, and the second terminal of the eighth transistor is electrically connected to the second voltage terminal.

[0055] The gate and the first terminal of the ninth transistor are both electrically connected to the first voltage terminal, and the second terminal of the ninth transistor is electrically connected to the nth level control node.

[0056] The gate of the tenth transistor is electrically connected to the nth carry control node, the first terminal of the tenth transistor is electrically connected to the nth control node, and the second terminal of the tenth transistor is electrically connected to the second voltage terminal.

[0057] The gate and the first terminal of the eleventh transistor are both electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the nth carry control node.

[0058] The gate of the twelfth transistor is electrically connected to the nth level control node, the first terminal of the twelfth transistor is electrically connected to the nth level carry control node, and the second terminal of the twelfth transistor is electrically connected to the second voltage terminal.

[0059] Optionally, the channel width-to-length ratio of the tenth transistor is greater than that of the ninth transistor.

[0060] Optionally, the carry-in energy storage module includes a second capacitor, and the sixth control module includes a thirteenth transistor and a fourteenth transistor;

[0061] The first terminal of the second capacitor is electrically connected to the nth level carry control node, and the second terminal of the second capacitor is electrically connected to the nth level control node.

[0062] The gate of the thirteenth transistor is electrically connected to the nth level carry control node, the first terminal of the thirteenth transistor is electrically connected to the carry control clock signal terminal, and the second terminal of the thirteenth transistor is electrically connected to the nth level carry signal output terminal.

[0063] The gate of the fourteenth transistor is electrically connected to the nth level control node, the first terminal of the fourteenth transistor is electrically connected to the carry signal output terminal of the nth level, and the second terminal of the fourteenth transistor is electrically connected to the second voltage terminal.

[0064] In a second aspect, embodiments of this disclosure provide a drive module including a plurality of the drive circuits described above.

[0065] Optionally, the drive module includes M drive units, where M is an integer greater than 1 and m is a positive integer less than or equal to M; the drive unit includes multiple drive circuits cascaded together.

[0066] The m-th drive unit includes q-level drive circuits. The first control terminal of the first-level drive circuit in the m-th drive unit is electrically connected to the corresponding pull-up start control terminal. The second control terminal of the first-level drive circuit in the m-th drive unit is electrically connected to the drive signal output terminal of the j-th drive circuit in the m-th drive unit. j is greater than or equal to 2 but less than q. j is an integer and q is a positive integer greater than 1.

[0067] The first control terminal of the q-th stage drive circuit in the m-th drive unit is electrically connected to the drive signal output terminal of the qi-th stage drive circuit in the m-th drive unit, where i is an integer, i is greater than or equal to 1 and less than q, and the second control terminal of the q-th stage drive circuit is electrically connected to the corresponding pull-down start control terminal.

[0068] The driving module described in at least one embodiment of this disclosure includes M starting voltage lines;

[0069] Multiple driving circuits in the m-th driving unit are electrically connected to the corresponding row pixel circuits in the m-th display area, and are used to provide driving signals to the corresponding row pixel circuits.

[0070] Optionally, the driving circuit further includes a cascaded control circuit, wherein the first node control circuit includes an input circuit; n is a positive integer; the cascaded control circuit includes a carry input terminal, a carry reset terminal, and a carry signal output terminal; the input circuit is electrically connected to the input control terminal; the second control terminal is a carry reset terminal; the driving module includes multiple cascaded driving circuits.

[0071] The drive module includes a carry input terminal and a starting voltage terminal of the first-stage drive circuit;

[0072] The carry input terminal of the a-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the ak-th stage drive circuit included in the drive module, where a is an integer greater than 1 and k is an integer greater than or equal to 1.

[0073] The carry reset terminal of the b-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the b+r-th stage drive circuit included in the drive module; b is a positive integer, and r is an integer greater than or equal to 1.

[0074] The carry reset terminal of the b-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the b+2-th stage drive circuit included in the drive module; b is a positive integer.

[0075] In a third aspect, embodiments of this disclosure provide a driving method applied to the aforementioned driving module, the driving method comprising: during a display cycle, when the display area corresponding to the m-th driving unit is refreshed,

[0076] During the corresponding input phase of the display cycle, the corresponding pull-up start control terminal provides a valid pull-up start control signal;

[0077] During the corresponding reset phase of the display cycle, the corresponding pull-down start control terminal provides a valid pull-down start control signal.

[0078] In a fourth aspect, embodiments of this disclosure provide a driving method applied to the aforementioned driving module, the driving method comprising:

[0079] When the input control terminal provides a valid input control signal, the corresponding stage drive circuit provides a valid drive signal;

[0080] When the input control terminal provides an invalid input control signal, the corresponding stage drive circuit stops providing a valid drive signal.

[0081] In a fifth aspect, embodiments of this disclosure provide a display device including the driving module described above.

[0082] The driving circuit, driving module, driving method, and display device described in the embodiments of this disclosure can perform flexible display. Attached Figure Description

[0083] Figure 1 is a schematic diagram of the effective display area of ​​the display panel;

[0084] Figure 2 is a schematic diagram showing the division of the effective display area of ​​the display panel;

[0085] Figure 3 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0086] Figure 4 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0087] Figure 5 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0088] Figure 6 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0089] Figure 7 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0090] Figure 8 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0091] Figure 9 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0092] Figures 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H and 10I are circuit diagrams of at least one embodiment of the first node control circuit;

[0093] Figures 11A, 11B and 11C are circuit diagrams of at least one embodiment of the first node reset circuit;

[0094] Figures 12A, 12B, 12C, 12D, and 12E are schematic diagrams of the display area division of the display panel;

[0095] Figure 13 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0096] Figure 14 is a circuit diagram of the first-stage driving circuit in the multi-stage driving circuit corresponding to each display area;

[0097] Figure 15 is a circuit diagram of the last stage of the multi-stage driving circuit corresponding to each display area;

[0098] Figure 16 is a circuit diagram of the intermediate stage driving circuit in the multi-stage driving circuit corresponding to each display area;

[0099] Figure 17 is a timing diagram of the normal display refresh operation of at least one embodiment shown in Figure 13 during operation;

[0100] Figure 18 is a schematic diagram of the display area division of the display panel;

[0101] Figure 19 is a timing diagram of the operation of at least one embodiment shown in Figure 13 when flexible display is performed and the refreshed area is repeatedly displayed within the second display area.

[0102] Figure 20 is a schematic diagram of the display area division of the display panel;

[0103] Figure 21 is a timing diagram of the operation of at least one embodiment shown in Figure 13 when flexible display is performed and the refreshed display area is repeatedly displayed within the second and third display areas.

[0104] Figure 22 is a schematic diagram of the display area division of the display panel;

[0105] Figure 23 is a timing diagram of the operation of at least one embodiment shown in Figure 13 when flexible display is performed and the refreshed display area is repeatedly displayed in the second and fourth display areas.

[0106] Figure 24 is a schematic diagram of the display area division of the display panel;

[0107] Figure 25 is a timing diagram of the operation of at least one embodiment shown in Figure 13 when flexible display is performed, the display refresh area is repeatedly displayed in the second display area and the fourth display area, and the refresh rate of the second display area is greater than the refresh rate of the fourth display area.

[0108] Figure 26 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0109] Figure 27 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0110] Figure 28A is a schematic diagram of the scanning and refreshing of the driving circuit included in the driving module of the display panel;

[0111] Figure 28B is a schematic diagram of the scanning and refreshing of the driving circuit included in the driving module of the display panel;

[0112] Figure 29 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0113] Figure 30 is a schematic diagram of the working state of at least one embodiment of the driving circuit shown in Figure 29;

[0114] Figure 31 is a schematic diagram of the working state of at least one embodiment of the driving circuit shown in Figure 29;

[0115] Figure 32 is a schematic diagram of the working state of at least one embodiment of the driving circuit shown in Figure 29;

[0116] Figure 33 is a schematic diagram of the working state of at least one embodiment of the driving circuit shown in Figure 29;

[0117] Figure 34 is a timing diagram of the operation of the driving module according to at least one embodiment of the present disclosure;

[0118] Figures 35A, 35B, and 35C are schematic diagrams showing the division of display areas;

[0119] Figure 36 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0120] Figure 37 is a schematic diagram of the working state of at least one embodiment of the driving circuit shown in Figure 36;

[0121] Figure 38 is a schematic diagram of the working state of at least one embodiment of the driving circuit shown in Figure 36;

[0122] Figure 39 is a schematic diagram of the working state of at least one embodiment of the driving circuit shown in Figure 36;

[0123] Figure 40 is a schematic diagram of the working state of at least one embodiment of the driving circuit shown in Figure 36;

[0124] Figure 41 is a timing diagram of the operation of the drive module according to at least one embodiment of the present disclosure. Detailed Implementation

[0125] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0126] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0127] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0128] Currently, various mobile video apps are popular among users. To enhance the video viewing experience and interactivity, users often watch videos in a small window mode (video playback occurs only in a small area of ​​the screen), while simultaneously viewing comments below. The entire display screen can be divided into four areas from top to bottom: time and status area, video playback area, comment area, and operation button area. Currently, the screen refresh rate is the same in all four areas. To increase the refresh rate of the video playback area, the refresh rate of all areas would be increased simultaneously, leading to increased screen power consumption and significantly shortening the overall battery life.

[0129] To improve the overall battery life and user experience, we have further optimized the display's operating status. We analyze and judge the displayed image, using a high refresh rate for areas requiring a high refresh rate and a low refresh rate for areas where a low refresh rate is possible. For example, the video playback area is refreshed at a high refresh rate, while the time and status area, comment area, and operation button area are refreshed at a low refresh rate. This disclosure proposes several new drive circuit architectures through optimization of the display's drive circuitry to achieve the above-mentioned flexible display effect.

[0130] In at least one embodiment of this disclosure, the display screen can achieve the following display states:

[0131] Normal display: The entire screen is scanned and refreshed line by line, and the refresh rate is consistent in all positions, as shown in Figure 1. In each frame of the display, each row of pixel circuits is refreshed at the same refresh rate, such as 60Hz.

[0132] Flexible display: Any area can be refreshed at a high frequency, while other areas can be refreshed at a low frequency. The position and range of the high-frequency refresh are adjustable, as shown in Figure 2. In each frame, the refresh rates of different display areas are not exactly the same; or, any area that needs to be displayed can be displayed, while other areas are not displayed, such as the standby screen, where the display panel only displays the time, etc.

[0133] As shown in Figure 1, in the effective display area A0 of the display panel, all pixel circuits have the same refresh rate.

[0134] As shown in Figure 2, the effective display area of ​​the display panel may include at least two areas with different refresh rates, such as three areas, for example, a first display area A1, a second display area A2 and a third display area A3. The refresh rate corresponding to the first display area A1 may be, for example, 40Hz, the refresh rate corresponding to the second display area A2 may be, for example, 80Hz, and the refresh rate corresponding to the third display area A3 may be, for example, 40Hz.

[0135] As shown in Figure 3, the driving circuit described in this embodiment includes a first node control circuit 31 and a first node reset circuit 32.

[0136] The first node control circuit 31 is electrically connected to the first control terminal SC1 and the first node PU respectively, and is used to control the potential of the first node PU under the control of the first control signal provided by the first control terminal SC1;

[0137] The first node reset circuit 32 is electrically connected to the second control terminal SC2 and the first node PU, respectively, and is used to control the potential of the first node PU to be reset under the control of the second control signal provided by the second control terminal SC2.

[0138] In at least one embodiment of this disclosure, the driving module may include multiple driving circuits, and the first node control circuit may be used to locate the starting position of the driving circuit in the driving module that performs display refresh, thereby enabling local display with any row open.

[0139] In at least one embodiment of this disclosure, the first control terminal includes at least one pull-up start control terminal;

[0140] The first node control circuit is used to control the potential of the first node to be an effective voltage under the control of the signal provided by the at least one pull-up start control terminal.

[0141] In a preferred embodiment, the first control terminal may include at least two pull-up start control terminals. Under the control of the signals provided by the at least two pull-up start control terminals, the first node control circuit controls the potential of the first node to be an effective voltage. By controlling the at least two pull-up start control terminals, the starting position of the display area can be located, and local display of any row can be realized.

[0142] In at least one embodiment of this disclosure, the second control terminal includes at least one pull-down start control terminal;

[0143] The first node reset circuit is used to control the potential of the first node to be an invalid voltage under the control of the signal provided by the at least one pull-down start control terminal.

[0144] In a preferred embodiment, the second control terminal may include at least two pull-down start control terminals. The first node reset circuit is used to control the potential of the first node to be an invalid voltage under the control of the signals provided by the at least two pull-down start control terminals. By controlling the at least two pull-down start control terminals, the end position of the display area can be located.

[0145] As shown in Figure 4, the driving circuit described in at least one embodiment of this disclosure further includes a cascaded control circuit 40;

[0146] The cascaded control circuit 40 is electrically connected to the carry control clock signal terminal CLKC, the carry input terminal IS, the carry reset terminal IR, and the nth stage carry signal output terminal Sn, respectively. It is used to provide the nth stage carry signal through the nth stage carry signal output terminal Sn according to the carry control clock signal provided by the carry control clock signal terminal CLKC, the carry input signal provided by the carry input terminal IS, and the carry reset signal provided by the carry reset terminal IR; n is a positive integer.

[0147] The first control terminal is electrically connected to the nth level carry signal output terminal Sn;

[0148] The first node control circuit 31 is also electrically connected to the input control terminal SW, and is used to control the potential of the first node PU under the control of the nth level carry signal and according to the input control signal provided by the input control terminal SW.

[0149] In at least one embodiment of this disclosure, the carry input terminal IS can be electrically connected to the carry signal output terminal of the na-th stage, and the carry reset terminal IR can be electrically connected to the carry signal output terminal of the (n+b)-th stage. a and b can be positive integers; for example, a can be equal to 1 and b can be equal to 2.

[0150] Optionally, the first voltage terminal can be a high voltage terminal.

[0151] In at least one embodiment of the driving circuit shown in Figure 4 of this disclosure, when the input control terminal SW provides a valid input control signal, the driving circuit provides a valid driving signal; when the input control terminal SW provides an invalid input control signal, the driving circuit stops providing a valid driving signal.

[0152] In at least one embodiment of this disclosure, the first node control circuit includes an input circuit;

[0153] The input circuit is electrically connected to the nth level carry signal output terminal, the input control terminal, and the first node, respectively, and is used to control the connection or disconnection between the input control terminal and the first node under the control of the nth level carry signal output terminal.

[0154] In at least one embodiment of this disclosure, when the first transistor included in the first node control circuit is an n-type transistor, the valid input control signal is a high-voltage signal and the invalid input control signal is a low-voltage signal.

[0155] When the first transistor included in the first node control circuit is a p-type transistor, the valid input control signal is a low voltage signal, and the invalid input control signal is a high voltage signal.

[0156] In at least one embodiment of this disclosure, when the transistor whose gate is electrically connected to the drive signal output terminal of the drive circuit is an n-type transistor, the effective drive signal is a high-voltage signal.

[0157] When the transistor whose gate is electrically connected to the drive signal output terminal of the drive circuit is a p-type transistor, the effective drive signal is a low-voltage signal.

[0158] As shown in Figure 5, based on at least one embodiment of the driving circuit shown in Figure 4, the first node control circuit includes an input circuit 50.

[0159] The input circuit 50 is electrically connected to the nth carry signal output terminal Sn, the input control terminal SW, and the first node PU, respectively, and is used to control the connection or disconnection between the input control terminal SW and the first node PU under the control of the nth carry signal output terminal Sn.

[0160] In at least one embodiment of this disclosure, the cascaded control circuit includes a first control module, a second control module, a third control module, and a first potential holding module;

[0161] The first control module is electrically connected to the carry control clock signal terminal, the carry input terminal, and the nth level carry control node, respectively, and is used to control the potential of the nth level carry control node according to the carry input signal under the control of the carry control clock signal;

[0162] The second control module is electrically connected to the nth carry control node, the first voltage terminal, and the nth carry signal output terminal, respectively, and is used to control the connection or disconnection between the nth carry signal output terminal and the first voltage terminal under the control of the potential of the nth carry control node;

[0163] The third control module is electrically connected to the carry reset terminal, the nth level carry signal output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth level carry signal output terminal and the second voltage terminal under the control of the carry reset signal;

[0164] The first potential holding module is electrically connected to the output terminal of the nth level carry signal and is used to maintain the potential of the nth level carry signal.

[0165] In a specific implementation, the cascaded control circuit may include a first control module, a second control module, a third control module, and a first potential holding module; the first control module, under the control of the carry control clock signal, controls the potential of the nth-level carry control node according to the carry input signal; the second control module, under the control of the potential of the nth-level carry control node, controls the nth-level carry signal output by the nth-level carry signal output terminal; the third control module, under the control of the carry reset signal, controls the nth-level carry signal output by the nth-level carry signal output terminal; and the first potential holding module maintains the potential of the nth-level carry signal.

[0166] Optionally, the second voltage terminal can be a low voltage terminal.

[0167] As shown in Figure 6, based on at least one embodiment of the driving circuit shown in Figure 5, the cascaded control circuit includes a first control module 61, a second control module 62, a third control module 62, and a first potential holding module 64.

[0168] The first control module 61 is electrically connected to the carry control clock signal terminal CLKC, the carry input terminal IS, and the nth level carry control node NCn, respectively, and is used to control the potential of the nth level carry control node NCn according to the carry input signal provided by the carry input terminal IS under the control of the carry control clock signal provided by the carry control clock signal terminal CLKC.

[0169] The second control module 62 is electrically connected to the nth carry control node NCn, the first voltage terminal V1 and the nth carry signal output terminal Sn respectively, and is used to control the connection or disconnection between the nth carry signal output terminal Sn and the first voltage terminal V1 under the control of the potential of the nth carry control node NCn.

[0170] The third control module 63 is electrically connected to the carry reset terminal IR, the nth level carry signal output terminal Sn, and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the nth level carry signal output terminal Sn and the second voltage terminal V2 under the control of the carry reset signal;

[0171] The first potential holding module 64 is electrically connected to the nth level carry signal output terminal Sn, and is used to maintain the potential of the nth level carry signal.

[0172] In at least one embodiment of this disclosure, the cascaded control circuit is further electrically connected to the nth-level carry control node and the nth-level control node, respectively, for controlling the potential of the nth-level carry control node according to the carry input signal provided by the carry input terminal and the carry reset signal provided by the carry reset terminal; controlling the potential of the nth-level control node under the control of the potential of the nth-level carry control node; controlling the connection or disconnection between the nth-level carry signal output terminal and the carry control clock signal terminal under the control of the potential of the nth-level carry control node; and resetting the nth-level carry signal provided by the nth-level carry signal output terminal under the control of the potential of the nth-level control node.

[0173] In practical implementation, the cascaded control circuit controls the potential of the nth-level carry control node based on the carry input signal and the carry reset signal. Under the control of the potential of the nth-level carry control node, the circuit controls the potential of the nth-level control node and the nth-level carry signal output from the nth-level carry signal output terminal. Under the control of the potential of the nth-level control node, the circuit resets the nth-level carry signal provided by the nth-level carry signal output terminal.

[0174] As shown in Figure 7, based on at least one embodiment of the driving circuit shown in Figure 4,

[0175] The cascaded control circuit 40 is also electrically connected to the nth-level carry control node NCn and the nth-level control node NSn, respectively. It is used to control the potential of the nth-level carry control node NCn according to the carry input signal provided by the carry input terminal IS and the carry reset signal provided by the carry reset terminal IR. Under the control of the potential of the nth-level carry control node NCn, it controls the potential of the nth-level control node NSn. Under the control of the potential of the nth-level carry control node NCn, it controls the connection or disconnection between the nth-level carry signal output terminal Sn and the carry control clock signal terminal CLKC. Under the control of the potential of the nth-level control node NSn, it resets the nth-level carry signal provided by the nth-level carry signal output terminal Sn.

[0176] In at least one embodiment of this disclosure, the first node control circuit includes a control circuit and an input circuit;

[0177] The control circuit is electrically connected to the nth level carry signal output terminal, the input control terminal, and the input control node, respectively, and is used to control the connection or disconnection between the input control terminal and the input control node under the control of the nth level carry signal output terminal;

[0178] The input circuit is electrically connected to the input control node and the first node respectively, and is used to control the potential of the first node according to the potential of the input control node.

[0179] In a specific implementation, the first node control circuit may include a control circuit and an input circuit; the control circuit, under the control of the nth level carry signal output terminal, controls the connection or disconnection between the input control terminal and the input control node; the input circuit, under the control of the potential of the input control node, controls the potential of the first node.

[0180] As shown in Figure 8, based on at least one embodiment of the driving circuit shown in Figure 7, the first node control circuit includes a control circuit 51 and an input circuit 50.

[0181] The control circuit 51 is electrically connected to the nth level carry signal output terminal Sn, the input control terminal SW, and the input control node NR, respectively, and is used to control the connection or disconnection between the input control terminal SW and the input control node NR under the control of the nth level carry signal output terminal Sn.

[0182] The input circuit 50 is electrically connected to the input control node NR and the first node PU, respectively, and is used to control the potential of the first node PU under the control of the potential of the input control node NR.

[0183] In at least one embodiment of this disclosure, the cascaded control circuit includes a fourth control module and a fifth control module;

[0184] The fourth control module is electrically connected to the carry input terminal, the carry reset terminal, the nth level carry control node, and the second voltage terminal, respectively. It is used to control the potential of the nth level carry control node under the control of the carry input signal, and to control the connection or disconnection between the nth level carry control node and the second voltage terminal under the control of the carry reset signal.

[0185] The fifth control module is electrically connected to the nth level carry control node and the nth level control node, respectively, and is used to control the potential of the nth level control node according to the potential of the nth level carry control node.

[0186] In a specific implementation, the cascaded control circuit may include a fourth control module and a fifth control module; the fourth control module controls the potential of the nth level carry control node under the control of the carry input signal, and controls the reset of the potential of the nth level carry control node under the control of the carry reset signal; the fifth control module controls the potential of the nth level control node according to the potential of the nth level carry control node.

[0187] In at least one embodiment of this disclosure, the cascaded control circuit further includes a carry-in energy storage module and a sixth control module;

[0188] The first end of the carry-in energy storage module is electrically connected to the nth level carry-in control node, and the second end of the carry-in energy storage module is electrically connected to the nth level control node; the carry-in energy storage module is used to store electrical energy.

[0189] The sixth control module is electrically connected to the nth level carry signal output terminal, the nth level carry control node, the nth level control node, the carry control clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth level carry signal output terminal and the carry control clock signal terminal under the control of the potential of the nth level carry control node, and to control the connection or disconnection between the nth level carry signal output terminal and the second voltage terminal under the control of the potential of the nth level control node.

[0190] In a specific implementation, the cascaded control circuit may further include a carry energy storage module and a sixth control module; the sixth control module, under the control of the potential of the nth carry control node, controls the nth carry signal output by the nth carry signal output terminal, and under the control of the potential of the nth control node, controls the reset of the nth carry signal provided by the nth carry signal output terminal.

[0191] As shown in Figure 9, based on at least one embodiment of the drive circuit shown in Figure 8, the cascaded control circuit includes a fourth control module 91 and a fifth control module 92.

[0192] The fourth control module 91 is electrically connected to the carry input terminal IS, the carry reset terminal IR, the nth level carry control node NCn, and the second voltage terminal V2, respectively. It is used to control the potential of the nth level carry control node NCn under the control of the carry input signal, and to control the connection or disconnection between the nth level carry control node NCn and the second voltage terminal V2 under the control of the carry reset signal.

[0193] The fifth control module 92 is electrically connected to the nth level carry control node NCn and the nth level control node NSn respectively, and is used to control the potential of the nth level control node NSn according to the potential of the nth level carry control node NCn;

[0194] The cascaded control circuit also includes a carry-in energy storage module 93 and a sixth control module 94;

[0195] The first end of the carry energy storage module 93 is electrically connected to the nth level carry control node NCn, and the second end of the carry energy storage module 93 is electrically connected to the nth level control node NSn; the carry energy storage module 93 is used to store electrical energy.

[0196] The sixth control module 94 is electrically connected to the nth level carry signal output terminal Sn, the nth level carry control node NCn, the nth level control node NSn, the carry control clock signal terminal CLKC, and the second voltage terminal V2, respectively. It is used to control the connection or disconnection between the nth level carry signal output terminal Sn and the carry control clock signal terminal CLKC under the control of the potential of the nth level carry control node NCn, and to control the connection or disconnection between the nth level carry signal output terminal Sn and the second voltage terminal V2 under the control of the potential of the nth level control node NSn.

[0197] Optionally, the second control terminal is the carry-reset terminal.

[0198] Optionally, the first node control circuit includes a first control transistor; the gate of the first control transistor is electrically connected to a first pull-up start control terminal, the first terminal of the first control transistor is electrically connected to the gate or a third voltage terminal of the first control transistor, and the second terminal of the first control transistor is electrically connected to the first node; or,

[0199] The first node control circuit includes at least two control transistors, namely a first control transistor and a second control transistor. The gate of the first control transistor is electrically connected to a first pull-up start control terminal. The first terminal of the first control transistor is electrically connected to a first pull-up start control terminal, a second pull-up start control terminal, or a third voltage terminal. The gate of the second control transistor is electrically connected to a second pull-up start control terminal. The first terminal of the second control transistor is electrically connected to the second terminal of the first control transistor. The second terminal of the second control transistor is electrically connected to the first node. Alternatively...

[0200] The first node control circuit includes at least three control transistors, namely a first control transistor, a second control transistor, and a third control transistor. The gate of the first control transistor is electrically connected to a first pull-up start control terminal. The first terminal of the first control transistor is electrically connected to a first pull-up start control terminal, a second pull-up start control terminal, a third pull-up start control terminal, or a third voltage terminal. The gate of the second control transistor is electrically connected to a second pull-up start control terminal, and the first terminal of the second control transistor is electrically connected to the second terminal of the first control transistor. The gate of the third control transistor is electrically connected to a third pull-up start control terminal, and the first terminal of the third control transistor is electrically connected to the second terminal of the second control transistor. The second terminal of the third control transistor is electrically connected to the first node.

[0201] Optionally, the third voltage terminal can be a high-level terminal.

[0202] As shown in Figure 10A, the first node control circuit may include a first control transistor MC1;

[0203] The gate and source of MC1 are electrically connected to the first pull-up start control terminal STU1, and the drain of MC1 is electrically connected to the first node PU.

[0204] In at least one embodiment shown in FIG10A, MC1 is an n-type transistor, but is not limited thereto.

[0205] In at least one embodiment of the first node control circuit shown in Figure 10A, when STU1 provides a high voltage signal, MC1 is turned on and the potential of PU is high.

[0206] When STU1 provides a low voltage signal, MC1 is turned off, and the potential of PU is low.

[0207] As shown in Figure 10B, the first node control circuit may include a first control transistor MC1;

[0208] The gate of MC1 is electrically connected to the first pull-up start control terminal STU1, the source of MC1 is electrically connected to the high-level terminal VGH, and the drain of MC1 is electrically connected to the first node PU.

[0209] In at least one embodiment shown in FIG10B, MC1 is an n-type transistor, but is not limited thereto.

[0210] In at least one embodiment of the first node control circuit shown in Figure 10B, when STU1 provides a high voltage signal, MC1 is turned on and the potential of PU is high.

[0211] When STU1 provides a low voltage signal, MC1 is turned off, and the potential of PU is low.

[0212] As shown in Figure 10C, the first node control circuit may include a first first control transistor MC11 and a second first control transistor MC21;

[0213] The gate and source of MC11 are both electrically connected to the first pull-up start control terminal STU1, and the drain of MC11 is electrically connected to the source of MC21.

[0214] The gate of MC21 is electrically connected to the second pull-up start control terminal STU2, and the drain of MC21 is electrically connected to the first node PU.

[0215] In at least one embodiment shown in Figure 10C, MC11 and MC21 are both n-type transistors, but this is not a limitation.

[0216] In at least one embodiment of the first node control circuit shown in Figure 10C, when STU1 and STU2 both provide high voltage signals, MC11 and MC21 are both turned on, and the potential of PU is high voltage.

[0217] When STU1 provides a high voltage signal and STU2 provides a low voltage signal, MC11 is turned on and MC21 is turned off, and the potential of PU is low voltage.

[0218] When STU1 provides a low voltage signal and STU2 provides a high voltage signal, MC11 is turned off and MC21 is turned on, and the potential of PU is low voltage.

[0219] When STU1 provides a low voltage signal and STU2 provides a low voltage signal, MC11 is turned off and MC21 is turned off, and the potential of PU is low voltage.

[0220] As shown in Figure 10D, the first node control circuit may include a first first control transistor MC11 and a second first control transistor MC21;

[0221] The gate of MC11 is electrically connected to the first pull-up start control terminal STU1, the source of MC11 is electrically connected to the gate of MC2, and the drain of MC11 is electrically connected to the source of MC21.

[0222] The gate of MC21 is electrically connected to the second pull-up start control terminal STU2, and the drain of MC21 is electrically connected to the first node PU.

[0223] In at least one embodiment shown in Figure 10D, MC11 and MC21 are both n-type transistors, but this is not a limitation.

[0224] In at least one embodiment of the first node control circuit shown in Figure 10D, when STU1 and STU2 both provide high voltage signals, MC11 and MC21 are both turned on, and the potential of PU is high voltage.

[0225] When STU1 provides a high voltage signal and STU2 provides a low voltage signal, MC11 is turned on and MC21 is turned off, and the potential of PU is low voltage.

[0226] When STU1 provides a low voltage signal and STU2 provides a high voltage signal, MC11 is turned off and MC21 is turned on, and the potential of PU is low voltage.

[0227] When STU1 provides a low voltage signal and STU2 provides a low voltage signal, MC11 is turned off and MC21 is turned off, and the potential of PU is low voltage.

[0228] As shown in Figure 10E, the first node control circuit may include a first first control transistor MC11 and a second first control transistor MC21.

[0229] The gate of MC11 is electrically connected to the first pull-up start control terminal STU1, the source of MC11 is electrically connected to the high-level terminal VGH, and the drain of MC11 is electrically connected to the source of MC21.

[0230] The gate of MC21 is electrically connected to the second pull-up start control terminal STU2, and the drain of MC21 is electrically connected to the first node PU.

[0231] In at least one embodiment shown in Figure 10E, MC11 and MC21 are both n-type transistors, but this is not a limitation.

[0232] In at least one embodiment of the first node control circuit shown in Figure 10E, when both STU1 and STU2 provide high voltage signals, MC11 and MC21 are both turned on, and the potential of PU is high voltage.

[0233] When STU1 provides a high voltage signal and STU2 provides a low voltage signal, MC11 is turned on and MC21 is turned off, and the potential of PU is low voltage.

[0234] When STU1 provides a low voltage signal and STU2 provides a high voltage signal, MC11 is turned off and MC21 is turned on, and the potential of PU is low voltage.

[0235] When STU1 provides a low voltage signal and STU2 provides a low voltage signal, MC11 is turned off and MC21 is turned off, and the potential of PU is low voltage.

[0236] As shown in Figure 10F, the first node control circuit may include a first first control transistor MC11, a second first control transistor MC21 and a third first control transistor MC31;

[0237] The gate and source of MC11 are both electrically connected to the first pull-up start control terminal STU1, and the drain of MC11 is electrically connected to the source of MC21.

[0238] The gate of MC21 is electrically connected to the second pull-up start control terminal STU2, and the drain of MC21 is electrically connected to the source of MC31.

[0239] The gate of MC31 is electrically connected to the third pull-up start control terminal STU3, and the drain of MC31 is electrically connected to the first node PU.

[0240] In at least one embodiment shown in Figure 10F, MC11, MC21 and MC31 are all n-type transistors, but are not limited thereto.

[0241] As shown in Figure 10G, the first node control circuit may include a first first control transistor MC11, a second first control transistor MC21 and a third first control transistor MC31.

[0242] The gate of MC11 is electrically connected to the first pull-up start control terminal STU1, the source of MC11 is electrically connected to the gate of MC21, and the drain of MC11 is electrically connected to the source of MC21.

[0243] The gate of MC21 is electrically connected to the second pull-up start control terminal STU2, and the drain of MC21 is electrically connected to the source of MC31.

[0244] The gate of MC31 is electrically connected to the third pull-up start control terminal STU3, and the drain of MC31 is electrically connected to the first node PU.

[0245] In at least one embodiment shown in Figure 10G, MC11, MC21 and MC31 are all n-type transistors, but are not limited thereto.

[0246] As shown in Figure 10H, the first node control circuit may include a first first control transistor MC11, a second first control transistor MC21 and a third first control transistor MC31;

[0247] The gate of MC11 is electrically connected to the first pull-up start control terminal STU1, the source of MC11 is electrically connected to the gate of MC31, and the drain of MC11 is electrically connected to the source of MC21.

[0248] The gate of MC21 is electrically connected to the second pull-up start control terminal STU2, and the drain of MC21 is electrically connected to the source of MC31.

[0249] The gate of MC31 is electrically connected to the third pull-up start control terminal STU3, and the drain of MC31 is electrically connected to the first node PU.

[0250] In at least one embodiment shown in Figure 10H, MC11, MC21 and MC31 are all n-type transistors, but are not limited thereto.

[0251] As shown in Figure 10I, the first node control circuit may include a first first control transistor MC11, a second first control transistor MC21 and a third first control transistor MC31;

[0252] The gate of MC11 is electrically connected to the first pull-up start control terminal STU1, the source of MC11 is electrically connected to the high-level terminal VGH, and the drain of MC11 is electrically connected to the source of MC21.

[0253] The gate of MC21 is electrically connected to the second pull-up start control terminal STU2, and the drain of MC21 is electrically connected to the source of MC31.

[0254] The gate of MC31 is electrically connected to the third pull-up start control terminal STU3, and the drain of MC31 is electrically connected to the first node PU.

[0255] In at least one embodiment shown in Figure 10I, MC11, MC21 and MC31 are all n-type transistors, but are not limited thereto.

[0256] In at least one embodiment of the first node control circuit shown in Figures 10F-10I, when STU1, STU2 and STU3 all provide high voltage signals, MC11, MC21 and MC31 are all turned on, and the potential of PU is high voltage.

[0257] When STU1 provides a high voltage signal, STU2 provides a high voltage signal, and STU3 provides a low voltage signal, MC11 and MC21 are turned on, MC31 is turned off, and the potential of PU is low voltage.

[0258] When STU1 provides a high voltage signal, STU2 provides a low voltage signal, and STU3 provides a high voltage signal, MC11 and MC31 are turned on, MC21 is turned off, and the potential of PU is low voltage.

[0259] When STU1 provides a high voltage signal, STU2 provides a low voltage signal, and STU3 provides a low voltage signal, MC11 is turned on, MC21 and MC31 are turned off, and the potential of PU is low voltage.

[0260] When STU1 provides a low voltage signal, STU2 provides a high voltage signal, and STU3 provides a high voltage signal, MC11 is turned off, MC21 and MC31 are turned on, and the potential of PU is low voltage.

[0261] When STU1 provides a low voltage signal, STU2 provides a high voltage signal, and STU3 provides a low voltage signal, MC21 is turned on, MC11 and MC31 are turned off, and the potential of PU is low voltage.

[0262] When STU1 provides a low voltage signal, STU2 provides a low voltage signal, and STU3 provides a high voltage signal, MC31 is turned on, MC11 and MC21 are turned off, and the potential of PU is low voltage.

[0263] When STU1 provides a low voltage signal, STU2 provides a low voltage signal, and STU3 provides a low voltage signal, MC11 is turned off, MC21 and MC31 are turned off, and the potential of PU is low voltage.

[0264] In at least one embodiment of this disclosure, the first node reset circuit includes a second control transistor; the gate of the second control transistor is electrically connected to a first pull-down start control terminal, the first terminal of the second control transistor is electrically connected to the first node, and the second terminal of the second control transistor is electrically connected to a first voltage terminal; or,

[0265] The first node reset circuit includes at least two control transistors, specifically a first second control transistor and a second second control transistor. The gate of the first second control transistor is electrically connected to a first pull-down start control terminal. The first terminal of the first second control transistor is electrically connected to the first node. The second terminal of the first second control transistor is electrically connected to the first terminal of the second second control transistor. The gate of the second second control transistor is electrically connected to a second pull-down start control terminal. The second terminal of the second second control transistor is electrically connected to a first voltage terminal. Alternatively...

[0266] The first node reset circuit includes at least three control transistors, namely a first second control transistor, a second second control transistor, and a third second control transistor. The gate of the first second control transistor is electrically connected to a first pull-down start control terminal, the first terminal of the first second control transistor is electrically connected to a first node, the second terminal of the first second control transistor is electrically connected to the first terminal of the second second control transistor, the gate of the second second control transistor is electrically connected to a second pull-down start control terminal, the second terminal of the second second control transistor is electrically connected to the first terminal of the third second control transistor, the gate of the third second control transistor is electrically connected to a third pull-down start control terminal, and the second terminal of the third second control transistor is electrically connected to a first voltage terminal.

[0267] As shown in Figure 11A, the first node reset circuit may include a second control transistor MC2;

[0268] The gate of MC2 is electrically connected to the first pull-down start control terminal STD1, the source of MC2 is electrically connected to the first node PU, and the drain of MC2 is electrically connected to the low voltage terminal VGL.

[0269] In at least one embodiment shown in FIG11A, MC2 is an n-type transistor, but is not limited thereto.

[0270] As shown in Figure 11B, the first node reset circuit may include a first second control transistor MC12 and a second second control transistor MC22.

[0271] The gate of MC12 is electrically connected to the first pull-down start control terminal STD1, the source of MC12 is electrically connected to the first node PU, and the drain of MC12 is electrically connected to the source of MC22.

[0272] The gate of MC22 is electrically connected to the second pull-down start control terminal STD2, and the drain of MC22 is electrically connected to the low voltage terminal VGL.

[0273] In at least one embodiment shown in Figure 11B, MC12 and MC22 are n-type transistors, but are not limited thereto.

[0274] As shown in Figure 11C, the first node reset circuit may include a first second control transistor MC12, a second second control transistor MC22, and a third second control transistor MC31.

[0275] The gate of MC12 is electrically connected to the first pull-down start control terminal STD1, the source of MC12 is electrically connected to the first node PU, and the drain of MC12 is electrically connected to the source of MC22.

[0276] The gate of MC22 is electrically connected to the second pull-down start control terminal STD2, and the drain of MC22 is electrically connected to the source of MC32.

[0277] The gate of MC32 is electrically connected to the third pull-down start control terminal STD3, and the drain of MC32 is electrically connected to the low voltage terminal VGL.

[0278] In at least one embodiment shown in Figure 11C, MC12, MC22 and MC32 are n-type transistors, but are not limited thereto.

[0279] In at least one embodiment of this disclosure, the effective display area of ​​the display panel can be divided into at least two fixed display areas along the scanning direction. The number of fixed display areas and the number of rows of pixel circuits disposed in the fixed display areas are determined according to the actual needs of the display product.

[0280] In specific implementation, when the circuit structure of the first node control circuit is as shown in Figures 10A and 10B, and the circuit structure of the first node reset circuit is as shown in Figure 11A, when the driving circuit includes b start control terminals, the number of fixed display areas is the integer obtained by dividing b by 2; b is a positive integer.

[0281] When the circuit structure of the first node control circuit is as shown in Figures 10C-10E, and the circuit structure of the first node reset circuit is as shown in Figure 11B, when the driving circuit includes b start control terminals, the number of fixed display areas is an integer obtained by dividing c by 2; where c is the number of combinations of selecting 2 start control terminals from the b start control terminals.

[0282] When the circuit structure of the first node control circuit is as shown in Figures 10F-10I, and the circuit structure of the first node reset circuit is as shown in Figure 11C, when the driving circuit includes b start control terminals, the number of fixed display areas is the integer obtained by dividing d by 2, where d is the number of combinations of selecting 3 start control terminals from the b start control terminals.

[0283] As shown in Figures 12A, 12B and 12C, the effective display area may include a first display area A1, a second display area A2 and a third display area A3 arranged sequentially from top to bottom;

[0284] As shown in Figures 12D and 12E, the effective display area may include a first display area A1, a second display area A2, a third display area A3, and a fourth display area A4, arranged sequentially from top to bottom. That is, the effective display area can be divided into multiple areas of the same or different areas.

[0285] As shown in Figure 13, for example, when the effective display area is divided into five display areas: the first display area, the second display area, the third display area, the fourth display area, and the fifth display area,

[0286] The multiple driving circuits corresponding to the first display area are: the first driving circuit GA1 to the i-th driving circuit GAi; i is a positive integer, i is greater than 1;

[0287] The multi-level driving circuit corresponding to the second display area is as follows: the (i+1)th driving circuit GAi+1 to the jth driving circuit GAj; j is a positive integer, and j is greater than i+1;

[0288] The multi-level driving circuit corresponding to the third display area is: the (j+1)th driving circuit GAj+1 to the (k)th driving circuit GAk; k is a positive integer, and k is greater than j+1;

[0289] The multi-level driving circuit corresponding to the fourth display area is as follows: the (k+1)th driving circuit GAk+1 to the Lth driving circuit GAL; L is a positive integer, and L is greater than k+1;

[0290] The multi-level driving circuit corresponding to the fifth display area is: the L+1th driving circuit GAL+1 to the mth driving circuit GAm; m is a positive integer, and m is greater than L+1;

[0291] GA1 to Gai are at least partially cascaded with each other; GAi+1 to GAj are at least partially cascaded with each other; GAj+1 to GAk are at least partially cascaded with each other; GAk+1 to GAL are at least partially cascaded with each other; GAL+1 to GAm are at least partially cascaded with each other.

[0292] The driving circuits corresponding to different display areas are not cascaded with each other;

[0293] The structure of the first-stage driving circuit in the multi-stage driving circuit corresponding to each display area is different from the structure of the intermediate-stage driving circuit in the multi-stage driving circuit corresponding to that display area.

[0294] The structure of the last stage driving circuit in the multi-stage driving circuit corresponding to each display area is different from the structure of the intermediate stage driving circuit in the multi-stage driving circuit corresponding to that display area.

[0295] The structure of the first-stage driving circuit in the multi-stage driving circuit corresponding to each display area is different from the structure of the last-stage driving circuit in the multi-stage driving circuit corresponding to that display area.

[0296] In at least one embodiment shown in FIG13, the number of partitions in the display area is the same as the number of start control terminals. For example, referring to FIG13, there are five partitions containing five start control terminals. That is, the driving circuit may include a first start control terminal STV1, a second start control terminal STV2, a third start control terminal STV3, a fourth start control terminal STV4, and a fifth start control terminal STV5.

[0297] In the first display area, GA1, the first pull-up start control terminal is electrically connected to the first start control terminal STV1, and the second pull-up start control terminal is electrically connected to the third start control terminal STV3.

[0298] In GAI, the first pull-down start control terminal is electrically connected to the first start control terminal STV1, and the second pull-down start control terminal is electrically connected to the second start control terminal STV2.

[0299] In the second display area, GAi+1, the first pull-up start control terminal is electrically connected to the second start control terminal STV2, and the second pull-up start control terminal is electrically connected to the fourth start control terminal STV4.

[0300] In GAj, the first pull-down start control terminal is electrically connected to the second start control terminal STV2, and the second pull-down start control terminal is electrically connected to the third start control terminal STV3.

[0301] In the third display area, GAj+1, the first pull-up start control terminal is electrically connected to the third start control terminal STV3, and the second pull-up start control terminal is electrically connected to the fifth start control terminal STV5.

[0302] In GAk, the first pull-down start control terminal is electrically connected to the third start control terminal STV3, and the second pull-down start control terminal is electrically connected to the fourth start control terminal STV4.

[0303] In the fourth display area, in GAk+1, the first pull-up start control terminal is electrically connected to the fourth start control terminal STV4, and the second pull-up start control terminal is electrically connected to the first start control terminal STV1.

[0304] In GAL, the first pull-down start control terminal is electrically connected to the fourth start control terminal STV4, and the second pull-down start control terminal is electrically connected to the fifth start control terminal STV5.

[0305] In the fifth display area, in GAL+1, the first pull-up start control terminal is electrically connected to the fifth start control terminal STV5, and the second pull-up start control terminal is electrically connected to the second start control terminal STV2.

[0306] In GAm, the first pull-down start control terminal is electrically connected to the fifth start control terminal STV5, and the second pull-down start control terminal is electrically connected to the first start control terminal STV1.

[0307] In Figure 13, GA2 is the second driving circuit, GA3 is the third driving circuit, GAI+2 is the (i+2)th driving circuit, GAI+3 is the (i+3)th driving circuit, GAj+2 is the (j+2)th driving circuit, GAI+3 is the (j+3)th driving circuit, GAk+2 is the (k+2)th driving circuit, GAk+3 is the (k+3)th driving circuit, GAL+2 is the (k+2)th driving circuit, and GAL+3 is the (k+3)th driving circuit.

[0308] As shown in Figure 14, in the first-level driving circuit of the multi-level driving circuit corresponding to each display area, the first node control circuit may include a first first control transistor MC11 and a second first control transistor MC21; the first node reset circuit may include a second control transistor MC2.

[0309] The gate and source of MC11 are both electrically connected to the first pull-up start control terminal STU1, and the drain of MC11 is electrically connected to the source of MC21.

[0310] The gate of MC21 is electrically connected to the second pull-up start control terminal STU2, and the drain of MC21 is electrically connected to the first node PU.

[0311] The first node reset circuit may include a second control transistor MC2;

[0312] The gate of MC2 is electrically connected to the second control terminal SC2, the source of MC2 is electrically connected to the first node PU, and the drain of MC2 is electrically connected to the low voltage terminal.

[0313] The first-stage driving circuit in the multi-stage driving circuit may further include a second node control circuit, a reset circuit, an output circuit, and a first energy storage circuit.

[0314] The second node control circuit includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18; the reset circuit includes the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21; the output circuit includes the twenty-second transistor M22 and the twenty-third transistor M23; and the first energy storage circuit includes the third capacitor C3.

[0315] The gate and source of M15 are both electrically connected to the high-voltage terminal GCH, and the source of M15 is electrically connected to the gate of M17.

[0316] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the gate of M17, and the drain of M16 is electrically connected to the low voltage terminal VGL.

[0317] The source of M17 is electrically connected to the high-voltage terminal GCH, and the drain of M17 is electrically connected to the second node PD.

[0318] The gate of M18 is electrically connected to the first node PU, the source of M18 is electrically connected to the second node PD, and the drain of M18 is electrically connected to the low voltage terminal VGL.

[0319] The gate of M19 is electrically connected to the second node PD, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the low voltage terminal VGL.

[0320] The gate of M20 is electrically connected to the frame reset line STV0, the source of M20 is electrically connected to the first node PU, and the drain of M20 is electrically connected to the low voltage terminal VGL.

[0321] The gate of M21 is electrically connected to the frame reset line STV0, the source of M21 is electrically connected to the drive signal output terminal GT, and the drain of M21 is electrically connected to the low voltage terminal VGL.

[0322] The gate of M22 is electrically connected to the first node PU, the source of M22 is electrically connected to the output clock signal terminal CLKO, and the drain of M22 is electrically connected to the drive signal output terminal GT.

[0323] The gate of M23 is electrically connected to the second node PD, the source of M23 is electrically connected to the drive signal output terminal GT, and the drain of M23 is electrically connected to the low voltage terminal VGL.

[0324] The first end of C3 is electrically connected to the first node PU, and the second end of C3 is electrically connected to the drive signal output terminal GT.

[0325] In at least one embodiment shown in Figure 14, SC2 is connected to the output terminal of the next stage driving circuit in the multi-stage driving circuit. It can be the next stage, the next two stages, or the next multiple stages. For example, it is connected to the output terminal of the next stage driving circuit, that is, SC2 is electrically connected to the driving signal output terminal of the second stage driving circuit in the multi-stage driving circuit.

[0326] All transistors are n-type transistors, but this is not a limitation.

[0327] As shown in Figure 15, in the last stage of the multi-stage driving circuit corresponding to each display area, the first node control circuit may include a first control transistor MC1; the first node reset circuit may include a first second control transistor MC12 and a second second control transistor M22.

[0328] The gate and source of MC1 are both electrically connected to the first control terminal SC1, and the drain of MC1 is electrically connected to the first node PU; the gate of MC1 is electrically connected to the GT terminal of the previous stage or multiple stages of the driving circuit.

[0329] The gate of MC12 is electrically connected to the first pull-down start control terminal STD1, the source of MC12 is electrically connected to the first node PU, and the drain of MC12 is electrically connected to the source of MC22.

[0330] The gate of MC22 is electrically connected to the second pull-down start control terminal STD2, and the drain of MC22 is electrically connected to the low voltage terminal VGL.

[0331] The first-stage driving circuit in the multi-stage driving circuit may further include a second node control circuit, a reset circuit, an output circuit, and a first energy storage circuit.

[0332] The second node control circuit includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18; the reset circuit includes the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21; the output circuit includes the twenty-second transistor M22 and the twenty-third transistor M23; and the first energy storage circuit includes the third capacitor C3.

[0333] The gate and source of M15 are both electrically connected to the high-voltage terminal GCH, and the source of M15 is electrically connected to the gate of M17.

[0334] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the gate of M17, and the drain of M16 is electrically connected to the low voltage terminal VGL.

[0335] The source of M17 is electrically connected to the high-voltage terminal GCH, and the drain of M17 is electrically connected to the second node PD.

[0336] The gate of M18 is electrically connected to the first node PU, the source of M18 is electrically connected to the second node PD, and the drain of M18 is electrically connected to the low voltage terminal VGL.

[0337] The gate of M19 is electrically connected to the second node PD, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the low voltage terminal VGL.

[0338] The gate of M20 is electrically connected to the frame reset line STV0, the source of M20 is electrically connected to the first node PU, and the drain of M20 is electrically connected to the low voltage terminal VGL.

[0339] The gate of M21 is electrically connected to the frame reset line STV0, the source of M21 is electrically connected to the drive signal output terminal GT, and the drain of M21 is electrically connected to the low voltage terminal VGL.

[0340] The gate of M22 is electrically connected to the first node PU, the source of M22 is electrically connected to the output clock signal terminal CLKO, and the drain of M22 is electrically connected to the drive signal output terminal GT.

[0341] The gate of M23 is electrically connected to the second node PD, the source of M23 is electrically connected to the drive signal output terminal GT, and the drain of M23 is electrically connected to the low voltage terminal VGL.

[0342] The first end of C3 is electrically connected to the first node PU, and the second end of C3 is electrically connected to the drive signal output terminal GT.

[0343] In at least one embodiment shown in Figure 15, SC1 is electrically connected to the drive signal output terminal GT of the penultimate drive circuit in the multi-stage drive circuit.

[0344] All transistors are n-type transistors, but this is not a limitation.

[0345] As shown in Figure 16, in the intermediate stage driving circuit of the multi-stage driving circuit corresponding to each display area, the first node control circuit may include a first control transistor MC1; the first node reset circuit may include a second control transistor MC2.

[0346] The gate and source of MC1 are both electrically connected to the first control terminal SC1, and the drain of MC1 is electrically connected to the first node PU; the gate of MC1 is electrically connected to the drive signal output terminal GT of the previous stage or multiple stages of the drive circuit.

[0347] The gate of MC2 is electrically connected to the second control terminal SC2, the source of MC2 is electrically connected to the first node PU, and the drain of MC2 is electrically connected to the low voltage terminal VGL.

[0348] The first-stage driving circuit in the multi-stage driving circuit may further include a second node control circuit, a reset circuit, an output circuit, and a first energy storage circuit.

[0349] The second node control circuit includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18; the reset circuit includes the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21; the output circuit includes the twenty-second transistor M22 and the twenty-third transistor M23; and the first energy storage circuit includes the third capacitor C3.

[0350] The gate and source of M15 are both electrically connected to the high-voltage terminal GCH, and the source of M15 is electrically connected to the gate of M17.

[0351] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the gate of M17, and the drain of M16 is electrically connected to the low voltage terminal VGL.

[0352] The source of M17 is electrically connected to the high-voltage terminal GCH, and the drain of M17 is electrically connected to the second node PD.

[0353] The gate of M18 is electrically connected to the first node PU, the source of M18 is electrically connected to the second node PD, and the drain of M18 is electrically connected to the low voltage terminal VGL.

[0354] The gate of M19 is electrically connected to the second node PD, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the low voltage terminal VGL.

[0355] The gate of M20 is electrically connected to the frame reset line STV0, the source of M20 is electrically connected to the first node PU, and the drain of M20 is electrically connected to the low voltage terminal VGL.

[0356] The gate of M21 is electrically connected to the frame reset line STV0, the source of M21 is electrically connected to the drive signal output terminal GT, and the drain of M21 is electrically connected to the low voltage terminal VGL.

[0357] The gate of M22 is electrically connected to the first node PU, the source of M22 is electrically connected to the output clock signal terminal CLKO, and the drain of M22 is electrically connected to the drive signal output terminal GT.

[0358] The gate of M23 is electrically connected to the second node PD, the source of M23 is electrically connected to the drive signal output terminal GT, and the drain of M23 is electrically connected to the low voltage terminal VGL.

[0359] The first end of C3 is electrically connected to the first node PU, and the second end of C3 is electrically connected to the drive signal output terminal GT.

[0360] In at least one embodiment shown in Figure 16, SC1 is electrically connected to the drive signal output terminal of the previous stage drive circuit adjacent to the intermediate stage drive circuit, and SC2 is electrically connected to the drive signal output terminal of the next stage drive circuit adjacent to the intermediate stage drive circuit.

[0361] All transistors are n-type transistors, but this is not a limitation.

[0362] In other words, within the multi-stage driving circuits of each display area, the only differences between the first-stage driving circuit, intermediate-stage driving circuit, and final-stage driving circuit can be the first-node control circuit and the first-node reset circuit; the rest of the driving circuits are identical. This simplifies the manufacturing process while enabling localized display in any area.

[0363] In at least one embodiment shown in Figure 13, when the multi-level driving circuit corresponding to the effective display area refreshes line by line from the first-level driving circuit to the last-level driving circuit, the corresponding start control signal is pulled high according to the corresponding position to realize input and reset actions, ensuring that each level of driving circuit can scan continuously. The timing of the first start control signal provided by the first start control terminal STV1, the timing of the second start control signal provided by the second start control terminal STV2, the timing of the third start control signal provided by the third start control terminal STV3, the timing of the fourth start control signal provided by the fourth start control terminal STV4, and the timing of the fifth start control signal provided by the fifth start control terminal STV5 are shown in Figure 18.

[0364] Considering the phase relationship of adjacent row driving circuits in adjacent display areas, the input stage of the first-stage driving circuit in the second display area should be before the reset stage of the last-stage driving circuit in the first display area; the input stage of the first-stage driving circuit in the third display area should be before the reset stage of the last-stage driving circuit in the second display area; the input stage of the first-stage driving circuit in the fourth display area should be before the reset stage of the last-stage driving circuit in the third display area; and the input stage of the first-stage driving circuit in the fifth display area should be before the reset stage of the last-stage driving circuit in the fourth display area.

[0365] In at least one embodiment shown in Figure 13, the output clock signal terminal of the odd-numbered stage driving circuit can be electrically connected to the first clock signal line CLK, and the output clock signal terminal of the even-numbered stage driving circuit can be electrically connected to the second clock signal line CLKB. Of course, the number of clock signal lines corresponding to the output clock signal terminal is not specifically limited, and can be 2, 4, 6, 8, 10, 12, 14, 16, etc.

[0366] Figure 17 is a timing diagram of the normal display refresh during one frame display time in operation of at least one embodiment shown in Figure 13.

[0367] In Figure 17, SI1 is the first input stage, SR1 is the first reset stage, SI2 is the second input stage, SR2 is the second reset stage, SI3 is the third input stage, SR3 is the third reset stage, SI4 is the fourth input stage, SR4 is the fourth reset stage, SI5 is the fifth input stage, and SR5 is the fifth reset stage.

[0368] In the first input stage, SI1, STV1 and STV3 provide high voltage signals, and the potential of the first node in GA1 is pulled high;

[0369] During the first reset phase, SR1, STV1, and STV2 provide high voltage signals, and the potential of the first node in GAi is reset.

[0370] During the time period between the first reset phase SI1 and the first reset phase SR1, the intermediate driving circuit in the multi-level driving circuit corresponding to the first display area sequentially refreshes the display.

[0371] In the second input stage, SI2, STV2 and STV4 provide high voltage signals, and the potential of the first node in GAi+1 is pulled high;

[0372] During the second reset phase, SR2, STV2 and STV3 all provide high voltage signals, and the potential of the first node in GAj is reset.

[0373] During the time period between the second reset phase SI2 and the second reset phase SR2, the intermediate driving circuit in the multi-level driving circuit corresponding to the second display area sequentially refreshes the display.

[0374] In the third input stage, SI3, STV3 and STV5 provide high voltage signals, and the potential of the first node in GAj+1 is pulled high.

[0375] During the third reset phase, SR3, STV3 and STV4 all provide high voltage signals, and the potential of the first node in GAk is reset.

[0376] During the time period between the third reset phase SI3 and the third reset phase SR3, the intermediate driving circuit in the multi-level driving circuit corresponding to the third display area sequentially refreshes the display.

[0377] In the fourth input stage, SI4, STV4 and STV1 all provide high voltage signals, and the potential of the first node in GAk+1 is pulled high.

[0378] In the fourth reset phase, SR4, STV4 and STV5 all provide high voltage signals, and the potential of the first node in GAL is reset.

[0379] During the time period between the fourth reset phase SI4 and the fourth reset phase SR4, the intermediate driving circuit in the multi-level driving circuit corresponding to the fourth display area sequentially refreshes the display.

[0380] In the fifth input stage, SI5, STV5 and STV2 all provide high voltage signals, and the potential of the first node in GAL+1 is pulled high.

[0381] During the fifth reset phase, SR5, STV5 and STV1 all provide high voltage signals, and the first node in GAm is reset.

[0382] During the time period between the fifth reset phase SI5 and the fifth reset phase SR5, the intermediate driving circuit in the multi-level driving circuit corresponding to the fifth display area sequentially refreshes the display.

[0383] In Figure 17, the node labeled PDi+1 is the second node in GAI+1, and the node labeled PUi+1 is the first node in GAI+1.

[0384] The following terminals are designated as drive signal outputs: GT1 for GA1, GT2 for GA2, GT3 for GA3, GTi-1 for GAI-1, GTi for GAI, GTi+1 for GAI+1, GTj-1 for GAj-1, GTj for GAj, and GTj+1 for GAj+1. The terminal labeled G... Tk-1 is the drive signal output terminal for GAk-1, GTk is the drive signal output terminal for GAk, GTk+1 is the drive signal output terminal for GAk+1, GTL-1 is the drive signal output terminal for GAL-1, GTL is the drive signal output terminal for GAL, GTL+1 is the drive signal output terminal for GAL+1, GTm-1 is the drive signal output terminal for GAm-1, GTm is the drive signal output terminal for GAm, and GTm+1 is the drive signal output terminal for GAm+1.

[0385] When at least one embodiment shown in Figure 13 is in operation, and flexible or local display is performed as shown in Figure 18, and the refreshed area is repeatedly displayed within the second display area A2, the working timing diagram is shown in Figure 19.

[0386] In Figure 18, the effective display area includes a first display area A1, a second display area A2, a third display area A3, a fourth display area A4, and a fifth display area A5 arranged from top to bottom.

[0387] In Figure 19, the time of frame a is labeled Fa, the time of frame a+1 is labeled Fa+1, the time of frame a+2 is labeled Fa+2, and the time of frame a+3 is labeled Fa+3, where a is a positive integer.

[0388] The time Fa of frame a includes the first second input stage SI12 and the first second reset stage SR12 set sequentially; the time Fa+1 of frame a+1 includes the second second input stage SI22 and the second second reset stage SR22 set sequentially; the time Fa+2 of frame a+2 includes the third second input stage SI32 and the third second reset stage SR32 set sequentially; and the time Fa+3 of frame a+3 includes the fourth second input stage SI42 and the fourth second reset stage SR42 set sequentially.

[0389] In SI12, SI22, SI32 and SI42, STV2 and STV4 provide high voltage signals, and the potential of the first node in GAi+1 is pulled high;

[0390] High voltage signals are provided in SR12, SR22, SR32 and SR42, STV2 and STV3, and the potential of the first node in GAj is reset;

[0391] During the time period between SI12 and SR12, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0392] During the time period between SI22 and SR22, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0393] During the time period between SI32 and SR32, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0394] During the time period between SI42 and SR42, at least a portion of the intermediate-level driving circuits in the multi-level driving circuit corresponding to the second display area sequentially refresh the display.

[0395] In practical implementation, when the area requiring high-frequency refresh happens to be within a certain display area (taking the second display area as an example), multiple refreshes can be performed only on the second display area. Since the driving circuits corresponding to other display areas have no high-level input, the potential at the output terminal of the driving signal remains low. Because only one display area is refreshed, the refresh time is shortened, which can increase the frequency of local refresh.

[0396] When at least one embodiment shown in Figure 13 is in operation, and flexible display is performed as shown in Figure 20, and the refreshed display area is repeatedly displayed within the second display area A2 and the third display area A3, the working timing diagram is shown in Figure 21.

[0397] In Figure 20, the effective display area includes a first display area A1, a second display area A2, a third display area A3, a fourth display area A4, and a fifth display area A5 arranged from top to bottom.

[0398] In Figure 21, the time of frame a is labeled Fa, the time of frame a+1 is labeled Fa+1, the time of frame a+2 is labeled Fa+2, and the time of frame a+3 is labeled Fa+3, where a is a positive integer.

[0399] The time Fa of frame a includes the first second input stage SI12, the first third input stage SI13, the first second reset stage SR12, and the first third reset stage SR13, which are set sequentially.

[0400] The time Fa+1 of frame a+1 includes the second second input stage SI22, the second third input stage SI23, the second second reset stage SR22, and the second third reset stage SR23, which are set sequentially.

[0401] The time Fa+2 of frame a+2 includes the third second input stage SI32, the third third input stage SI33, the third second reset stage SR32 and the third third reset stage SR33 set sequentially.

[0402] The time Fa+3 of frame a+3 includes the fourth second input stage SI42, the fourth third input stage SI43, the fourth second reset stage SR42, and the fourth third reset stage SR43, which are set sequentially.

[0403] In SI12, SI22, SI32 and SI42, STV2 and STV4 provide high voltage signals, and the potential of the first node in GAi+1 is pulled high;

[0404] High voltage signals are provided in SR12, SR22, SR32 and SR42, STV2 and STV3, and the potential of the first node in GAj is reset;

[0405] During the time period between SI12 and SR12, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0406] During the time period between SI22 and SR22, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0407] During the time period between SI32 and SR32, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0408] During the time period between SI42 and SR42, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0409] High voltage signals are provided in SI13, SI23, SI33 and SI43, STV3 and STV5, and the potential of the first node in GAj+1 is pulled high.

[0410] In SR13, SR23, SR33 and SR43, STV3 and STV3 both provide high voltage signals, and the potential of the first node in GAk is reset;

[0411] During the time period between SI13 and SR13, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the third display area sequentially refresh the display.

[0412] During the time period between SI23 and SR23, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the third display area sequentially refresh the display.

[0413] During the time period between SI33 and SR33, at least a portion of the intermediate-level driving circuit in the multi-level driving circuit corresponding to the third display area sequentially refreshes the display.

[0414] During the time period between SI43 and SR43, at least a portion of the intermediate-level driving circuits in the multi-level driving circuit corresponding to the third display area sequentially refresh the display.

[0415] When a high-frequency refresh rate is required across two or more display areas (taking the second and third display areas as an example), only the drive circuits corresponding to the second and third display areas need to be refreshed multiple times. Since the drive circuits for other display areas have no high-level input, their drive signal outputs remain consistently low. Because only two display areas are refreshed, the refresh time is shortened, allowing for an increase in the frequency of partial refreshes.

[0416] When at least one embodiment shown in Figure 13 is in operation, and flexible display is performed as shown in Figure 22, and the refreshed display area is repeatedly displayed within the second display area A2 and the fourth display area A4, the working timing diagram is shown in Figure 23.

[0417] In Figure 22, the effective display area includes the first display area A1, the second display area A2, the third display area A3, the fourth display area A4, and the fifth display area A5, which are arranged from top to bottom.

[0418] In Figure 23, the time of frame a is labeled Fa, the time of frame a+1 is labeled Fa+2, the time of frame a+2 is labeled Fa+3, and a is a positive integer.

[0419] The time Fa of frame a includes the first second input stage SI12, the first fourth input stage SI14, the first second reset stage SR12, and the first fourth reset stage SR14, which are set sequentially.

[0420] The time Fa+1 of frame a+1 includes the second second input stage SI22, the second fourth input stage SI24, the second second reset stage SR22, and the second fourth reset stage SR24, which are set sequentially.

[0421] The time Fa+2 of frame a+2 includes the third second input stage SI32, the third fourth input stage SI34, the third second reset stage SR32, and the third fourth reset stage SR34, which are set sequentially.

[0422] The time Fa+3 of frame a+3 includes the fourth second input stage SI42, the fourth fourth input stage SI44, the fourth second reset stage SR42, and the fourth fourth reset stage SR44, which are set sequentially.

[0423] In SI12, SI22, SI32 and SI42, STV2 and STV4 provide high voltage signals, and the potential of the first node in GAi+1 is pulled high;

[0424] High voltage signals are provided in SR12, SR22, SR32 and SR42, STV2 and STV3, and the potential of the first node in GAj is reset;

[0425] During the time period between SI12 and SR12, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0426] During the time period between SI22 and SR22, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0427] During the time period between SI32 and SR32, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0428] During the time period between SI42 and SR42, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0429] In SI14, SI24, SI34 and SI44, STV4 and STV1 both provide high voltage signals, and the potential of the first node in GAk+1 is pulled high.

[0430] High voltage signals are provided in SR14, SR24, SR34 and SR44, STV4 and STV5, and the potential of the first node in GAL is reset.

[0431] During the time period between SI14 and SR14, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the fourth display area sequentially refresh the display.

[0432] During the time period between SI24 and SR24, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the fourth display area sequentially refresh the display.

[0433] During the time period between SI34 and SR34, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the fourth display area sequentially refresh the display.

[0434] During the time period between SI44 and SR44, at least a portion of the intermediate-level driving circuits in the multi-level driving circuit corresponding to the fourth display area sequentially refresh the display.

[0435] When at least one embodiment shown in Figure 13 is in operation, flexible display is performed as shown in Figure 24, and the refreshed display area is repeatedly displayed within the second display area A2 and the fourth display area A4, and the refresh rate of the second display area A2 is greater than the refresh rate of the fourth display area A4, the working timing diagram is shown in Figure 25.

[0436] In Figure 24, the effective display area includes a first display area A1, a second display area A2, a third display area A3, a fourth display area A4, and a fifth display area A5 arranged from top to bottom.

[0437] When a high-frequency refresh rate is required across two or more display areas (taking the second and fourth display areas as an example), multiple refreshes can be performed only on the drive circuits corresponding to the second and fourth display areas. Since the drive circuits for other display areas have no high-level input, their drive signal outputs remain consistently low. Because only two display areas are refreshed, the refresh time is shortened, allowing for an increase in the frequency of partial refreshes.

[0438] In Figure 25, the time of frame a is labeled Fa, the time of frame a+1 is labeled Fa+2, the time of frame a+2 is labeled Fa+3, and the time of frame a+3 is labeled Fa+3, where a is a positive integer.

[0439] The time Fa of frame a includes the first second input stage SI12, the first fourth input stage SI14, the first second reset stage SR12, and the first fourth reset stage SR14, which are set sequentially.

[0440] The time Fa+1 of frame a+1 includes the second second input phase SI22 and the second second reset phase SR22, which are set sequentially.

[0441] The time Fa+2 of frame a+2 includes the third second input stage SI32, the third fourth input stage SI34, the third second reset stage SR32, and the third fourth reset stage SR34, which are set sequentially.

[0442] The time Fa+3 of frame a+3 includes the fourth second input phase SI42 and the fourth second reset phase SR42, which are set sequentially.

[0443] In SI12, SI22, SI32 and SI42, STV2 and STV4 provide high voltage signals, and the potential of the first node in GAi+1 is pulled high;

[0444] High voltage signals are provided in SR12, SR22, SR32 and SR42, STV2 and STV3, and the potential of the first node in GAj is reset;

[0445] During the time period between SI12 and SR12, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0446] During the time period between SI22 and SR22, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0447] During the time period between SI32 and SR32, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0448] During the time period between SI42 and SR42, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the second display area sequentially refresh the display.

[0449] In SI14 and SI34, STV4 and STV1 both provide high voltage signals, and the potential of the first node in GAk+1 is pulled high.

[0450] High voltage signals are provided in SR14 and SR34, STV4 and STV5, and the potential of the first node in GAL is reset.

[0451] During the time period between SI14 and SR14, at least a portion of the intermediate-level driving circuits in the multi-level driving circuits corresponding to the fourth display area sequentially refresh the display.

[0452] During the time period between SI34 and SR34, at least a portion of the intermediate-level driving circuits in the multi-level driving circuit corresponding to the fourth display area sequentially refresh the display.

[0453] When a high-frequency refresh rate is required across two or more display areas (taking the second and fourth display areas as an example), and the refresh rate of the second display area is twice that of the fourth display area, multiple refreshes can be performed only on the driving circuits corresponding to the second and fourth display areas in odd-numbered frames, and only on the driving circuits corresponding to the second display area in even-numbered frames. The driving circuits corresponding to other display areas, having no high-level input, have their drive signal outputs consistently kept low. Because only two display areas are refreshed, the refresh time is shortened, allowing for an increase in the frequency of partial refreshes.

[0454] At least one embodiment of this disclosure only requires adding a few signal traces and locally optimizing the GOA (Gate Driver On Array) architecture. While having virtually no impact on the bezel, it can also enable flexible display of local display areas according to screen requirements, covering one or any number of display areas, and the refresh rate of different display areas is adjustable.

[0455] Optionally, the input circuit includes a first transistor;

[0456] The gate of the first transistor is electrically connected to the nth carry signal output terminal, the first electrode of the first transistor is electrically connected to the input control terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0457] Optionally, the first control module includes a second transistor and a third transistor, the second control module includes a fourth transistor, the third control module includes a fifth transistor, and the first potential holding module includes a first capacitor;

[0458] The gate of the second transistor is electrically connected to the carry control clock signal terminal, the first terminal of the second transistor is electrically connected to the carry input terminal, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor.

[0459] The gate of the third transistor is electrically connected to the first terminal of the third transistor, and the second terminal of the third transistor is electrically connected to the nth carry control node;

[0460] The gate of the fourth transistor is electrically connected to the nth carry control node, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the nth carry signal output terminal.

[0461] The gate of the fifth transistor is electrically connected to the carry reset terminal, the first terminal of the fifth transistor is electrically connected to the nth carry signal output terminal, and the second terminal of the fifth transistor is electrically connected to the second voltage terminal.

[0462] The first terminal of the first capacitor is electrically connected to the nth level carry signal output terminal, and the second terminal of the first capacitor is electrically connected to the DC voltage terminal.

[0463] Optionally, the control circuit includes a sixth transistor, and the input circuit includes a first transistor;

[0464] The gate of the sixth transistor is electrically connected to the nth carry signal output terminal, the first terminal of the sixth transistor is electrically connected to the input control terminal, and the second terminal of the sixth transistor is electrically connected to the gate of the first transistor.

[0465] The gate of the first transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the first transistor is electrically connected to the first node.

[0466] In at least one embodiment of this disclosure, the fourth control module includes a seventh transistor and an eighth transistor, and the fifth control module includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

[0467] The gate and the first terminal of the seventh transistor are both electrically connected to the carry input terminal, and the second terminal of the seventh transistor is electrically connected to the gate of the nth carry control node.

[0468] The gate of the eighth transistor is electrically connected to the carry-reset terminal, the first terminal of the eighth transistor is electrically connected to the nth carry control node, and the second terminal of the eighth transistor is electrically connected to the second voltage terminal.

[0469] The gate and the first terminal of the ninth transistor are both electrically connected to the first voltage terminal, and the second terminal of the ninth transistor is electrically connected to the nth level control node.

[0470] The gate of the tenth transistor is electrically connected to the nth carry control node, the first terminal of the tenth transistor is electrically connected to the nth control node, and the second terminal of the tenth transistor is electrically connected to the second voltage terminal.

[0471] The gate and the first terminal of the eleventh transistor are both electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the nth carry control node.

[0472] The gate of the twelfth transistor is electrically connected to the nth level control node, the first terminal of the twelfth transistor is electrically connected to the nth level carry control node, and the second terminal of the twelfth transistor is electrically connected to the second voltage terminal.

[0473] In at least one embodiment of this disclosure, the channel width-to-length ratio of the tenth transistor is greater than that of the ninth transistor.

[0474] Optionally, the carry-in energy storage module includes a second capacitor, and the sixth control module includes a thirteenth transistor and a fourteenth transistor;

[0475] The first terminal of the second capacitor is electrically connected to the nth level carry control node, and the second terminal of the second capacitor is electrically connected to the nth level control node.

[0476] The gate of the thirteenth transistor is electrically connected to the nth level carry control node, the first terminal of the thirteenth transistor is electrically connected to the carry control clock signal terminal, and the second terminal of the thirteenth transistor is electrically connected to the nth level carry signal output terminal.

[0477] The gate of the fourteenth transistor is electrically connected to the nth level control node, the first terminal of the fourteenth transistor is electrically connected to the carry signal output terminal of the nth level, and the second terminal of the fourteenth transistor is electrically connected to the second voltage terminal.

[0478] As shown in Figure 26, based on at least one embodiment of the driving circuit shown in Figure 6, the input circuit includes a first transistor M1; the first node reset circuit includes a second control transistor MC2.

[0479] The gate of the first transistor M1 is electrically connected to the nth carry signal output terminal Sn, the source of the first transistor M1 is electrically connected to the input control terminal SW, and the second terminal of the first transistor M1 is electrically connected to the first node PU.

[0480] The gate of MC2 is electrically connected to the carry-reset terminal IR, the source of MC2 is electrically connected to the first node PU, and the drain of MC2 is electrically connected to the low voltage terminal VGL.

[0481] The first control module includes a second transistor M2 and a third transistor M3, the second control module includes a fourth transistor M4, the third control module includes a fifth transistor M5, and the first potential holding module includes a first capacitor C1.

[0482] The gate of the second transistor M2 is electrically connected to the carry control clock signal terminal CLKC, the source of the second transistor M2 is electrically connected to the carry input terminal IS, IS can be the carry signal output terminal of the previous stage or multiple stages of the drive circuit, and the drain of the second transistor M2 is electrically connected to the source of the third transistor M3.

[0483] The gate of the third transistor M3 is electrically connected to the source of the third transistor M3, and the drain of the third transistor M3 is electrically connected to the nth carry control node NSn.

[0484] The gate of the fourth transistor M4 is electrically connected to the nth carry control node NSn, the source of the fourth transistor M4 is electrically connected to the high voltage terminal GCH, and the drain of the fourth transistor M4 is electrically connected to the nth carry signal output terminal Sn.

[0485] The gate of the fifth transistor M5 is electrically connected to the carry-reset terminal IR. The carry-reset terminal IR can be electrically connected to the carry signal output terminal of the previous stage or multiple stages of the driving circuit. The source of the fifth transistor M5 is electrically connected to the carry signal output terminal Sn of the nth stage. The drain of the fifth transistor M5 is electrically connected to the low voltage terminal.

[0486] The first terminal of the first capacitor C1 is electrically connected to the nth carry signal output terminal Sn, and the second terminal of the first capacitor C1 is electrically connected to the low voltage terminal VGL.

[0487] The driving circuit may further include a driving unit, which includes a second node control circuit, a reset circuit, an output circuit, and a first energy storage circuit.

[0488] The second node control circuit includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18; the reset circuit includes the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, and the twenty-fourth transistor M24; the output circuit includes the twenty-second transistor M22 and the twenty-third transistor M23; and the first energy storage circuit includes the third capacitor C3.

[0489] The gate and source of M15 are both electrically connected to the high-voltage terminal GCH, and the source of M15 is electrically connected to the gate of M17.

[0490] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the gate of M17, and the drain of M16 is electrically connected to the low voltage terminal VGL.

[0491] The source of M17 is electrically connected to the high-voltage terminal GCH, and the drain of M17 is electrically connected to the second node PD.

[0492] The gate of M18 is electrically connected to the first node PU, the source of M18 is electrically connected to the second node PD, and the drain of M18 is electrically connected to the low voltage terminal VGL.

[0493] The gate of M19 is electrically connected to the second node PD, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the low voltage terminal VGL.

[0494] The gate of M20 is electrically connected to the frame reset line STV0, the source of M20 is electrically connected to the first node PU, and the drain of M20 is electrically connected to the low voltage terminal VGL.

[0495] The gate of M21 is electrically connected to the frame reset line STV0, the source of M21 is electrically connected to the nth drive signal output terminal GTn, and the drain of M21 is electrically connected to the low voltage terminal VGL.

[0496] The gate of M24 is electrically connected to the frame reset line STV0, the source of M24 is electrically connected to the nth carry signal output terminal Sn, and the drain of M24 is electrically connected to the low voltage terminal VGL.

[0497] The gate of M22 is electrically connected to the first node PU, the source of M22 is electrically connected to the output clock signal terminal CLKO, and the drain of M22 is electrically connected to the nth stage drive signal output terminal GTn.

[0498] The gate of M23 is electrically connected to the second node PD, the source of M23 is electrically connected to the nth stage drive signal output terminal GTn, and the drain of M23 is electrically connected to the low voltage terminal VGL.

[0499] The first end of C3 is electrically connected to the first node PU, and the second end of C3 is electrically connected to the nth stage drive signal output terminal GTn.

[0500] In at least one embodiment of the driving circuit shown in Figure 26, all transistors are n-type transistors.

[0501] In at least one embodiment of the driving circuit shown in Figure 26 of this disclosure, based on the driving circuit of 11T1C, the input cascading is optimized and separated from the driving signal output terminal. Each stage of the driving circuit is cascaded and transmitted through the carry signal output terminal. An input control signal provided by the input control terminal SW is added to the source of M1. The nth stage carry signal connected to the gate of M1 and the input control signal connected to the source of M1 jointly control whether the driving circuit has a high-level output. The driving circuit has a high-level input only when both Sn and SW provide high voltage signals.

[0502] In at least one embodiment of the driving circuit shown in Figure 26, the driving circuit can be an nth stage driving circuit, IS can be electrically connected to the carry signal output terminal of the (n-1)th stage, IR can be electrically connected to the carry signal output terminal of the (n+2)th stage, and n is a positive integer.

[0503] Figure 27 is a structural diagram of a drive module according to at least one embodiment of the present disclosure. At least one embodiment of the drive module shown in Figure 27 includes at least one embodiment of the multi-stage drive circuit shown in Figure 26.

[0504] As shown in Figure 27, each of the driving circuits includes a cascaded control unit and a driving unit; the cascaded unit includes a cascaded control circuit, a first node control circuit and a first node reset circuit, and the first node control circuit includes an input circuit.

[0505] The first-stage drive circuit includes a first drive unit GAD1 and a first cascaded control unit J1;

[0506] The second-stage drive circuit includes a second drive unit GAD2 and a second cascaded control unit J2;

[0507] The third-stage drive circuit includes the third drive unit GAD3 and the third cascade control unit J3;

[0508] The (n-1)th stage drive circuit includes the (n-1)th drive unit GADn-1 and the (n-1)th cascaded control unit Jn-1; n is a positive integer;

[0509] The nth stage drive circuit includes the nth drive unit GADn and the nth cascade control unit Jn;

[0510] The (n+1)th stage drive circuit includes the (n+1)th drive unit GADn+1 and the (n+1)th cascaded control unit Jn+1;

[0511] The m-th stage drive circuit includes the m-th drive unit GADm and the m-th cascaded control unit Jm; m is a positive integer.

[0512] In Figure 27, S1 is the first-level carry signal output terminal, S2 is the second-level carry signal output terminal, S3 is the third-level carry signal output terminal, S4 is the fourth-level carry signal output terminal, and S5 is the fifth-level carry signal output terminal.

[0513] The terminal labeled Sn-2 is the carry signal output terminal for the (n-2)th level, the terminal labeled Sn-1 is the carry signal output terminal for the (n-1)th level, the terminal labeled Sn is the carry signal output terminal for the nth level, the terminal labeled Sn+1 is the carry signal output terminal for the (n+1)th level, the terminal labeled Sn+2 is the carry signal output terminal for the (n+2)th level, the terminal labeled Sn+3 is the carry signal output terminal for the (n+3)th level, the terminal labeled Sm-1 is the carry signal output terminal for the mth level, and the terminal labeled Sm is the carry signal output terminal for the mth level.

[0514] The line labeled STV0 is the frame reset line, the line labeled STV is the start voltage line, the line labeled CLK is the first clock signal line, and the line labeled CLK' is the third clock signal line. The phase of the first clock signal provided by CLK and the phase of the third clock signal provided by CLK' are different and can be optionally inverted.

[0515] As shown in Figure 27, in J1, the carry input terminal is electrically connected to the starting voltage line STV.

[0516] In the odd-level drive circuit, the carry control clock signal terminal is electrically connected to CLK', and the output clock signal terminal is electrically connected to CLK.

[0517] In the even-level drive circuit, the carry control clock signal terminal is electrically connected to CLK, and the output clock signal terminal is electrically connected to CLK'.

[0518] In J1, the carry control clock signal terminal is electrically connected to CLK', and the output clock signal terminal is electrically connected to CLK;

[0519] In J2, the carry control clock signal terminal is electrically connected to CLK, and the output clock signal terminal is electrically connected to CLK'.

[0520] In J3, the carry control clock signal terminal is electrically connected to CLK', and the output clock signal terminal is electrically connected to CLK;

[0521] In Jn-1, the carry control clock signal terminal is electrically connected to CLK', and the output clock signal terminal is electrically connected to CLK;

[0522] In Jn, the carry control clock signal terminal is electrically connected to CLK', and the output clock signal terminal is electrically connected to CLK;

[0523] In Jn+1, the carry control clock signal terminal is electrically connected to CLK', and the output clock signal terminal is electrically connected to CLK;

[0524] In Jm, the carry control clock signal terminal is electrically connected to CLK', and the output clock signal terminal is electrically connected to CLK.

[0525] In at least one embodiment of this disclosure, the cascade control unit is used for cascading between upper and lower level drive circuits, and the drive unit is used to output drive signals for the corresponding row. Taking the nth drive unit as an example, the signals input to the nth drive unit include the nth level carry signal provided by Sn, the output clock signal, and the input control signal provided by SW. When both Sn and SW provide high voltage signals, the nth drive unit can work normally, and the nth level drive signal output terminal GTn has normal pulse output. When Sn outputs a high voltage signal and SW provides a low voltage signal, the nth drive unit cannot work normally and there is no pulse output. Therefore, by adjusting the high and low levels of the input control signal provided by SW, the row that needs to be refreshed can be controlled.

[0526] When at least one embodiment of the driving circuit shown in FIG27 includes at least one embodiment of the driving circuit shown in FIG26, the at least one embodiment of the driving module shown in FIG27, during operation,

[0527] When the (n-2)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a high voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a high voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a high voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a high voltage signal, and the voltage signal of the first node PUn of the nth stage is a low voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a low voltage signal, the voltage signal of the first node PUn+2 of the (n+2)th stage is a low voltage signal, the drive signal output terminal GTn-2 of the (n-2)th stage outputs a high voltage signal, the drive signal output terminal GTn-1 of the (n-1)th stage outputs a low voltage signal, the drive signal output terminal GTn of the nth stage outputs a low voltage signal, the drive signal output terminal GTn+1 of the (n+1)th stage outputs a low voltage signal, the drive signal output terminal GTn+2 of the (n+2)th stage outputs a low voltage signal, CLK outputs a high voltage signal, CLK' outputs a low voltage signal, and SW outputs a high voltage signal.

[0528] When the (n-1)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a high voltage signal, the carry signal output terminal Sn of the nth stage outputs a high voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a high voltage signal, and the voltage signal of the first node PUn of the nth stage is a high voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a low voltage signal, the voltage signal of the first node PUn+2 of the (n+2)th stage is a low voltage signal, the drive signal output terminal GTn-2 of the (n-2)th stage outputs a low voltage signal, the drive signal output terminal GTn-1 of the (n-1)th stage outputs a high voltage signal, the drive signal output terminal GTn of the nth stage outputs a low voltage signal, the drive signal output terminal GTn+1 of the (n+1)th stage outputs a low voltage signal, the drive signal output terminal GTn+2 of the (n+2)th stage outputs a low voltage signal, CLK outputs a low voltage signal, CLK' outputs a high voltage signal, and SW outputs a high voltage signal.

[0529] When the nth stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a high voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a high voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a low voltage signal, and the voltage signal of the first node PUn of the nth stage is a high voltage signal. The voltage signal of the first node PUn+1 of stage n+1 is a high voltage signal, the voltage signal of the first node PUn+2 of stage n+2 is a low voltage signal, the drive signal output terminal GTn-2 of stage n-2 outputs a low voltage signal, the drive signal output terminal GTn-1 of stage n-1 outputs a low voltage signal, the drive signal output terminal GTn of stage n outputs a high voltage signal, the drive signal output terminal GTn+1 of stage n+1 outputs a low voltage signal, the drive signal output terminal GTn+2 of stage n+2 outputs a low voltage signal, CLK outputs a high voltage signal, CLK' outputs a low voltage signal, and SW outputs a high voltage signal.

[0530] When the (n+1)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a high voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a high voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a low voltage signal, and the voltage signal of the first node PUn of the nth stage is a low voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a high voltage signal, the voltage signal of the first node PUn+2 of the (n+2)th stage is a high voltage signal, the drive signal output terminal GTn-2 of the (n-2)th stage outputs a low voltage signal, the drive signal output terminal GTn-1 of the (n-1)th stage outputs a low voltage signal, the drive signal output terminal GTn of the nth stage outputs a low voltage signal, the drive signal output terminal GTn+1 of the (n+1)th stage outputs a high voltage signal, the drive signal output terminal GTn+2 of the (n+2)th stage outputs a low voltage signal, CLK outputs a low voltage signal, CLK' outputs a high voltage signal, and SW outputs a high voltage signal.

[0531] When the (n+2)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a high voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a low voltage signal, and the voltage signal of the first node PUn of the nth stage is a low voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a low voltage signal, the voltage signal of the first node PUn+2 of the (n+2)th stage is a high voltage signal, the drive signal output terminal GTn-2 of the (n-2)th stage outputs a low voltage signal, the drive signal output terminal GTn-1 of the (n-1)th stage outputs a low voltage signal, the drive signal output terminal GTn of the nth stage outputs a low voltage signal, the drive signal output terminal GTn+1 of the (n+1)th stage outputs a low voltage signal, the drive signal output terminal GTn+2 of the (n+2)th stage outputs a high voltage signal, CLK outputs a high voltage signal, CLK' outputs a low voltage signal, and SW outputs a high voltage signal.

[0532] When the (n+3)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a low voltage signal, and the voltage signal of the first node PUn of the nth stage is a low voltage signal. The voltage signal of the first node PUn+1 of stage n+1 is a low voltage signal, the voltage signal of the first node PUn+2 of stage n+2 is a low voltage signal, the drive signal output terminal GTn-2 of stage n-2 outputs a low voltage signal, the drive signal output terminal GTn-1 of stage n-1 outputs a low voltage signal, the drive signal output terminal GTn of stage n outputs a low voltage signal, the drive signal output terminal GTn+1 of stage n+1 outputs a low voltage signal, the drive signal output terminal GTn+2 of stage n+2 outputs a low voltage signal H, CLK outputs a low voltage signal, CLK' outputs a high voltage signal, and SW outputs a high voltage signal.

[0533] The pulse width of the carry signal provided by each level of the carry signal output terminal is two lines of scan time, the pulse width of the potential of the first node of each level is two lines of scan time, and the pulse width of the drive signal provided by each level of the drive signal output terminal is one line of scan time.

[0534] As shown in Figure 28A, during the Nth frame time FN, all the stage drive circuits in the drive module perform normal scanning and refreshing, that is, during the Nth frame time FN, SW outputs a high voltage signal.

[0535] As shown in Figure 28B, at frame N+1 time FN+1, the high-frequency refresh area can be controlled by adjusting the potential of the input control signal provided by SW. Display refresh is performed only in the high-frequency refresh area, which can be one or more discontinuous areas.

[0536] In Figure 28A, the area labeled A0 is the effective display area;

[0537] In Figure 28B, the area labeled A1 is the first display area, the area labeled A2 is the second display area, the area labeled A3 is the third display area, the area labeled A4 is the fourth display area, and the area labeled A5 is the fifth display area.

[0538] When input is received to the driving circuits corresponding to the second display area A2 and the fourth display area A4 (that is, when the corresponding carry signal output terminal outputs a high voltage signal), SW provides a high voltage signal to refresh the display of the second display area A2 and the fourth display area A4.

[0539] When input is received to the driving circuits corresponding to the first display area A1, the third display area A3, and the fifth display area A5, SW provides a low voltage signal and does not refresh the display of the first display area A1, the third display area A3, and the fifth display area A5.

[0540] At frame N+2, the action of FN or FN+1 can be repeated, or the area of ​​the signal can be selected for display refresh.

[0541] In at least one embodiment of the drive module shown in Figure 27, when scanning and refreshing normally line by line, SW always provides a high voltage signal. The output of the nth stage drive signal is controlled by the nth stage carry signal. The nth stage carry signal also serves as a cascade signal to control the cascade of each stage drive circuit.

[0542] As shown in Figure 29, based on at least one embodiment of the driving circuit shown in Figure 26, IS can be electrically connected to the (n-1)th level carry signal output terminal Sn-1, and IR can be electrically connected to the (n+2)th level carry signal output terminal Sn+2; the carry control clock signal terminal is electrically connected to the first clock signal line CLK, and the output clock signal terminal is electrically connected to the third clock signal line CLK'.

[0543] As shown in Figure 30, in at least one embodiment of the driving circuit shown in Figure 29, when Sn-1 outputs a high voltage signal, CLK provides a high voltage signal, M2, M3 and M4 are turned on, the potential of the nth level carry signal provided by Sn is pulled high, SW provides a high voltage signal, M1 is turned on, the potential of PU is high voltage, CLK' provides a low voltage signal, and GTn outputs a low voltage signal; at this time, Sn+2 outputs a low voltage signal, and M5 is turned off.

[0544] As shown in Figure 31, when Sn provides a high voltage signal, SW provides a high voltage signal, CLK provides a low voltage signal, CLK' provides a high voltage signal, Sn-1 provides a high voltage signal, M1 is turned on, the voltage signal of PU is a high voltage signal, M22 is turned on, and GTn outputs a high voltage signal.

[0545] As shown in Figure 32, when Sn+2 outputs a high voltage signal, M5 is turned on, Sn outputs a low voltage signal, at this time, CLK and Sn-1 both output low voltage signals, M2, M3 and M4 are all turned off, M1 is turned off, MC2 is turned on, and PU and VGL are connected; the potential of PU is low voltage, CLK' outputs a high voltage signal, the potential of PD is high voltage, and GTn outputs a low voltage signal.

[0546] As shown in Figure 33, when Sn outputs a high voltage signal and SW provides a low voltage signal, M1 is turned on, the potential of PU is low voltage, and GTn outputs a low voltage signal; at this time, CLK outputs a low voltage signal, Sn-1 outputs a high voltage signal, M2 is turned off, Sn+2 outputs a low voltage signal, M5 is turned off, and M22 is turned off.

[0547] When the drive module described in at least one embodiment of this disclosure is in operation, if only the selected drive circuit is refreshed and other drive circuits are not refreshed, the cascade control units in each drive circuit of the drive module work normally, and the carry signal output terminals of each drive circuit output the corresponding carry signal normally. When the carry reaches the refresh stage drive circuit, the input control terminal SW provides a high voltage signal, and when the carry reaches the non-refresh stage drive circuit, the input control terminal SW provides a low voltage signal.

[0548] As shown in Figure 34, when the driving module described in at least one embodiment of this disclosure is working, it performs normal step-by-step scanning within the Nth frame time FN; and scans the locally selected level driving circuit within the N+1th frame time; N is a positive integer; the locally selected level is exemplified by the third to fifth level driving circuits, the eighth level driving circuit, and the ninth level driving circuit.

[0549] In Figure 34, the terminal labeled STV0 is the frame reset terminal, the terminal labeled STV is the start voltage line, the terminal labeled CLK' is the third clock signal line, the terminal labeled CLK is the first clock signal line, the terminal labeled SW is the input control terminal, the terminal labeled S1 is the first-level carry signal output terminal, the terminal labeled S2 is the second-level carry signal output terminal, the terminal labeled S3 is the third-level carry signal output terminal, the terminal labeled S4 is the fourth-level carry signal output terminal, the terminal labeled S5 is the fifth-level carry signal output terminal, and the terminal labeled S6 is the sixth-level carry signal output terminal. The terminal labeled GT1 is the first-stage drive signal output terminal, GT2 is the second-stage drive signal output terminal, GT3 is the third-stage drive signal output terminal, GT4 is the fourth-stage drive signal output terminal, GT5 is the fifth-stage drive signal output terminal, GT6 is the sixth-stage drive signal output terminal, GT7 is the seventh-stage drive signal output terminal, GT8 is the eighth-stage drive signal output terminal, GT9 is the ninth-stage drive signal output terminal, and GT10 is the tenth-stage drive signal output terminal.

[0550] The terminal labeled Sn-1 is the carry signal output terminal of the (n-1)th level, the terminal labeled Sn is the carry signal output terminal of the nth level, and the terminal labeled Sn+1 is the carry signal output terminal of the (n+1)th level.

[0551] The terminal labeled GTn-1 is the output terminal of the (n-1)th stage drive signal, the terminal labeled GTn is the output terminal of the nth stage drive signal, the terminal labeled GTn+1 is the output terminal of the (n+1)th stage drive signal, and the terminal labeled GTE is the output terminal of the last stage drive signal.

[0552] In practice, the normal refresh rate is set to 120Hz, with three frames as one cycle, as shown in Figure 35A. At frame N time FN, normal progressive display refresh is performed, as shown in Figure 35B. At frame N+1 time FN+1, the second display area A2 and the fourth display area A4 are refreshed, as shown in Figure 35C. At frame N+2 time FN+2, the second display area A2 is refreshed.

[0553] In at least one embodiment corresponding to Figures 35A, 35B and 35C, the effective display area includes a first display area A1, a second display area A2, a third display area A3, a fourth display area A4 and a fifth display area A5.

[0554] After flexible display, A2 is the high refresh rate display area, A4 is the second highest refresh rate area, and A1, A3, and A5 are the low refresh rate areas.

[0555] As shown in Figure 36, based on at least one embodiment of the driving circuit shown in Figure 9, the control circuit includes a sixth transistor M6, the input circuit includes a first transistor M1, and the first node reset circuit includes a second control transistor MC2.

[0556] The gate of the sixth transistor M6 is electrically connected to the nth carry signal output terminal Sn, the source of the sixth transistor M6 is electrically connected to the input control terminal SW, and the drain of the sixth transistor M6 is electrically connected to the gate of the first transistor M1.

[0557] The gate of the first transistor M1 is electrically connected to the source of the first transistor M1, and the drain of the first transistor M1 is electrically connected to the first node PU.

[0558] The gate of MC2 is electrically connected to the carry-reset terminal, the source of MC2 is electrically connected to the first node PU, and the drain of MC2 is electrically connected to the low-voltage terminal VGL; the carry-reset terminal is electrically connected to the (n-1)th stage carry signal output terminal Sn-1.

[0559] The fourth control module includes a seventh transistor M7 and an eighth transistor M8, and the fifth control module includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12.

[0560] The gate and source of the seventh transistor M7 are both electrically connected to the carry input terminal, and the drain of the seventh transistor M7 is electrically connected to the gate of the nth carry control node NSn; the carry input terminal is electrically connected to the (n-1)th carry signal output terminal Sn-1.

[0561] The gate of the eighth transistor M8 is electrically connected to the carry reset terminal, the source of the eighth transistor M8 is electrically connected to the nth carry control node NSn, and the drain of the eighth transistor M8 is electrically connected to the low voltage terminal VGL; the carry reset terminal is electrically connected to the (n+2)th carry signal output terminal Sn+2.

[0562] The gate and source of the ninth transistor M9 are both electrically connected to the high-voltage terminal GCH, and the drain of the ninth transistor M9 is electrically connected to the nth control node NCn.

[0563] The gate of the tenth transistor M10 is electrically connected to the nth carry control node NSn, the source of the tenth transistor M10 is electrically connected to the nth control node NCn, and the drain of the tenth transistor M10 is electrically connected to the low voltage terminal VGL.

[0564] The gate and source of the eleventh transistor M11 are both electrically connected to the high voltage terminal GCH, and the drain of the eleventh transistor M11 is electrically connected to the nth carry control node NSn.

[0565] The gate of the twelfth transistor M12 is electrically connected to the nth level control node NCn, the source of the twelfth transistor M12 is electrically connected to the nth level carry control node NSn, and the drain of the twelfth transistor M12 is electrically connected to the low voltage terminal VGL.

[0566] The carry-in energy storage module includes a second capacitor C2, and the sixth control module includes a thirteenth transistor M13 and a fourteenth transistor M14;

[0567] The first terminal of the second capacitor C2 is electrically connected to the nth level carry control node NSn, and the second terminal of the second capacitor C2 is electrically connected to the nth level control node NCn.

[0568] The gate of the thirteenth transistor M13 is electrically connected to the nth carry control node NSn, the source of the thirteenth transistor M13 is electrically connected to the carry control clock signal terminal, and the drain of the thirteenth transistor M13 is electrically connected to the nth carry signal output terminal Sn; the carry control clock signal terminal is electrically connected to the third clock signal line CLK'.

[0569] The gate of the fourteenth transistor M14 is electrically connected to the nth control node NCn, the source of the fourteenth transistor M14 is electrically connected to the nth carry signal output terminal Sn, and the drain of the fourteenth transistor M14 is electrically connected to the low voltage terminal VGL.

[0570] The driving circuit may further include a driving unit, which includes a second node control circuit, a reset circuit, an output circuit, and a first energy storage circuit.

[0571] The second node control circuit includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18; the reset circuit includes the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21; the output circuit includes the twenty-second transistor M22 and the twenty-third transistor M23; and the first energy storage circuit includes the third capacitor C3.

[0572] The gate and source of M15 are both electrically connected to the high-voltage terminal GCH, and the source of M15 is electrically connected to the gate of M17.

[0573] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the gate of M17, and the drain of M16 is electrically connected to the low voltage terminal VGL.

[0574] The source of M17 is electrically connected to the high-voltage terminal GCH, and the drain of M17 is electrically connected to the second node PD.

[0575] The gate of M18 is electrically connected to the first node PU, the source of M18 is electrically connected to the second node PD, and the drain of M18 is electrically connected to the low voltage terminal VGL.

[0576] The gate of M19 is electrically connected to the second node PD, the source of M19 is electrically connected to the first node PU, and the drain of M19 is electrically connected to the low voltage terminal VGL.

[0577] The gate of M20 is electrically connected to the frame reset line STV0, the source of M20 is electrically connected to the first node PU, and the drain of M20 is electrically connected to the low voltage terminal VGL.

[0578] The gate of M21 is electrically connected to the frame reset line STV0, the source of M21 is electrically connected to the nth drive signal output terminal GTn, and the drain of M21 is electrically connected to the low voltage terminal VGL.

[0579] The gate of M22 is electrically connected to the first node PU, the source of M22 is electrically connected to the output clock signal terminal, and the drain of M22 is electrically connected to the nth stage drive signal output terminal GTn; the output clock signal terminal is electrically connected to the first clock signal line CLK.

[0580] The gate of M23 is electrically connected to the second node PD, the source of M23 is electrically connected to the nth stage drive signal output terminal GTn, and the drain of M23 is electrically connected to the low voltage terminal VGL.

[0581] The first end of C3 is electrically connected to the first node PU, and the second end of C3 is electrically connected to the nth stage drive signal output terminal GTn.

[0582] In at least one embodiment shown in Figure 36, all transistors are n-type transistors, but this is not a limitation.

[0583] In at least one embodiment of this disclosure, the channel width-to-length ratio of the tenth transistor M10 is greater than that of the ninth transistor M9. When the potential of NSn is high, both M9 and M10 are turned on. By setting the width-to-length ratio of M10 to be greater than that of M9, the potential of NCn is made low.

[0584] In at least one embodiment of the driving circuit shown in Figure 36 of this disclosure, based on the driving circuit of 11T1C, the input is optimized by cascading and separated from the driving signal output terminal. Each stage of the driving circuit is cascaded and transmitted through the carry signal output terminal. The nth stage carry signal and the input control signal provided by SW jointly control whether the driving circuit has a high-level output. The driving circuit has a high-level input only when both Sn and SW provide high voltage signals.

[0585] In at least one embodiment of the driving circuit shown in Figure 36, the driving circuit can be an nth stage driving circuit, IS can be electrically connected to the carry signal output terminal of the (n-1)th stage, IR can be electrically connected to the carry signal output terminal of the (n+2)th stage, and n is a positive integer.

[0586] When the structure of the driving circuit included in the driving module is as shown in Figure 36, the structure of the driving module described in at least one embodiment of this disclosure can be as shown in Figure 27.

[0587] When at least one embodiment of the driving circuit shown in FIG27 includes at least one embodiment of the driving circuit shown in FIG36, the signal level states of each node in different stages of the driving module shown in FIG27 during operation can be as follows:

[0588] When the (n-2)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a high voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a high voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a high voltage signal, and the voltage signal of the first node PUn of the nth stage is a low voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a low voltage signal, the voltage signal of the first node PUn+2 of the (n+2)th stage is a low voltage signal, the drive signal output terminal GTn-2 of the (n-2)th stage outputs a high voltage signal, the drive signal output terminal GTn-1 of the (n-1)th stage outputs a low voltage signal, the drive signal output terminal GTn of the nth stage outputs a low voltage signal, the drive signal output terminal GTn+1 of the (n+1)th stage outputs a low voltage signal, the drive signal output terminal GTn+2 of the (n+2)th stage outputs a low voltage signal, CLK outputs a high voltage signal, CLK' outputs a low voltage signal, and SW outputs a high voltage signal.

[0589] When the (n-1)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a high voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a high voltage signal, and the voltage signal of the first node PUn of the nth stage is a high voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a low voltage signal, the voltage signal of the first node PUn+2 of the (n+2)th stage is a low voltage signal, the drive signal output terminal GTn-2 of the (n-2)th stage outputs a low voltage signal, the drive signal output terminal GTn-1 of the (n-1)th stage outputs a high voltage signal, the drive signal output terminal GTn of the nth stage outputs a low voltage signal, the drive signal output terminal GTn+1 of the (n+1)th stage outputs a low voltage signal, the drive signal output terminal GTn+2 of the (n+2)th stage outputs a low voltage signal, CLK outputs a low voltage signal, CLK' outputs a high voltage signal, and SW outputs a high voltage signal.

[0590] When the nth stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a high voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a low voltage signal, and the voltage signal of the first node PUn of the nth stage is a high voltage signal. The voltage signal of the first node PUn+1 of stage n+1 is a high voltage signal, the voltage signal of the first node PUn+2 of stage n+2 is a low voltage signal, the drive signal output terminal GTn-2 of stage n-2 outputs a low voltage signal, the drive signal output terminal GTn-1 of stage n-1 outputs a low voltage signal, the drive signal output terminal GTn of stage n outputs a high voltage signal, the drive signal output terminal GTn+1 of stage n+1 outputs a low voltage signal, the drive signal output terminal GTn+2 of stage n+2 outputs a low voltage signal, CLK outputs a high voltage signal, CLK' outputs a low voltage signal, and SW outputs a high voltage signal.

[0591] When the (n+1)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn+1 of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a high voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage is a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage is a low voltage signal, and the voltage signal of the first node PUn of the nth stage is a low voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a high voltage signal, the voltage signal of the first node PUn+2 of the (n+2)th stage is a high voltage signal, the drive signal output terminal GTn-2 of the (n-2)th stage outputs a low voltage signal, the drive signal output terminal GTn-1 of the (n-1)th stage outputs a low voltage signal, the drive signal output terminal GTn of the nth stage outputs a low voltage signal, the drive signal output terminal GTn+1 of the (n+1)th stage outputs a high voltage signal, the drive signal output terminal GTn+2 of the (n+2)th stage outputs a low voltage signal, CLK outputs a low voltage signal, CLK' outputs a high voltage signal, and SW outputs a high voltage signal.

[0592] When the (n+2)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage outputs a low voltage signal, and the voltage signal of the first node PUn of the nth stage outputs a low voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a low voltage signal, the voltage signal of the first node PUn+2 of the (n+2)th stage is a high voltage signal, the drive signal output terminal GTn-2 of the (n-2)th stage outputs a low voltage signal, the drive signal output terminal GTn-1 of the (n-1)th stage outputs a low voltage signal, the drive signal output terminal GTn of the nth stage outputs a low voltage signal, the drive signal output terminal GTn+1 of the (n+1)th stage outputs a low voltage signal, the drive signal output terminal GTn+2 of the (n+2)th stage outputs a high voltage signal, CLK outputs a high voltage signal, CLK' outputs a low voltage signal, and SW outputs a high voltage signal.

[0593] When the (n+3)th stage drive circuit is scanned, the carry signal output terminal Sn-2 of the (n-2)th stage outputs a low voltage signal, the carry signal output terminal Sn-1 of the (n-1)th stage outputs a low voltage signal, the carry signal output terminal Sn of the nth stage outputs a low voltage signal, the carry signal output terminal Sn of the (n+1)th stage outputs a low voltage signal, the carry signal output terminal Sn+2 of the (n+2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-2 of the (n-2)th stage outputs a low voltage signal, the voltage signal of the first node PUn-1 of the (n-1)th stage outputs a low voltage signal, and the voltage signal of the first node PUn of the nth stage outputs a low voltage signal. The voltage signal of the first node PUn+1 of the (n+1)th stage is a low voltage signal. The voltage signal of the first node PUn+2 of the (n+2)th stage is a low voltage signal. The drive signal output terminal GTn-2 of the (n-2)th stage outputs a low voltage signal. The drive signal output terminal GTn-1 of the (n-1)th stage outputs a low voltage signal. The drive signal output terminal GTn of the nth stage outputs a low voltage signal. The drive signal output terminal GTn+1 of the (n+1)th stage outputs a low voltage signal. The drive signal output terminal GTn+2 of the (n+2)th stage outputs a low voltage signal. CLK outputs a low voltage signal. CLK' outputs a high voltage signal. SW outputs a high voltage signal.

[0594] The pulse width of the carry signal provided by each level of the carry signal output terminal is one line scan time, the pulse width of the potential of the first node of each level is two lines scan time, and the pulse width of the drive signal provided by each level of the drive signal output terminal is one line scan time.

[0595] As shown in Figure 37, in at least one embodiment of the driving circuit shown in Figure 36, when Sn-1 outputs a high voltage signal, M7 is turned on, the voltage signal of NSn is a high voltage signal, Sn+2 provides a high voltage signal, M8 is turned off, M9 and M10 are turned on, the voltage signal of NCn is a low voltage signal, M13 is turned on, M14 is turned off, CLK' outputs a low voltage signal, Sn outputs a low voltage signal, SW provides a high voltage signal, M6 is turned off, CLK outputs a high voltage signal, PU's voltage signal is a low voltage signal, and GTn outputs a low voltage signal.

[0596] As shown in Figure 38, in at least one embodiment of the driving circuit shown in Figure 36, when Sn-1 outputs a low voltage signal and Sn+2 outputs a low voltage signal H, M7 and M8 are turned off, the voltage signal of NSn remains a high voltage signal, M10 and M9 are turned on, the voltage signal of NCn is a low voltage signal, M12 and M14 are turned off, M13 is turned on, CLK' outputs a high voltage signal, Sn outputs a high voltage signal; SW provides a high voltage signal, M6 and M1 are turned on, the voltage signal of PU is a high voltage signal, CLK provides a low voltage signal, M22 is turned on, and GTn outputs a low voltage signal.

[0597] As shown in Figure 39, in at least one embodiment of the driving circuit shown in Figure 36, when Sn+1 outputs a high voltage signal, Sn-1 outputs a low voltage signal, Sn+2 outputs a low voltage signal, M7 and M8 are turned off, M9 is turned on, the voltage signal of NSn is maintained as a high voltage signal, M10 is turned on, the voltage signal of NCn is a low voltage signal, M13 is turned on, M14 is turned off, CLK' provides a low voltage signal, Sn outputs a low voltage signal, M6 is turned off, the voltage signal of PU is a high voltage signal, CLK outputs a high voltage signal, M22 is turned on, and GTn outputs a high voltage signal.

[0598] As shown in Figure 40, in at least one embodiment of the driving circuit shown in Figure 36, when Sn+2 outputs a high voltage signal, Sn-1 outputs a low voltage signal, M8 is turned on, M7 is turned off, the voltage signal of NSn is a low voltage signal, M9 is turned on, M10 is turned off, the voltage signal of NCn is a high voltage signal, M13 is turned off, M14 is turned on, Sn outputs a low voltage signal, SW provides a high voltage signal, M6 is turned off, the voltage signal of PU is a low voltage signal, CLK provides a low voltage signal, and GTn outputs a low voltage signal.

[0599] As shown in Figure 41, when the driving module described in at least one embodiment of this disclosure is working, it performs normal step-by-step scanning within the Nth frame time FN; and scans the locally selected level driving circuit within the N+1th frame time; N is a positive integer; the locally selected level is exemplified by the third to fifth level driving circuits, the eighth level driving circuit, and the ninth level driving circuit.

[0600] In Figure 41, the terminal labeled STV0 is the frame reset terminal, the terminal labeled STV is the start voltage line, the terminal labeled CLK' is the third clock signal line, the terminal labeled CLK is the first clock signal line, the terminal labeled SW is the input control terminal, the terminal labeled S1 is the first-level carry signal output terminal, the terminal labeled S2 is the second-level carry signal output terminal, the terminal labeled S3 is the third-level carry signal output terminal, the terminal labeled S4 is the fourth-level carry signal output terminal, the terminal labeled S5 is the fifth-level carry signal output terminal, and the terminal labeled S6 is the sixth-level carry signal output terminal. The terminal labeled GT1 is the first-stage drive signal output terminal, GT2 is the second-stage drive signal output terminal, GT3 is the third-stage drive signal output terminal, GT4 is the fourth-stage drive signal output terminal, GT5 is the fifth-stage drive signal output terminal, GT6 is the sixth-stage drive signal output terminal, GT7 is the seventh-stage drive signal output terminal, GT8 is the eighth-stage drive signal output terminal, GT9 is the ninth-stage drive signal output terminal, and GT10 is the tenth-stage drive signal output terminal.

[0601] The terminal labeled Sn-1 is the carry signal output terminal of the (n-1)th level, the terminal labeled Sn is the carry signal output terminal of the nth level, and the terminal labeled Sn+1 is the carry signal output terminal of the (n+1)th level.

[0602] The terminal labeled GTn-1 is the output terminal of the (n-1)th stage drive signal, the terminal labeled GTn is the output terminal of the nth stage drive signal, the terminal labeled GTn+1 is the output terminal of the (n+1)th stage drive signal, and the terminal labeled GTE is the output terminal of the last stage drive signal.

[0603] The driving module described in this embodiment includes multiple driving circuits as described above.

[0604] In at least one embodiment of this disclosure, the driving module includes M driving units, where M is an integer greater than 1 and m is a positive integer less than or equal to M; the driving unit includes a plurality of driving circuits cascaded together.

[0605] The m-th drive unit includes q-level drive circuits. The first control terminal of the first-level drive circuit in the m-th drive unit is electrically connected to the corresponding pull-up start control terminal. The second control terminal of the first-level drive circuit in the m-th drive unit is electrically connected to the drive signal output terminal of the j-th drive circuit in the m-th drive unit. j is greater than or equal to 2 but less than q. j is an integer and q is a positive integer greater than 1.

[0606] The first control terminal of the q-th stage drive circuit in the m-th drive unit is electrically connected to the drive signal output terminal of the qi-th stage drive circuit in the m-th drive unit, where i is an integer, i is greater than or equal to 1 and less than q, and the second control terminal of the q-th stage drive circuit is electrically connected to the corresponding pull-down start control terminal.

[0607] The driving module described in at least one embodiment of this disclosure includes M starting voltage lines;

[0608] Multiple driving circuits in the m-th driving unit are electrically connected to the corresponding row pixel circuits in the m-th display area, and are used to provide driving signals to the corresponding row pixel circuits.

[0609] In at least one embodiment of this disclosure, the driving circuit further includes a cascaded control circuit, wherein the first node control circuit includes an input circuit; n is a positive integer; the cascaded control circuit includes a carry input terminal, a carry reset terminal, and a carry signal output terminal; the input circuit is electrically connected to the input control terminal; the second control terminal is a carry reset terminal; the driving module includes multiple cascaded driving circuits.

[0610] The drive module includes a carry input terminal and a starting voltage terminal of the first-stage drive circuit;

[0611] The carry input terminal of the a-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the ak-th stage drive circuit included in the drive module, where a is an integer greater than 1 and k is an integer greater than or equal to 1.

[0612] The carry reset terminal of the b-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the b+r-th stage drive circuit included in the drive module; b is a positive integer, and r is an integer greater than or equal to 1.

[0613] The carry reset terminal of the b-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the b+2-th stage drive circuit included in the drive module; b is a positive integer.

[0614] The driving method described in this embodiment is applied to the aforementioned driving module. The driving method includes: during a display cycle, when the display area corresponding to the m-th driving unit is refreshed,

[0615] During the corresponding input phase of the display cycle, the corresponding pull-up start control terminal provides a valid pull-up start control signal;

[0616] During the corresponding reset phase of the display cycle, the corresponding pull-down start control terminal provides a valid pull-down start control signal.

[0617] The driving method described in this embodiment is applied to the above-mentioned driving module, and the driving method includes:

[0618] When the input control terminal provides a valid input control signal, the corresponding stage drive circuit provides a valid drive signal;

[0619] When the input control terminal provides an invalid input control signal, the corresponding stage drive circuit stops providing a valid drive signal.

[0620] The display device described in this disclosure includes the driving module described above.

[0621] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving circuit, comprising a first node control circuit and a first node reset circuit; The first node control circuit is electrically connected to the first control terminal and the first node respectively, and is used to control the potential of the first node under the control of the first control signal provided by the first control terminal; The first node reset circuit is electrically connected to the second control terminal and the first node, respectively, and is used to control the reset of the potential of the first node under the control of the second control signal provided by the second control terminal.

2. The driving circuit as described in claim 1, wherein, The first control terminal includes at least one pull-up start control terminal; The first node control circuit is used to control the potential of the first node to be an effective voltage under the control of the signal provided by the at least one pull-up start control terminal.

3. The driving circuit as described in claim 1, wherein, The second control terminal includes at least one pull-down start control terminal; The first node reset circuit is used to control the potential of the first node to be an invalid voltage under the control of the signal provided by the at least one pull-down start control terminal.

4. The driving circuit as described in claim 1, wherein, It also includes cascaded control circuits; The cascaded control circuit is electrically connected to the carry control clock signal terminal, the carry input terminal, the carry reset terminal, and the nth-level carry signal output terminal, respectively. It is used to provide the nth-level carry signal through the nth-level carry signal output terminal based on the carry control clock signal provided by the carry control clock signal terminal, the carry input signal provided by the carry input terminal, and the carry reset signal provided by the carry reset terminal; n is a positive integer. The first control terminal is electrically connected to the nth level carry signal output terminal; The first node control circuit is also electrically connected to the input control terminal, and is used to control the potential of the first node according to the input control signal provided by the input control terminal under the control of the nth level carry signal.

5. The driving circuit as described in claim 4, wherein, The first node control circuit includes an input circuit; The input circuit is electrically connected to the nth level carry signal output terminal, the input control terminal, and the first node, respectively, and is used to control the connection or disconnection between the input control terminal and the first node under the control of the nth level carry signal output terminal.

6. The driving circuit as described in claim 4, wherein, The cascaded control circuit includes a first control module, a second control module, a third control module, and a first potential holding module; The first control module is electrically connected to the carry control clock signal terminal, the carry input terminal, and the nth level carry control node, respectively, and is used to control the potential of the nth level carry control node according to the carry input signal under the control of the carry control clock signal; The second control module is electrically connected to the nth carry control node, the first voltage terminal, and the nth carry signal output terminal, respectively, and is used to control the connection or disconnection between the nth carry signal output terminal and the first voltage terminal under the control of the potential of the nth carry control node; The third control module is electrically connected to the carry reset terminal, the nth level carry signal output terminal, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the nth level carry signal output terminal and the second voltage terminal under the control of the carry reset signal; The first potential holding module is electrically connected to the output terminal of the nth level carry signal and is used to maintain the potential of the nth level carry signal.

7. The driving circuit as described in claim 4, wherein, The cascaded control circuit is also electrically connected to the nth-level carry control node and the nth-level control node, respectively. It is used to control the potential of the nth-level carry control node according to the carry input signal provided by the carry input terminal and the carry reset signal provided by the carry reset terminal. Under the control of the potential of the nth-level carry control node, it controls the potential of the nth-level control node. Under the control of the potential of the nth-level carry control node, it controls the connection or disconnection between the nth-level carry signal output terminal and the carry control clock signal terminal. Under the control of the potential of the nth-level control node, it resets the nth-level carry signal provided by the nth-level carry signal output terminal.

8. The driving circuit as described in claim 4, wherein, The first node control circuit includes a control circuit and an input circuit; The control circuit is electrically connected to the nth level carry signal output terminal, the input control terminal, and the input control node, respectively, and is used to control the connection or disconnection between the input control terminal and the input control node under the control of the nth level carry signal output terminal; The input circuit is electrically connected to the input control node and the first node respectively, and is used to control the potential of the first node according to the potential of the input control node.

9. The driving circuit as described in claim 7, wherein, The cascaded control circuit includes a fourth control module and a fifth control module; The fourth control module is electrically connected to the carry input terminal, the carry reset terminal, the nth level carry control node, and the second voltage terminal, respectively. It is used to control the potential of the nth level carry control node under the control of the carry input signal, and to control the connection or disconnection between the nth level carry control node and the second voltage terminal under the control of the carry reset signal. The fifth control module is electrically connected to the nth level carry control node and the nth level control node, respectively, and is used to control the potential of the nth level control node according to the potential of the nth level carry control node.

10. The driving circuit as described in claim 9, wherein, The cascaded control circuit also includes a carry-in energy storage module and a sixth control module; The first end of the carry-in energy storage module is electrically connected to the nth level carry-in control node, and the second end of the carry-in energy storage module is electrically connected to the nth level control node; The sixth control module is electrically connected to the nth level carry signal output terminal, the nth level carry control node, the nth level control node, the carry control clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the nth level carry signal output terminal and the carry control clock signal terminal under the control of the potential of the nth level carry control node, and to control the connection or disconnection between the nth level carry signal output terminal and the second voltage terminal under the control of the potential of the nth level control node.

11. The driving circuit according to any one of claims 4 to 10, wherein, The second control terminal is the carry-reset terminal.

12. The driving circuit as described in claim 2, wherein, The first node control circuit includes a first control transistor; the gate of the first control transistor is electrically connected to a first pull-up start control terminal, the first terminal of the first control transistor is electrically connected to the gate or a third voltage terminal of the first control transistor, and the second terminal of the first control transistor is electrically connected to the first node; or... The first node control circuit includes at least two control transistors, namely a first control transistor and a second control transistor. The gate of the first control transistor is electrically connected to a first pull-up start control terminal. The first terminal of the first control transistor is electrically connected to a first pull-up start control terminal, a second pull-up start control terminal, or a third voltage terminal. The gate of the second control transistor is electrically connected to a second pull-up start control terminal. The first terminal of the second control transistor is electrically connected to the second terminal of the first control transistor. The second terminal of the second control transistor is electrically connected to the first node. Alternatively... The first node control circuit includes at least three control transistors, namely a first control transistor, a second control transistor, and a third control transistor. The gate of the first control transistor is electrically connected to a first pull-up start control terminal. The first terminal of the first control transistor is electrically connected to a first pull-up start control terminal, a second pull-up start control terminal, a third pull-up start control terminal, or a third voltage terminal. The gate of the second control transistor is electrically connected to a second pull-up start control terminal, and the first terminal of the second control transistor is electrically connected to the second terminal of the first control transistor. The gate of the third control transistor is electrically connected to a third pull-up start control terminal, and the first terminal of the third control transistor is electrically connected to the second terminal of the second control transistor. The second terminal of the third control transistor is electrically connected to the first node.

13. The driving circuit as described in claim 3, wherein, The first node reset circuit includes at least two control transistors, specifically a first second control transistor and a second second control transistor. The gate of the first second control transistor is electrically connected to a first pull-down start control terminal. The first terminal of the first second control transistor is electrically connected to the first node. The second terminal of the first second control transistor is electrically connected to the first terminal of the second second control transistor. The gate of the second second control transistor is electrically connected to a second pull-down start control terminal. The second terminal of the second second control transistor is electrically connected to a first voltage terminal. Alternatively... The first node reset circuit includes at least three control transistors, namely a first second control transistor, a second second control transistor, and a third second control transistor. The gate of the first second control transistor is electrically connected to a first pull-down start control terminal, the first terminal of the first second control transistor is electrically connected to a first node, the second terminal of the first second control transistor is electrically connected to the first terminal of the second second control transistor, the gate of the second second control transistor is electrically connected to a second pull-down start control terminal, the second terminal of the second second control transistor is electrically connected to the first terminal of the third second control transistor, the gate of the third second control transistor is electrically connected to a third pull-down start control terminal, and the second terminal of the third second control transistor is electrically connected to a first voltage terminal.

14. The driving circuit as described in claim 5, wherein, The input circuit includes a first transistor; The gate of the first transistor is electrically connected to the nth carry signal output terminal, the first electrode of the first transistor is electrically connected to the input control terminal, and the second electrode of the first transistor is electrically connected to the first node.

15. The driving circuit as described in claim 6, wherein, The first control module includes a second transistor and a third transistor, the second control module includes a fourth transistor, the third control module includes a fifth transistor, and the first potential holding module includes a first capacitor; The gate of the second transistor is electrically connected to the carry control clock signal terminal, the first terminal of the second transistor is electrically connected to the carry input terminal, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor. The gate of the third transistor is electrically connected to the first terminal of the third transistor, and the second terminal of the third transistor is electrically connected to the nth carry control node; The gate of the fourth transistor is electrically connected to the nth carry control node, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the nth carry signal output terminal. The gate of the fifth transistor is electrically connected to the carry reset terminal, the first terminal of the fifth transistor is electrically connected to the nth carry signal output terminal, and the second terminal of the fifth transistor is electrically connected to the second voltage terminal. The first terminal of the first capacitor is electrically connected to the nth level carry signal output terminal, and the second terminal of the first capacitor is electrically connected to the DC voltage terminal.

16. The driving circuit as claimed in claim 8, wherein, The control circuit includes a sixth transistor, and the input circuit includes a first transistor; The gate of the sixth transistor is electrically connected to the nth carry signal output terminal, the first terminal of the sixth transistor is electrically connected to the input control terminal, and the second terminal of the sixth transistor is electrically connected to the gate of the first transistor. The gate of the first transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the first transistor is electrically connected to the first node.

17. The driving circuit as claimed in claim 9, wherein, The fourth control module includes a seventh transistor and an eighth transistor, and the fifth control module includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; The gate and the first terminal of the seventh transistor are both electrically connected to the carry input terminal, and the second terminal of the seventh transistor is electrically connected to the gate of the nth carry control node. The gate of the eighth transistor is electrically connected to the carry-reset terminal, the first terminal of the eighth transistor is electrically connected to the nth carry control node, and the second terminal of the eighth transistor is electrically connected to the second voltage terminal. The gate and the first terminal of the ninth transistor are both electrically connected to the first voltage terminal, and the second terminal of the ninth transistor is electrically connected to the nth level control node. The gate of the tenth transistor is electrically connected to the nth carry control node, the first terminal of the tenth transistor is electrically connected to the nth control node, and the second terminal of the tenth transistor is electrically connected to the second voltage terminal. The gate and the first terminal of the eleventh transistor are both electrically connected to the first voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the nth carry control node. The gate of the twelfth transistor is electrically connected to the nth level control node, the first terminal of the twelfth transistor is electrically connected to the nth level carry control node, and the second terminal of the twelfth transistor is electrically connected to the second voltage terminal.

18. The driving circuit as claimed in claim 17, wherein, The channel width-to-length ratio of the tenth transistor is greater than that of the ninth transistor.

19. The driving circuit as claimed in claim 10, wherein, The carry-in energy storage module includes a second capacitor, and the sixth control module includes a thirteenth transistor and a fourteenth transistor; The first terminal of the second capacitor is electrically connected to the nth level carry control node, and the second terminal of the second capacitor is electrically connected to the nth level control node. The gate of the thirteenth transistor is electrically connected to the nth level carry control node, the first terminal of the thirteenth transistor is electrically connected to the carry control clock signal terminal, and the second terminal of the thirteenth transistor is electrically connected to the nth level carry signal output terminal. The gate of the fourteenth transistor is electrically connected to the nth level control node, the first terminal of the fourteenth transistor is electrically connected to the carry signal output terminal of the nth level, and the second terminal of the fourteenth transistor is electrically connected to the second voltage terminal.

20. A drive module comprising a plurality of drive circuits as described in any one of claims 1 to 19.

21. The drive module as described in claim 20, wherein, The drive module includes M drive units, where M is an integer greater than 1 and m is a positive integer less than or equal to M; each drive unit includes multiple drive circuits cascaded together. The m-th drive unit includes q-level drive circuits. The first control terminal of the first-level drive circuit in the m-th drive unit is electrically connected to the corresponding pull-up start control terminal. The second control terminal of the first-level drive circuit in the m-th drive unit is electrically connected to the drive signal output terminal of the j-th drive circuit in the m-th drive unit. j is greater than or equal to 2 but less than q. j is an integer and q is a positive integer greater than 1. The first control terminal of the q-th stage drive circuit in the m-th drive unit is electrically connected to the drive signal output terminal of the qi-th stage drive circuit in the m-th drive unit, where i is an integer, i is greater than or equal to 1 and less than q, and the second control terminal of the q-th stage drive circuit is electrically connected to the corresponding pull-down start control terminal.

22. The drive module as described in claim 21, wherein, Includes M initial voltage lines; Multiple driving circuits in the m-th driving unit are electrically connected to the corresponding row pixel circuits in the m-th display area, and are used to provide driving signals to the corresponding row pixel circuits.

23. The drive module as described in claim 20, wherein, The driving circuit further includes a cascaded control circuit. The first node control circuit includes an input circuit; n is a positive integer; the cascaded control circuit includes a carry input terminal, a carry reset terminal, and a carry signal output terminal; the input circuit is electrically connected to the input control terminal; the second control terminal is a carry reset terminal; the driving module includes multiple cascaded driving circuits. The drive module includes a carry input terminal and a starting voltage terminal of the first-stage drive circuit; The carry input terminal of the a-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the ak-th stage drive circuit included in the drive module, where a is an integer greater than 1 and k is an integer greater than or equal to 1. The carry reset terminal of the b-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the b+r-th stage drive circuit included in the drive module; b is a positive integer, and r is an integer greater than or equal to 1. The carry reset terminal of the b-th stage drive circuit included in the drive module is electrically connected to the carry signal output terminal of the b+2-th stage drive circuit included in the drive module; b is a positive integer.

24. A driving method applied to the driving module of claim 21, the driving method comprising: During the display cycle, when the display area corresponding to the m-th driving unit is refreshed, During the corresponding input phase of the display cycle, the corresponding pull-up start control terminal provides a valid pull-up start control signal; During the corresponding reset phase of the display cycle, the corresponding pull-down start control terminal provides a valid pull-down start control signal.

25. A driving method applied to the driving module of claim 23, the driving method comprising: When the input control terminal provides a valid input control signal, the corresponding stage drive circuit provides a valid drive signal; When the input control terminal provides an invalid input control signal, the corresponding stage drive circuit stops providing a valid drive signal.

26. A display device comprising the driving module as described in any one of claims 20 to 23.

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