Radio frequency front-end module and radio frequency chip

Abstract

The present invention is applicable to the technical field of radio frequency, and particularly to a radio frequency front-end module and a radio frequency chip. The radio frequency front-end module comprises a substrate, and a first die and a second die that are arranged on the substrate; the first die is electrically connected to the second die; the first die is provided with a bias circuit, and the bias circuit is used for providing a bias voltage; the second die is provided with an amplification circuit and a temperature compensation circuit, the amplification circuit is used for performing amplification processing on a received signal, and the temperature compensation circuit is used for performing compensation processing on an error caused by temperature; a first end of the bias circuit is used for receiving an enable signal, and a second end of the bias circuit is electrically connected to a first end of the temperature compensation circuit; a first end of the amplification circuit is used for receiving an external logic control signal, and a second end of the amplification circuit is connected to a second end of the temperature compensation circuit. Compared with the prior art, the present invention effectively reduces the complexity of the radio frequency front-end module and the radio frequency chip in realizing transmission power control, reduces radiation, reduce the energy consumption, and prolongs the service life.

Description

RF front-end module and RF chip Technical Field

[0001] This invention relates to the field of radio frequency technology, and in particular to a radio frequency front-end module and a radio frequency chip. Background Technology

[0002] Mobile communication terminals have become increasingly prevalent in today's society for wireless communication, and their ever-growing processing capabilities have gradually transformed them into mobile multimedia centers. Currently, there are two main technological approaches in mobile communication: cellular mobile communication and Wi-Fi. These two systems are still evolving, sharing the common characteristics of larger communication bandwidth and higher transmission rates to meet the ever-growing needs of users.

[0003] In communication systems such as Wi-Fi, radio frequency (RF) amplifier modules are often required. These modules are used to output RF signals. Since Wi-Fi is a Time Division Duplexing (TDD) system, an enable signal is typically used to control the operation of the amplifier circuit. This enable signal is synchronized with the RF signal in the time domain and has specific timing requirements. Because the RF amplifier module requires a certain amount of time (usually several microseconds) to reach normal gain after being turned on, there is a slow rise in the leading edge of the output signal, which can lead to performance degradation.

[0004] Therefore, there is an urgent need for a new RF front-end module and RF chip to solve the above problems. Summary of the Invention

[0005] This invention provides an RF front-end module and an RF chip, which aims to reduce the complexity of RF front-end module and RF chip in implementing transmit power control, reduce radiation, reduce energy consumption, and improve service life.

[0006] In a first aspect, the present invention provides a radio frequency front-end module, the radio frequency front-end module including a substrate and a first chip and a second chip disposed on the substrate, the first chip and the second chip being electrically connected.

[0007] The first chip has a bias circuit for providing a bias voltage; the second chip has an amplifier circuit and a temperature compensation circuit. The amplifier circuit amplifies the received signal, and the temperature compensation circuit compensates for errors caused by temperature. The first terminal of the bias circuit receives an enable signal, and the second terminal of the bias circuit is electrically connected to the first terminal of the temperature compensation circuit. The first terminal of the amplifier circuit receives an external logic control signal, and the second terminal of the amplifier circuit is connected to the second terminal of the temperature compensation circuit. The third terminal of the amplifier circuit outputs a signal.

[0008] The bias circuit includes a first resistor, a cascaded diode circuit, a voltage regulator circuit, and a first pulse generating circuit and / or a second pulse generating circuit. The first terminal of the first resistor serves as the first terminal of the bias circuit. The second terminal of the first resistor and the first terminal of the cascaded diode circuit are connected to the first terminal of the voltage regulator circuit. The second terminal of the cascaded diode circuit is grounded. The second terminal of the voltage regulator circuit serves as the second terminal of the bias circuit. The first terminal of the first pulse generating circuit is connected to the first terminal of the first resistor. The second terminal of the first pulse generating circuit is connected to the second terminal of the first resistor. The first terminal of the second pulse generating circuit is connected to the third terminal of the voltage regulator circuit. The second terminal of the second pulse generating circuit is grounded. The first pulse generating circuit and the second pulse generating circuit are used to generate pulse signals, and the voltage regulator circuit is used to provide a stable bias voltage.

[0009] Preferably, the voltage regulator circuit includes a first transistor, a second transistor, a second resistor, a third resistor, a fourth resistor, and a first capacitor. The collector of the first transistor is connected to the first end of the second resistor and is used to connect to the supply voltage. The base of the first transistor and the second end of the second resistor are respectively connected to the collector of the second transistor. The emitter of the first transistor is connected to the first end of the third resistor and the first end of the first capacitor. The emitter of the first transistor serves as the second end of the voltage regulator circuit. The emitter of the second transistor serves as the first end of the voltage regulator circuit. The base of the second transistor is connected to the second end of the third resistor and the first end of the fourth resistor. The base of the second transistor serves as the third end of the voltage regulator circuit. The second end of the fourth resistor is grounded, and the second end of the first capacitor is grounded.

[0010] Preferably, the first pulse generating circuit includes a fifth resistor and a second capacitor, wherein the first end of the fifth resistor serves as the first end of the first pulse generating circuit, the second end of the fifth resistor is connected to the first end of the second capacitor, and the second end of the second capacitor serves as the second end of the first pulse generating circuit.

[0011] Preferably, the second pulse generating circuit includes a sixth resistor and a third capacitor. The first end of the sixth resistor serves as the first end of the second pulse generating circuit, and the second end of the sixth resistor is connected to the first end of the third capacitor. The second end of the third capacitor serves as the second end of the second pulse generating circuit.

[0012] Preferably, the cascaded diode circuit includes a third transistor and a fourth transistor. The collector of the third transistor serves as the first terminal of the cascaded diode circuit. The base of the third transistor is connected to the second terminal of the first resistor and the emitter of the third transistor. The emitter of the third transistor is connected to the collector of the fourth transistor and the base of the fourth transistor. The emitter of the fourth transistor serves as the second terminal of the cascaded diode circuit.

[0013] Preferably, the temperature compensation circuit includes a seventh resistor, an eighth resistor, a ninth resistor, and a fifth transistor. The first end of the seventh resistor is connected to the power supply voltage, the second end of the seventh resistor is connected to the collector of the fifth transistor, the base of the fifth transistor serves as the first terminal of the temperature compensation circuit, the emitter of the fifth transistor is connected to the first terminals of the eighth resistor and the ninth resistor, respectively, the second terminal of the eighth resistor is grounded, and the second terminal of the ninth resistor serves as the second terminal of the temperature compensation circuit.

[0014] Preferably, the amplification circuit includes a fourth capacitor, a fifth capacitor, a first inductor, and a sixth transistor. The first terminal of the fourth capacitor serves as the first terminal of the amplification circuit, the second terminal of the fourth capacitor is connected to the base of the sixth transistor, the base of the sixth transistor serves as the second terminal of the amplification circuit, the emitter of the sixth transistor is grounded, and the collector of the sixth transistor is connected to the first terminal of the first inductor and the first terminal of the fifth capacitor, respectively. The second terminal of the first inductor is used to connect to an external power supply voltage, and the second terminal of the fifth capacitor serves as the third terminal of the amplification circuit.

[0015] Preferably, the first chip is further provided with a first pin, which is connected to the second terminal of the voltage regulator circuit, and the second chip is further provided with a second pin, which is connected to the first terminal of the temperature compensation circuit. The first pin and the second pin are connected by a wire.

[0016] Secondly, the present invention also provides a radio frequency chip, the radio frequency chip comprising the radio frequency front-end module as described in any of the above embodiments.

[0017] Compared with existing technologies, this invention utilizes a substrate and a first chip and a second chip disposed on the substrate, which are electrically connected. The first chip has a bias circuit for providing a bias voltage. The second chip has an amplifier circuit and a temperature compensation circuit. The amplifier circuit amplifies the received signal, and the temperature compensation circuit compensates for temperature-induced errors. The first terminal of the bias circuit receives an enable signal, and the second terminal of the bias circuit is electrically connected to the first terminal of the temperature compensation circuit. The first terminal of the amplifier circuit receives an external logic control signal, and the second terminal of the amplifier circuit is connected to the second terminal of the temperature compensation circuit. The third terminal of the amplifier circuit outputs a signal. This invention effectively reduces the complexity of RF front-end modules and RF chips in achieving transmit power control, reduces radiation, lowers energy consumption, and increases service life. Attached Figure Description

[0018] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0019] Figure 1 is a schematic diagram of the structure of an RF front-end module with a first pulse generation circuit provided in an embodiment of the present invention;

[0020] Figure 2 shows the voltage waveform of the RF front-end module in Figure 1;

[0021] Figure 3 is a schematic diagram of the structure of the radio frequency front-end module with a second pulse generation circuit provided in an embodiment of the present invention;

[0022] Figure 4 shows the voltage waveform of the RF front-end module in Figure 3. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] Example 1

[0025] Please refer to Figures 1-4. This invention provides a radio frequency (RF) front-end module 100, which includes a substrate and a first chip DIE1 and a second chip DIE2 disposed on the substrate. The first chip DIE1 and the second chip DIE2 are electrically connected. Specifically, the first chip DIE1 can be a CMOS process chip, but is not limited to CMOS process, and the second chip DIE2 can be a GAAS process chip, but is not limited to GAAS process; both can be chips manufactured using other processes.

[0026] The first chip DIE1 is provided with a bias circuit 1, which is used to provide a bias voltage; the second chip DIE2 is provided with an amplifier circuit 3 and a temperature compensation circuit 2. The amplifier circuit 3 is used to amplify the received signal, and the temperature compensation circuit 2 is used to compensate for the error caused by temperature to the signal; the first terminal of the bias circuit 1 is used to receive an enable signal, the second terminal of the bias circuit 1 is electrically connected to the first terminal of the temperature compensation circuit 2, the first terminal of the amplifier circuit 3 is used to receive an external logic control signal, the second terminal of the amplifier circuit 3 is connected to the second terminal of the temperature compensation circuit 2, and the third terminal of the amplifier circuit 3 is used to output a signal;

[0027] The bias circuit 1 includes a first resistor R1, a cascaded diode circuit 11, and a voltage regulator circuit 12. The first end of the first resistor R1 serves as the first end of the bias circuit 1. The second end of the first resistor R1 and the first end of the cascaded diode circuit 11 are connected to the first end of the voltage regulator circuit 12. The second end of the cascaded diode circuit 11 is grounded, and the second end of the voltage regulator circuit 12 serves as the second end of the bias circuit 1. The voltage regulator circuit 12 is used to provide a stable bias voltage.

[0028] The bias circuit 1 further includes a first pulse generating circuit 13 and / or a second pulse generating circuit 14. The first terminal of the first pulse generating circuit 13 is connected to the first terminal of the first resistor R1, the second terminal of the first pulse generating circuit 13 is connected to the second terminal of the first resistor R1, the first terminal of the second pulse generating circuit 14 is connected to the third terminal of the voltage regulator circuit 12, and the second terminal of the second pulse generating circuit 14 is grounded. The first pulse generating circuit 13 and the second pulse generating circuit 14 are used to generate pulse signals. In this embodiment of the invention, the voltage regulator circuit 12 includes a first transistor Q1, a second transistor Q2, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first capacitor C1. The collector of the first transistor Q1 is connected to the first end of the second resistor R2 and is used to connect to the supply voltage VDD. The base of the first transistor Q1 and the second end of the second resistor R2 are respectively connected to the collector of the second transistor Q2. The emitter of the first transistor Q1 is connected to the first end of the third resistor R3 and the first end of the first capacitor C1. The emitter of the first transistor Q1 serves as the second end of the voltage regulator circuit 12, and the emitter of the second transistor Q2 serves as the first end of the voltage regulator circuit 12. The base of the second transistor Q2 is connected to the second end of the third resistor R3 and the first end of the fourth resistor R4. The base of the second transistor Q2 serves as the third end of the voltage regulator circuit 12. The second end of the fourth resistor R4 is grounded, and the second end of the first capacitor C1 is grounded. Specifically, the first transistor Q1 and the second transistor Q2 are NPN transistors.

[0029] In this embodiment of the invention, the first pulse generating circuit 13 includes a fifth resistor R5 and a second capacitor C2. The first end of the fifth resistor R5 serves as the first end of the first pulse generating circuit 13, and the second end of the fifth resistor R5 is connected to the first end of the second capacitor C2. The second end of the second capacitor C2 serves as the second end of the first pulse generating circuit 13.

[0030] In this embodiment of the invention, the second pulse generating circuit 14 includes a sixth resistor R6 and a third capacitor C3. The first end of the sixth resistor R6 serves as the first end of the second pulse generating circuit 14, and the second end of the sixth resistor R6 is connected to the first end of the third capacitor C3. The second end of the third capacitor C3 serves as the second end of the second pulse generating circuit 14.

[0031] In this embodiment of the invention, the cascaded diode circuit 11 includes a third transistor Q3 and a fourth transistor Q4. The collector of the third transistor Q3 serves as the first terminal of the cascaded diode circuit 11. The base of the third transistor Q3 is connected to the second terminal of the first resistor R1 and the emitter of the third transistor Q3. The emitter of the third transistor Q3 is connected to the collector and the base of the fourth transistor Q4. The emitter of the fourth transistor Q4 serves as the second terminal of the cascaded diode circuit 11. Specifically, the third transistor Q3 and the fourth transistor Q4 are NPN transistors. Since the base and collector of the third transistor Q3 are connected, forming a PN junction with the emitter of the third transistor Q3, and the base and collector of the fourth transistor Q4 are connected, forming a PN junction with the emitter of the fourth transistor Q4, the base and collector of the third transistor Q3 will maintain a stable standard voltage Vref. Meanwhile, since the third transistor Q3 and the fourth transistor Q4 can be connected in more cascades, different standard voltages Vref can be generated.

[0032] In this embodiment of the invention, the temperature compensation circuit 2 includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a fifth transistor Q5. The first end of the seventh resistor R7 is connected to the power supply voltage VDD, and the second end of the seventh resistor R7 is connected to the collector of the fifth transistor Q5. The base of the fifth transistor Q5 serves as the first end of the temperature compensation circuit 2. The emitter of the fifth transistor Q5 is connected to the first end of the eighth resistor R8 and the first end of the ninth resistor R9, respectively. The second end of the eighth resistor R8 is grounded, and the second end of the ninth resistor R9 serves as the second end of the temperature compensation circuit 2.

[0033] In this embodiment of the invention, the amplifier circuit 3 includes a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, and a sixth transistor Q6. The first terminal of the fourth capacitor C4 serves as the first terminal of the amplifier circuit 3, and the second terminal of the fourth capacitor C4 is connected to the base of the sixth transistor Q6. The base of the sixth transistor Q6 serves as the second terminal of the amplifier circuit 3. The emitter of the sixth transistor Q6 is grounded, and the collector of the sixth transistor Q6 is connected to the first terminal of the first inductor L1 and the first terminal of the fifth capacitor C5. The second terminal of the first inductor L1 is used to connect to the external power supply voltage VCC, and the second terminal of the fifth capacitor C5 serves as the third terminal of the amplifier circuit 3.

[0034] In this embodiment of the invention, the first chip DIE1 further includes a first pin PAD1, which is connected to the second terminal of the voltage regulator circuit 12. The second chip DIE2 further includes a second pin PAD2, which is connected to the first terminal of the temperature compensation circuit 2. The first pin PAD1 and the second pin PAD2 are connected by a wire. The first pin PAD1 and the second pin PAD2 can also be connected in other ways, such as bonding wire connection or inverted connection.

[0035] In this embodiment of the invention, when the RF front-end module 100 is initially in its initial state, the enable signal voltage is 0V, so the collector voltage of the third transistor Q3 is 0V, and the emitter voltage of the first transistor Q1 is 0V. If, for some reason, the emitter voltage of the first transistor Q1 increases, after passing through the third resistor R3, the base voltage of the second transistor Q2 increases, and the collector and emitter of the second transistor Q2 conduct, thereby pulling down the collector voltage of the second transistor Q2, which in turn lowers the emitter voltage of the first transistor Q1. Therefore, the emitter voltage of the first transistor Q1 is always kept at a low voltage.

[0036] When the enable signal voltage goes high, for example, 3.3V, the collector of the third transistor Q3 remains high, and the base voltage is between the PN junction voltages of the third transistor Q3 and the fourth transistor Q4, such as 1.4V, i.e., a standard voltage Vref = 1.4V. At this time, the emitter of the first transistor Q1 outputs a stable high voltage VPAD1. When VPAD1 rises due to some reason, the base voltage of the second transistor Q2 rises, and the collector voltage of the second transistor Q2 falls, thus causing VPAD1 to fall. When VPAD1 falls due to some reason, the base voltage of the second transistor Q2 falls, and the collector voltage of the second transistor Q2 rises, causing VPAD1 to rise. Therefore, through the negative feedback effect of the first transistor Q1 and the second transistor Q2, VPAD1 can maintain a stable voltage. The voltage division ratio of the third resistor R3 and the fourth resistor R4 can be used to adjust the voltage value of VPAD1. When the voltage division ratio (R3 / R4) of the third resistor R3 and the fourth resistor R4 increases, VPAD1 increases; when it decreases, VPAD1 decreases.

[0037] Please refer to Figures 1-2. Figure 1 is a schematic diagram of the structure of the RF front-end module 100 with the first pulse generation circuit 13 provided in an embodiment of the present invention. Figure 2 is a voltage waveform diagram of the RF front-end module 100 in Figure 1. When the bias circuit 1 includes the first pulse generation circuit 13, a steep rising edge is generated instantaneously when the enable signal is turned on. This rising edge signal is transmitted to the base and collector of the third transistor Q3 through the series circuit composed of the fifth resistor R5 and the second capacitor C2, generating a sharp pulse higher than the normal level at the collector of the third transistor Q3. After the closed-loop action of the first transistor Q1 and the second transistor Q2, a sharp pulse is generated at the leading edge of VPAD1. Its voltage waveform diagram is shown in Figure 2. This causes the leading edge of the bias voltage (current) finally transmitted to the base of the sixth transistor Q6 to also generate a sharp pulse. This pulse allows the sixth transistor Q6 to turn on more quickly, thereby optimizing the RF performance.

[0038] Please refer to Figures 3 and 4. Figure 3 is a schematic diagram of the structure of the RF front-end module 100 with the second pulse generation circuit 14 provided in an embodiment of the present invention. Figure 4 is a voltage waveform diagram of the RF front-end module 100 in Figure 3. A series circuit consisting of a sixth resistor R6 and a third capacitor C3 is added at the base of the second transistor Q2, and the second terminal of the third capacitor C3 is grounded. When the enable signal changes to a high level, the emitter of the first transistor Q1 will generate a steep high-level rising edge. This rising edge signal is transmitted to the base of the second transistor Q2 through the voltage divider network consisting of the third resistor R3, the fourth resistor R4, the sixth resistor R6, and the third capacitor C3. At this time, the third capacitor C3 will be charged. The impedance of the series network consisting of the sixth resistor R6 and the third capacitor C3 is low, and the voltage at the emitter of the first transistor is also low. Therefore, the emitter of the first transistor Q1 will output a pulse higher than the normal voltage. After a few microseconds to tens of microseconds, the voltage of the third capacitor C3 increases, the impedance of the series network composed of the sixth resistor R6 and the third capacitor C3 increases, and the emitter output voltage of the first transistor Q1 tends to stabilize.

[0039] It should be noted that Figures 1 and 3 are only schematic diagrams of the structure of the first pulse generating circuit 13 or the second pulse generating circuit 14 for the RF front-end module 100. The first pulse generating circuit 13 and the second pulse generating circuit 14 are in an AND / OR relationship. The first pulse generating circuit 13 and the second pulse generating circuit 14 can also be set in the bias circuit 1 simultaneously according to the actual situation.

[0040] It should be noted that the structure of each circuit in this invention is not limited to any particular form (such as cascaded diode circuit 11, voltage regulator circuit 12, pulse generation circuit 13, etc.). Any existing circuit that can achieve these functions is feasible. For example, taking voltage regulator circuit 12 as an example, in this invention, voltage regulator circuit 12 is specifically a circuit structure composed of a first transistor Q1, a second transistor Q2, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first capacitor C1, which is used to provide a stable bias voltage. It should be noted that for this invention, voltage regulator circuit 12 is not limited to the above structure; any other existing voltage regulator circuit that can achieve the function of providing a stable bias voltage is feasible.

[0041] Compared with existing technologies, this invention utilizes a substrate and a first chip and a second chip disposed on the substrate, which are electrically connected. The first chip has a bias circuit for providing a bias voltage. The second chip has an amplifier circuit and a temperature compensation circuit. The amplifier circuit amplifies the received signal, and the temperature compensation circuit compensates for temperature-induced errors. The first terminal of the bias circuit receives an enable signal, and the second terminal of the bias circuit is electrically connected to the first terminal of the temperature compensation circuit. The first terminal of the amplifier circuit receives an external logic control signal, and the second terminal of the amplifier circuit is connected to the second terminal of the temperature compensation circuit. The third terminal of the amplifier circuit outputs a signal. This invention effectively reduces the complexity of RF front-end modules and RF chips in achieving transmit power control, reduces radiation, lowers energy consumption, and increases service life.

[0042] Example 2

[0043] This invention also provides a radio frequency (RF) chip, which includes the RF front-end module 100 as described in the above embodiments and can achieve the same technical effects. Please refer to the description in the above embodiments, which will not be repeated here.

[0044] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0045] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A radio frequency front-end module, characterized in that, The radio frequency front-end module includes a substrate and a first chip and a second chip disposed on the substrate, wherein the first chip and the second chip are electrically connected. The first chip has a bias circuit for providing a bias voltage; the second chip has an amplifier circuit and a temperature compensation circuit. The amplifier circuit amplifies the received signal, and the temperature compensation circuit compensates for errors caused by temperature. The first terminal of the bias circuit receives an enable signal, and the second terminal of the bias circuit is electrically connected to the first terminal of the temperature compensation circuit. The first terminal of the amplifier circuit receives an external logic control signal, and the second terminal of the amplifier circuit is connected to the second terminal of the temperature compensation circuit. The third terminal of the amplifier circuit outputs a signal. The bias circuit includes a first resistor, a cascaded diode circuit, a voltage regulator circuit, and a first pulse generating circuit and / or a second pulse generating circuit. The first terminal of the first resistor serves as the first terminal of the bias circuit. The second terminal of the first resistor and the first terminal of the cascaded diode circuit are connected to the first terminal of the voltage regulator circuit. The second terminal of the cascaded diode circuit is grounded. The second terminal of the voltage regulator circuit serves as the second terminal of the bias circuit. The first terminal of the first pulse generating circuit is connected to the first terminal of the first resistor. The second terminal of the first pulse generating circuit is connected to the second terminal of the first resistor. The first terminal of the second pulse generating circuit is connected to the third terminal of the voltage regulator circuit. The second terminal of the second pulse generating circuit is grounded. The first pulse generating circuit and the second pulse generating circuit are used to generate pulse signals, and the voltage regulator circuit is used to provide a stable bias voltage.

2. The radio frequency front-end module as described in claim 1, characterized in that, The voltage regulator circuit includes a first transistor, a second transistor, a second resistor, a third resistor, a fourth resistor, and a first capacitor. The collector of the first transistor is connected to the first end of the second resistor and is used to connect to the supply voltage. The base of the first transistor and the second end of the second resistor are respectively connected to the collector of the second transistor. The emitter of the first transistor is connected to the first end of the third resistor and the first end of the first capacitor. The emitter of the first transistor serves as the second terminal of the voltage regulator circuit. The emitter of the second transistor serves as the first terminal of the voltage regulator circuit. The base of the second transistor is connected to the second end of the third resistor and the first end of the fourth resistor. The base of the second transistor serves as the third terminal of the voltage regulator circuit. The second end of the fourth resistor is grounded, and the second end of the first capacitor is grounded.

3. The radio frequency front-end module as described in claim 1, characterized in that, The first pulse generating circuit includes a fifth resistor and a second capacitor. The first end of the fifth resistor serves as the first end of the first pulse generating circuit, and the second end of the fifth resistor is connected to the first end of the second capacitor. The second end of the second capacitor serves as the second end of the first pulse generating circuit.

4. The radio frequency front-end module as described in claim 1, characterized in that, The second pulse generating circuit includes a sixth resistor and a third capacitor. The first end of the sixth resistor serves as the first end of the second pulse generating circuit, and the second end of the sixth resistor is connected to the first end of the third capacitor. The second end of the third capacitor serves as the second end of the second pulse generating circuit.

5. The radio frequency front-end module as described in claim 1, characterized in that, The cascaded diode circuit includes a third transistor and a fourth transistor. The collector of the third transistor serves as the first terminal of the cascaded diode circuit. The base of the third transistor is connected to the second terminal of the first resistor and the collector of the third transistor, respectively. The emitter of the third transistor is connected to the collector of the fourth transistor and the base of the fourth transistor, respectively. The emitter of the fourth transistor serves as the second terminal of the cascaded diode circuit.

6. The radio frequency front-end module as described in claim 1, characterized in that, The temperature compensation circuit includes a seventh resistor, an eighth resistor, a ninth resistor, and a fifth transistor. The first end of the seventh resistor is connected to the power supply voltage, the second end of the seventh resistor is connected to the collector of the fifth transistor, the base of the fifth transistor serves as the first terminal of the temperature compensation circuit, the emitter of the fifth transistor is connected to the first terminal of the eighth resistor and the first terminal of the ninth resistor, the second terminal of the eighth resistor is grounded, and the second terminal of the ninth resistor serves as the second terminal of the temperature compensation circuit.

7. The radio frequency front-end module as described in claim 1, characterized in that, The amplifier circuit includes a fourth capacitor, a fifth capacitor, a first inductor, and a sixth transistor. The first terminal of the fourth capacitor serves as the first terminal of the amplifier circuit. The second terminal of the fourth capacitor is connected to the base of the sixth transistor, which serves as the second terminal of the amplifier circuit. The emitter of the sixth transistor is grounded. The collector of the sixth transistor is connected to the first terminal of the first inductor and the first terminal of the fifth capacitor. The second terminal of the first inductor is used to connect to an external power supply voltage. The second terminal of the fifth capacitor serves as the third terminal of the amplifier circuit.

8. The radio frequency front-end module as described in claim 1, characterized in that, The first chip is further provided with a first pin, which is connected to the second end of the voltage regulator circuit. The second chip is further provided with a second pin, which is connected to the first end of the temperature compensation circuit. The first pin and the second pin are connected by a wire.

9. A radio frequency chip, characterized in that, The radio frequency chip includes the radio frequency front-end module as described in any one of claims 1-8.

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