Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a base substrate (1), a driver circuit layer assembly (2), a first electrode (3) and second electrodes (6), wherein the base substrate, the driver circuit layer assembly, the first electrode and the second electrodes are stacked. The driver circuit layer assembly (2) comprises a gate layer (21) and a conductor layer (24), and the gate layer (21) comprises a gate (211) and gate lines (212) extending in a first direction (X). The conductor layer (24) comprises data lines (241) and signal wires (244), the data lines and the signal wires extend in a second direction (Y), every two adjacent gate lines (212) form a gate line group (212Z), and a plurality of data lines (241) intersect with a plurality of gate line groups (212Z) to define a display area (AA) into a plurality of pixel areas (PXQ), and the driver circuit layer assembly (2) comprises first transistors (T1) and second transistors (T2). Every two adjacent second electrodes (6) are a first pixel electrode (6a) and a second pixel electrode (6b), the first pixel electrode (6a) comprises a first electrode portion (6a1) and a first lead portion (6a2) connected to each other, the second pixel electrode (6b) comprises a second electrode portion (6b1) and a second lead portion (6b2) connected to each other, the first lead portion (6a2) is connected to the corresponding first transistor (T1), the first transistor (T1) and the first electrode portion (6a1) are located in the same pixel column (PXL), the second lead portion (6b2) is connected to the corresponding second transistor (T2), and the second electrode portion (6b1) and the second transistor (T2) are respectively located in adjacent pixel columns (PXL). The orthographic projections of the second lead portions (6b2) on the base substrate (1) obliquely intersect with the orthographic projections of the signal wires (244) on the base substrate (1).

Description

Array substrate and display device

[0001] Cross-referencing

[0002] This disclosure claims priority to patent application No. PCT / CN2024 / 129376, filed on November 1, 2024, entitled "Array Substrate and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0004] Liquid crystal displays (LCDs) are widely used in various display fields, such as homes, public places, offices, and personal electronic products.

[0005] However, with the development of technology, current display products cannot meet the increasingly higher requirements of customers.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0008] According to one aspect of this disclosure, an array substrate is provided having a display area and a non-display area, the non-display area including a fan-out region and a bonding region, the array substrate comprising:

[0009] Substrate;

[0010] A driving circuit layer group is disposed on one side of the substrate. The driving circuit layer group includes a gate layer and a conductor layer. The gate layer includes a gate and a gate line, and the gate line extends along a first direction. The conductor layer includes data lines and signal lines, and the data lines and signal lines extend along a second direction. Two adjacent gate lines form a gate line group. Multiple data lines and multiple gate line groups are intersected to define the display area as multiple pixel areas. The second direction intersects with the first direction. The driving circuit layer group includes multiple transistors, and the multiple transistors include a first transistor and a second transistor.

[0011] A first electrode and a second electrode are disposed on the side of the driving circuit layer group away from the substrate. A second insulating layer is disposed between the second electrode and the first electrode. Two adjacent second electrodes are a first pixel electrode and a second pixel electrode. The first pixel electrode includes a first electrode portion and a first lead portion connected to each other. The second pixel electrode includes a second electrode portion and a second lead portion connected to each other. The first lead portion is connected to the first transistor. The first transistor and the first electrode portion are located in the same pixel column. The second lead portion is connected to the second transistor. The second electrode portion and the second transistor are located in adjacent pixel columns.

[0012] The orthographic projection of the second lead portion on the substrate is obliquely intersected with the orthographic projection of the signal trace on the substrate.

[0013] In one exemplary embodiment of this disclosure, the array substrate further includes a conductive auxiliary layer, the conductive auxiliary layer including a first auxiliary trace, the first auxiliary trace being electrically connected to the first electrode; the orthographic projection of the first auxiliary trace on the substrate does not overlap with the orthographic projections of the first lead portion and the second lead portion on the substrate.

[0014] In one exemplary embodiment of this disclosure, the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the first auxiliary trace near the corner of the first auxiliary trace on the substrate, while the other portions of the orthographic projection of the second electrode on the substrate do not overlap with the orthographic projection of the first auxiliary trace on the substrate.

[0015] In one exemplary embodiment of this disclosure, the first auxiliary trace extends along the second direction, and the orthographic projection of the first auxiliary trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

[0016] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0017] A spacer portion is disposed on the side of the second insulating layer away from the substrate, and the orthographic projection of the spacer portion on the substrate does not overlap with the orthographic projection of the first auxiliary trace on the substrate.

[0018] In one exemplary embodiment of this disclosure, the first electrode portion and the second electrode portion are located within the same pixel region.

[0019] In one exemplary embodiment of this disclosure, three pixel regions arranged along the first direction form a group, and a first auxiliary trace is provided in a group of pixel regions, or a first auxiliary trace is provided between two adjacent groups of pixel regions.

[0020] In one exemplary embodiment of this disclosure, the conductive auxiliary layer further includes a third auxiliary trace, the orthographic projection of the third auxiliary trace on the substrate is located between the orthographic projections of two adjacent second electrodes on the substrate, the third auxiliary trace is disconnected, and the virtual extension line of the third auxiliary trace intersects with the second lead portion.

[0021] In one exemplary embodiment of this disclosure, in the second direction, the first transistor and the second transistor are each located on opposite sides of the pixel region.

[0022] In one exemplary embodiment of this disclosure, the plurality of transistors include multiple groups of transistors, each group of transistors includes two transistors, the two transistors in the same group are located between two adjacent gate lines in the same group, the two transistors in the same group are connected to opposite sides of the same data line in the first direction and are staggered in the second direction; the two gates of the two transistors in the same group are connected one-to-one to two adjacent gate lines in the same group.

[0023] In one exemplary embodiment of this disclosure, the gate line is configured as a straight line extending along the first direction.

[0024] In an exemplary embodiment of this disclosure, the data line and the signal trace are configured as strips extending along the second direction, a portion of the signal trace is located within the pixel region, the driving circuit layer group includes a first insulating layer, the first insulating layer is located between the conductor layer and the first electrode, the first electrode is connected to the signal trace through a third via on the first insulating layer, and the orthographic projection of the third via on the substrate is located between the orthographic projections of two adjacent transistors on the substrate.

[0025] In one exemplary embodiment of this disclosure, the orthographic projection of the second lead portion on the substrate overlaps with the orthographic projection of the signal trace on the substrate, while the orthographic projection of the first lead portion on the substrate does not overlap with the orthographic projection of the signal trace on the substrate.

[0026] In an exemplary embodiment of this disclosure, the second lead portion includes a third segment and a fourth segment. The third segment is connected to the second electrode portion, and the fourth segment is connected to one end of the third segment away from the second electrode portion. The fourth segment is connected to the second transistor. The fourth segment extends along the first direction, and the third segment extends along a third direction. The third direction intersects the first direction and the second direction. The orthographic projection of the third segment on the substrate is obliquely intersected with the orthographic projection of the signal trace on the substrate.

[0027] In one exemplary embodiment of this disclosure, the included angle between the third segment and the fourth segment is greater than or equal to 135° and less than 180°.

[0028] In one exemplary embodiment of this disclosure, a portion of the second pixel electrodes among the plurality of second pixel electrodes are third sub-pixel electrodes, and a portion of the second pixel electrodes among the plurality of second pixel electrodes are fourth sub-pixel electrodes. The third sub-pixel electrodes and the fourth sub-pixel electrodes are located in adjacent pixel columns and adjacent pixel rows, such that the third sub-pixel electrodes and the fourth sub-pixel electrodes are arranged obliquely opposite to each other.

[0029] In an exemplary embodiment of this disclosure, the orthographic projection of the second lead portion of the third sub-pixel electrode on the substrate and the orthographic projection of the second lead portion of the fourth sub-pixel electrode on the substrate are obliquely intersecting with the orthographic projection of the same signal trace on the substrate. The fourth segment of the third sub-pixel electrode and the fourth segment of the fourth sub-pixel electrode are located between two gate lines in the same group. The third segment of the third sub-pixel electrode and the third segment of the fourth sub-pixel electrode are opposite to and parallel to each other in a fourth direction, which is perpendicular to the third direction.

[0030] In an exemplary embodiment of this disclosure, the second electrode portion of the third sub-pixel electrode has a third edge line and a fourth edge line disposed opposite to each other. The third edge line intersects the first direction, and the fourth edge line intersects the first direction. The third segment of the third sub-pixel electrode is closer to the third edge line than the fourth edge line. The angle between the edge line of the third segment of the third sub-pixel electrode closer to the second electrode portion and the third edge line is an acute angle.

[0031] The second lead portion of the third sub-pixel electrode further includes a fifth segment, which is connected between the third segment and the second electrode portion. The angle between the edge of the fifth segment connected to the third edge and the third edge is a right angle or an obtuse angle, and the angle between the fifth segment and the edge of the third segment near the second electrode portion is also a right angle or an obtuse angle.

[0032] In an exemplary embodiment of this disclosure, the second electrode portion of the fourth sub-pixel electrode has a third edge line and a fourth edge line disposed opposite to each other. The third edge line intersects the first direction, and the fourth edge line intersects the first direction. The third segment of the fourth sub-pixel electrode is closer to the fourth edge line than the third edge line, and the angle between the edge line of the third segment of the fourth sub-pixel electrode closer to the second electrode portion and the fourth edge line is an obtuse angle.

[0033] In an exemplary embodiment of this disclosure, the third segment of the fourth sub-pixel electrode is connected to the edge line of the second electrode portion extending along the first direction, one side edge line of the third segment of the fourth sub-pixel electrode is connected to the second electrode portion, and the opposite side edge line of the third segment of the fourth sub-pixel electrode is connected to the second electrode portion through a straight edge line extending along the second direction; the fifth segment of the third sub-pixel electrode is connected to the edge line of the second electrode portion extending along the first direction.

[0034] In one exemplary embodiment of this disclosure, the third segment is connected to the edge of the second electrode portion near the second transistor connected thereto.

[0035] In an exemplary embodiment of this disclosure, the first lead portion includes a first segment and a second segment, the first segment being connected to the first electrode portion, the second segment being connected to the end of the first segment away from the first electrode portion, the second segment being connected to the first transistor, and the extension direction of the first segment intersecting the extension direction of the second segment.

[0036] In an exemplary embodiment of this disclosure, the first segment extends along the second direction, and the second segment extends along the first direction; the orthographic projection of the first lead portion on the substrate overlaps with the orthographic projection of the first transistor on the substrate; the first segment is connected to the edge line of the first electrode portion extending along the first direction, but not connected to the corner of the first electrode portion.

[0037] In one exemplary embodiment of this disclosure, a portion of the plurality of first pixel electrodes are first sub-pixel electrodes, and a portion of the plurality of first pixel electrodes are second sub-pixel electrodes. The first sub-pixel electrodes and the second sub-pixel electrodes are located in adjacent pixel columns and adjacent pixel rows, such that the first sub-pixel electrodes and the second sub-pixel electrodes are arranged obliquely opposite each other.

[0038] In an exemplary embodiment of this disclosure, the first electrode portion of the first sub-pixel electrode has a first edge line and a second edge line disposed opposite to each other. The first edge line intersects the first direction, and the second edge line intersects the first direction. The first segment of the first sub-pixel electrode is closer to the first edge line than the second edge line. The angle between the edge line of the second segment of the first sub-pixel electrode away from the first segment and the first edge line is an obtuse angle.

[0039] In one exemplary embodiment of this disclosure, the outer corner where the first segment and the second segment of the first sub-pixel electrode connect is a right angle.

[0040] In an exemplary embodiment of this disclosure, the first electrode portion of the second sub-pixel electrode has a first edge line and a second edge line disposed opposite to each other. The first edge line intersects the first direction, and the second edge line intersects the first direction. The first segment of the second sub-pixel electrode is closer to the second edge line than the first edge line. The angle between the edge line of the second segment of the second sub-pixel electrode away from the first segment and the second edge line is an acute angle. The outer corner portion where the first segment and the second segment of the second sub-pixel electrode connect is provided with a chamfer.

[0041] In one exemplary embodiment of this disclosure, the chamfer includes a chamfer edge line, the angle between the chamfer edge line and the second edge line is an obtuse angle, and the angle between the chamfer edge line and the second edge line away from the first segment is an obtuse angle.

[0042] In one exemplary embodiment of this disclosure, the gate layer is disposed on one side of the substrate, and the driving circuit layer group further includes:

[0043] A gate insulating layer is disposed on the side of the gate layer opposite to the substrate.

[0044] An active layer is disposed on the side of the gate insulating layer away from the substrate. The active layer includes a first conductive connection portion, a channel portion, and a second conductive connection portion connected in sequence. A conductor layer is disposed on the side of the active layer away from the substrate. The conductor layer also includes a source and a drain. The source is connected to the first conductive connection portion. The data line is connected to the source. The drain is connected to the second conductive connection portion. Two pixel columns are disposed between two adjacent data lines.

[0045] A first insulating layer is disposed on the side of the conductor layer opposite to the substrate. A first via is disposed on the first insulating layer. A second via is disposed on the second insulating layer and communicates with the first via. The second electrode is connected to the drain electrode through the second via and the first via.

[0046] According to another aspect of this disclosure, a display device is provided, comprising:

[0047] The array substrate is any one of the array substrates described above; the display device includes alternating rows of red sub-pixels, green sub-pixels and blue sub-pixels, and the orthographic projection of the first auxiliary trace on the substrate is located between the orthographic projections of the red sub-pixels and the green sub-pixels on the substrate.

[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0050] Figure 1 is a schematic diagram of an example embodiment of the array substrate disclosed herein.

[0051] Figure 2 is a schematic diagram of the cross-sectional structure of a portion of the area shown in Figure 1.

[0052] Figure 3 is an equivalent circuit diagram of the array substrate of this disclosure.

[0053] Figure 4 is a partial top view of the gate layer in Figure 2.

[0054] Figure 5 is a schematic diagram of the structure after the active layer is formed based on Figure 4.

[0055] Figure 6 is a schematic diagram of the structure after the conductor layer is formed based on Figure 5.

[0056] Figure 7 is a partial top view of the conductor layer in Figure 6.

[0057] Figure 8 is a schematic diagram of the structure after the first insulating layer and the first via are formed based on Figure 6.

[0058] Figure 9 is a schematic diagram of the structure after forming a conductive auxiliary layer based on Figure 8.

[0059] Figure 10 is a schematic diagram of the structure of the first auxiliary wiring in Figure 9.

[0060] Figure 11 is a schematic diagram of the structure after the second electrode is formed based on Figure 9.

[0061] Figure 12 is a partial top view of the structure of the second electrode in Figure 11.

[0062] Figure 13 is a schematic diagram of the structure after the septum portion is formed based on Figure 11.

[0063] Figure 14 is a schematic diagram showing a poor display of alternating bright and dark areas in the sky blue image.

[0064] Figure 15 is a schematic cross-sectional view of the section cut according to NN in Figure 11.

[0065] Figure 16 is a schematic diagram of another example embodiment of the array substrate disclosed herein.

[0066] Figure 17 is a schematic diagram of an example embodiment of the data lines in the display area of ​​the array substrate of this disclosure.

[0067] Figure 18 is a schematic diagram of another example embodiment of the data lines in the display area of ​​the array substrate of this disclosure.

[0068] Figure 19 is a schematic cross-sectional view of the section cut according to MM in Figure 16.

[0069] Figure 20 is a schematic diagram of another example embodiment after forming a conductive auxiliary layer based on Figure 8.

[0070] Figure 21 is a schematic diagram of the structure after the second electrode is formed based on Figure 20.

[0071] Figure 22 is a schematic diagram of the electric field when an acute angle is formed at the connection between the electrode part and the lead part of the second electrode.

[0072] Figure 23 is a schematic diagram of the effect of the electric field on the liquid crystal in Figure 22.

[0073] Figure 24 is a magnified view of a portion roughly indicated by I in Figure 12.

[0074] Figure 25 is a schematic diagram of the electric field when the connection between the electrode part and the lead part of the second electrode forms an obtuse angle of three connected segments.

[0075] Figure 26 is a schematic diagram of the effect of the electric field on the liquid crystal in Figure 25.

[0076] Figure 27 is a schematic diagram of the electric field when the connection between the electrode part and the lead part of the second electrode forms an obtuse angle.

[0077] Figure 28 is a schematic diagram of the effect of the electric field on the liquid crystal in Figure 27.

[0078] Figure 29 is a simulated diagram of scratches appearing on the display panel.

[0079] Figure 30 is a schematic diagram comparing the voltages of the first pixel electrode and the second pixel electrode.

[0080] Figure 31 is a magnified view of a portion roughly indicated by Q in Figure 12.

[0081] Explanation of reference numerals in the attached drawings: 1. Substrate; 2. Driving circuit layer group; TFTZ, Thin Film Transistor Group; TFT, Thin Film Transistor; T1, First Transistor; T2, Second Transistor; 21, Gate Layer; 211, Gate; 212Z, Gate Line Group; 212, Gate Line; 213, Capacitor Compensation Section; 22, Gate Insulating Layer; 23, Active Layer; 231, First Conductive Connection Section; 232, Channel Section; 233, Second Conductive Connection Section; 24, Conductor Layer; 241, Data Line; 2411, First Part; 2412, Second Part; 242, Source; 243, Drain; 2431, Electrode Block; 2432, Connector Block; 2433, Compensation Block; 244, Signal Line; 25, First Insulating Layer; 25a, Inorganic Layer; 25b, Organic Layer; 251, First Via; 252, Third Via; 253, Fourth Via; 3. First Electrode; 4. Conductive auxiliary layer; 41. First auxiliary trace; 42. Second auxiliary trace; 43. Third auxiliary trace; 431. Virtual extension line; 5. Second insulating layer; 51. Second via; 6. Second electrode; 6a. First pixel electrode; 6aa. First sub-pixel electrode; 6ab. Second sub-pixel electrode; 6a1. First electrode portion; 6a11. First edge line; 6a12. Second edge line; 6a2. First lead portion; 6a21. First segment; 6a22. Second segment; 6a23. Chamfered edge line; 6b. Second pixel electrode; 6ba. Third sub-pixel electrode; 6bb. Fourth sub-pixel electrode; 6b1. Second electrode portion; 6b11. Third edge line; 6b12. Fourth edge line; 6b2. Second lead portion; 6b21. Third segment; 6b22. Fourth segment; 6b23. Fifth segment; 6b24. Straight edge line; 10. Liquid Crystal Display (LCD); AA, Display Area; NAA, Non-Display Area; Fanout; BOD, Bonding Area; IC, Driver Chip; PXQ, Pixel Area; PXH, Pixel Row; PXL, Pixel Column; PX, Pixel; PX1, First Pixel; PX2, Second Pixel; R, First Subpixel; G, Second Subpixel; B, Third Subpixel; PS, Spacer; FPC, Flexible Printed Circuit Board; PCB, Printed Circuit Board; ZX1, First Center Line; ZX2, Second Center Line; X, First Direction; Y, Second Direction; Z1, Third Direction; Z2, Fourth Direction. Detailed Implementation

[0082] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0083] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0084] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0085] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0086] This disclosure provides an array substrate, as shown in Figures 1-30. The array substrate has a display area AA and a non-display area NAA. The array substrate may include a substrate 1, a driving circuit layer group 2, a first electrode 3, a second insulating layer 5, and a second electrode 6. The driving circuit layer group 2 is disposed on one side of the substrate 1. The driving circuit layer group 2 may include a gate layer 21 and a conductor layer 24. The gate layer 21 may include a gate 211 and a gate line 212, and the gate line 212 extends along a first direction X. The conductor layer 24 may include data lines 241 and signal lines 244, and the data lines 241 and signal lines 244 extend along a second direction Y. Two adjacent gate lines 212 form a gate line group 212Z. Multiple data lines 241 and multiple gate line groups 212Z are intersected to define the display area AA as multiple pixel areas PXQ. The second direction Y intersects with the first direction X. The driving circuit layer group 2 may include multiple transistors. Each transistor includes a first transistor T1 and a second transistor T2; a first electrode 3 and a second electrode 6 are disposed on the side of the driving circuit layer group 2 away from the substrate 1; a second insulating layer 5 is disposed between the second electrode 6 and the first electrode 3; two adjacent second electrodes 6 are a first pixel electrode 6a and a second pixel electrode 6b; the first pixel electrode 6a may include a first electrode portion 6a1 and a first lead portion 6a2 connected to each other; the second pixel electrode 6b may include a second electrode portion 6b1 and a second lead portion 6b2 connected to each other; the first lead portion 6a2 is connected to the first transistor T1; the first transistor T1 and the first electrode portion 6a1 are located in the same pixel column PXL; the second lead portion 6b2 is connected to the second transistor T2; the second electrode portion 6b1 and the second transistor T2 are respectively located in adjacent pixel columns PXL; the orthographic projection of the second lead portion 6b2 on the substrate 1 intersects obliquely with the orthographic projection of the signal trace 244 on the substrate 1.

[0087] The array substrate disclosed herein reduces the length of the second lead portion 6b2, thereby minimizing or even eliminating the difference between the length of the second lead portion 6b2 and the length of the first lead. This minimizes or even eliminates the difference between the capacitance formed by the second pixel electrode 6b and the second electrode 6 (common electrode) and the capacitance formed by the first pixel electrode 6a and the second electrode 6 (common electrode), thereby reducing the pixel switching voltage ΔVp of the first pixel electrode 6a. This also reduces the likelihood of flickering issues in high pixel density (Pixels Per Inch, PPI) display panels.

[0088] Referring to FIG1, the array substrate may include a display area AA (Active Area) and a non-display area NAA. Specifically, the non-display area NAA may surround the outer periphery of the display area AA. The array substrate may be rectangular, and the display area AA may be rectangular, such that the non-display area NAA is a rectangular frame.

[0089] Referring to FIG2, the array substrate may include a substrate 1, a driving circuit layer group 2, a first electrode 3, a conductive auxiliary layer 4, a second insulating layer 5, and a second electrode 6. The material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layer material may be any of the aforementioned materials. Of course, the substrate 1 may also be a single layer, and may be any of the aforementioned materials.

[0090] The driving circuit layer group 2 may include multiple transistors arranged in an array. Specifically, referring to Figures 2 and 4, the driving circuit layer group 2 may include a gate layer 21, a gate insulating layer 22, an active layer 23, a conductor layer 24, and a first insulating layer 25. The gate layer 21 is disposed on one side of the substrate 1. The gate layer 21 may include a gate 211, a gate line 212, and a capacitance compensation part 213. The capacitance compensation part 213 is connected to the gate line 212, and the gate line 212 is connected to the gate 211. Alternatively, a portion of the gate line 212 may be reused as the gate 211. The gate line 212 may extend along a first direction X. The gate layer 21 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate layer 21 may be a single-layer film or a multilayer film.

[0091] A gate insulating layer 22 is disposed on the side of the gate layer 21 facing away from the substrate 1. The gate insulating layer 22 may include silicon compounds, metal oxides, or the like. For example, the gate insulating layer 22 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These can be used individually or in combination. The gate insulating layer 22 may be a single-layer film or a multilayer film, wherein the multilayer film is formed as a stacked structure of different materials. The gate insulating layer 22 may be disposed only on the side of the gate layer 21 facing away from the substrate 1; of course, the gate insulating layer 22 may also be disposed over the entire surface of the substrate 1.

[0092] Referring to Figures 2 and 5, the active layer 23 is disposed on the side of the gate insulating layer 22 facing away from the substrate 1. The active layer 23 may include polycrystalline silicon. However, this disclosure is not limited thereto, and the active layer 23 may include monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor, etc. The active layer 23 may include a first conductive connection portion 231, a channel portion 232, and a second conductive connection portion 233 connected in sequence. For example, the first conductive connection portion 231 and the second conductive connection portion 233 are connected to opposite ends of the channel portion 232.

[0093] Referring to Figures 2, 6, and 7, the conductor layer 24 is disposed on the side of the active layer 23 facing away from the substrate 1. The conductor layer 24 may include at least one metal selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The conductor layer 24 may be a single-layer film or a multilayer film. For example, the conductor layer 24 may be formed as a stacked structure having Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu. The conductor layer 24 may include a data line 241, a source 242, and a drain 243. The source 242 may be part of the data line 241, or the source 242 may be connected to the data line 241. The source electrode 242 is connected to the first conductive connection portion 231, and the drain electrode 243 is connected to the second conductive connection portion 233. The data line 241 extends along the second direction Y. The orthographic projection of the drain electrode 243 on the substrate 1 overlaps with the orthographic projection of the capacitor compensation portion 213 on the substrate 1. A capacitor can be formed through the drain electrode 243 and the capacitor compensation portion 213 to compensate for the storage capacitor and avoid capacitance inconsistency caused by process fluctuations.

[0094] Referring to Figures 2 and 8, a first insulating layer 25 is provided on the side of the conductor layer 24 facing away from the substrate 1. The first insulating layer 25 may include an inorganic layer 25a. The material of the inorganic layer 25a may be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0095] The first insulating layer 25 may also include an organic layer 25b, which may be made of organic materials, such as polyimide (PI), polycarbonate, polyacrylate, polyetherimide, etc. Of course, the first insulating layer 25 may consist only of the organic layer 25b, or it may include two inorganic layers.

[0096] The channel 232, gate 211, source 242 and drain 243 constitute a thin-film transistor (TFT), that is, the transistor is a thin-film transistor (TFT).

[0097] It should be noted that the thin-film transistor TFT described in this specification is a top-gate type thin-film transistor TFT. In other exemplary embodiments of this disclosure, the thin-film transistor TFT can also be a bottom-gate type or a dual-gate type (two gates 211), and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistor TFTs with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source 242" and the "drain 243" are sometimes interchanged. Therefore, in this specification, the "source 242" and the "drain 243" can be interchanged.

[0098] Furthermore, the transistor described in this specification is a thin-film transistor (TFT). The following description uses a thin-film transistor (TFT) as an example of a transistor. In other exemplary embodiments of this disclosure, the transistor may also be other conventional transistors.

[0099] A first electrode 3 is disposed on the side of the driving circuit layer group 2 facing away from the substrate 1. Specifically, the first electrode 3 is disposed on the side of the first insulating layer 25 facing away from the substrate 1. The material of the first electrode 3 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first electrode 3 may be a common electrode.

[0100] Referring to Figures 2, 9, and 10, a conductive auxiliary layer 4 is provided on the side of the first electrode 3 facing away from the substrate 1. The conductive auxiliary layer 4 can be made of metal. The conductive auxiliary layer 4 may include a first auxiliary trace 41 and a second auxiliary trace 42.

[0101] A second insulating layer 5 is provided on the side of the conductive auxiliary layer 4 facing away from the substrate 1. The material of the second insulating layer 5 can be an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0102] Referring to Figures 2, 11, and 12, a second electrode 6 is disposed on the side of the second insulating layer 5 facing away from the substrate 1. The material of the second electrode 6 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. A first via 251 is disposed on the first insulating layer 25, and a second via 51 communicating with the first via 251 is disposed on the second insulating layer 5. The second electrode 6 may be a pixel electrode. The second electrode 6 can be connected to the drain 243 through the second via 51 on the second insulating layer 5 and the first via 251 on the first insulating layer 25. A display driving signal can be input to the second electrode 6 through the drain 243.

[0103] Of course, in some other exemplary embodiments of this disclosure, the second electrode 6 may be disposed on the side of the first insulating layer 25 away from the substrate 1. The second electrode 6 may be connected to the drain 243 through the first via 251 on the first insulating layer 25, and a display driving signal may be input to the second electrode 6 through the drain 243. A second insulating layer 5 is disposed on the side of the second electrode 6 away from the substrate 1, a first electrode 3 is disposed on the side of the second insulating layer 5 away from the substrate 1, and a conductive auxiliary layer 4 is disposed on the side of the first electrode 3 away from the substrate 1; alternatively, the conductive auxiliary layer 4 may be disposed on the side of the first electrode 3 close to the substrate 1.

[0104] Referring to Figure 3, the array substrate may include multiple pixels PX arranged in an array. Each pixel PX may include three sub-pixels of different colors: a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. Specifically, each pixel PX may include the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B arranged sequentially along a first direction X. More specifically, the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are arranged periodically along the first direction X to form a pixel row PXH. In other words, multiple pixels PX are arranged along the first direction X to form a pixel row PXH, or, within each pixel row PXH, the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are arranged periodically along the first direction X. Multiple sub-pixels PX are arranged sequentially along a second direction Y to form a pixel column PXL. For example, multiple first sub-pixels R, multiple second sub-pixels G, and multiple third sub-pixels B are arranged sequentially along the second direction Y to form a pixel column PXL.

[0105] The first sub-pixel R can be defined by the first pixel electrode, the second sub-pixel G can be defined by the second pixel electrode, and the third sub-pixel B can be defined by the third pixel electrode.

[0106] Referring to Figures 3 and 11, multiple gate lines 212 are used to transmit scan signals. The scanning direction of the gate lines 212 is from the nth row pixel PX to the (n+1)th row pixel PX, where n is an integer greater than or equal to 1. The gate lines 212 can extend along a first direction X, and multiple gate lines 212 can be arranged along a second direction Y to transmit scan signals to different sub-pixels. Two adjacent gate lines 212 form a gate line group 212Z.

[0107] Data lines 241 can extend along the second direction Y, and multiple data lines 241 can be arranged along the first direction X. Multiple data lines 241 intersect with multiple gate line groups 212Z to define the display area AA as multiple pixel regions PXQ. Every two sub-pixels PX are confined within one pixel region PXQ, meaning every two second electrodes 6 are located within the same pixel region PXQ. This results in two columns of sub-pixels PX of different colors being provided between every two adjacent data lines 241, i.e., two columns of pixels PXL being provided between every two adjacent data lines 241. Two gate lines 212 are provided between two adjacent rows of pixels PXH.

[0108] Two sub-pixels PX located within the same pixel region PXQ are connected to the same data line 241 and driven through the same data line 241. Two sub-pixels PX located within the same pixel region PXQ are connected to different gate lines 212 and driven through two different gate lines 212. The two gate lines 212 connected to the same pixel region PXQ are parallel to each other and located on opposite sides of the pixel region PXQ. This structure is a dual-gate structure. Using a dual-gate liquid crystal display panel increases the number of gate lines 212 on the array substrate, thereby reducing the number of data lines 241, and thus reducing the number of source driver ICs, thereby lowering costs.

[0109] The resolution of the array substrate using a dual-gate structure can be improved from FHD (1920×1080) to QD (3840x2160), and the pixel density can be increased from 150 to about 200. The pixel period is reduced. In order to ensure that the aperture ratio (transmittance) does not decrease, the connection space between the second electrode 6 and the drain of the transistor is reduced. The disordered electric field in the black matrix BM region affects the degree of orderly arrangement of liquid crystal in the effective area of ​​the pixel, which increases. As shown in Figure 29, the Trace Mura problem is prone to occur, that is, when fingers or other objects draw lines on a high-brightness screen, the liquid crystal recovers its orderly arrangement more slowly, resulting in dark lines (scratches). The refresh rate can be increased from 60Hz to 120Hz and above, significantly reducing the pixel PX charging time. The pixel PX charging time can be reduced from 7.7μs (Dual Gate FHD 60Hz) to 2.6μs~1.8μs (Dual Gate QD 120Hz~165Hz). The significant reduction in pixel PX charging time makes pixel PX charging very challenging. The common electrode (first electrode 3) is pulled by the coupling of the gate line 212 and the data line 241 signal line. If the voltage of the common electrode has not recovered to the set value at the end of charging, the pixel PX voltage will change, and the grayscale display will be abnormal. Therefore, improving the recovery capability and uniformity of the common electrode is the key to ensuring the quality of dual gate structure products.

[0110] The first auxiliary trace 41 is directly connected to the first electrode 3 (common electrode). The resistance of the first electrode 3 can be reduced through the first auxiliary trace 41, thereby improving the recovery capability and uniformity of the first electrode 3, and improving high-frequency Excel Crosstalk and low-frequency Flicker.

[0111] Referring to Figures 11 and 12, two adjacent second electrodes 6 are first pixel electrodes 6a and second pixel electrodes 6b. Specifically, two second electrodes 6 located within the same pixel region PXQ are first pixel electrodes 6a and second pixel electrodes 6b. The first pixel electrode 6a may include a first electrode portion 6a1 and a first lead portion 6a2 connected to each other. The second pixel electrode 6b may include a second electrode portion 6b1 and a second lead portion 6b2 connected to each other. The first lead portion 6a2 is connected to a first transistor T1. The first transistor T1 and the first electrode portion 6a1 are located in the same pixel column PXL. The second lead portion 6b2 is connected to a second transistor T2. The second electrode portion 6b1 and the second transistor T2 are located in adjacent pixel columns PXL, respectively.

[0112] The second insulating layer 5 is an inorganic material, and its planarization effect is weak, as is its buffering effect on the ramping of the second electrode 6. The widths of the first lead portion 6a2 and the second lead portion 6b2 are small, making them prone to breakage during ramping. This would prevent the first pixel electrode 6a and the second pixel electrode 6b from conducting and thus prevent display driving. The orthographic projection of the first auxiliary trace 41 on the substrate 1 does not overlap with the orthographic projections of the first lead portion 6a2 and the second lead portion 6b2 on the substrate 1, thus avoiding the defect of the sub-pixel PX not being displayed due to the first lead portion 6a2 and the second lead portion 6b2 breaking because they cross the protrusion formed by the first auxiliary trace 41.

[0113] In some exemplary embodiments of this disclosure, the first pixel electrode 6a and the second pixel electrode 6b are connected to the same data line 241, such that the length of the second lead portion 6b2 of the second pixel electrode 6b, which is away from the data line 241, is greater than the length of the first lead portion 6a2, so that the first lead portion 6a2 and the second lead portion 6b2 can be connected to the same data line 241.

[0114] Alternatively, the orthographic projection of the second electrode 6 on the substrate 1 may overlap with the orthographic projection of the first auxiliary trace 41 near the corner of the first auxiliary trace 41 on the substrate 1, while the other parts of the orthographic projection of the second electrode 6 on the substrate 1 may not overlap with the orthographic projection of the first auxiliary trace 41 on the substrate 1. This can mitigate or even avoid the defect of the sub-pixel PX being unable to be displayed due to the second electrode 6 breaking due to the second electrode 6 crossing the first auxiliary trace 41 and forming a ramp.

[0115] Referring to Figures 9-11, the first auxiliary trace 41 extends along the second direction Y, which can avoid the first auxiliary trace 41 from overlapping with the second electrode 6, thereby avoiding the second electrode 6 from breaking due to the second electrode 6 crossing the first auxiliary trace 41 and causing the sub-pixel PX to be unable to be displayed.

[0116] The orthographic projection of the first auxiliary trace 41 on the substrate 1 at least partially overlaps with the orthographic projection of the data line 241 on the substrate 1. For example, the edge of the orthographic projection of the first auxiliary trace 41 on the substrate 1 may coincide with the edge of the orthographic projection of the data line 241 on the substrate 1. Alternatively, the orthographic projection of the first auxiliary trace 41 on the substrate 1 may cover and be larger than the orthographic projection of the data line 241 on the substrate 1. Or, the orthographic projection of the data line 241 on the substrate 1 may cover and be larger than the orthographic projection of the first auxiliary trace 41 on the substrate 1.

[0117] Of course, in some other example embodiments of this disclosure, a portion of the orthographic projection of the first auxiliary trace 41 on the substrate 1 may at least partially overlap with a portion of the orthographic projection of the data line 241 on the substrate 1, that is, the first auxiliary trace 41 may be slightly offset to both sides relative to the data line 241 in the first direction X.

[0118] Specifically, the shape of the first auxiliary trace 41 can be basically the same as the shape of the data line 241. The line width of the first auxiliary trace 41 can be slightly wider than the line width of the data line 241, or the line width of the data line 241 can be slightly wider than the line width of the first auxiliary trace 41. Specifically, the ratio of the line width of the first auxiliary trace 41 to the line width of the data line 241 can be greater than or equal to 0.9 and less than or equal to 3. For example, the ratio of the line width of the first auxiliary trace 41 to the line width of the data line 241 can be 0.92, 0.95, 0.97, 1, 1.03, 1.05, 1.08, 1.3, 1.5, 1.8, 2, 2.2, 2.5, 2.7, etc.

[0119] This configuration ensures that the second electrode 6 (pixel PX electrode) formed subsequently does not need to cross the first auxiliary trace 41 when connected to the corresponding data line 241.

[0120] Alternatively, referring to Figures 2 and 13, the array substrate may further include a spacer portion PS. The spacer portion PS is disposed on the side of the second insulating layer 5 away from the substrate 1. The orthographic projection of the spacer portion PS on the substrate 1 does not overlap with the orthographic projection of the first auxiliary trace 41 on the substrate 1. Since the first auxiliary trace 41 causes unevenness on the side of the second insulating layer 5 away from the substrate 1, the height of the second insulating layer 5 will be higher at the location where the first auxiliary trace 41 is set. The spacer portion PS is not disposed directly above the first auxiliary trace 41, so as to avoid the abnormal shape and inconsistent height of the spacer portion PS caused by the spacer portion PS being formed on the uneven substrate layer, thereby avoiding uneven display caused by uneven gap between the array substrate and the color filter substrate.

[0121] In this example embodiment, three pixel regions PXQ arranged along the first direction X are grouped together, and a first auxiliary trace 41 is provided between two adjacent groups of pixel regions PXQ.

[0122] Of course, in some other example embodiments of this disclosure, a first auxiliary trace 41 may be provided in a set of pixel regions PXQ.

[0123] For example, as shown in FIG3, six second electrodes 6 are provided in the three pixel regions PXQ. The six second electrodes 6 form two pixels PX. Therefore, the two pixels PX are a pixel group, and the two pixels PX are the first pixel PX1 and the second pixel PX2. That is, a pixel group includes a first sub-pixel R, a second sub-pixel G, a third sub-pixel B, and a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B arranged sequentially along the first direction X.

[0124] A data line 241 can be provided on the side of the first pixel PX1 away from the second pixel PX2, a data line 241 can be provided between the second sub-pixel G and the third sub-pixel B of the first pixel PX1, and a data line 241 can be provided between the first sub-pixel R and the second sub-pixel G of the second pixel PX2.

[0125] The first auxiliary trace 41 can be located between the adjacent second sub-pixel G and the third sub-pixel B in the first pixel PX1, or between the adjacent first sub-pixel R and the second sub-pixel G in the second pixel PX2, or between two adjacent pixel groups.

[0126] Since it is necessary to ensure the setting density of the spacer PS to ensure the support effect of the spacer PS, one of the above three positions can generally be selected; of course, any two of the above three positions can also be selected. In addition, in general, multiple first auxiliary lines 41 can be evenly arranged. Of course, in some other example embodiments of this disclosure, multiple first auxiliary lines 41 can be unevenly arranged. For example, the positions of the first auxiliary lines 41 can be different in different pixel groups.

[0127] The first auxiliary trace 41 can essentially run through the entire array substrate. The first auxiliary trace 41 can be directly connected to the common signal line, transmitting the common signal to the first electrode 3, thus allowing the first electrode 3 and the first auxiliary trace 41 to jointly transmit the common signal. Alternatively, the first electrode 3 can be directly connected to the common signal line, transmitting the common signal to the first auxiliary trace 41, similarly allowing the first electrode 3 and the first auxiliary trace 41 to jointly transmit the common signal. The number of first auxiliary traces 41 is limited.

[0128] Referring to Figures 20 and 21, the virtual extension line 431 in Figure 21 is represented by a bold black dashed line. The conductive auxiliary layer 4 may also include a third auxiliary trace 43. The orthographic projection of the third auxiliary trace 43 on the substrate 1 is located between the orthographic projections of two adjacent second electrodes 6 on the substrate 1. The third auxiliary trace 43 is disconnected, and the virtual extension line 431 of the third auxiliary trace 43 intersects with the second lead portion 6b2. Specifically, the orthographic projection of each segment of the third auxiliary trace 43 on the substrate 1 is located between the orthographic projections of two adjacent second electrode portions 6b1 on the substrate 1. In the second direction Y, each segment of the third auxiliary trace 43 does not protrude from the second electrode portion 6b1. This arrangement increases the number of auxiliary traces, further reducing the resistance of the first electrode 3 and reducing power consumption.

[0129] Furthermore, if the array substrate using a dual-gate structure is not charged sufficiently, it is prone to defects such as mixed colors and vertical stripes. Referring to the sky blue image shown in Figure 14, the dashed circle represents sufficient pre-charge and the pixel PX is brighter; the solid circle represents insufficient pre-charge and the pixel PX is darker. This alternation of bright and dark displays macroscopically manifests as vertical stripes.

[0130] In some exemplary embodiments of this disclosure, referring to Figures 3 and 11, in the second direction Y, the first transistor T1 and the second transistor T2 are each located on opposite sides of the pixel region PXQ, that is, the first transistor T1 is located on one side of the pixel region PXQ in the second direction Y, and the second transistor T2 is located on the opposite side of the pixel region PXQ in the second direction Y; the first transistor T1 and the second transistor T2 are not located within the pixel region PXQ.

[0131] Referring to Figures 3 and 6, the orthographic projection of the thin-film transistor (TFT) on the substrate 1 is located between the orthographic projections of each pair of adjacent gate lines 212 on the substrate 1. In other words, the orthographic projection of the TFT on the substrate 1 is located inside the orthographic projection of each pair of adjacent gate lines 212 on the substrate 1. This eliminates the need for a winding structure for the gate lines 212, allowing them to be set as straight lines extending along the first direction X. As a result, the impedance of the straight gate lines 212 can be reduced by 10% to 20% compared to the winding structure gate lines 212. This reduces the gate delay synchronically, effectively increasing the current of the thin-film transistor TFT and improving the charging rate, thereby avoiding vertical stripe problems caused by charging differences in special images such as color mixing.

[0132] Specifically, the orthographic projection of the active layer 23 on the substrate 1 lies between the orthographic projections of two adjacent gate lines 212 on the substrate 1, meaning the orthographic projection of the active layer 23 on the substrate 1 lies inside the orthographic projections of the two adjacent gate lines 212 on the substrate 1; the orthographic projection of the drain 243 on the substrate 1 lies between the orthographic projections of two adjacent gate lines 212 on the substrate 1, meaning the orthographic projection of the drain 243 on the substrate 1 lies inside the orthographic projections of the two adjacent gate lines 212 on the substrate 1; the orthographic projection of the source 242 on the substrate 1 also lies between the orthographic projections of two adjacent gate lines 212 on the substrate 1, meaning the orthographic projection of the source 242 on the substrate 1 lies inside the orthographic projections of the two adjacent gate lines 212 on the substrate 1. Multiple gates 211 are connected to one gate line 212, and the multiple gates 211 are located between two adjacent gate lines 212, meaning the gates 211 are located inside the two adjacent gate lines 212.

[0133] With this configuration, as shown in Figures 11 and 12, the second electrode 6 (pixel PX electrode) of each sub-pixel PX does not need to be designed to avoid the thin-film transistor TFT, making the edges of the second electrode 6 of each sub-pixel PX relatively flat, avoiding electric field disturbance at the junction, and thus avoiding trace mura defects; moreover, the aperture ratio is larger, for example, the aperture ratio can be improved by 2% to 5% compared with the prior art.

[0134] Alternatively, as shown in FIG6, the multiple thin-film transistors (TFTs) may include multiple groups of thin-film transistor groups (TFTZ). Each group of thin-film transistors (TFTZ) may include two thin-film transistors (TFTs). The two thin-film transistors (TFTs) in the same group are located between two adjacent gate lines 212 in the same group. For example, the two thin-film transistors (TFTs) in the same group may be a first thin-film transistor (TFT1) and a second thin-film transistor (TFT2). The two adjacent gate lines 212 in the same group may be a first gate line 212a and a second gate line 212b. The first thin-film transistor (TFT1) is located between the first gate line 212a and the second gate line 212b, and the second thin-film transistor (TFT2) is also located between the first gate line 212a and the second gate line 212b. Two thin-film transistors (TFTs) of the same group are connected to opposite sides of the same data line 241 in the first direction X, that is, two thin-film transistors (TFTs) of the same group are connected to the same data line 241 but are not located on the same side of the data line 241; two thin-film transistors (TFTs) of the same group are staggered in the second direction Y. For example, the first thin-film transistor TFT1 can be set closer to the first gate line 212a, and the second thin-film transistor TFT2 can be set closer to the second gate line 212b; of course, it is also possible that the first thin-film transistor TFT1 is set closer to the second gate line 212b, and the second thin-film transistor TFT2 is set closer to the first gate line 212a.

[0135] Specifically, the two gates 211 of the two thin-film transistors (TFTs) in the same group are connected one-to-one to two adjacent gate lines 212 in the same group. For example, the gate 211 of the first thin-film transistor TFT1 can be connected to the first gate line 212a; the gate 211 of the second thin-film transistor TFT2 can be connected to the second gate line 212b.

[0136] In addition, the two sources 242 of the two thin-film transistor TFTs in the same group are connected to opposite sides of the same data line 241 in the first direction X, and are staggered in the second direction Y. For example, the source 242 of the first thin-film transistor TFT1 can be set closer to the first gate line 212a, and the source 242 of the second thin-film transistor TFT2 can be set closer to the second gate line 212b; of course, it is also possible that the source 242 of the first thin-film transistor TFT1 is set closer to the second gate line 212b, and the source 242 of the second thin-film transistor TFT is set closer to the first gate line 212a.

[0137] In some exemplary embodiments of this disclosure, referring to Figures 6-8, the drain 243 may include an electrode block 2431, a connecting block 2432, and a compensation block 2433 connected sequentially in the first direction X. The electrode block 2431, connecting block 2432, and compensation block 2433 are all solid structures without any intermediate hollow structures. The electrode block 2431 is connected to the second conductive connection portion 233. The second electrode 6 is connected to the connecting block 2432 through the second via 51 and the first via 251. The electrode block 2431 and the compensation block 2433 are offset in the second direction Y, meaning they are not on the same straight line in the second direction Y. Specifically, in the second direction Y, the distance between the electrode block 2431 and the gate line 212 is less than the distance between the compensation block 2433 and the gate line 212, i.e., the distance between the compensation block 2433 and the gate line 212 is less than the distance between the compensation block 2433 and the gate line 212. The larger distance between 212 is to meet the requirements of process margin (i.e., the range of process parameter fluctuations); the smaller distance between electrode block 2431 and gate line 212 is to ensure the connection between electrode block 2431 and second conductive connection part 233. In addition, electrode block 2431 needs to be positioned opposite to source 242, so that the center line of electrode block 2431 extending along the first direction X coincides with the center line of source 242 extending along the first direction X, so as to ensure the functional effect of thin film transistor.

[0138] To ensure that the source 242 and the electrode block 2431 are positioned opposite each other, the size of the source 242 in the second direction Y can be set to be larger than the size of the electrode block 2431 in the second direction Y, resulting in a larger size of the source 242 in the second direction Y. In the second direction Y, the orthographic projection of the portion of the source 242 extending beyond the active layer 23 on the substrate 1 overlaps with the orthographic projection of the gate line 212 on the substrate 1, which can reduce the occupied area of ​​the source 242, thereby compressing the occupied area of ​​the thin film transistor and improving the aperture ratio.

[0139] The width of the connecting block 2432 is greater than the width of the electrode block 2431 and the compensation block 2433, that is, the width of the connecting block 2432 is greater than the width of the electrode block 2431 and also greater than the width of the compensation block 2433, so as to ensure the area of ​​the second via 51 and the first via 251, thereby ensuring the connection strength and connection area between the second electrode 6 and the connecting block 2432.

[0140] The orthographic projection of the compensation block 2433 on the substrate 1 overlaps with the orthographic projection of the capacitor compensation part 213 on the substrate 1, forming a capacitor and performing capacitor compensation.

[0141] In some exemplary embodiments of this disclosure, referring to Figures 6 and 7, the data line 241 is configured as a strip extending along the second direction Y. Specifically, the data line 241 is configured as a zigzag line extending along the second direction Y, with the bend position designed to match the structure of the second electrode 6. This means that the data line 241 is generally configured as a straight line extending along the second direction Y, rather than the "bow"-shaped structure in the related art, thereby reducing the length of the data line 241 and significantly reducing its impedance. For example, the impedance of the data line 241 can be reduced by 50%, thereby effectively improving the charging rate and avoiding vertical stripe problems caused by charging differences in special images such as color mixing.

[0142] Referring to Figures 3, 6, and 7, the conductor layer 24 may further include a signal trace 244, which can be used as a touch trace. The signal trace 244 is configured as a strip extending along the second direction Y. Specifically, the signal trace 244 is configured as a zigzag line extending along the second direction Y, with the bend position to match the structure of the second electrode 6. This means that the signal trace 244 is generally configured as a straight line extending along the second direction Y, rather than the "bow"-shaped structure in related technologies, thereby reducing the length of the signal trace 244 and significantly reducing its impedance. For example, the impedance of the signal trace 244 can be reduced by 50%, thereby effectively improving touch performance.

[0143] A portion of the signal trace 244 is located within the pixel region PXQ. For example, the signal trace 244 and the data line 241 can be arranged in a basically parallel manner. The signal trace 244 and the data line 241 are arranged alternately, that is, there is a signal trace 244 between two adjacent data lines 241 and a data line 241 between two adjacent signal traces 244, so that there are also two pixel columns PXL between two adjacent signal traces 244.

[0144] Specifically, as shown in FIG3, a signal trace 244 is provided between the first sub-pixel R and the second sub-pixel G of the first pixel PX1, a signal trace 244 is provided between the third sub-pixel B of the first pixel PX1 and the first sub-pixel R of the second pixel PX2, and a signal trace 244 is provided between the second sub-pixel G and the third sub-pixel B of the second pixel PX2.

[0145] In this case, the first electrode 3 can be reused as a touch electrode; that is, when implementing the display function, the first electrode 3 is used as a common electrode; when implementing the touch function, the first electrode 3 is used as a touch electrode. Of course, the signal trace 244 can also be used as a common electrode line.

[0146] Referring to Figures 11 and 15, the first electrode 3 can be connected to the signal trace 244 through the third via 252 on the first insulating layer 25, so that when the first electrode 3 is used as a touch electrode, touch signals can be transmitted through the signal trace 244. The orthogonal projection of the third via 252 on the substrate 1 is located between the orthogonal projections of two adjacent transistors on the substrate 1. Specifically, the orthogonal projection of the third via 252 on the substrate 1 is located between two adjacent data lines 241, and between the orthogonal projections of two adjacent transistors connected to different data lines 241 on the substrate 1. That is, the arrangement of the gate line 212 and the thin-film transistor TFT can accommodate the third via 252 connecting the signal trace 244 to the first electrode 3, so that the data line 241 and the signal trace 244 do not need to be bent into an "arch" shape, thereby reducing the impedance of the signal trace 244 by 50%, which can effectively improve the touch performance, and the impedance of the data line 241 can be reduced by 50%, which can effectively improve the charging rate.

[0147] Of course, in some other exemplary embodiments of this disclosure, the signal trace 244 may also be a dummy trace. A dummy trace may not be powered. The dummy trace is only set up to ensure the consistency of the process. In this case, the signal trace 244 does not need to be connected to the first electrode 3.

[0148] Referring to Figure 30, L1 is the gate voltage curve, L2 is the positive frame pixel voltage curve of the first pixel electrode 6a, L3 is the negative frame pixel voltage curve of the first pixel electrode 6a, L4 is the positive frame pixel voltage curve of the second pixel electrode 6b, and L5 is the negative frame pixel voltage curve of the second pixel electrode 6b. Since the second lead portion 6b2 is used to connect the second electrode portion 6b1 and the second transistor T2 located in adjacent pixel columns PXL, the length of the second lead portion 6b2 needs to be set to be relatively long. On the other hand, the first lead portion 6a2 is used to connect the first transistor T1 and the first electrode portion 6a1 located in the same pixel column PXL, so the length of the first lead portion 6a2 can be set to be relatively short. This results in the capacitance formed by the second pixel electrode 6b and the second electrode 6 (common electrode, intermediate Vcom) being greater than the capacitance formed by the first pixel electrode 6a and the second electrode 6 (common electrode, intermediate Vcom). Consequently, the pixel transition voltage ΔVp1 of the first pixel electrode 6a is too large, while the pixel transition voltage ΔVp1 of the second pixel electrode 6b is too small. The difference between the two is ΔV, which can easily lead to screen flickering. Screen flickering is more likely to occur in display panels with high pixel density (Pixels Per Inch, PPI).

[0149] Referring to Figures 11 and 12, the orthographic projection of the second lead portion 6b2 on the substrate 1 overlaps with the orthographic projection of the signal trace 244 on the substrate 1, meaning the second lead portion 6b2 needs to cross the signal trace 244; alternatively, the orthographic projection of the second lead portion 6b2 on the substrate 1 and the orthographic projection of the signal trace 244 on the substrate 1 are arranged obliquely. The orthographic projection of the first lead portion 6a2 on the substrate 1 does not overlap with the orthographic projection of the signal trace 244 on the substrate 1, meaning the first lead portion 6a2 does not need to cross the signal trace 244.

[0150] Specifically, the second lead portion 6b2 may include a third segment 6b21 and a fourth segment 6b22. The third segment 6b21 is connected to the second electrode portion 6b1, and the fourth segment 6b22 is connected to the end of the third segment 6b21 facing away from the second electrode portion 6b1. The fourth segment 6b22 is connected to the second transistor T2, that is, the second electrode portion 6b1, the third segment 6b21, the fourth segment 6b22, and the second transistor T2 are connected sequentially. The fourth segment 6b22 extends along the first direction X, so that the fourth segment 6b22 is arranged parallel to the gate line 212, which is beneficial to improving the aperture ratio. The third segment 6b21 extends along the third direction Z1, which intersects the first direction X and the second direction Y. That is, the extension direction of the third segment 6b21 intersects both the first direction X and the second direction Y. The orthographic projection of the third segment 6b21 on the substrate 1 is obliquely intersected with the orthographic projection of the signal trace 244 on the substrate 1. This obliquely intersects the orthographic projection of the second lead portion 6b2 on the substrate 1 with the orthographic projection of the signal trace 244 on the substrate 1, thereby reducing the length of the second lead portion 6b2. This minimizes or even eliminates the difference between the length of the second lead portion 6b2 and the length of the first lead, thereby minimizing or even eliminating the difference between the capacitance formed by the second pixel electrode 6b and the second electrode 6 (common electrode) and the capacitance formed by the first pixel electrode 6a and the second electrode 6 (common electrode). This further reduces the pixel switching voltage ΔVp of the first pixel electrode 6a. For display panels with high pixel density (Pixels Per Inch, PPI), flickering is also prone to occur.

[0151] It should be noted that the term "oblique intersection setting" refers to a setting that does not have a perpendicular intersection setting.

[0152] In some exemplary embodiments of this disclosure, the included angle J1 between the third segment 6b21 and the fourth segment 6b22 is greater than or equal to 135° and less than 180°, that is, the included angle between the third direction Z1 and the first direction X is greater than or equal to 135° and less than 180°; for example, the included angle between the third segment 6b21 and the fourth segment 6b22 can be 140°, 145°, 150°, 155°, 160°, 165°, 170°, 175°, etc.

[0153] Alternatively, the included angle J1 between the third segment 6b21 and the fourth segment 6b22 is greater than or equal to 155° and less than 165°. For example, the included angle J1 between the third segment 6b21 and the fourth segment 6b22 can be 157°, 159°, 162°, 164°, etc.

[0154] The larger the angle J1 between the third segment 6b21 and the fourth segment 6b22, the closer the second lead portion 6b2 is to a straight line, and the smaller the space occupied by the second lead portion 6b2 in the second direction Y, which is beneficial to improving the opening ratio.

[0155] If the angle J1 between the third segment 6b21 and the fourth segment 6b22 is too large, the second lead portion 6b2 will be unable to cross the gate line 212, resulting in an excessively large overlap area with the gate line 212. If the angle J1 between the third segment 6b21 and the fourth segment 6b22 is too small, the second lead portion 6b2 will occupy too much space in the second direction Y, which is not conducive to improving the aperture ratio. The above-mentioned numerical range not only allows the second lead portion 6b2 to cross the gate line 212, thereby reducing the overlap area between the second lead portion 6b2 and the gate line 212, but also makes the space occupied by the second lead portion 6b2 in the second direction Y smaller, which is beneficial to improving the aperture ratio.

[0156] A portion of the multiple second pixel electrodes 6b is a third sub-pixel electrode 6ba, meaning the third sub-pixel electrode 6ba is the same as the second pixel electrode 6b. Therefore, the third sub-pixel electrode 6ba also includes a second electrode portion 6b1 and a second lead portion 6b2. Similarly, a portion of the multiple second pixel electrodes 6b is a fourth sub-pixel electrode 6bb, meaning the fourth sub-pixel electrode 6bb is the same as the second pixel electrode 6b. Therefore, the fourth sub-pixel electrode 6bb also includes a second electrode portion 6b1 and a second lead portion 6b2.

[0157] The third sub-pixel electrode 6ba and the fourth sub-pixel electrode 6bb are located in adjacent pixel column PXL and adjacent pixel row PXH, so that the third sub-pixel electrode 6ba and the fourth sub-pixel electrode 6bb are obliquely opposite each other; that is, the adjacent third sub-pixel electrode 6ba and the fourth sub-pixel electrode 6bb are not adjacent in the first direction X, nor are they adjacent in the second direction Y, but are obliquely adjacent.

[0158] Alternatively, referring to Figures 11 and 12, the orthographic projections of the second lead portion 6b2 of the third sub-pixel electrode 6ba and the second lead portion 6b2 of the fourth sub-pixel electrode 6bb on the substrate 1 are obliquely intersecting with the orthographic projection of the same signal trace 244 on the substrate 1. The fourth segment 6b22 of the third sub-pixel electrode 6ba and the fourth segment 6b22 of the fourth sub-pixel electrode 6bb are located between two gate lines 212 in the same group. The third segment 6b21 of the second lead portion 6b2 of the third sub-pixel electrode 6ba and the third segment 6b21 of the second lead portion 6b2 of the fourth sub-pixel electrode 6bb are opposite to and parallel to each other in the fourth direction Z2, which is perpendicular to the third direction Z1. The fourth segment 6b22 of the third sub-pixel electrode 6ba and the fourth segment 6b22 of the fourth sub-pixel electrode 6bb extend to opposite sides in the first direction X.

[0159] The distance between two gate lines 212 in the same group along the second direction Y is S, and the distance between the edges of the third segment 6b21 of the third sub-pixel electrode 6ba and the third segment 6b21 of the fourth sub-pixel electrode 6bb along the fourth direction Z2 is A. We can obtain the formula: S=A / cos(180°-J1). Therefore, the larger J1 is, the smaller S is, that is, the smaller the distance S between two gate lines 212 in the same group along the second direction Y is, which can improve the aperture ratio.

[0160] In some exemplary embodiments of this disclosure, referring to Figures 12 and 24, the second electrode portion 6b1 of the third sub-pixel electrode 6ba has a third edge line 6b11 and a fourth edge line 6b12 disposed opposite to each other. The third edge line 6b11 intersects the first direction X, and the fourth edge line 6b12 intersects the first direction X. The second electrode portion 6b1 is configured as a structure that is approximately “<”, with the third edge line 6b11 located on the outer side and the fourth edge line 6b12 located on the inner side. The third segment 6b21 of the third sub-pixel electrode 6ba is closer to the third edge line 6b11 than the fourth edge line 6b12. The angle between the edge line of the third segment 6b21 of the third sub-pixel electrode 6ba near the second electrode portion 6b1 and the third edge line 6b11 is an acute angle. That is, the angle between the outer contour of the third sub-pixel electrode 6ba formed at the connection between the third segment 6b21 and the third edge line 6b11 is an acute angle (as shown by the angle between the two dashed lines in Figure 24). Referring to Figures 22 and 23, when the angle between the edge line of the third segment 6b21 and the third edge line 6b11 is an acute angle, the electric fields generated by the edge line of the third segment 6b21 and the third edge line 6b11 have a greater influence on each other, resulting in a stronger disordered electric field and a larger area of ​​disordered arrangement of the liquid crystal 10 (for example, the size of b in the figure).

[0161] Referring to Figures 12 and 24, the second lead portion 6b2 of the third sub-pixel electrode 6ba may further include a fifth segment 6b23. The fifth segment 6b23 is connected between the third segment 6b21 and the second electrode portion 6b1. The angle J2 between the edge of the fifth segment 6b23 connected to the third edge line 6b11 and the third edge line 6b11 is a right angle or an obtuse angle. That is, the angle J2 between the edge of the fifth segment 6b23 closest to the third edge line 6b11 and the third edge line 6b11 is a right angle or an obtuse angle. Specifically, the angle is greater than or equal to 90° and less than or equal to 180°. For example, the angle J2 can be 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145°, 150°, 155°, etc. °, 160°, 165°, 170°, 175°, etc.; the angle J3 between the edge line of the fifth segment 6b23 connected to the third edge line 6b11 and the edge line of the third segment 6b21 near the second electrode part 6b1 is also a right angle or an obtuse angle, that is, the angle J3 between the edge line of the fifth segment 6b23 near the third edge line 6b11 and the edge line of the third segment 6b21 near the second electrode part 6b1 is also a right angle or an obtuse angle; specifically, the included angle J3 is greater than or equal to 90° and less than or equal to 180°, for example, the included angle J3 can be 95°, 100°, 105°, 110°, 115°, 120°, 125°, 130°, 135°, 140°, 145°, 150°, 155°, 160°, 165°, 170°, 175°, etc.

[0162] With this configuration, as shown in Figures 25 and 26, the electric field generated between the second lead portion 6b2 and the second electrode portion 6b1 is divided into three segments, with an obtuse angle between each segment. This reduces the mutual influence of the electric fields and weakens the resulting disordered electric field. The disordered area of ​​the liquid crystal 10 (e.g., the size of c in the figure) becomes smaller, which helps to improve trace mura defects and enhance the display effect.

[0163] The fifth segment 6b23 of the third sub-pixel electrode 6ba is connected to the edge line extending along the first direction X of the second electrode portion 6b1, so that the fifth segment 6b23 is connected to the corner of the second electrode portion 6b1 as little as possible. Since the electric field at the corner of the second electrode portion 6b1 is more complex, the fifth segment 6b23 is connected to the corner of the second electrode portion 6b1 as little as possible or even not at all, to avoid forming a more complex electric field and thus improve the end electric field, so that the electric field at all places is more uniform and the trace mura (scratching) defect is improved; moreover, the Vop voltage (Vertical Output Pump Voltage) can be set higher, thereby indirectly improving the transmittance, since the transmittance of the liquid crystal 10 is proportional to the effective value of the Vop voltage.

[0164] In some exemplary embodiments of this disclosure, referring to Figures 12 and 31, the second electrode portion 6b1 of the fourth sub-pixel electrode 6bb has a third edge line 6b11 and a fourth edge line 6b12 disposed opposite to each other. The third edge line 6b11 intersects the first direction X, and the fourth edge line 6b12 intersects the first direction X. The structure of the second electrode portion 6b1 of the fourth sub-pixel electrode 6bb is the same as the structure of the second electrode portion 6b1 of the third sub-pixel electrode 6ba. The third segment 6b21 of the fourth sub-pixel electrode 6bb is closer to the fourth edge line 6b12 than the third edge line 6b11. The angle J6 between the edge line of the third segment 6b21 of the fourth sub-pixel electrode 6bb and the fourth edge line 6b12 is an obtuse angle. Referring to Figures 27 and 28, the electric fields generated between the second lead portion 6b2 and the second electrode portion 6b1 have less mutual influence, resulting in a weaker disordered electric field. The disordered area of ​​the liquid crystal 10 (e.g., the size of a in the figure) is smaller, which is beneficial to improving Trace Mura defects and enhancing the display effect.

[0165] In some exemplary embodiments of this disclosure, referring to Figures 12 and 31, the third segment 6b21 of the fourth sub-pixel electrode 6bb is connected to the edge line extending along the first direction X of the second electrode portion 6b1, such that the third segment 6b21 is connected to the corner portion of the second electrode portion 6b1 as little as possible or not at all. One side edge line of the third segment 6b21 of the fourth sub-pixel electrode 6bb is connected to the second electrode portion 6b1; specifically, the side edge line of the third segment 6b21 of the fourth sub-pixel electrode 6bb closest to the fourth edge line 6b12 is connected to the edge line extending along the first direction X of the second electrode portion 6b1; the opposite side edge line of the third segment 6b21 of the fourth sub-pixel electrode 6bb is connected to the second electrode portion 6b1 via a straight edge line 6b24 extending along the second direction Y.

[0166] The edge line of the third segment 6b21 of the fourth sub-pixel electrode 6bb away from the fourth edge line 6b12 is connected to the edge line of the second electrode portion 6b1 extending in the first direction X by a straight edge line 6b24 extending in the second direction Y.

[0167] Since the electric field at the corner of the second electrode 6b1 is more complex, the third segment 6b21 is connected to the corner of the second electrode 6b1 as little as possible or not at all, to avoid forming a more complex electric field and thus improve the end electric field, so that the electric field at each place is more uniform and the Trace Mura (scratching) is improved; moreover, the Vop voltage (Vertical Output Pump Voltage) can be set higher, thereby indirectly improving the transmittance, since the transmittance of the liquid crystal 10 is proportional to the effective value of the Vop voltage.

[0168] Alternatively, the third segment 6b21 is connected to the edge of the second electrode portion 6b1 near the second transistor T2 connected thereto. Specifically, the third segment 6b21 is connected to the edge line of the second electrode portion 6b1 extending along the first direction X, and to the end of the edge line extending along the first direction X near the end of the second transistor T2 connected to the second electrode portion 6b1. With this configuration, the length of the second lead portion 6b2 can be further reduced, so that the difference between the length of the second lead portion 6b2 and the length of the first lead portion 6a2 is minimized or even zero. This minimizes or even eliminates the difference between the capacitance formed by the second pixel electrode 6b and the second electrode 6 (common electrode) and the capacitance formed by the first pixel electrode 6a and the second electrode 6 (common electrode), thereby reducing the pixel switching voltage ΔVp of the first pixel electrode 6a. This also reduces the risk of flickering in high pixel density (Pixels Per Inch, PPI) display panels.

[0169] In some exemplary embodiments of this disclosure, referring to FIG12, the first lead portion 6a2 may include a first segment 6a21 and a second segment 6a22. The first segment 6a21 is connected to the first electrode portion 6a1, the second segment 6a22 is connected to the end of the first segment 6a21 opposite to the first electrode portion 6a1, and the second segment 6a22 is connected to the first transistor T1. That is, the first electrode portion 6a1, the first segment 6a21, the second segment 6a22 and the first transistor T1 are connected in sequence.

[0170] The extension direction of the first segment 6a21 intersects the extension direction of the second segment 6a22, that is, the first lead portion 6a2 is set as a broken line structure, thereby increasing the length of the first lead portion 6a2, so that the difference between the length of the second lead portion 6b2 and the length of the first lead portion 6a2 is minimized or even zero, thereby minimizing or even eliminating the difference between the capacitance formed by the second pixel electrode 6b and the second electrode 6 (common electrode) and the capacitance formed by the first pixel electrode 6a and the second electrode 6 (common electrode), and further reducing the pixel switching voltage ΔVp of the first pixel electrode 6a. For display panels with high pixel density (Pixels Per Inch, PPI), flickering defects are also prone to occur.

[0171] Specifically, the first segment 6a21 can extend along the second direction Y, and the second segment 6a22 can extend along the first direction X, so that the second segment 6a22 is arranged parallel to the gate line 212, which is beneficial to improving the aperture ratio.

[0172] Alternatively, referring to Figures 11 and 12, the orthographic projection of the first lead portion 6a2 on the substrate 1 overlaps with the orthographic projection of the first transistor T1 on the substrate 1. Specifically, the orthographic projection of the first lead portion 6a2 on the substrate 1 overlaps with the orthographic projection of the active layer 23 of the first transistor T1 on the substrate 1, that is, the first lead portion 6a2 crosses the active layer 23 of the first transistor T1 and connects to the drain 243.

[0173] The second lead 6b2 is directly connected to the drain 243 without crossing the active layer 23 of the second transistor T2. For example, the overlapping area of ​​the orthographic projection of the first lead portion 6a2 on the substrate 1 and the orthographic projection of the active layer 23 of the first transistor T1 on the substrate 1 is the first overlapping area, and the overlapping area of ​​the orthographic projection of the second lead portion 6b2 on the substrate 1 and the orthographic projection of the active layer 23 of the second transistor T2 on the substrate 1 is the second overlapping area. The first overlapping area is greater than the second overlapping area, which further increases the length of the first lead portion 6a2, and further reduces the difference between the length of the second lead portion 6b2 and the length of the first lead portion 6a2 as much as possible or even to zero. This reduces the difference between the capacitance formed by the second pixel electrode 6b and the second electrode 6 (common electrode) and the capacitance formed by the first pixel electrode 6a and the second electrode 6 (common electrode), thereby reducing the pixel switching voltage ΔVp of the first pixel electrode 6a. For display panels with high pixel density (Pixels Per Inch, PPI), flickering is also likely to occur.

[0174] In some exemplary embodiments of this disclosure, referring to Figures 11 and 12, the first segment 6a21 is connected to the edge line extending along the first direction X of the first electrode portion 6a1, such that the first segment 6a21 is connected to the corner portion of the first electrode portion 6a1 as little as possible or even not at all. Since the electric field at the corner portion of the first electrode portion 6a1 is more complex, the first segment 6a21 is connected to the corner portion of the first electrode portion 6a1 as little as possible or even not at all, to avoid forming a more complex electric field and thus improve the end electric field, so that the electric field at each place is more uniform, improving the Trace Mura (scratching) defect; and the Vop voltage (Vertical Output Pump Voltage) can be set higher, thereby indirectly improving the transmittance, since the transmittance of the liquid crystal 10 is proportional to the effective value of the Vop voltage.

[0175] A portion of the plurality of first pixel electrodes 6a is a first sub-pixel electrode 6aa. That is, the first sub-pixel electrode 6aa is the same as the first pixel electrode 6a. Therefore, the first sub-pixel electrode 6aa also includes a first electrode portion 6a1 and a first lead portion 6a2. A portion of the plurality of first pixel electrodes 6a is a second sub-pixel electrode 6ab. That is, the second sub-pixel electrode 6ab is the same as the first pixel electrode 6a. Therefore, the second sub-pixel electrode 6ab also includes a first electrode portion 6a1 and a first lead portion 6a2.

[0176] The first sub-pixel electrode 6aa and the second sub-pixel electrode 6ab are located in adjacent pixel column PXL and adjacent pixel row PXH, so that the first sub-pixel electrode 6aa and the second sub-pixel electrode 6ab are obliquely opposite each other; that is, the adjacent first sub-pixel electrode 6aa and the second sub-pixel electrode 6ab are not adjacent in the first direction X, nor are they adjacent in the second direction Y, but are obliquely adjacent.

[0177] In some exemplary embodiments of this disclosure, referring to FIG12, the first electrode portion 6a1 of the first sub-pixel electrode 6aa has a first edge line 6a11 and a second edge line 6a12 disposed opposite to each other. The first edge line 6a11 intersects the first direction X, and the second edge line 6a12 intersects the first direction X. The first electrode portion 6a1 is configured in a structure that is approximately “<”, with the first edge line 6a11 located on the outer side and the second edge line 6a12 located on the inner side. The first segment 6a21 of the first sub-pixel electrode 6aa is closer to the first edge line 6a11 than the second edge line 6a12, that is, the first segment 6a21 of the first sub-pixel electrode 6aa is disposed closer to the first edge line 6a11. The angle J4 between the edge line of the second segment 6a22 of the first sub-pixel electrode 6aa away from the first segment 6a21 and the first edge line 6a11 is an obtuse angle. Alternatively, it can be said that the outer edge line at the connection between the first electrode portion 6a1 and the first lead portion 6a2 of the first sub-pixel electrode 6aa forms an obtuse angle J4. In this case, as shown in Figures 27 and 28, the electric fields generated between the first lead portion 6a2 and the second electrode portion 6b1 have less mutual influence, resulting in a weaker disordered electric field. The disordered area of ​​the liquid crystal 10 (e.g., the size of a in the figure) is smaller, which is beneficial for improving Trace Mura defects and enhancing the display effect.

[0178] Alternatively, as shown in FIG12, the outer corner where the first segment 6a21 and the second segment 6a22 of the first sub-pixel electrode 6aa are connected is a right angle, that is, the first segment 6a21 and the second segment 6a22 of the first sub-pixel electrode 6aa are vertically connected.

[0179] It should be noted that a right angle is not limited to exactly 90 degrees; it can have a certain margin of error. The range of error varies depending on the equipment and manufacturing process. Therefore, angles within the range of error determined by the equipment and manufacturing process are considered right angles. Furthermore, due to manufacturing limitations, it is difficult to fabricate perfectly right angles at corners; corners typically have a rounded transition. Therefore, the outer corner connecting the first segment 6a21 and the second segment 6a22 of the first sub-pixel electrode 6aa is a right angle; in other words, the outer corner connecting the first segment 6a21 and the second segment 6a22 of the first sub-pixel electrode 6aa does not have a chamfered edge.

[0180] In some exemplary embodiments of this disclosure, referring to FIG12, the first electrode portion 6a1 of the second sub-pixel electrode 6ab has a first edge line 6a11 and a second edge line 6a12 disposed opposite to each other. The first edge line 6a11 intersects the first direction X, and the second edge line 6a12 intersects the first direction X. The structure of the first electrode portion 6a1 of the second sub-pixel electrode 6ab is the same as the structure of the first electrode portion 6a1 of the first sub-pixel electrode 6aa. The first segment 6a21 of the second sub-pixel electrode 6ab is closer to the second edge line 6a12 than the first edge line 6a11, that is, the first segment 6a21 of the second sub-pixel electrode 6ab is disposed closer to the second edge line 6a12. The angle J5 between the edge line of the second segment 6a22 of the second sub-pixel electrode 6ab away from the first segment 6a21 and the second edge line 6a12 is an acute angle. Alternatively, it can be said that the outer edge line at the connection between the second electrode portion 6b1 and the second lead portion 6b2 of the second sub-pixel electrode 6ab forms an acute angle J5. Referring to Figures 22 and 23, in this case, the electric fields generated by the edge line of the first electrode portion 6a1 and the second edge line 6a12 have a greater influence on each other, resulting in a stronger disordered electric field and a larger area of ​​disordered arrangement of the liquid crystal 10 (e.g., the size of b in the figure).

[0181] Referring to FIG12, the outer corner where the first segment 6a21 and the second segment 6a22 of the second sub-pixel electrode 6ab connect is provided with a chamfer. The chamfer makes the outer corner where the first segment 6a21 and the second segment 6a22 of the second sub-pixel electrode 6ab connect form an obtuse angle. Specifically, the chamfer includes a chamfer edge line 6a23. The angle between the chamfer edge line 6a23 and the second edge line 6a12 is an obtuse angle, and the angle between the chamfer edge line 6a23 and the edge line of the second segment 6a22 away from the first segment 6a21 is an obtuse angle.

[0182] With this configuration, as shown in Figures 25 and 26, the electric field generated between the first lead portion 6a2 and the first electrode portion 6a1 is divided into three segments, with an obtuse angle between each segment. This reduces the mutual influence of the electric fields and weakens the resulting disordered electric field. The disordered area of ​​the liquid crystal 10 (e.g., the size of c in the figure) becomes smaller, which helps to improve trace mura defects and enhance the display effect.

[0183] Referring to FIG16, the data line 241 is not only set in the display area AA, but also extends from the display area AA to the fanout area Fanout, passes through the fanout area Fanout to the bonding area BOD, and connects to the bonding pin of the bonding area BOD, so as to achieve bonding connection with the driver chip IC in the bonding area BOD.

[0184] One, two, or more driver chip ICs can be set in the bonding area BOD. One driver chip IC is connected to a portion of the data lines 241 in the display area AA. Since the length of the driver chip IC in the first direction X is less than the length of the display area AA connected to it in the first direction X, some data lines 241 need to be bent to extend to the bonding pin, which makes the length of these data lines 241 longer. Moreover, the length of the data lines 241 increases with the increase of the distance from the first center line ZX1 in the first direction X, so that the lengths of multiple data lines 241 can be different. The first center line ZX1 is the center line of a portion of the bonding area BOD used to bond the driver chip IC, extending along the second direction Y. It can also be said that the first center line ZX1 is the center line of the driver chip IC extending in the second direction Y.

[0185] The resistance of data line 241 increases with the increase of the distance from the first center line ZX1 in the first direction X, resulting in poor uniformity of the resistance of data line 241. This leads to a large difference in the charging rate of sub-pixels PX in different columns, resulting in uneven display color of sub-pixels PX in different columns.

[0186] In some exemplary embodiments of this disclosure, referring to FIG17, at least a portion of the data line 241 may include a first portion 2411 and a second portion 2412, the first portion 2411 being connected to the second portion 2412, the width of the second portion 2412 being greater than the width of the first portion 2411, such that the resistance of the second portion 2412 is less than the resistance of the first portion 2411.

[0187] The orthographic projection of the second portion 2412 on the substrate 1 lies within the region between the mutually distant edges of the orthographic projections of the two gate lines 212 on the substrate 1 of the same group. For example, the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with the orthographic projection of the gate line 212 on the substrate 1. Specifically, a portion of the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with a portion of the orthographic projection of the gate line 212 on the substrate 1. Alternatively, the orthographic projection of the second portion 2412 on the substrate 1 may lie within the orthographic projection of the gate line 212 on the substrate 1. Alternatively, the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with the region between the orthographic projections of the two gate lines 212 on the substrate 1 of the same group. Alternatively, the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with the orthographic projection of the gate line 212 on the substrate 1, and at least partially overlap with the region between the orthographic projections of the two gate lines 212 on the substrate 1 of the same group. With this configuration, even if the width of the data cable 241 is increased, the opening ratio will not be affected; moreover, increasing the width of the data cable 241 at the ramp point prevents the data cable 241 from breaking.

[0188] Because the longer the data line 241 is farther from the first center line ZX1, the greater its resistance, and the shorter the data line 241 is closer to the first center line ZX1, the smaller its resistance; the number of second parts 2412 increases with the distance from the first center line ZX1 in the first direction X, that is, the data line 241 farther from the first center line ZX1 includes more second parts 2412, and the data line 241 closer to the first center line ZX1 includes fewer second parts 2412; the more second parts 2412 there are, the more the resistance of the data line 241 decreases, which makes the resistance of the data line 241 farther from the first center line ZX1 decrease more; the more second parts 2412 there are, the less the resistance of the data line 241 decreases, which makes the resistance of the data line 241 closer to the first center line ZX1 decrease less; thus, the resistance of multiple data lines 241 is basically the same, the charging rate of sub-pixels PX in different columns is basically the same, and thus the display color of sub-pixels PX in different columns is more uniform, achieving the purpose of uniform image quality.

[0189] It should be noted that "the number of second parts 2412 increases with the increase of distance from the first center line ZX1 in the first direction X" means that the number of second parts 2412 generally increases with the distance from the first center line ZX1 in the first direction X. Specifically, the second part 2412 can be omitted on some data lines 241. For example, since the length of one, two, or more data lines 241 closest to the first center line ZX1 is the shortest and the resistance is the smallest, the second part 2412 can be omitted on one, two, or more data lines 241 closest to the first center line ZX1, so that this part of the data lines 241 only includes the first part 2411. In addition, since the lengths of two, three, or more adjacent data lines 241 are not significantly different, their resistances are also not significantly different. Therefore, the number of second parts 2412 included in two, three, or more adjacent data lines 241 can be the same.

[0190] In some other exemplary embodiments of this disclosure, referring to FIG18, at least a portion of the data line 241 may include a first portion 2411 and a second portion 2412, the first portion 2411 being connected to the second portion 2412, the width of the second portion 2412 being smaller than the width of the first portion 2411, such that the resistance of the second portion 2412 is greater than the resistance of the first portion 2411. The orthographic projection of the second portion 2412 on the substrate 1 at least partially overlaps with the orthographic projection of the gate line 212 on the substrate 1. For example, a portion of the orthographic projection of the second portion 2412 on the substrate 1 may at least partially overlap with a portion of the orthographic projection of the gate line 212 on the substrate 1, or the orthographic projection of the second portion 2412 on the substrate 1 may be located within the orthographic projection of the gate line 212 on the substrate 1. This configuration can reduce the parasitic capacitance between the data line 241 and the gate line 212, reduce the mutual interference between the data line 241 and the gate line 212, and has no impact on the aperture ratio.

[0191] Because the longer the data line 241 is farther from the first center line ZX1, the greater its resistance, and the shorter the data line 241 is closer to the first center line ZX1, the smaller its resistance; the number of second parts 2412 decreases as the distance from the first center line ZX1 in the first direction X increases, that is, the number of second parts 2412 included in the data line 241 farther from the first center line ZX1 is smaller, and the number of second parts 2412 included in the data line 241 closer to the first center line ZX1 is larger; the fewer the number of second parts 2412, the less the resistance of the data line 241 increases, so the resistance of the data line 241 further away from the first center line ZX1 increases less; the more the number of second parts 2412, the more the resistance of the data line 241 increases, so the resistance of the data line 241 closer to the first center line ZX1 increases more; thus, the resistance of multiple data lines 241 is basically the same, the charging rate of sub-pixels PX in different columns is basically the same, and the display color of sub-pixels PX in different columns is more uniform, thus achieving the purpose of uniform image quality.

[0192] It should be noted that "the number of second parts 2412 decreases as the distance from the first center line ZX1 in the first direction X increases" means that the number of second parts 2412 generally decreases with increasing distance from the first center line ZX1 in the first direction X. Specifically, second parts 2412 may not be provided on some data lines 241. For example, since the longest and highest resistance of one, two, or more data lines 241 furthest from the first center line ZX1, second parts 2412 may not be provided on these data lines, so that these data lines 241 only include the first part 2411. Furthermore, since the lengths of two, three, or more adjacent data lines 241 are not significantly different, their resistances are also not significantly different. Therefore, the number of second parts 2412 included in two, three, or more adjacent data lines 241 can be the same.

[0193] Alternatively, the connection between the second part 2412 and the first part 2411 can be arc-shaped, so that the second part 2412 and the first part 2411 can be smoothly connected. For example, the connection between the second part 2412 and the first part 2411 can be set as an arc-shaped structure to avoid sharp corners, thereby avoiding sharp corner breakdown defects caused by static electricity (ESD) in the manufacturing process.

[0194] In some other exemplary embodiments of this disclosure, referring to Figures 16 and 19, in Figure 16, the thick solid lines represent the first auxiliary trace 41 and the second auxiliary trace 42, and the thin solid lines represent the data line 241; the conductive auxiliary layer 4 may further include the second auxiliary trace 42, which extends along the second direction Y. Specifically, the second auxiliary trace 42 may be configured as a straight line extending along the second direction Y. The orthographic projection of the second auxiliary trace 42 on the substrate 1 at least partially overlaps with the orthographic projection of the data line 241 on the substrate 1. For example, the orthographic projection of the second auxiliary trace 42 on the substrate 1 may be located within the orthographic projection of the data line 241 on the substrate 1, or a portion of the orthographic projection of the second auxiliary trace 42 on the substrate 1 may overlap with a portion of the orthographic projection of the data line 241 on the substrate 1.

[0195] A fourth via 253 is provided on the first insulating layer 25, which is connected to the data line 241. The second auxiliary trace 42 is connected to the data line 241 through the fourth via 253, so that the second auxiliary trace 42 and the data line 241 are connected in parallel, thereby reducing the resistance of the data line 241 through the second auxiliary trace 42.

[0196] The longer the data line 241 is farther from the first center line ZX1, the greater its resistance; conversely, the shorter the data line 241 is closer to the first center line ZX1, the smaller its resistance. The number of second auxiliary traces 42 increases with the distance from the first center line ZX1 in the first direction X. That is, the farther the data line 241 is from the first center line ZX1, the more second auxiliary traces 42 are provided; the closer the data line 241 is to the first center line ZX1, the fewer second auxiliary traces 42 are provided. The more data lines there are, the greater the reduction in resistance after being connected in parallel with data line 241, resulting in a greater reduction in resistance for data line 241 that is further away from the first center line ZX1; the fewer the second auxiliary traces 42 there are, the less the reduction in resistance after being connected in parallel with data line 241, resulting in a less reduction in resistance for data line 241 that is closer to the first center line ZX1; thus, the resistance of multiple data lines 241 is basically the same, the charging rate of sub-pixels PX in different columns is basically the same, and the display color of sub-pixels PX in different columns is more uniform, achieving the purpose of uniform image quality.

[0197] It should be noted that "the number of second auxiliary traces 42 increases with the increase of the distance from the first center line ZX1 in the first direction X" means that the number of second auxiliary traces 42 generally increases with the distance from the first center line ZX1 in the first direction X. Specifically, second auxiliary traces 42 can be not set in parallel on some data lines 241. For example, since the length of one, two, or more data lines 241 closest to the first center line ZX1 is the shortest and the resistance is the smallest, second auxiliary traces 42 can be not set in parallel on one, two, or more data lines 241 closest to the first center line ZX1. In addition, since the lengths of some adjacent two, three, or more data lines 241 are not much different, their resistances are also not much different. Therefore, the number of second auxiliary traces 42 connected in parallel on adjacent two, three, or more data lines 241 can be the same.

[0198] Alternatively, referring to FIG19, the orthographic projection of the fourth via 253 on the substrate 1 at least partially overlaps with the orthographic projection of the gate line 212 on the substrate 1. For example, the orthographic projection of the fourth via 253 on the substrate 1 may be located within the orthographic projection of the gate line 212 on the substrate 1, or a portion of the orthographic projection of the fourth via 253 on the substrate 1 may overlap with a portion of the orthographic projection of the gate line 212 on the substrate 1. Therefore, the fourth via 253 is disposed at the intersection of the data line 241 and the gate line 212.

[0199] The first electrode 3, as a common electrode, is essentially a single piece. Since the second auxiliary trace 42 overlaps with the data line 241, it cannot overlap with the first electrode 3. Therefore, an opening needs to be provided on the first electrode 3 to accommodate the second auxiliary trace 42 and prevent it from overlapping with the first electrode 3. Because the fourth via 253 connects to the data line 241, and the fourth via 253 is located at the intersection of the data line 241 and the gate line 212, most of the second auxiliary trace 42 is located between two adjacent gate lines 212. This reduces the extension of the second auxiliary trace 42 to the display area of ​​each sub-pixel, avoiding the need for openings on the first electrode 3 in the display area of ​​each sub-pixel, thus ensuring the overlap area between the first electrode 3 and the second electrode 6; and also facilitating process operations.

[0200] The above mainly describes the specific structure of the display area AA of the array substrate. The following describes the specific structure of the non-display area NAA of the array substrate.

[0201] Referring to Figure 1, the non-display area (NAA) may include a data pad (DP), a data pad opposite (DPO), a gate pad left (GPL), and a gate pad left (GPR). Gate driver on array (GOA) circuits are provided on the gate pad left (GPL) and gate pad right (GPR). The gate pad left (GPL) and gate pad right (GPR) are positioned opposite each other in the first direction X. The gate pad left (GPL) generally corresponds to the coverage area of ​​the left bezel, and the gate pad right (GPR) generally corresponds to the coverage area of ​​the right bezel. The data pad side (DP) generally corresponds to the coverage area of ​​the bottom bezel. The data pad side (DP) and the data pad opposite (DPO) are positioned opposite each other in the second direction Y. The data pad opposite (DPO) generally corresponds to the coverage area of ​​the top bezel.

[0202] The data bonding side DP can include a fanout area and a bonding area BOD. The display area AA and the bonding area BOD are connected on opposite sides of the fanout area in the second direction Y. That is, the fanout area is connected between the display area AA and the bonding area BOD. Specifically, the fanout area is connected to the display area AA, and the bonding area BOD is connected to the side of the fanout area away from the display area AA. The bonding area BOD is provided with multiple bonding pins. Some bonding pins are used to bond the driver chip IC, and other bonding pins are used to bond the flexible circuit board FPC. Various traces are provided in the fanout area.

[0203] A printed circuit board (PCB) is bonded to the end of the flexible circuit board (FPC) away from the array substrate. The flexible circuit board (FPC) can be bent so that the PCB is located on the side of the array substrate away from the color filter substrate.

[0204] The array substrate using a dual-gate structure requires fewer driver ICs, which helps to reduce the length of the printed circuit board (PCB) and facilitates the design of a small P-board.

[0205] Referring to FIG1, in some exemplary embodiments of this disclosure, since the position of the connector CNT is required to be relatively close to the center line of the array substrate, the driver chip ICs on both sides can also be moved towards the center line, so that the printed circuit board PCB can be made smaller.

[0206] Based on the same inventive concept, this disclosure provides a display device that may include the array substrate described in any of the above-described embodiments. The specific structure of the array substrate has been described in detail above, and therefore will not be repeated here.

[0207] The display device can be a liquid crystal display panel, an OLED (Organic Light-Emitting Display) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, and so on.

[0208] When the display device can be a liquid crystal display panel, the display device may also include a color filter substrate, and the color filter substrate and the array substrate are bonded together by a frame.

[0209] The display device may include alternating rows of red, green, and blue subpixels, i.e., a row of red, green, and blue subpixels forms a subpixel column group, and multiple subpixel column groups are arranged sequentially. The orthographic projection of the first auxiliary trace on the substrate is located between the orthographic projections of the red and green subpixel columns on the substrate. For example, the first auxiliary trace may be provided between each red and green subpixel column, or the first auxiliary trace may be provided between a portion of the red and green subpixel columns, while no first auxiliary trace is provided between another portion of the red and green subpixel columns.

[0210] Specifically, the first auxiliary line 41 can be located between the first sub-pixel R (red sub-pixel column) and the second sub-pixel G (green sub-pixel column) in the second pixel PX2.

[0211] Because the second lead of the second pixel electrode is connected across the first sub-pixel R (red sub-pixel column) and the second sub-pixel G (green sub-pixel column) in the first pixel PX1, and the second lead of the second pixel electrode is connected across the second sub-pixel G (green sub-pixel column) and the third sub-pixel B (blue sub-pixel column) in the second pixel PX2, if the first auxiliary trace 41 is located in the above positions, the second lead would need to cross the first auxiliary trace 41, which could easily lead to the second lead breaking and failing to display. Therefore, the first auxiliary trace 41 is located between the first sub-pixel R (red sub-pixel column) and the second sub-pixel G (green sub-pixel column) in the second pixel PX2, which can prevent the first auxiliary trace 41 from overlapping with the second lead, thereby preventing the second lead from breaking and failing to display.

[0212] In addition, a spacer PS is provided between two adjacent pixel groups, namely between the third sub-pixel B (blue sub-pixel column) of the first pixel PX1 and the first sub-pixel R (red sub-pixel column) of the second pixel PX2. If the first auxiliary trace 41 is located here, the spacer PS will be formed on the first auxiliary trace 41, resulting in an abnormal shape of the spacer PS and a larger cell gap at that point, which can easily cause uneven display. Therefore, the first auxiliary trace 41 is located between the adjacent first sub-pixel R (red sub-pixel column) and second sub-pixel G (green sub-pixel column) in the second pixel PX2, which can prevent the first auxiliary trace 41 from overlapping with the spacer PS, thereby avoiding uneven display.

[0213] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0214] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0215] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0216] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate having a display area and a non-display area, wherein the non-display area includes a fan-out area and a bonding area, wherein, The array substrate includes: Substrate; A driving circuit layer group is disposed on one side of the substrate. The driving circuit layer group includes a gate layer and a conductor layer. The gate layer includes a gate and a gate line, and the gate line extends along a first direction. The conductor layer includes data lines and signal lines, and the data lines and signal lines extend along a second direction. Two adjacent gate lines form a gate line group. Multiple data lines and multiple gate line groups are intersected to define the display area as multiple pixel areas. The second direction intersects with the first direction. The driving circuit layer group includes multiple transistors, and the multiple transistors include a first transistor and a second transistor. A first electrode and a second electrode are disposed on the side of the driving circuit layer group away from the substrate. A second insulating layer is disposed between the second electrode and the first electrode. Two adjacent second electrodes are a first pixel electrode and a second pixel electrode. The first pixel electrode includes a first electrode portion and a first lead portion connected to each other. The second pixel electrode includes a second electrode portion and a second lead portion connected to each other. The first lead portion is connected to the first transistor. The first transistor and the first electrode portion are located in the same pixel column. The second lead portion is connected to the second transistor. The second electrode portion and the second transistor are located in adjacent pixel columns. The orthographic projection of the second lead portion on the substrate is obliquely intersected with the orthographic projection of the signal trace on the substrate.

2. The array substrate according to claim 1, wherein, The array substrate further includes a conductive auxiliary layer, which includes a first auxiliary trace electrically connected to the first electrode; the orthographic projection of the first auxiliary trace on the substrate does not overlap with the orthographic projections of the first lead portion and the second lead portion on the substrate.

3. The array substrate according to claim 2, wherein, The orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the first auxiliary trace near the corner of the first auxiliary trace on the substrate. Other parts of the orthographic projection of the second electrode on the substrate do not overlap with the orthographic projection of the first auxiliary trace on the substrate.

4. The array substrate according to claim 2, wherein, The first auxiliary trace extends along the second direction, and the orthographic projection of the first auxiliary trace on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

5. The array substrate according to claim 2, wherein, The array substrate further includes: A spacer portion is disposed on the side of the second insulating layer away from the substrate, and the orthographic projection of the spacer portion on the substrate does not overlap with the orthographic projection of the first auxiliary trace on the substrate.

6. The array substrate according to claim 2, wherein, The first electrode portion and the second electrode portion are located within the same pixel region.

7. The array substrate according to claim 6, wherein, The three pixel regions arranged along the first direction form a group, and a first auxiliary trace is provided in a group of pixel regions, or a first auxiliary trace is provided between two adjacent groups of pixel regions.

8. The array substrate according to claim 7, wherein, The conductive auxiliary layer further includes a third auxiliary trace, the orthographic projection of which is located between the orthographic projections of two adjacent second electrodes on the substrate, the third auxiliary trace being disconnected, and the virtual extension of which intersects with the second lead portion.

9. The array substrate according to claim 1, wherein, In the second direction, the first transistor and the second transistor are each located on opposite sides of the pixel region.

10. The array substrate according to claim 9, wherein, The plurality of transistors include multiple groups of transistors, each group of transistors includes two transistors, the two transistors in the same group are located between two adjacent gate lines in the same group, the two transistors in the same group are connected to opposite sides of the same data line in the first direction and are staggered in the second direction; the two gates of the two transistors in the same group are connected one-to-one to two adjacent gate lines in the same group.

11. The array substrate according to claim 9, wherein, The grid lines are configured as straight lines extending along the first direction.

12. The array substrate according to claim 7, wherein, The data line and the signal trace are configured as strips extending along the second direction. A portion of the signal trace is located within the pixel region. The driving circuit layer group includes a first insulating layer located between the conductor layer and the first electrode. The first electrode is connected to the signal trace through a third via on the first insulating layer. The orthographic projection of the third via on the substrate is located between the orthographic projections of two adjacent transistors on the substrate.

13. The array substrate according to claim 12, wherein, The orthographic projection of the second lead portion on the substrate overlaps with the orthographic projection of the signal trace on the substrate, while the orthographic projection of the first lead portion on the substrate does not overlap with the orthographic projection of the signal trace on the substrate.

14. The array substrate according to any one of claims 1 to 13, wherein, The second lead portion includes a third segment and a fourth segment. The third segment is connected to the second electrode portion, and the fourth segment is connected to the end of the third segment away from the second electrode portion. The fourth segment is connected to the second transistor. The fourth segment extends along the first direction, and the third segment extends along a third direction. The third direction intersects the first direction and the third direction intersects the second direction. The orthographic projection of the third segment on the substrate is obliquely intersected with the orthographic projection of the signal trace on the substrate.

15. The array substrate according to claim 14, wherein, The angle between the third segment and the fourth segment is greater than or equal to 135° and less than 180°.

16. The array substrate according to claim 14, wherein, A portion of the multiple second pixel electrodes are third sub-pixel electrodes, and a portion of the multiple second pixel electrodes are fourth sub-pixel electrodes. The third sub-pixel electrodes and the fourth sub-pixel electrodes are located in adjacent pixel columns and adjacent pixel rows, so that the third sub-pixel electrodes and the fourth sub-pixel electrodes are arranged obliquely opposite each other.

17. The array substrate according to claim 16, wherein, The orthographic projection of the second lead portion of the third sub-pixel electrode on the substrate and the orthographic projection of the second lead portion of the fourth sub-pixel electrode on the substrate intersect obliquely with the orthographic projection of the same signal trace on the substrate. The fourth segment of the third sub-pixel electrode and the fourth segment of the fourth sub-pixel electrode are located between two gate lines in the same group. The third segment of the third sub-pixel electrode and the third segment of the fourth sub-pixel electrode are opposite to and parallel to each other in a fourth direction, which is perpendicular to the third direction.

18. The array substrate according to claim 16, wherein, The second electrode portion of the third sub-pixel electrode has a third edge line and a fourth edge line disposed opposite to each other. The third edge line intersects the first direction, and the fourth edge line intersects the first direction. The third segment of the third sub-pixel electrode is closer to the third edge line than the fourth edge line. The angle between the edge line of the third segment of the third sub-pixel electrode closer to the second electrode portion and the third edge line is an acute angle. The second lead portion of the third sub-pixel electrode further includes a fifth segment, which is connected between the third segment and the second electrode portion. The angle between the edge of the fifth segment connected to the third edge and the third edge is a right angle or an obtuse angle, and the angle between the fifth segment and the edge of the third segment near the second electrode portion is also a right angle or an obtuse angle.

19. The array substrate according to claim 16 or 18, wherein, The second electrode portion of the fourth sub-pixel electrode has a third edge line and a fourth edge line disposed opposite to each other. The third edge line intersects the first direction, and the fourth edge line intersects the first direction. The third segment of the fourth sub-pixel electrode is closer to the fourth edge line than the third edge line. The angle between the edge line of the third segment of the fourth sub-pixel electrode closer to the second electrode portion and the fourth edge line is an obtuse angle.

20. The array substrate according to claim 18, wherein, The third segment of the fourth sub-pixel electrode is connected to the edge line of the second electrode portion extending along the first direction; one side edge line of the third segment of the fourth sub-pixel electrode is connected to the second electrode portion; the opposite side edge line of the third segment of the fourth sub-pixel electrode is connected to the second electrode portion via a straight edge line extending along the second direction; the fifth segment of the third sub-pixel electrode is connected to the edge line of the second electrode portion extending along the first direction.

21. The array substrate according to claim 14, wherein, The third segment is connected to the edge of the second electrode portion near the second transistor to which it is connected.

22. The array substrate according to claim 14, wherein, The first lead portion includes a first segment and a second segment. The first segment is connected to the first electrode portion, and the second segment is connected to the end of the first segment away from the first electrode portion. The second segment is connected to the first transistor, and the extension direction of the first segment intersects the extension direction of the second segment.

23. The array substrate according to claim 22, wherein, The first segment extends along the second direction, and the second segment extends along the first direction; the orthographic projection of the first lead portion on the substrate overlaps with the orthographic projection of the first transistor on the substrate; the first segment is connected to the edge line of the first electrode portion extending along the first direction, and is not connected to the corner of the first electrode portion.

24. The array substrate according to claim 22, wherein, A portion of the plurality of first pixel electrodes are first sub-pixel electrodes, and a portion of the plurality of first pixel electrodes are second sub-pixel electrodes. The first sub-pixel electrodes and the second sub-pixel electrodes are located in adjacent pixel columns and adjacent pixel rows, such that the first sub-pixel electrodes and the second sub-pixel electrodes are arranged obliquely opposite each other.

25. The array substrate according to claim 24, wherein, The first electrode portion of the first sub-pixel electrode has a first edge line and a second edge line disposed opposite to each other. The first edge line intersects the first direction, and the second edge line intersects the first direction. The first segment of the first sub-pixel electrode is closer to the first edge line than the second edge line. The angle between the edge line of the second segment of the first sub-pixel electrode that is away from the first segment and the first edge line is an obtuse angle.

26. The array substrate according to claim 25, wherein, The outer corner where the first segment and the second segment of the first sub-pixel electrode connect is at a right angle.

27. The array substrate according to claim 24 or 25, wherein, The first electrode portion of the second sub-pixel electrode has a first edge line and a second edge line disposed opposite to each other. The first edge line intersects with the first direction, and the second edge line intersects with the first direction. The first segment of the second sub-pixel electrode is closer to the second edge line than the first edge line. The angle between the edge line of the second segment of the second sub-pixel electrode away from the first segment and the second edge line is an acute angle. The outer corner where the first segment and the second segment of the second sub-pixel electrode connect is provided with a chamfer.

28. The array substrate according to claim 27, wherein, The chamfer includes a chamfered edge line, the angle between the chamfered edge line and the second edge line is an obtuse angle, and the angle between the chamfered edge line and the edge line of the second segment away from the first segment is an obtuse angle.

29. The array substrate according to any one of claims 1 to 28, wherein, The gate layer is disposed on one side of the substrate, and the driving circuit layer group further includes: A gate insulating layer is disposed on the side of the gate layer opposite to the substrate. An active layer is disposed on the side of the gate insulating layer away from the substrate. The active layer includes a first conductive connection portion, a channel portion, and a second conductive connection portion connected in sequence. A conductor layer is disposed on the side of the active layer away from the substrate. The conductor layer also includes a source and a drain. The source is connected to the first conductive connection portion. The data line is connected to the source. The drain is connected to the second conductive connection portion. Two pixel columns are disposed between two adjacent data lines. A first insulating layer is disposed on the side of the conductor layer opposite to the substrate. A first via is disposed on the first insulating layer. A second via is disposed on the second insulating layer and communicates with the first via. The second electrode is connected to the drain electrode through the second via and the first via.

30. A display device, wherein, include: The array substrate is the array substrate according to any one of claims 1 to 29; The display device includes alternating rows of red, green, and blue sub-pixels, with the orthographic projection of a first auxiliary trace on the substrate located between the orthographic projections of the red and green sub-pixels on the substrate.

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